Multi-time programmable memory device based on memristor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor integration, and discloses a multi-time programmable memory device based on a memristor structure and a preparation method thereof.The device comprises a substrate, a buried oxide layer is arranged in the middle of the substrate, and the top of the substrate is isolated into a collector region through the buried oxide layer; the top of the collector region is provided with a base region, and the top of the base region is provided with shallow trench isolation and an emitter region; oxide layers are arranged at the tops of the collector region and the base region, a first dielectric layer is arranged at the top of each oxide layer, and a second dielectric layer is arranged at the top of each first dielectric layer; three groups of grooves are downwards formed in the surfaces of the first dielectric layer and the second dielectric layer, a resistive layer is deposited on the inner wall of the groove in the left side, and metal is deposited on the inner walls of the groove in the middle and the groove in the right side to form contact holes; the top of the left groove is provided with a cathode, the top of the middle groove is provided with an emitter, and the top of the right groove is provided with a base. According to the invention, the switching time from the HRS to the LHS can be reduced, and the method has a wider application scene.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integration technology, and in particular to a multi-time programmable memory device based on a memristor structure and a preparation method thereof. Background Art

[0002] Artificial intelligence, as a cutting-edge and strategic technology that leads the future, is the core driving force of the fourth scientific and technological revolution and a powerful weapon to accelerate industrial recovery and create new jobs. The hardware optimization design of neural chips is an important direction for achieving strong artificial intelligence, and memristors are the core components of neural chips. Passive circuit elements associated with charge (q) have resistances that satisfy relationship. Simply put, the working principle of a memristor is that its resistance switches between a high-resistance state (HRS) and a low-resistance state (LRS). When switching from HRS to LRS, this process is defined as setting (set), and conversely, the process of switching from LRS to HRS is defined as resetting (reset). Moreover, when the initial resistance is relatively large, the formation of the conductive filaments of the new device requires a process to complete the rapid switching between HRS and LRS. Therefore, under normal circumstances, a large voltage bias is first required to switch the resistance of the memristor from the initial state to LRS. This process is called forming. Subsequently, a smaller bias voltage can achieve switching between LRS and HRS.

[0003] An excellent memristor has the following performance parameters: operating voltage, operating current, on / off ratio, cycle life, retention characteristics, and erase / write speed. Existing memristors cannot achieve both high operating voltage and high erase / write speed. To reduce the switching time from HRS to LHS (to within 10ns), a higher operating voltage (typically 4-5V) must be applied to the memristor. Similarly, applying a lower operating voltage results in a longer switching time (typically 20ns-100ns). Therefore, balancing these two parameters is crucial. The present invention proposes a multi-time programmable memory device based on a memristor structure and a method for fabricating the same. Summary of the Invention

[0004] In response to the problems in the related art, the present invention proposes a multi-time programmable memory device based on a memristor structure and a preparation method thereof, combining bipolar transistors and memristors to form a multi-time programmable device, which can reduce the switching time from HRS to LHS (switching time is 0.1ns-10ns), and at the same time, the operating voltage only requires 1-3V. Moreover, since the structure is compatible with CMOS process, it has a broader application scenario, thereby overcoming the above-mentioned technical problems existing in the existing related technology.

[0005] To this end, the specific technical solutions adopted in the present invention are as follows:

[0006] According to one aspect of the present invention, a multi-time programmable memory device based on a memristor structure is provided, including a substrate, a buried oxide layer is provided in the middle of the substrate, and the buried oxide layer isolates the top of the substrate as a collector region; a base region is provided on the top of the collector region, a shallow trench isolation is provided on one side of the top of the base region, and an emitter region is provided on the other side of the top of the base region; an oxide layer is provided on the top of the collector region and the base region, a first dielectric layer is provided on the top of the oxide layer, and a second dielectric layer is provided on the top of the first dielectric layer; three groups of grooves are opened downward on the surfaces of the first dielectric layer and the second dielectric layer, wherein a resistive layer is deposited on the inner wall of the groove on the left, and metal is deposited on the inner walls of the groove in the middle and the groove on the right to form contact holes; a cathode is provided on the top of the groove on the left, an emitter is provided on the top of the groove in the middle, and a base is provided on the top of the groove on the right.

[0007] According to another aspect of the present invention, a method for preparing a multi-time programmable memory device based on a memristor structure is provided, comprising the following steps:

[0008] S1, implanting a predetermined dose of oxygen atoms downwardly into the front surface of the first conductive type substrate, performing high temperature annealing so that the oxygen atoms react with the interior of the substrate to form a buried oxide layer, and using the substrate above the buried oxide layer as a collector region;

[0009] S2. Performing inversion light doping of a second conductivity type on the surface of the collector region to form a base region, forming shallow trench isolation on the surface of the device, and forming an oxide layer on the surface of the collector region by a coating process;

[0010] S3, performing a first conductivity type heavily doped ion implantation process on the surface of the oxide layer based on a patterned mask, and forming an emitter region in the base region;

[0011] S4. Depositing a first dielectric layer and a second dielectric layer on the surface of the oxide layer respectively, forming three groups of grooves on the first dielectric layer and the second dielectric layer based on a patterned mask, and depositing metal silicide in the three groups of grooves;

[0012] S5. Deposit a resistive switching layer in the groove on the left, deposit metal in the two grooves on the right to form contact holes, and form a cathode, emitter and base at the top of the grooves through a metallization process to obtain a multi-time programmable memory device based on a memristor structure.

[0013] Furthermore, the implantation dose of oxygen atoms is 1x10 17 ~1x10 19 cm -2 The temperature of the high temperature annealing is 1200°C to 1400°C.

[0014] Furthermore, forming shallow trench isolation on the surface of the device includes the following steps:

[0015] A trench etching process is performed on the surface of the device, followed by oxide filling and oxide planarization to form shallow trench isolation.

[0016] Furthermore, the emitter region is heavily doped, and the emitter region is located in a left area of ​​the base region.

[0017] Furthermore, the first dielectric layer is an insulating layer, the second dielectric layer is an interlayer dielectric layer, and the second dielectric layer is located above the first dielectric layer.

[0018] Furthermore, the forming of the grooves on the first dielectric layer and the second dielectric layer based on the patterned mask includes the following steps:

[0019] By using a patterned mask, the first dielectric layer and the second dielectric layer are sequentially subjected to glue coating, soft baking, mask alignment, exposure, photoresist development and etching processes to form grooves.

[0020] Furthermore, the groove is located above the collector region, the emitter region and the base region.

[0021] Furthermore, the resistive switching layer is made of any one of silicon-based resistive switching layer materials or metal oxides.

[0022] Furthermore, the cathode is located at the top of the groove on the left, the emitter is located at the top of the middle groove, and the base is located at the top of the groove on the right.

[0023] The beneficial effects of the present invention are as follows: the present invention combines bipolar transistors and memristors to form a multi-time programmable device, the operating voltage of which is only 1-3V, and the bipolar transistor has a current gain effect during amplification, which increases the potential difference between the collector region and the cathode, forms a larger electric field, and a large number of oxygen vacancies in the resistive layer quickly migrate to form conductive filaments, resulting in a decrease in device resistance, thereby achieving rapid switching from a high resistance state (HRS) to a low resistance state (LRS), reducing switching time and improving erase speed; when a reverse voltage is applied to the cathode, the oxygen vacancies in the resistive layer migrate back to their original position, the conductive filaments break, the resistance increases, and the device switches from a low resistance state to a high resistance state (HRS). At the same time, because the structure is compatible with CMOS technology, it has a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a structural diagram of a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention;

[0026] Figure 2 is a flow chart of a method for preparing a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention;

[0027] Figure 3 1 is a schematic diagram of the preparation process of step S1 in the method for preparing a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention;

[0028] Figure 4 2 is a schematic diagram of the preparation process of step S2 in the method for preparing a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention;

[0029] Figure 5 3 is a schematic diagram of the preparation process of step S3 in the method for preparing a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention;

[0030] Figure 6 3 is a schematic diagram of the preparation process of step S4 in the method for preparing a multi-time programmable memory device based on a memristor structure according to an embodiment of the present invention.

[0031] In the picture:

[0032] 100, substrate; 101, buried oxide layer; 1001, collector region; 101T, shallow trench isolation; 102, base region; 103, emitter region; 1031, oxide layer; 104, metal silicide; 105, first dielectric layer; 106, second dielectric layer; 107, groove; 1071, resistive layer; 1072, contact hole; 108M, emitter; 109M, base; 112M, cathode. DETAILED DESCRIPTION

[0033] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. By referring to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0034] According to an embodiment of the present invention, a multi-time programmable memory device based on a memristor structure and a manufacturing method thereof are provided.

[0035] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figure 1As shown, according to one embodiment of the present invention, a multi-time programmable memory device based on a memristor structure is provided, comprising a substrate 100, a buried oxide layer 101 is provided in the middle of the substrate 100, and the buried oxide layer 101 isolates the top of the substrate 100 into a collector region 1001; a base region 102 is provided on the top of the collector region 1001, a shallow trench isolation 101T is provided on one side of the top of the base region 102, and an emitter region 103 is provided on the other side of the top of the base region 102; an oxide layer 1031 is provided on the top of the collector region 1001 and the base region 102, and a thin film is formed on the top of the oxide layer 1031. A first dielectric layer 105 is provided, and a second dielectric layer 106 is provided on top of the first dielectric layer 105; three groups of grooves 107 are opened downward on the surfaces of the first dielectric layer 105 and the second dielectric layer 106, wherein a resistive layer 1071 is deposited on the inner wall of the groove 107 on the left, and metal is deposited on the inner walls of the middle groove 107 and the right groove 107 to form contact holes 1072; a cathode 112M is provided on the top of the left groove 107, an emitter 108M is provided on the top of the middle groove 107, and a base 109M is provided on the top of the right groove 107.

[0036] According to another embodiment of the present invention, Figure 2-Figure 6 As shown, a method for preparing a multi-time programmable memory device based on a memristor structure is provided, comprising the following steps:

[0037] S1, implanting a predetermined dose of oxygen atoms downwardly into the front surface of the first conductive type substrate, performing high temperature annealing so that the oxygen atoms react with the interior of the substrate to form a buried oxide layer, and using the substrate above the buried oxide layer as a collector region;

[0038] Specifically, if Figure 3 As shown, a substrate 100 of a first conductive type is provided, and a dose of 1x10 17 ~1x10 19 cm -2 Oxygen atoms are then annealed at a high temperature of 1200°C to 1400°C, causing the oxygen atoms to react with the interior of the substrate 100, ultimately forming a buried oxide layer 101 under the surface of the substrate 100. At this time, the substrate 100 above the buried oxide layer 101 serves as a collector region, marked as 1001;

[0039] S2, performing a second conductivity type inversion light doping on the surface of the collector region to form a base region, forming a shallow trench isolation on the surface of the device (i.e., the surface of the multi-time programmable memory device to be prepared), and forming an oxide layer on the surface of the collector region by a coating process;

[0040] Specifically, if Figure 4As shown, a second conductive type inversion light doping is performed on the surface of the collector region 1001 to form a base region 102, and then trench etching, oxide filling and oxide planarization are performed on the surface of the device to form a shallow trench isolation 101T, and finally an oxide layer 1031 is formed on its surface by a coating process;

[0041] S3, performing a first conductivity type heavily doped ion implantation process on the surface of the oxide layer based on a patterned mask, and forming an emitter region in the base region;

[0042] Specifically, if Figure 5 As shown, on the surface of the oxide layer 1031, heavily doped ions of the first conductivity type are implanted through a mask to form an emitter region 103, wherein the emitter region 103 is heavily doped and is located on the left side of the base region 102;

[0043] S4. Depositing a first dielectric layer and a second dielectric layer on the surface of the oxide layer respectively, forming three groups of grooves on the first dielectric layer and the second dielectric layer based on a patterned mask, and depositing metal silicide in the three groups of grooves;

[0044] Specifically, if Figure 6 As shown, a first dielectric layer 105 and a second dielectric layer 106 are deposited on the surface of the oxide layer 1031, respectively. The first dielectric layer 105 is an insulating layer, and the second dielectric layer 106 is an interlayer dielectric layer (a dielectric material is filled in the insulating layer to prevent the formation of voids and defects). A groove 107 is formed on the surface of the device using a patterned mask through the steps of coating, soft baking, mask alignment, exposure, photoresist development, and etching. The groove 107 is located above the collector region 1001, the emitter region 103, and the base region 102. A metal silicide 104 is deposited in the groove 107.

[0045] S5. Deposit a resistive switching layer in the groove on the left, deposit metal in the two grooves on the right to form contact holes, and form a cathode, emitter and base at the top of the grooves through a metallization process to obtain a multi-time programmable memory device based on a memristor structure.

[0046] Specifically, metal is deposited in the two grooves 107 on the right to form contact holes 1072, and a resistive switching layer 1071 is deposited in the groove 107 on the left. Subsequently, a cathode 112M, an emitter 108M, and a base 109M are formed respectively through a metallization process.

[0047] Among them, the resistive layer material can be a silicon-based resistive layer material, such as one of Si, SiOx, SiNy and SiOxNy; it can also be made of metal oxides such as HfO2, ZrO2, ZnO, TaO, tungsten oxide, perovskite, gallium oxide, indium oxide, etc.

[0048] In order to facilitate understanding of the above technical solutions of the present invention, the working principle or operation mode of the present invention in actual process is described in detail below.

[0049] When the first conductivity type is P-type and the second conductivity type is N-type, a positive voltage is applied to the emitter 109M relative to the base 108M (the forward voltage difference is about 0.6V), and a negative voltage (1.5V-3V) is applied to the cathode 112M. At this time, the bipolar transistor is in the on state, and the emitter region 103 tends to flow laterally to the surface of the collector region 1001. The current shows a multiplication effect. A large number of holes gather on the surface of the collector region 1001, and the potential increases, further increasing the potential difference with the cathode 112M. Under the action of this strong electric field, a large number of oxygen vacancies in the resistive layer 1071 quickly migrate to form conductive filaments, resulting in a decrease in device resistance, thereby achieving a rapid switch from a high resistance state (HRS) to a low resistance state (LRS), reducing the switching time and improving the erase speed; when a positive voltage is applied to the cathode 112M, the oxygen vacancies in the resistive layer 1071 migrate back to their original positions, the conductive filaments break, the resistance increases, and the device switches from a low resistance state to a high resistance state (HRS);

[0050] When the first conductivity type is N-type and the second conductivity type is P-type, a negative voltage is applied to the emitter 109M relative to the base 108M (the negative voltage difference is about 0.6V), and a positive voltage (1.5V-3V) is applied to the cathode 112M. At this time, the bipolar transistor is in the on state, and the emitter region 103 tends to flow laterally to the surface of the collector region 1001. The current shows a multiplication effect, a large number of electrons gather on the surface of the collector region 1001, and the potential decreases, further increasing the potential difference with the cathode 112M. Under the action of this strong electric field, a large number of oxygen vacancies in the resistive layer 1071 quickly migrate to form conductive filaments, resulting in a decrease in device resistance, thereby achieving a rapid switch from a high resistance state (HRS) to a low resistance state (LRS), reducing the switching time and improving the erase speed; when the cathode 112M applies a reverse voltage, the oxygen vacancies in the resistive layer 1071 migrate back to their original position, the conductive filaments break, the resistance increases, and the device switches from a low resistance state to a high resistance state (HRS).

[0051] In summary, with the help of the above technical solution of the present invention, the present invention combines bipolar transistors and memristors to form a multi-time programmable device, the operating voltage of which is only 1-3V, and the bipolar transistor has a current gain effect during amplification, which increases the potential difference between the collector region and the cathode, forming a larger electric field. A large number of oxygen vacancies in the resistive layer quickly migrate to form conductive filaments, resulting in a decrease in device resistance, thereby achieving rapid switching from a high resistance state (HRS) to a low resistance state (LRS), reducing switching time and improving erase speed; when a reverse voltage is applied to the cathode, the oxygen vacancies in the resistive layer migrate back to their original position, the conductive filaments break, the resistance increases, and the device switches from a low resistance state to a high resistance state (HRS). At the same time, since this structure is compatible with CMOS technology, it has a wider range of application scenarios.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-time programmable memory device based on a memristor structure, characterized in that: The invention comprises a substrate (100), wherein a buried oxide layer (101) is provided in the middle of the substrate (100), and the buried oxide layer (101) isolates the top of the substrate (100) as a collector region (1001); A base region (102) is provided on the top of the collector region (1001), a shallow trench isolation (101T) is provided on one side of the top of the base region (102), and an emitter region (103) is provided on the other side of the top of the base region (102); An oxide layer (1031) is provided on the top of the collector region (1001) and the base region (102), a first dielectric layer (105) is provided on the top of the oxide layer (1031), and a second dielectric layer (106) is provided on the top of the first dielectric layer (105); Three groups of grooves (107) are provided downwardly on the surfaces of the first dielectric layer (105) and the second dielectric layer (106), wherein a resistive switching layer (1071) is deposited on the inner wall of the left groove (107), and metal is deposited on the inner wall of the middle groove (107) and the right groove (107) to form a contact hole (1072); A cathode (112M) is provided at the top of the groove (107) on the left, an emitter (108M) is provided at the top of the middle groove (107), and a base (109M) is provided at the top of the groove (107) on the right.

2. A method for preparing a multi-time programmable memory device based on a memristor structure, for realizing the preparation of the multi-time programmable memory device based on a memristor structure according to claim 1, characterized in that: The following steps are involved: S1, implanting a predetermined dose of oxygen atoms downwardly into the front surface of the first conductive type substrate, performing high temperature annealing so that the oxygen atoms react with the interior of the substrate to form a buried oxide layer, and using the substrate above the buried oxide layer as a collector region; S2. Performing inversion light doping of a second conductivity type on the surface of the collector region to form a base region, forming shallow trench isolation on the surface of the device, and forming an oxide layer on the surface of the collector region by a coating process; S3, performing a first conductivity type heavily doped ion implantation process on the surface of the oxide layer based on a patterned mask, and forming an emitter region in the base region; S4. Depositing a first dielectric layer and a second dielectric layer on the surface of the oxide layer respectively, forming three groups of grooves on the first dielectric layer and the second dielectric layer based on a patterned mask, and depositing metal silicide in the three groups of grooves; S5. Deposit a resistive switching layer in the groove on the left, deposit metal in the two grooves on the right to form contact holes, and form a cathode, emitter and base at the top of the grooves through a metallization process to obtain a multi-time programmable memory device based on a memristor structure.

3. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, characterized in that: The implantation dose of oxygen atoms is 1x10 17 ~1x10 19 cm -2 The temperature of the high temperature annealing is 1200°C to 1400°C.

4. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: Forming shallow trench isolation on the surface of the device includes the following steps: A trench etching process is performed on the surface of the device, followed by oxide filling and oxide planarization to form shallow trench isolation.

5. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: The emitter region is heavily doped and is located in a left area of ​​the base region.

6. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: The first dielectric layer is an insulating layer, the second dielectric layer is an interlayer dielectric layer, and the second dielectric layer is located above the first dielectric layer.

7. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: The forming of the grooves on the first dielectric layer and the second dielectric layer based on the patterned mask comprises the following steps: By using a patterned mask, the first dielectric layer and the second dielectric layer are sequentially subjected to glue coating, soft baking, mask alignment, exposure, photoresist development and etching processes to form grooves.

8. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: The groove is located on the collector region, the emitter region and the base region.

9. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, wherein: The resistive switching layer is made of any one of silicon-based resistive switching layer materials or metal oxides.

10. The method for preparing a multi-time programmable memory device based on a memristor structure according to claim 2, characterized in that: The cathode is located at the top of the groove on the left, the emitter is located at the top of the middle groove, and the base is located at the top of the groove on the right.

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