Chip packaging structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of chip packaging. The chip packaging structure comprises a stacking structure, a wiring layer, a protection layer and a plurality of first filling blocks. The stacked structure includes a plurality of dies arranged in a stacked manner. The wiring layer is located on one side of the stacked structure. A plurality of interconnection structures are arranged in the wiring layer, and any two bare chips in the stacking structure are connected with each other through at least one interconnection structure. And the protection layer is positioned on one side, far away from the stacking structure, of the wiring layer. One first filling block is located on one side, far away from the stacking structure, of one interconnection structure, and the first filling blocks penetrate through the protection layer in the stacking direction. The chip packaging structure can be applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] At present, as high-performance computing, AI, 5G and other applications have increasingly higher requirements for storage bandwidth, the high-bandwidth memory (HBM) module structure implemented by vertically stacking multiple layers of dynamic random access memory (DRAM) is becoming an increasingly mainstream solution. Summary of the Invention

[0003] In one aspect, a chip packaging structure is provided, including a stacking structure, a wiring layer, a protection layer, and a plurality of first filling blocks.

[0004] The stack structure includes a plurality of dies arranged in a stack.

[0005] The wiring layer is located on one side of the stacking structure. A plurality of interconnection structures are provided in the wiring layer, and any two bare chips in the stacking structure are connected to each other through at least one of the interconnection structures.

[0006] The protection layer is located on a side of the wiring layer away from the stacking structure.

[0007] One of the first filling blocks is located on a side of the interconnect structure away from the stacking structure, and the first filling block penetrates the protection layer along the stacking direction.

[0008] In some embodiments, the plurality of dies includes at least one first die and at least one second die.

[0009] The interconnect structure connected to the second bare chip is disconnected, and along the stacking direction, an area where the interconnect structure is disconnected overlaps with a first filling block located on one side of the interconnect structure.

[0010] In some embodiments, the second die comprises a defective die and the first die comprises a qualified die.

[0011] In some embodiments, the interconnect structure includes a first conductive pad and at least two connection structures, wherein one end of the at least two connection structures is connected to the first conductive pad, and the other ends of the at least two connection structures are respectively connected to different bare chips.

[0012] The first conductive pad of the interconnect structure connected to the second die is disconnected.

[0013] In some embodiments, the first conductive pad of the interconnect structure connected to the second die has a laser fuse trace.

[0014] In some embodiments, an area of ​​the first filling block close to one end of the wiring layer is greater than or equal to an area of ​​a region where the interconnect structure is disconnected.

[0015] In some embodiments, an area of ​​one end of the first filling block close to the wiring layer is smaller than an area of ​​one end of the first filling block away from the wiring layer.

[0016] In some embodiments, the chip package structure further includes a test structure and a second filling block.

[0017] A test structure is located in the wiring layer, and the test structure is connected to at least one of the bare chips.

[0018] The second filling block is located at a side of the test structure away from the stacking structure, and the second filling block penetrates the protection layer along the stacking direction.

[0019] In some embodiments, the chip packaging structure further includes a packaging layer covering the stacking structure, the wiring layer and the protection layer.

[0020] Part of the material of the encapsulation layer forms the first filling block and the second filling block.

[0021] In another aspect, a method for preparing a chip packaging structure is provided, comprising the following steps:

[0022] Multiple bare chips are stacked to form a stacked structure.

[0023] A wiring layer is formed on one side of the stacking structure; a plurality of interconnection structures are formed in the wiring layer, and any two bare chips in the stacking structure are connected to each other through at least one of the interconnection structures.

[0024] A protection layer is formed on a side of the wiring layer away from the stack structure.

[0025] A plurality of first openings are formed in the protective layer. One of the first openings is located on a side of the interconnection structure away from the stacking structure, and the first opening penetrates the protective layer along the stacking direction.

[0026] The plurality of dies in the stacked structure are inspected.

[0027] Based on the presence of a defective die in the stacked structure, the interconnection structure connected to the defective die is disconnected through the first opening.

[0028] In some embodiments, the interconnect structure connected to the defective die is disconnected by a laser fusing process.

[0029] In some embodiments, the method for preparing the chip packaging structure further includes: forming a test structure in the wiring layer, wherein the test structure is connected to at least one of the bare chips.

[0030] A second opening is formed in the protection layer. The second opening is located on a side of one of the test structures away from the stacking structure, and the second opening penetrates the protection layer along the stacking direction.

[0031] The inspecting the plurality of dies in the stack structure includes inspecting the dies connected to the test structure through the second opening and the test structure.

[0032] In some embodiments, the method for preparing the chip packaging structure further includes: forming a packaging layer, wherein the packaging layer covers the stacking structure, the wiring layer, and the protective layer.

[0033] Part of the material of the encapsulation layer fills the first opening to form a first filling block, and fills the second opening to form a second filling block.

[0034] In some embodiments, the interconnect structure includes a first conductive pad and at least two connection structures, wherein one end of the connection structure is connected to the first conductive pad and the other end is connected to different dies in the stacked structure.

[0035] The step of disconnecting an internal circuit of an interconnect structure connected to the defective die includes disconnecting a first conductive pad of the interconnect structure connected to the defective die.

[0036] In another aspect, a storage system is provided, comprising the chip packaging structure and a controller as described above, wherein the controller is connected to the chip packaging structure.

[0037] In another aspect, an electronic device is provided, comprising: a processor and the storage system as described above, wherein the processor is coupled to the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0039] Figure 1 A structural diagram of an electronic device provided according to some embodiments of the present disclosure;

[0040] Figure 2A A structural diagram of a storage system provided according to some embodiments of the present disclosure;

[0041] Figure 2B Another structural diagram of a storage system provided according to some embodiments of the present disclosure;

[0042] Figure 3 for Figure 2B A structural diagram of the AA area of ​​the chip package structure;

[0043] Figure 4 for Figure 3 The planar structure diagram of the wiring layer in ;

[0044] Figure 5 for Figure 2B Another structural diagram of the AA area of ​​the chip package structure;

[0045] Figure 6 for Figure 2B Another structural diagram of the AA region of the chip package structure;

[0046] Figure 7 for Figure 6 The planar structure diagram of the wiring layer in ;

[0047] Figure 8 for Figure 2B Another structural diagram of the AA region of the chip package structure;

[0048] Figure 9 A local area structural diagram of a chip package structure provided according to some embodiments of the present disclosure;

[0049] Figure 10 A flowchart of a method for preparing a chip packaging structure according to some embodiments of the present disclosure;

[0050] Figure 11 Based on Figure 10 A structural diagram corresponding to step S1 in the provided method for preparing a chip packaging structure;

[0051] Figure 12 Based on Figure 10 Structural diagram corresponding to step S2 and step S7 in the provided method for preparing a chip packaging structure;

[0052] Figure 13 for Figure 12 A structural diagram of the BB region in ;

[0053] Figure 14 Based on Figure 10 Structural diagram corresponding to step S3, step S4 and step S8 in the provided method for preparing a chip packaging structure;

[0054] Figure 15 for Figure 14 A structural diagram of the BB region in ;

[0055] Figure 16 Based on Figure 10 A structural diagram corresponding to step S6 in the provided method for preparing a chip packaging structure;

[0056] Figure 17 Based on Figure 10 The structural diagram corresponding to step S9 in the method for preparing the chip packaging structure provided. DETAILED DESCRIPTION

[0057] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0058] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something with no intervening features or layers (i.e., directly on something).

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] like Figure 1As shown, some embodiments of the present disclosure provide an electronic device 1000. The electronic device 1000 includes, but is not limited to, any one of a mobile phone, a tablet computer, a laptop computer, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, and a wearable device (such as a smart watch, a smart bracelet, or smart glasses). The embodiments of the present application do not limit the type of electronic device.

[0065] In some embodiments, please refer to Figure 1 The electronic device 1000 includes a storage system 100 and a processor 200 , and the processor 200 is coupled to the storage system 100 to interact with the storage system 100 .

[0066] Exemplarily, the processor 200 may be a central processing unit (CPU), or other general-purpose processors, a graphics processing unit (GPU), a system on a chip (SoC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0067] The storage system 100 is described in detail below.

[0068] The storage system 100 may be integrated into a memory card. Memory cards include, for example, PC cards (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC), Secure Digital (SD) cards, and UFS.

[0069] The storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0070] In some embodiments, as Figure 2A As shown, Figure 2A FIG1 is a structural diagram of a storage system 100 provided according to some embodiments of the present disclosure. The storage system 100 includes a chip package structure 10 and a controller 50. The controller 50 is electrically connected to the chip package structure 10 and can control the chip package structure 10 to store data.

[0071] For example, the controller 50 may be integrated with the chip packaging structure 10 , or may be disposed outside the chip packaging structure 10 and electrically connected to the chip packaging structure 10 through leads or a transfer film layer.

[0072] In some embodiments, the controller 50 in the storage system 100 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0073] In other embodiments, the controller 50 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0074] In some embodiments, the controller 50 may be configured to manage data stored in the chip package structure 10 and communicate with an external device (eg, a host).

[0075] In some embodiments, the controller 50 may also be configured to control operations of the chip package structure 10 , such as read, erase, and program operations.

[0076] In some embodiments, the controller 50 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 10 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0077] In some embodiments, the controller 50 is further configured to process error correction codes on data read from or written to the chip package structure 10 .

[0078] Of course, the controller 50 may also perform any other suitable functions, such as formatting the chip package structure 10 ; for example, the controller 50 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0079] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0080] In some embodiments, as Figure 1 and Figure 2B As shown, Figure 2B FIG1 is a block diagram of a memory system 100 according to some embodiments of the present disclosure. The memory system 100 further includes a transfer layer 20. The chip package structure 10 and the processor 200 are electrically connected via the transfer layer 20. By integrating the chip package structure 10 and the processor 200 on the transfer layer 20, the distance between the chip package structure 10 and the processor 200 can be reduced, and the signal transmission speed between the chip package structure 10 and the processor 200 can be increased.

[0081] Exemplarily, the chip package structure 10 and the processor 200 are located on the same side of the transfer layer 20 .

[0082] For example, the transfer layer 20 may be a redistribution layer (RDL) produced through a redistribution process. The RDL may include multiple layers of metal traces and multiple layers of dielectric layers, with each adjacent layer of metal traces separated by a dielectric layer. The dielectric layer may be made of an insulating material such as a resin. To electrically connect metal traces on different layers, conductive channels may be formed within the dielectric layer to electrically connect the metal traces on different layers.

[0083] The transfer layer 20 may also be an interposer, comprising a substrate, a redistribution layer integrated on the substrate, and conductive pathways extending through the substrate, the conductive pathways being electrically connected to metal traces in the redistribution layer. For example, when the substrate is a silicon substrate made of a semiconductor material containing silicon, the interposer is a silicon interposer (Si interposer).

[0084] For example, the transfer layer 20 may be electrically connected to the chip package structure 10 and the processor 200 through the bumps 30 .

[0085] The chip packaging structure 10 is described in detail below.

[0086] In some embodiments, please refer to Figure 2B The chip package structure 10 includes a stack structure D. The stack structure D includes a plurality of bare chips 1 (which can be expressed as Die in English) that are stacked.

[0087] It should be noted that the bare die 1 involved in each embodiment of the present disclosure is a device that has been cut and tested from a wafer but not packaged. This bare die 1 has pads for packaging and may not be directly used in actual circuits. The bare die 1 can be used in actual circuits after being packaged into a semiconductor chip.

[0088] Figure 2B In the illustrated embodiment, the stacking structure D includes four bare chips 1 as an example, but the number of bare chips 1 in the stacking structure D is not limited to this. The number of bare chips 1 in the stacking structure D can be set based on actual needs. For example, the number of bare chips 1 in the stacking structure D can be 2, 3, 5, 6, 7 or 8, etc.

[0089] For example, please refer to Figure 2B The stacking method of the multiple bare chips 1 in the stacking structure D can be 3D vertical stacking, which can reduce the packaging size of the chip packaging structure 10, is conducive to the miniaturization of the chip packaging structure 10, and improves the integration of the chip packaging structure 10.

[0090] For example, the die 1 may include a NAND flash memory die, a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc. When the die 1 is a memory die, the storage density of the single chip package structure 10 can be increased by stacking multiple die 1 in the single chip package structure 10. Compared with a single die 1, an increase in the number of die 1 will correspondingly increase the storage capacity.

[0091] When die 1 is a dynamic random access memory (DRAM) die, chip package structure 10 may be a high-bandwidth memory (HBM). High-bandwidth memory (HBM) is a high-performance random access memory (RAM) that is a 3D stack of DRAM die. It is often used in conjunction with high-performance graphics accelerators and network devices that access large data sets. High-bandwidth memory (HBM) generally achieves higher bandwidth while using less power in a smaller form factor.

[0092] In some embodiments, please refer to Figure 2B , the plurality of dies 1 includes at least one first die 1 a and at least one second die 1 b .

[0093] Illustratively, the plurality of dies 1 may include one first die 1 a , or may include multiple first dies 1 a , for example, two first dies 1 a , three first dies 1 a , four first dies 1 a , or five first dies 1 a .

[0094] The plurality of dies 1 may include one second die 1 b , or may include a plurality of second dies 1 b , for example, two second dies 1 b , three second dies 1 b , four second dies 1 b , or five second dies 1 b .

[0095] Exemplarily, the first die 1 a includes a qualified die 1 , and the second die 1 b includes a defective die 1 .

[0096] The above-mentioned “defective die 1 ” means that the die 1 has defects due to various reasons and thus may not be able to achieve normal functions.

[0097] For example, the cause of the defect in the die 1 may be mechanical shock or stress.

[0098] For example, the cause of the defect in the die 1 may also be contamination, excessive temperature, or excessive voltage. Figure 2B The chip package structure 10 further includes a buffer die 8. The buffer die 8 is disposed on one side of the stack structure D and is electrically connected to the die 1 in the stack structure D.

[0099] Exemplarily, the buffer die 8 may include a logic die, a base die, etc.

[0100] By way of example, the buffer die 8 can implement several logic functions. The buffer die 8 can include a circuit region. The circuit region can be a region including a wafer and circuits provided by components formed on the wafer. Some of the circuits can constitute a physical layer circuit. When the physical layer circuit is a transmitting circuit, the physical layer circuit can be configured as a driver, and when the physical layer circuit is a receiving circuit, the physical layer circuit can be configured as a buffer. The circuit region can be formed of silicon, etc.

[0101] For example, please refer to Figure 2B The die 1 in the stack structure D can be electrically connected to the buffer die 8 through the conductive structure 2 (eg, electrical connector, etc.).

[0102] The conductive structure 2 may include one or more through silicon vias (TSVs), which have the advantages of high density and short vertical interconnection distance, and are conducive to improving the data transmission speed between the die 1 and the buffer die 8 in the stack structure D.

[0103] In some embodiments, as Figure 2B and Figure 3 As shown, Figure 3 for Figure 2B FIG. 1 shows a structural diagram of the AA region of the chip package structure 10. The chip package structure 10 further includes a wiring layer 4. The wiring layer 4 is located on one side of the stack structure D. Multiple interconnect structures 41 are provided within the wiring layer 4. Any two dies 1 in the stack structure D are interconnected via at least one interconnect structure 41.

[0104] For example, Figure 3 and Figure 4 As shown, Figure 4 for Figure 3 FIG. 4 is a planar structural diagram of the wiring layer 4 in FIG. The interconnect structure 41 includes a first conductive pad 411 and at least two connection structures 412. One end of the at least two connection structures 412 is connected to the first conductive pad 411, and the other ends of the at least two connection structures 412 are respectively connected to different bare chips 1.

[0105] For example, when the interconnect structure 41 includes two connection structures 412, one end of each of the connection structures 412 is connected to the first conductive pad 411, the other end of one of the two connection structures 412 is connected to the first die 1a, and the other end of the other of the two connection structures 412 is connected to the second die 1b. That is, the first die 1a and the second die 1b in the stacked structure D are interconnected via the interconnect structure 41.

[0106] The connection structure 412 may include pads, conductive pillars, and leads, etc. For example, the connection structure 412 may be formed into a multi-layer or single-layer structure. When the connection structure 412 is formed into a multi-layer structure, the connection structure 412 may include pads and conductive pillars. When the connection structure 412 is formed into a single-layer structure, the connection structure 412 may include pads, conductive pillars, or leads, etc. However, this is merely an example, and the arrangement of the connection structure 412 is not limited thereto. The number, spacing, arrangement, etc. of the connection structures 412 are not specifically limited, but may be fully modified by those skilled in the art based on design details.

[0107] In some embodiments, please refer to Figure 3 and Figure 4 A test structure 42 is further provided in the wiring layer 4. The test structure 42 is connected to at least one die 1 in the stacked structure D. The test structure 42 can test the performance of the die 1 connected thereto, for example, to test whether the die 1 is a qualified die or a defective die.

[0108] In some embodiments, please refer to Figure 3 The chip package structure 10 further includes a protective layer 3. The protective layer 3 is located on a side of the wiring layer 4 away from the stacking structure D. The protective layer 3 can protect the wiring layer 4 and prevent the wiring layer 4 from being damaged physically or chemically by the outside.

[0109] For example, the protective layer 3 may include a passivation layer. The material of the passivation layer may include an insulating material. For example, the material of the passivation layer may be a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide resin), a thermosetting resin or a resin mixed with an inorganic filler (e.g., ABF (Ajinomoto Build-up Film)), etc.

[0110] In some embodiments, as Figure 5 As shown, combined with Figure 3 , Figure 5 for Figure 2B A structural diagram of the AA region of the chip package structure 10 in FIG. A second filling block 52 is provided in the protective layer 3. The second filling block 52 is located on a side of a test structure 42 away from the stacking structure D, and the second filling block 52 penetrates the protective layer 3 along the stacking direction.

[0111] Because the second filler block 52 is located within the protective layer 3, before forming the second filler block 52 within the protective layer 3, a second opening 32 for accommodating the second filler block 52 needs to be formed within the protective layer 3. Since the second filler block 52 penetrates the protective layer 3 along the stacking direction, the second opening 32 also penetrates the protective layer 3 along the stacking direction. Furthermore, since the second filler block 52 is located on the side of a test structure 42 away from the stacking structure D, the second opening 32 is also located on the side of a test structure 42 away from the stacking structure D.

[0112] That is to say, before the second filling block 52 is formed in the second opening 32, the second opening 32 penetrates the protective layer 3 along the stacking direction and is located on the side of a test structure 42 away from the stacking structure D, which can expose the test structure 42 located in the wiring layer 4, making it easier for the test structure 42 to be electrically connected to external devices.

[0113] For example, please refer to Figure 3 The second opening 32 exposes the test structure 42 located in the wiring layer 4 , and the second opening 32 may expose a test pad 421 of the test structure 42 .

[0114] For example, the second opening 32 may be formed in the protective layer 3 by a laser drilling process, and residues in the protective layer 3 resulting from the laser drilling process may be removed by a descumming or etching process.

[0115] After forming the stack structure D, the plurality of dies 1 within the stack structure D can be tested using the test structure 42 to analyze whether the plurality of dies 1 within the stack structure D include the second die 1 b. If the plurality of dies 1 within the stack structure D include at least one second die 1 b, the second die 1 b needs to be removed. For example, if the second die 1 b is a defective die, the second die 1 b within the stack structure D needs to be removed to ensure normal operation of the chip package structure 10.

[0116] It is difficult to remove the second die 1b in the stacking structure D. In addition, other die 1 in the stacking structure D may be damaged during the removal process, causing other die 1 to malfunction.

[0117] Based on this, in some embodiments, please continue to refer to Figure 5 The chip packaging structure 10 further includes a plurality of first filling blocks 51 , one first filling block 51 being located on a side of an interconnection structure 41 away from the stacking structure D, and the first filling block 51 penetrating the protective layer 3 along the stacking direction.

[0118] Because the first filler blocks 51 are located within the protective layer 3, before forming the first filler blocks 51 within the protective layer 3, it is necessary to open a first opening 31 within the protective layer 3 for receiving the first filler blocks 51. Since the first filler blocks 51 penetrate the protective layer 3 along the stacking direction, the first opening 31 also penetrates the protective layer 3 along the stacking direction. Furthermore, since one first filler block 51 is located on the side of one interconnect structure 41 away from the stacking structure D, one first opening 31 is also located on the side of one interconnect structure 41 away from the stacking structure D.

[0119] That is, before the first filling block 51 is formed in the first opening 31 , the first opening 31 penetrates the protective layer 3 along the stacking direction, and a first opening 31 is located on a side of an interconnection structure 41 away from the stacking structure D, which can expose the interconnection structure 41 located in the wiring layer 4 .

[0120] like Figure 6 、 Figure 7 and Figure 8 As shown, Figure 6 and Figure 8 Both Figure 2B A structural diagram of the AA region of the chip package structure 10, Figure 7 for Figure 6 FIG3 is a planar structural diagram of the wiring layer 4 in the stack structure D. When the plurality of dies 1 in the stack structure D include at least one second die 1b (for example, the second die 1b includes a defective die 1), the interconnect structure 41 connected to the second die 1b can be disconnected via the first opening 31, that is, the connection between the second die 1b and the other dies 1 in the stack structure D (for example, the first die 1a) is disconnected, so that the second die 1b is isolated. In this way, the second die 1b in the stack structure D does not need to be removed, the operation is less difficult, and damage to the other dies 1 in the stack structure D (for example, the first die 1a (i.e., the qualified die)) can be avoided.

[0121] It is understandable that if Figure 6 As shown, since the interconnection structure 41 connected to the second die 1 b is disconnected via the first opening 31 , the disconnected region of the interconnection structure 41 overlaps with the first opening 31 in the stacking direction, and an overlapping region mm exists.

[0122] like Figure 8 As shown, since the first filling block 51 is formed in the first opening 31 , the disconnected region of the interconnection structure 41 and the first filling block 51 also overlap in the stacking direction, and an overlapping region mm exists.

[0123] For example, please refer to Figure 8The end of the first filling block 51 away from the wiring layer 4 is the first end 51 a of the first filling block 51 , and the end of the first filling block 51 close to the wiring layer 4 is the second end 51 b of the first filling block 51 .

[0124] The area of ​​one end of the first filling block 51 close to the wiring layer 4 (ie, the second end 51 b of the first filling block 51 ) is greater than or equal to the area of ​​the disconnected region of the interconnection structure 41 .

[0125] For example, Figure 8 As shown, when the area of ​​one end of the first filling block 51 close to the wiring layer 4 (i.e., the second end 51b of the first filling block 51) is larger than the area of ​​the region where the interconnection structure 41 is broken, in the stacking direction, the area of ​​the overlapping region mm of the region where the interconnection structure 41 is broken and the first filling block 51 is smaller than the area of ​​one end of the first filling block 51 close to the wiring layer 4 (i.e., the second end 51b of the first filling block 51).

[0126] For another example, when the area of ​​one end of the first filling block 51 close to the wiring layer 4 (i.e., the second end 51b of the first filling block 51) is equal to the area of ​​the region where the interconnection structure 41 is broken, in the stacking direction, the area of ​​the overlapping region mm of the region where the interconnection structure 41 is broken and the first filling block 51 is equal to the area of ​​one end of the first filling block 51 close to the wiring layer 4 (i.e., the second end 51b of the first filling block 51).

[0127] For example, please refer to Figure 8 The area of ​​one end of the first filling block 51 close to the wiring layer 4 (ie, the second end 51b of the first filling block 51) is smaller than the area of ​​one end of the first filling block 51 away from the wiring layer (ie, the first end 51a of the first filling block 51).

[0128] For example, the first opening 31 may be formed in the protective layer 3 by a laser drilling process, and residues in the protective layer 3 resulting from the laser drilling process may be removed by a descumming or etching process.

[0129] For example, please refer to Figure 5 The first opening 31 exposes the interconnection structure 41 located in the wiring layer 4 , and the first opening 31 may expose the first conductive pad 411 of the interconnection structure 41 .

[0130] The aforementioned “disconnecting the interconnection structure 41 connected to the second die 1 b via the first opening 31 ” may specifically be disconnecting the first conductive pad 411 of the interconnection structure 41 connected to the second die 1 b via the first opening 31 .

[0131] For example, the interconnection structure 41 connected to the second die 1 b (eg, the second die 1 b includes the defective die 1 ) may be disconnected by a laser fusing process.

[0132] For example, when the first opening 31 exposes the first conductive pad 411 of the interconnect structure 41, the first conductive pad 411 of the interconnect structure 41 connected to the second die 1b can be disconnected by a laser melting process. The disconnected first conductive pad 411 has a laser melting mark.

[0133] The “laser melting mark” may be, for example, a darker color in the area adjacent to the disconnected portion of the first conductive pad 411 than in other areas of the first conductive pad 411. The “laser melting mark” may also be a curled state in the area adjacent to the disconnected portion of the first conductive pad 411.

[0134] In some embodiments, as Figure 9 As shown, Figure 9 FIG1 is a structural diagram of a local region of a chip package structure 10 provided according to some embodiments of the present disclosure. The chip package structure 10 further includes an encapsulation layer 6. The encapsulation layer 6 covers the stacking structure D, the wiring layer 4, and the protective layer 3. On the one hand, the encapsulation layer 6 can increase the strength of the chip package structure 10. On the other hand, the encapsulation layer 6 can also protect the stacking structure D, the wiring layer 4, and the protective layer 3 within the chip package structure 10, thereby protecting the stacking structure D, the wiring layer 4, and the protective layer 3 from the external environment (such as moisture, temperature, and contamination).

[0135] Illustratively, the encapsulation layer 6 may include epoxy resin, an expanding monomer, and a curing agent.

[0136] In some embodiments, please refer to Figure 9 Part of the material of the encapsulation layer 6 forms the first filling block 51 and the second filling block 52 , that is, the material used to form the encapsulation layer 6 is the same as the material used to form the first filling block 51 and the second filling block 52 .

[0137] Exemplarily, the encapsulation layer 6 , the first filling block 51 , and the second filling block 52 may be an integrated structure.

[0138] It should be noted that the above-mentioned "integrated structure" does not mean that the encapsulation layer 6 and the first filling block 51, and the encapsulation layer 6 and the second filling block 52 are simply in contact with each other, but rather means that the encapsulation layer 6 and the first filling block 51, and the encapsulation layer 6 and the second filling block 52 are formed integrally (or continuously) with each other through the same process using the same material.

[0139] By forming the encapsulation layer 6 and the first filler block 51, as well as the encapsulation layer 6 and the second filler block 52 integrally (or continuously) with each other using the same material through the same process, that is, forming the first filler block 51 and the second filler block 52 simultaneously with the encapsulation layer 6, the manufacturing process of the chip packaging structure 10 can be simplified, thereby improving the manufacturing efficiency of the chip packaging structure 10.

[0140] The following is a detailed description of the method for preparing the chip packaging structure 10 .

[0141] like Figure 10 As shown, Figure 10 Flowchart of a method for preparing a chip package structure 10 according to some embodiments. The method for preparing the chip package structure 10 includes the following steps:

[0142] S1: If Figure 11 As shown, Figure 11 Based on Figure 10 The structure diagram corresponding to step S1 in the method for preparing the chip package structure 10 is provided. A plurality of bare chips 1 are stacked to form a stacked structure D.

[0143] S2: If Figure 12 As shown, Figure 12 Based on Figure 10 The structure diagram corresponding to step S2 and step S7 in the manufacturing method of the provided chip packaging structure 10. A wiring layer 4 is formed on one side of the stacking structure D.

[0144] like Figure 13 As shown, Figure 13 for Figure 12 A structural diagram of the BB region in FIG. A plurality of interconnect structures 41 are formed in the wiring layer 4 . Any two dies 1 in the stacking structure D are connected to each other via at least one interconnect structure 41 .

[0145] S7: Please continue reading Figure 12 and Figure 13 , a test structure 42 is formed in the wiring layer 4 . The test structure 42 is connected to at least one bare die 1 .

[0146] S3: If Figure 14 As shown, Figure 14 Based on Figure 10 The structure diagram corresponding to step S3, step S4 and step S8 in the method for manufacturing the chip packaging structure 10 is provided. A protection layer 3 is formed on a side of the wiring layer 4 away from the stacking structure D.

[0147] S4: As Figure 15 As shown, Figure 15 for Figure 14 A plurality of first openings 31 are formed in the protective layer 3. One first opening 31 is located on a side of an interconnection structure 41 away from the stacking structure D, and the first opening 31 penetrates the protective layer 3 along the stacking direction.

[0148] S8: Please continue reading Figure 14 and Figure 15, a second opening 32 is formed in the protective layer 3. The second opening 32 is located on a side of the test structure 42 away from the stacking structure D, and the second opening 32 penetrates the protective layer 3 along the stacking direction.

[0149] S5: Detect the plurality of dies 1 in the stack structure D.

[0150] Based on forming the test structure 42 in the wiring layer 4 , the above-mentioned step S5 includes step S51 .

[0151] S51 : testing the die 1 connected to the test structure 42 through the second opening 32 and the test structure 42 .

[0152] S6: As Figure 16 As shown, Figure 16 Based on Figure 10 The structure diagram corresponding to step S6 in the method for preparing the chip package structure 10 is provided. Based on the presence of a defective die 1 in the stacking structure D, the interconnection structure 41 connected to the defective die 1 is disconnected through the first opening 31 .

[0153] By forming multiple first openings 31 in the protective layer 3, and making one first opening 31 located on a side of an interconnection structure 41 away from the stacking structure D, and the first opening 31 penetrating the protective layer 3 along the stacking direction, when there is a defective die 1 in the stacking structure D, the interconnection structure 41 connected to the defective die 1 is disconnected through the first opening 31, that is, the connection between the defective die 1 and other die 1 in the stacking structure D (for example, qualified die 1) is disconnected, so that the defective die 1 is isolated. In this way, there is no need to remove the defective die 1 in the stacking structure D, the operation is less difficult, and damage to other die 1 in the stacking structure D (for example, qualified die 1) can be avoided.

[0154] Exemplarily, the above-mentioned steps S4 and S8 can be performed simultaneously in the same process, that is, the first opening 31 can be compatible with the formation process of the second opening 32, which is beneficial to simplify the preparation steps of the chip packaging structure 10 and reduce the preparation cost of the chip packaging structure 10.

[0155] For example, please refer to Figure 16 The interconnect structure 41 includes a first conductive pad 411 and at least two connection structures 412. One end of the connection structure 412 is connected to the first conductive pad 411, and the other end is connected to different dies 1 in the stack structure D.

[0156] For example, the interconnection structure 41 connected to the defective die 1 may be disconnected by a laser fusing process.

[0157] For example, the first conductive pad 411 of the interconnect structure 41 connected to the defective die 1 may be disconnected by a laser fusing process.

[0158] When the interconnection structure 41 connected to the defective bare chip 1 is disconnected by the laser fusing process, no additional mask is required, the operation is simple, and the manufacturing cost of the chip packaging structure 10 is reduced.

[0159] In some embodiments, please refer to Figure 10 The method for preparing the chip packaging structure 10 further includes the following steps:

[0160] S9: As Figure 17 As shown, Figure 17 Based on Figure 10 The structure diagram corresponding to step S9 in the method for preparing the chip packaging structure 10 is provided. The packaging layer 6 is formed, and the packaging layer 6 covers the stacking structure D, the wiring layer 4 and the protection layer 3.

[0161] Part of the material of the encapsulation layer 6 fills the first opening 31 to form a first filling block 51 , and fills the second opening 32 to form a second filling block 52 .

[0162] That is to say, the first filling block 51 and the second filling block 52 are formed at the same time as the encapsulation layer 6 is formed. The encapsulation layer 6, the first filling block 51 and the second filling block 52 can be formed under the same process, which is conducive to simplifying the preparation steps of the chip packaging structure 10 and reducing the preparation cost of the chip packaging structure 10.

[0163] Illustratively, the process of forming the encapsulation layer 6 may be one of a compression molding process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process.

[0164] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A stacked structure comprising a plurality of dies arranged in a stack; a wiring layer, located on one side of the stack structure; A plurality of interconnect structures are provided in the wiring layer, and any two bare chips in the stacked structure are connected to each other via at least one of the interconnect structures; a protective layer, located on a side of the wiring layer away from the stacking structure; A plurality of first filling blocks are provided, one of the first filling blocks is located on a side of the interconnection structure away from the stacking structure, and the first filling block penetrates the protection layer along the stacking direction.

2. The chip packaging structure according to claim 1, wherein: the plurality of dies including at least one first die and at least one second die; The interconnect structure connected to the second bare chip is disconnected, and along the stacking direction, an area where the interconnect structure is disconnected overlaps with a first filling block located on one side of the interconnect structure.

3. The chip packaging structure according to claim 2, wherein: The second die comprises a defective die, and the first die comprises a qualified die.

4. The chip packaging structure according to claim 2, wherein: The interconnect structure includes a first conductive pad and at least two connection structures, one end of each of the at least two connection structures is connected to the first conductive pad, and the other ends of the at least two connection structures are respectively connected to different bare chips; The first conductive pad of the interconnect structure connected to the second die is disconnected.

5. The chip packaging structure according to claim 4, wherein: The first conductive pad of the interconnect structure connected to the second die has a laser fuse trace.

6. The chip packaging structure according to claim 2, wherein: The area of ​​the first filling block close to one end of the wiring layer is greater than or equal to the area of ​​the region where the interconnection structure is disconnected.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: An area of ​​one end of the first filling block close to the wiring layer is smaller than an area of ​​one end of the first filling block away from the wiring layer.

8. The chip packaging structure according to any one of claims 1 to 6, wherein: Also includes: a test structure located in the wiring layer, the test structure being connected to at least one of the bare chips; The second filling block is located at a side of the test structure away from the stacking structure, and the second filling block penetrates the protection layer along the stacking direction.

9. The chip packaging structure according to claim 8, wherein: Also included is a packaging layer covering the stacked structure, the wiring layer and the protective layer; Part of the material of the encapsulation layer forms the first filling block and the second filling block.

10. A method for preparing a chip packaging structure, characterized in that: include: Stacking multiple bare chips to form a stacked structure; forming a wiring layer on one side of the stack structure; A plurality of interconnect structures are formed in the wiring layer, and any two bare chips in the stacked structure are connected to each other via at least one of the interconnect structures; forming a protective layer on a side of the wiring layer away from the stack structure; forming a plurality of first openings in the protective layer, wherein one of the first openings is located on a side of the interconnect structure away from the stacking structure, and the first opening penetrates the protective layer along the stacking direction; detecting the plurality of dies in the stacked structure; Based on the presence of a defective die in the stacked structure, the interconnection structure connected to the defective die is disconnected through the first opening.

11. The method for preparing a chip packaging structure according to claim 10, wherein: The interconnection structure connected to the defective die is disconnected by a laser fusing process.

12. The method for preparing a chip packaging structure according to claim 10 or 11, characterized in that: Also includes: forming a test structure in the wiring layer, wherein the test structure is connected to at least one of the bare chips; forming a second opening in the protective layer, the second opening being located on a side of the test structure away from the stacking structure, and the second opening penetrating the protective layer along the stacking direction; The detecting the plurality of dies in the stacked structure comprises: The die connected to the test structure is inspected through the test structure via the second opening.

13. The method for preparing a chip packaging structure according to claim 12, wherein: Also includes: forming a packaging layer, wherein the packaging layer covers the stacked structure, the wiring layer, and the protective layer; Part of the material of the encapsulation layer fills the first opening to form a first filling block, and fills the second opening to form a second filling block.

14. The method for preparing a chip packaging structure according to claim 10 or 11, characterized in that: The interconnect structure includes a first conductive pad and at least two connection structures; one end of the connection structure is connected to the first conductive pad, and the other end is connected to different dies in the stack structure; The method of disconnecting an internal circuit of an interconnect structure connected to the defective die comprises: A first conductive pad of the interconnect structure connected to the defective die is disconnected.

15. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 9; The controller is connected to the chip packaging structure.

16. An electronic device, characterized in that: include: A processor, and the storage system according to claim 15, wherein the processor is coupled to the storage system.

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