Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment, and the preparation method of the semiconductor structure comprises the steps: forming a first electrode, a second electrode and a through hole which penetrates through the first electrode and the second electrode on a substrate; performing oxidation treatment on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole; forming a metal oxide channel layer in the through hole; wherein the first electrode and the second electrode are made of metal, the end face of the first electrode and the end face of the second electrode comprise metal oxide which forms the metal through oxidation treatment, and ohmic contact is formed between the metal oxide channel layer and the metal oxide. According to the invention, the contact resistance between the metal oxide channel layer and the electrode can be effectively reduced, and meanwhile, an additional patterning process is not added.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, so as to reduce the contact resistance between the channel layer and the electrode while simplifying the manufacturing process.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a stacked first electrode, a dielectric layer, and a second electrode on the substrate, and a through hole that sequentially penetrates the second electrode and the dielectric layer toward the substrate and extends at least to the upper surface of the first electrode;

[0008] performing oxidation treatment on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole;

[0009] forming a metal oxide channel layer in the through hole;

[0010] The materials of the first electrode and the second electrode include metal, the end surfaces of the first electrode and the second electrode include metal oxide containing the metal formed by oxidation treatment, and an ohmic contact is formed between the metal oxide channel layer and the metal oxide.

[0011] In some embodiments, the end surface of the first electrode and the end surface of the second electrode are oxidized using a plasma process containing O2 or O3 gas.

[0012] In some embodiments, the oxidation treatment of the end surface of the first electrode and the end surface of the second electrode exposed by the through hole includes:

[0013] While the metal oxide channel layer is being formed, an oxidation treatment is performed on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole.

[0014] In some embodiments, forming the first initial electrode and the second initial electrode on the substrate includes:

[0015] forming a first initial electrode made of indium and / or tin on the substrate;

[0016] forming a second initial electrode made of indium and / or tin on the substrate;

[0017] The end surface of the first electrode and the end surface of the second electrode are made of metal oxide containing indium and / or tin.

[0018] In some embodiments, forming a metal oxide channel layer in the through hole includes:

[0019] A metal oxide channel layer containing at least one of indium, gallium, zinc and tin is formed in the through hole.

[0020] An embodiment of the present application provides a semiconductor structure, including:

[0021] substrate;

[0022] a first electrode, a second electrode, and a dielectric layer structure, wherein the first electrode is located on the substrate, the second electrode is stacked with the first electrode and spaced apart in a direction perpendicular to the substrate, and the dielectric layer structure includes a dielectric layer located between the first electrode and the second electrode and a dielectric layer located above the second electrode;

[0023] a through hole, penetrating the second electrode and each of the dielectric layers and extending at least to the upper surface of the first electrode;

[0024] a metal oxide channel layer, located in the through hole and contacting end surfaces of the first electrode and the second electrode exposed in the through hole;

[0025] The material of the first electrode and the second electrode comprises metal, the end surface of the first electrode and the end surface of the second electrode comprise metal oxide of the metal, and there is ohmic contact between the metal oxide channel layer and the metal oxide.

[0026] In some embodiments, the metal material of the metal oxide channel layer is selected from one or more of indium, gallium, zinc, and tin.

[0027] In some embodiments, the material of the first electrode and the second electrode includes at least one of indium and tin.

[0028] In some embodiments, the semiconductor structure includes a read transistor and a write transistor stacked on the substrate, and at least one of the read transistor and the write transistor includes the first electrode, the second electrode, and the metal oxide channel layer.

[0029] In some embodiments, the through holes have the same aperture in different regions perpendicular to the substrate.

[0030] In some embodiments, the oxygen concentration of the metal oxide channel layer in the region contacting the end surfaces of the first electrode and the second electrode is consistent with the oxygen concentration of the channel region between the first electrode and the second electrode.

[0031] An electronic device includes the semiconductor structure as described above.

[0032] The preparation method of the above-mentioned semiconductor structure of the present application can directly oxidize the end portions of the first electrode and / or the second electrode exposed in the through hole. The formed metal oxide forms an ohmic contact when in contact with the metal oxide channel layer, which reduces the contact resistance without requiring additional photolithography and etching processes, thereby effectively reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0035] Figures 2 to 13 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a semiconductor structure provided in one embodiment. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, first, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In one embodiment, see Figure 1 , provides a method for preparing a semiconductor structure, comprising the following steps:

[0042] Step S10, providing a substrate 100;

[0043] Step S20, see Figure 2 A first initial electrode 2101, a second initial electrode 2201, and a dielectric material layer structure 3101 are formed on a substrate 100. The second initial electrode 2201 is stacked with the first initial electrode 2101 and spaced apart in a direction perpendicular to the substrate. The dielectric material layer structure 3101 is at least located between the first initial electrode 2101 and the second initial electrode 2201 and above the second initial electrode 2201. The dielectric material layer structure 3101 may include multiple layers, including at least a dielectric layer located between the first initial electrode 2101 and the second initial electrode 2201, and a dielectric layer located above the second initial electrode 2201.

[0044] Step S30, see Figure 3 , etching is performed from the dielectric material layer structure 3101 away from the top surface of the substrate toward the substrate 100 to form a through hole 10 that penetrates the second initial electrode 220, penetrates each of the dielectric layers, and extends at least to the upper surface of the first initial electrode 210, and forms the first electrode 210, the second electrode 220, and the dielectric layer structure 310;

[0045] Step S40, see Figure 7 , performing oxidation treatment on the end surface of the first electrode 210 and the end surface of the second electrode 220 exposed by the through hole 10;

[0046] In which, the material of the first electrode and the second electrode includes metal, and the end surface of the first electrode and the end surface of the second electrode include a metal oxide containing the metal formed by the oxidation treatment; and a metal oxide channel layer 511, a gate dielectric layer 512 and a gate electrode 513 are formed in the through hole 10, which at least cover the side walls and bottom of the through hole and are stacked in sequence, and the metal oxide channel layer 511 contacts the oxidized end surface of the first electrode 210 and / or the oxidized end surface of the second electrode 220.

[0047] An ohmic contact is formed between the metal oxide channel layer and the metal oxide.

[0048] In some embodiments, the end surface of the first electrode and the end surface of the second electrode are made of metal oxide containing indium and / or tin.

[0049] In some embodiments, forming a metal oxide channel layer in the through hole includes forming a metal oxide channel layer containing at least one of indium, gallium, zinc, and tin in the through hole.

[0050] For example, the first electrode and the second electrode are indium metal, and the end surface of the indium metal exposed in the through hole is oxidized to indium oxide. The metal oxide channel layer can be IGZO, and the contact between IGZO and indium oxide is an ohmic contact.

[0051] In step S10, the base 100 may include a semiconductor substrate. The semiconductor substrate may be a single-layer structure or a multi-layer structure. For example, the semiconductor substrate may include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the semiconductor substrate may also include a semiconductor substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of semiconductor substrate should not limit the scope of protection of this application.

[0052] In addition, as an example, the base 100 may further include other structures or film layers formed on the semiconductor substrate, which may be specifically configured according to actual needs.

[0053] In step S20, refer to Figure 2 The dielectric layer structure 310 includes multiple dielectric layers formed by different processes, such as a first dielectric layer, a second dielectric layer, and a third dielectric layer. Accordingly, as an example, the dielectric material layer structure 3101 before forming the through-hole may include a first dielectric material layer, a second dielectric material layer, and a third dielectric material layer. A first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer, and a third dielectric layer are alternately formed on the substrate. The first conductive layer is patterned to form a first initial electrode, and the second conductive layer is patterned to form a second initial electrode.

[0054] The material of the first initial electrode 2101 and / or the material of the second initial electrode 2201 is a material that forms an ohmic contact with the metal oxide channel layer after oxidation, for example, indium (In) or tin (Sn), or a metal material containing both In and Sn, which can be oxidized to form a transparent conductive layer.

[0055] Generally, the end faces of the first electrode and the second electrode are oxidized to indium oxide or indium tin oxide. When the end faces are oxidized to a certain extent, the oxygen in the indium oxide or indium tin oxide is relatively saturated, and the oxygen in the metal oxide channel layer serving as the channel layer is difficult to be absorbed by the indium oxide or indium tin oxide. The oxygen concentration of the metal oxide channel layer in the area in contact with the end faces of the first electrode and the second electrode is consistent with the oxygen concentration in the channel area between the first electrode and the second electrode.

[0056] The first initial electrode 2101 and the second initial electrode 2201 may be made of the same material or different materials.

[0057] In step S30, refer to Figure 3 After forming the stacked structure comprising the first initial electrode 2101, the second initial electrode 2201, and the dielectric material layer structure 3101, the stacked structure can be dry-etched perpendicular to the substrate to form a through-hole. The through-hole 10 can extend at least to the upper surface of the first initial electrode 2101. Generally, the through-hole 10 formed by dry etching (anisotropic etching) has a substantially uniform aperture in a direction perpendicular to the substrate.

[0058] While forming the through hole, the first initial electrode 2101 remaining after etching forms the first electrode 210 ; and the second initial electrode 2201 remaining after etching forms the second electrode 220 .

[0059] The first electrode 210 and the second electrode 220 may each include an upper surface and a lower surface parallel to the substrate, and an end surface exposed by the through hole. One of the first electrode 210 and the second electrode 220 serves as the source of the transistor, and the other serves as the drain of the transistor. The first electrode 210 and the second electrode 220 are insulated and isolated by a dielectric layer structure 310.

[0060] The end surface of the second electrode 220 is arranged in a ring shape. The end surface of the first electrode 220 penetrated by the through hole is arranged in a ring shape.

[0061] As an example, the through hole 10 can be etched downward to the inside of the first electrode 210 without penetrating the first electrode 210, thereby increasing the oxidized area of ​​the first electrode 210. In this example, the oxidized area of ​​the first electrode 210 includes not only the end surface of the through hole side wall, but also the upper surface of the first electrode 210 exposed at the bottom of the through hole, thereby increasing the contact area between the first electrode and the metal oxide channel layer 511, thereby reducing the contact resistance between the first electrode 210 and the metal oxide channel layer 511.

[0062] As an example, the through hole 10 may penetrate the first electrode 210 to expose the substrate. In this case, only the end surface of the first electrode 210 contacts the metal oxide channel layer 511, and the end surface is arranged in a ring shape.

[0063] In step S40, refer to Figure 7 After the through hole is formed by etching, the hole wall does not need to be etched back. The end surface of the first electrode 210 and the end surface of the second electrode 220 exposed by the through hole 10 can be directly oxidized at the same time. The oxidized end surfaces of the first and second electrodes are the contact areas between the first and second electrodes and the metal oxide channel layer 511.

[0064] In this case, no additional photolithography or etching process is required to form the contact region between the first electrode and / or the second electrode and the metal oxide semiconductor layer, thereby simplifying the process and forming the ohmic contact.

[0065] The metal oxide channel layer 511 contacts the oxidized end surfaces of the first electrode 210 and the second electrode 220. At this time, the metal oxide channel layer 511 and the first electrode 210 and the second electrode 220 form an ohmic contact, which can effectively increase the operating current of the transistor.

[0066] When forming the metal oxide channel layer 511 , a metal oxide channel layer containing at least one of indium, gallium, zinc, and tin may be formed in the through hole.

[0067] In this embodiment, by selecting In or Sn as the metal material for the first electrode 210 and / or the second electrode 220, and simultaneously oxidizing the surface of the first electrode 210 and / or the second electrode 220 through the through-hole to form a metal oxide, the metal oxide channel layer (e.g., IGZO, IZO, IGO, etc.) contacts the end surfaces of the metal oxide of the first electrode 210 and the second electrode 220. This effectively reduces the operating current of the transistor without requiring additional photolithography or etching processes.

[0068] In one embodiment, before forming the metal oxide channel layer 511 , the end surfaces of the first electrode 210 and the second electrode 220 exposed by the through hole 10 are subjected to oxidation treatment.

[0069] At this time, step S40 may include:

[0070] Step S41a, performing oxidation treatment on the first electrode 210 and the second electrode 220 through the through hole 10;

[0071] In step S42 a , a metal oxide channel layer, a gate dielectric layer, and a gate electrode are sequentially stacked in the through hole 10 .

[0072] In step S41a, when the material of the first electrode 210 and the material of the second electrode 220 are either indium or tin, the end surfaces of the two electrodes are oxidized to form indium oxide or indium tin oxide. For example, when the material of the first electrode 210 and the second electrode 220 is indium, tin can be introduced as a precursor during the oxygenation process, thereby forming indium tin oxide (ITO) only on the end surfaces of the first electrode 210 and the second electrode 220. No other material film containing indium or tin remains on other structural surfaces.

[0073] See also Figure 4 As an example, before forming the metal oxide channel layer, the first electrode 210 and the second electrode 220 are oxidized using a plasma process of an oxygen-containing gas to form oxidized end faces. The oxygen-containing gas includes an O2 and / or O3 plasma atmosphere.

[0074] Using plasma technology to oxidize the first and second electrodes 210 and 220 in an atmosphere including O2 and / or O3, the end surfaces of the first and second electrodes 210 and 220 are fully oxidized, resulting in good conductivity. The bulk of the first and second electrodes outside the end surfaces remains unoxidized. In this case, the oxidized end surfaces of the first and second electrodes 210 and 220 form good ohmic contact with the metal oxide channel layer 511, effectively reducing the contact resistance between the electrodes and the channel layer.

[0075] Of course, the process for oxidizing the end surface of the first electrode 210 and the end surface of the second electrode 220 is not limited to the plasma process. For example, thermal annealing can also be performed in an annealing device into which gases such as O2 and / or O3 are introduced, thereby oxidizing the end surface of the first electrode 210 and the end surface of the second electrode 220.

[0076] In step S42a, refer to Figure 5 , a metal oxide channel material layer 511a may be formed on the upper surface of the dielectric layer structure 310, the sidewall of the through hole 10, and the bottom of the through hole 10. Then, refer to Figure 6 A gate dielectric material layer 512a is formed on the surface of the metal oxide channel material layer 511a. Then, a gate electrode material layer 513a is formed on the surface of the gate dielectric material layer 512a. The gate electrode material layer 513a can fill the remaining space of the through hole 10.

[0077] The metal oxide channel material layer 511a, the gate dielectric material layer 512a, and the gate electrode material layer 513a can be formed by a deposition process. The deposition process may include, but is not limited to, atomic layer deposition (ALD). The material of the metal oxide channel material layer 511a may include, but is not limited to, indium gallium zinc oxide (IGZO). The material of the gate dielectric material layer 512a may include, but is not limited to, a high-k material (such as HfO2, Al2O3, etc.). The material of the gate electrode material layer 513a may include, but is not limited to, a metal material such as TiN and IZO.

[0078] Afterwards, as an example, according to the requirements of the embodiment, please refer to Figure 7 , part or all of the gate electrode material layer 513a, gate dielectric material layer 512a, and metal oxide channel material layer located outside the through hole 10 can be removed through processes such as photolithography and etching to form the gate electrode 513, gate dielectric layer 512, and metal oxide channel layer 511, respectively. In some embodiments, the metal oxide channel layer 511 can extend from the through hole 10 to the upper surface of the dielectric layer structure 310, and the gate electrode 513 can be T-shaped, thereby increasing the contact area between the gate electrode 513 and the first electrode 210 and reducing the contact resistance therebetween.

[0079] As another example, the gate electrode material layer 513a, the gate dielectric material layer 512a, and the first channel material layer outside the through hole 10 can also be completely removed by a CMP process to form the gate electrode 513, the gate dielectric layer 512, and the first channel layer. In this case, the gate electrode 513, the gate dielectric layer 512, and the metal oxide channel layer 511 can be located only within the through hole 10.

[0080] In this embodiment, before forming the metal oxide channel layer 511, the first electrode 210 and the second electrode 220 are oxidized. This allows the end surfaces of the first electrode 210 and the second electrode 220 to be fully oxidized, resulting in good conductivity. This process also provides greater controllability, resulting in more uniform performance of the resulting device. Furthermore, this process does not affect transistor fabrication.

[0081] In one embodiment, step S40 includes:

[0082] In step S41b, a metal oxide channel material layer 511a is formed on the upper surface of the dielectric layer structure 310, the sidewalls of the through hole 10 and the bottom of the through hole 10. During the formation of the metal oxide channel material layer 511a, the surfaces of the first electrode 210 and the second electrode 220 are oxidized.

[0083] Afterwards, you can also include:

[0084] Step S42b, forming a gate dielectric material on the surface of the metal oxide channel material layer 511a, and forming a gate electrode material layer 513a on the surface of the gate dielectric material layer 512a;

[0085] In step S43b, at least a portion of the gate electrode material layer 513a, the gate dielectric material layer 512a, and the first channel material layer outside the through hole 10 is removed to form a gate electrode 513, a gate dielectric layer 512, and a first channel layer, respectively.

[0086] In step S41b, a metal oxide channel material layer 511a can be formed using a process such as atomic layer deposition (ALD). During the formation of the metal oxide channel material layer 511a, oxygen gas needs to be introduced. During the formation of the metal oxide channel material layer 511a, the surfaces of the first electrode 210 and the second electrode 220 can be oxidized.

[0087] It can be understood that at this time, the material of the first electrode 210 and the material of the second electrode 220 are both metal materials that can be oxidized to form transparent conductive materials.

[0088] In step S42b, a gate dielectric material layer 512a may be formed on the surface of the metal oxide channel material layer 511a by a deposition process such as ALD. Thereafter, a gate electrode material layer 513a may be formed on the surface of the gate dielectric material layer 512a. The gate electrode material layer 513a may fill the remaining space of the through hole 10.

[0089] In step S43b, as an example, portions of the gate electrode material layer 513a, the gate dielectric material layer 512a, and the metal oxide channel material layer outside the through hole 10 can be removed by photolithography, etching, or other processes to form the gate electrode 513, the gate dielectric layer 512, and the metal oxide channel layer 511. In this case, the metal oxide channel layer 511 can extend from the through hole 10 to the upper surface of the dielectric layer structure 310, and the gate electrode 513 can be T-shaped.

[0090] As another example, the gate electrode material layer 513a, the gate dielectric material layer 512a, and the first channel material layer outside the through hole 10 can be completely removed by a CMP process, etc., to form the gate electrode 513, the gate dielectric layer 512, and the first channel layer. In this case, the gate electrode 513, the gate dielectric layer 512, and the metal oxide channel layer 511 can be located only within the through hole 10.

[0091] In this embodiment, during the process of forming the metal oxide channel material layer 511 a , the end surface of the first electrode 210 and the end surface of the second electrode 220 are oxidized, thereby effectively simplifying the process.

[0092] In one embodiment, the semiconductor structure may include a transistor, which may be a read transistor or a write transistor. In some embodiments, a read transistor 510 a and a write transistor 510 b of a memory cell are sequentially stacked on a substrate according to the above method, and the first electrode 210 of the write transistor 510 b is formed on the surface of the gate electrode 513 of the read transistor 510 a, and the two are electrically connected.

[0093] After providing the substrate in step S10, refer to Figures 2 to 7 , performing the above steps S20 to S40 on the substrate to form a read transistor 510a. Then, refer to Figures 8 to 13 , and then above the formed read transistor 510a, steps S20 to S40 are performed again to form a write transistor 510b.

[0094] As an example, see Figure 8 When forming the write transistor 510b, a first initial electrode 2101 of the write transistor 510b can be formed on the gate electrode 513 of the read transistor 510a through deposition, photolithography, etching, and other processes. A fourth dielectric material layer is then formed to cover the first initial electrode 2101 of the write transistor 510b and its exposed structure. A second initial electrode 2201 of the write transistor 510b is then formed on the fourth dielectric material layer through deposition, photolithography, etching, and other processes. Finally, a fifth dielectric material layer is formed to cover the second initial electrode 2201 of the write transistor 510b and the fourth dielectric material layer.

[0095] At this time, the dielectric material layer structure 3101 when forming the write transistor 510 b includes a fourth dielectric material layer and a fifth dielectric material layer.

[0096] Afterwards, see Figure 9 The first trench 10 of the write transistor 510b can be formed by processes such as photolithography and etching. Simultaneously, the first electrode 210 and the second electrode 220 of the write transistor and the dielectric layer structure 310 are formed. When the dielectric material layer structure 3101 includes a fourth dielectric material layer and a fifth dielectric material layer, the fourth dielectric material layer and the fifth dielectric material layer remaining after etching form the fourth dielectric layer and the fifth dielectric layer, respectively.

[0097] Then, see Figure 10 , the end surface of the first electrode 210 and / or the end surface of the second electrode 220 exposed by the first trench 10 of the write transistor 510b can be oxidized by plasma technology. Then, refer to Figure 11 Then, a metal oxide channel material layer 511a is formed on the upper surface of the dielectric layer structure 310 of the write transistor, the sidewall of the first trench 10, and the bottom of the first trench 10 by a deposition process such as ALD. Figure 12A gate dielectric material layer 512a is formed on the surface of the metal oxide channel material layer 511a through deposition processes such as ALD, and a gate electrode material layer 513a is formed on the surface of the gate dielectric material layer 512a. The gate electrode material layer 513a can fill the remaining space of the first trench 10.

[0098] Then, see Figure 13 At least part of the gate electrode material layer 513a, the gate dielectric material layer 512a and the metal oxide channel material layer 511a outside the first trench 10 may be removed to form a gate electrode 513, a gate dielectric layer 512 and a metal oxide channel layer 511, respectively.

[0099] At this time, the metal oxide channel layer 511 of the write transistor 510b can extend from the first trench 10 to the upper surface of the dielectric layer structure 310, and the gate electrode 513 of the write transistor 510b can be T-shaped. The write transistor 510b can also be located only in the first trench 10.

[0100] In this embodiment, the write transistor 510b and the read transistor 510a can form a memory cell with a 2TOC architecture. In this case, the contact resistance between the electrodes and the channels of the write and read transistors can be effectively reduced, thereby effectively improving the performance of the memory cell.

[0101] In one embodiment, before forming the write transistor 510b, the method further includes:

[0102] Step S60, see Figure 8 A first conductive via structure 610 extending to the first electrode 210 and the second electrode 220 is formed in the dielectric layer structure 310 of the read transistor 510 a .

[0103] The material of the first conductive via structure 610 may include, but is not limited to, metal material.

[0104] When the metal oxide channel layer 511 of the transistor (such as the read transistor 510 a and / or the write transistor 510 b ) extends from the through hole 10 to the upper surface of the dielectric layer structure 310 , and the gate electrode 513 is T-shaped, the preparation process of the read transistor 510 a and / or the write transistor 510 b , after step S40 , further includes:

[0105] Step S50, see Figure 7 or Figure 13 , forming a first filling dielectric layer 320 covering the dielectric layer structure 310 and exposing the upper surface of the gate electrode 513 .

[0106] At this time, see Figure 8When forming the first conductive via structure 610 in step S60, the first filling dielectric layer 320 and the dielectric layer structure 310 of the read transistor 510a can be sequentially etched to form a first via. The first conductive via structure 610 is then formed within the first via. The first conductive via structure 610 penetrates the first filling dielectric layer 320 of the read transistor 510a and extends to the first electrode 210 and the second electrode 220.

[0107] Of course, when the gate electrode 513, the gate dielectric layer 512, and the metal oxide channel layer 511 are only located within the through hole 10, the upper surface of the gate electrode 513 is flush or nearly flush with the upper surface of the dielectric layer structure 310. In this case, the dielectric layer structure 310 can be directly etched to form the first conductive through hole structure 610.

[0108] Also, see Figure 8 , while forming the first initial electrode 2101 of the write transistor 510b, the connecting electrode 400 is also formed. At this time, a first conductive material layer can be formed on the entire surface, and then the first conductive material layer can be patterned by photolithography, etching, or other processes to form the first initial electrode 2101 of the write transistor 510b and the connecting electrode 400.

[0109] The connecting electrode 400 covers the first conductive via structure 610 , thereby electrically connecting the first electrode 210 and the second electrode 220 of the read transistor 510 a , and further being used for source / drain signal transmission of the read transistor 510 a .

[0110] In one embodiment, see Figure 13 , after forming the write transistor 510b, further comprising:

[0111] Step S70 , forming a first electrode 210 extending to the write transistor 510 b , a second electrode 220 of the write transistor 510 b , and a second conductive via structure 620 connected to the electrode 400 in the dielectric layer structure 310 of the write transistor 510 b ;

[0112] In step S80 , a wiring layer 700 is formed on the second conductive via structure 620 and the gate electrode 513 of the write transistor 510 b .

[0113] In step S70 , the material of the second conductive via structure 620 may include, but is not limited to, a metal material.

[0114] When the metal oxide channel layer 511 of the write transistor 510b extends from the first trench 10 to the upper surface of the dielectric layer structure 310 of the write transistor, and the gate electrode 513 of the write transistor 510b is T-shaped, a first filling dielectric layer 320 is also provided on the dielectric layer structure 310 of the write transistor 510b, exposing the upper surface of the gate electrode 513. At this point, the first filling dielectric layer 320 of the write transistor 510b and the dielectric layer structure 310 of the write transistor can be sequentially etched to form a second through hole. A second conductive through hole structure 620 is then formed within the second through hole. The second conductive through hole structure 620 penetrates the first filling dielectric layer 320 of the write transistor 510b and extends to the first electrode 210 of the write transistor 510b, the second electrode 220 of the write transistor 510b, and the connecting electrode 400.

[0115] Of course, when the gate electrode 513, gate dielectric layer 512, and metal oxide channel layer 511 of the write transistor 510b are located only within the first trench 10, the upper surface of the gate electrode 513 of the write transistor 510b is flush or nearly flush with the upper surface of the write transistor dielectric layer structure 310. In this case, step S70 can directly etch the write transistor dielectric layer structure 310 to form the first conductive via structure 610.

[0116] In step S80, when forming the wiring layer 700, a wiring material layer may be formed on the entire surface first, and then the wiring material layer is patterned by photolithography, etching, etc., thereby forming the wiring layer 700. The material of the wiring layer 700 may include but is not limited to metal materials.

[0117] The wiring layer 700 covers the second conductive through-hole structure 620 and the gate electrode 513 of the write transistor 510b, thereby electrically connecting the first electrode 210 of the read transistor 510a, the second electrode 220 of the read transistor 510a, the first electrode 210 of the write transistor 510b, the second electrode 220 of the write transistor 510b and the gate electrode 513 of the write transistor 510b, thereby introducing or leading out the source / drain signal of the read transistor 510a, the source / drain signal of the write transistor 510b and the gate electrode 513 of the write transistor 510b.

[0118] As an example, after forming the wiring layer 700, a second filling material layer may be deposited on the entire surface and then subjected to a CMP process to remove the second filling dielectric material layer located on the wiring layer 700, thereby forming a second filling dielectric layer 330 whose upper surface is flush or nearly flush with the wiring layer 700. The material of the second filling dielectric layer 330, the material of the first filling dielectric layer 320, and the material of the dielectric layer structure 310 may be the same or different.

[0119] It should be understood that although Figure 1The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0120] In one embodiment, see Figure 7 or Figure 13 , also provides a semiconductor structure, which includes a substrate 100, a first electrode 210, a second electrode 220, and a dielectric layer structure 310.

[0121] The base 100 may include a semiconductor substrate. As an example, the base 100 may also include other structures or film layers formed on the semiconductor substrate, which may be configured according to actual needs.

[0122] One of the first electrode 210 and the second electrode 220 serves as the source of the transistor, and the other serves as the drain of the transistor. The material of the first electrode 210 and / or the material of the second electrode 220 is a metal material that can be oxidized to form a transparent conductive material. Examples of metal materials that can be oxidized to form a transparent conductive layer include indium (In) and / or tin (Sn).

[0123] The first electrode 210 is located on the substrate 100. It is understood that the first electrode 210 can be formed directly on the substrate 100 or an intermediate layer can be present between the first electrode 210 and the substrate 100. The second electrode 220 is stacked and spaced apart from the first electrode 210, and the two can be insulated and isolated by a dielectric layer structure 310.

[0124] The dielectric layer structure 310 covers and isolates the first electrode 210 and the second electrode 220 .

[0125] As an example, dielectric layer structure 310 may include a first dielectric layer (not shown), a second dielectric layer (not shown), and a first dielectric layer (not shown). The first dielectric layer may be located on substrate 100. The first electrode 210 may be located on the first dielectric layer. The second dielectric layer may cover the first electrode 210 and the first dielectric layer. The second electrode 220 may be located on the second dielectric layer. The first dielectric layer may cover the second electrode 220 and the second dielectric layer.

[0126] The semiconductor structure further includes a through hole 10 , a metal oxide channel layer 511 , a gate dielectric layer 512 and a gate electrode 513 .

[0127] The through hole 10 passes through the second electrode 220 from the dielectric layer structure 310 and extends to the first electrode 210 .

[0128] As an example, the diameters of the through hole 10 in different regions in a direction perpendicular to the substrate 100 are consistent.

[0129] The metal oxide channel layer 511 is at least located on the sidewalls and the bottom of the through hole 10 , the gate dielectric layer 513 is located on the surface of the metal oxide channel layer 511 , and the gate electrode is located on the surface of the gate dielectric layer.

[0130] End surfaces of the first electrode 210 and / or the second electrode 220 close to the through hole are oxidized and in contact with the metal oxide channel layer 511 .

[0131] As an example, the material of the metal oxide channel layer 511 is selected from any one or more of In, Ga, Sn, and Zn. For example, the material of the metal oxide channel layer 511 may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0132] As an example, end surfaces of the first electrode 210 and the second electrode 220 close to the through hole are oxidized into indium oxide (InO), tin oxide (SnO) or indium tin oxide (ITO).

[0133] Transparent conductive materials such as indium oxide, tin oxide, and indium tin oxide have good electrical conductivity, so the oxidized end surfaces of the first electrode 210 and the second electrode 220 have good electrical conductivity. The metal oxide channel layer 511 contacts the end surfaces of the first electrode 210 and / or the second electrode 220 that have been oxidized to the transparent conductive material. Therefore, the contact resistance between the metal oxide channel layer 511 and the first electrode 210 and / or the second electrode 220 can be effectively reduced.

[0134] As an example, the first electrode 210 and the second electrode 220 form an ohmic contact with the metal oxide channel layer 511 .

[0135] In this embodiment, the contact resistance between the electrode and the metal oxide channel layer 511 can be reduced by oxidizing the electrode end surface without etching the electrode back from the through hole 10, thereby simplifying the process and not easily causing structural damage.

[0136] At the same time, the end surfaces of the first electrode 210 and / or the second electrode 220 that have been oxidized to form a transparent conductive material are saturated or nearly saturated with oxygen, making it difficult for them to deprive oxygen from the metal oxide channel layer 511. This does not affect the oxygen vacancy concentration in the metal oxide channel layer 511, thereby not affecting device performance. In this case, as an example, the oxygen vacancy concentration at each location in the metal oxide channel layer is consistent. It will be understood that "consistent concentration" here means that the pore diameter is the same, or the difference in concentration is very small, within the range of process errors.

[0137] In one embodiment, see Figure 13 The semiconductor structure includes a read transistor 510 a and a write transistor 510 b of a memory cell stacked on the substrate 100 .

[0138] At least one of the read transistor 510 a and the write transistor 510 b includes the first electrode, the second electrode, and the metal oxide channel layer.

[0139] The dielectric layer structure 310 of the read transistor 510a may include a first dielectric layer (not shown), a second dielectric layer (not shown), and a first dielectric layer (not shown). The first dielectric layer may be located on the substrate 100. The first electrode 210 may be located on the first dielectric layer. The second dielectric layer may cover the first electrode 210 and the first dielectric layer. The second electrode 220 may be located on the second dielectric layer. The first dielectric layer may cover the second electrode 220 and the second dielectric layer.

[0140] The dielectric layer structure 310 of the write transistor 510b may include a fourth dielectric layer (not shown) and a fifth dielectric layer (not shown). The fourth dielectric layer may cover the first electrode 210 and its exposed structure. The second electrode 220 may be located on the fourth dielectric layer. The fifth dielectric layer may cover the second electrode 220 and the fourth dielectric layer.

[0141] At the same time, the first electrode 210 of the write transistor 510 b is formed on the surface of the gate electrode 513 of the read transistor 510 a .

[0142] In this embodiment, the write transistor 510b and the read transistor 510a can form a memory cell with a 2TOC architecture. In this case, the contact resistance between the electrode and the channel of the write transistor 510b and the read transistor 510a can be effectively reduced, thereby effectively improving the performance of the memory cell.

[0143] In one embodiment, see Figure 13 The semiconductor structure further includes a first conductive via structure 610 , a connecting electrode 400 and a second conductive via structure 620 .

[0144] The first conductive via structure 610 penetrates the dielectric layer structure 310 and extends to the first electrode 210 of the read transistor 510a and the second electrode 220 of the read transistor 510a. The material of the first conductive via structure 610 may include, but is not limited to, a metal material.

[0145] As an example, for the read transistor 510a, the metal oxide channel layer 511 extends from the through hole 10 to the upper surface of the dielectric layer structure 310, and the gate electrode 513 is T-shaped, the read transistor 510a also includes a first filling dielectric layer 320, the first filling dielectric layer 320 covers the dielectric layer structure 310 and exposes the upper surface of the gate electrode 513.

[0146] At this time, the first conductive via structure 610 may penetrate the first filling dielectric layer 320 and the dielectric layer structure 310 and extend to the first electrode 210 and the second electrode 220 .

[0147] The connecting electrode 400 and the first electrode 210 of the write transistor 510 b are located in the same metal layer and cover the first conductive via structure 610 , thereby electrically connecting the first electrode 210 and the second electrode 220 of the read transistor 510 a .

[0148] The second conductive via structure 620 penetrates the dielectric layer structure 310 of the write transistor 510 b and extends to the first electrode 210 of the write transistor 510 b , the second electrode 220 of the write transistor 510 b , and the connecting electrode 400 .

[0149] As an example, for the write transistor 510b, the metal oxide channel layer 511 extends from the through hole 10 to the upper surface of the dielectric layer structure 310, and the gate electrode 513 is T-shaped, the write transistor 510b also includes a first filling dielectric layer 320, the first filling dielectric layer 320 covers the dielectric layer structure 310 and exposes the upper surface of the gate electrode 513.

[0150] At this time, the second conductive via structure 620 can penetrate the first filling dielectric layer 320 of the write transistor 510b and the dielectric layer structure 310 of the write transistor, and extend to the first electrode 210 of the write transistor 510b, the second electrode 220 of the write transistor 510b, and the connecting electrode 400.

[0151] As an example, the semiconductor structure may further include a wiring layer 700 .

[0152] The wiring layer 700 covers the second conductive through-hole structure 620 and the gate electrode 513 of the write transistor 510b, thereby electrically connecting the first electrode 210 of the read transistor 510a, the second electrode 220 of the read transistor 510a, the first electrode 210 of the write transistor 510b, the second electrode 220 of the write transistor 510b and the gate electrode 513 of the write transistor 510b, thereby introducing or leading out the source / drain signal of the read transistor 510a, the source / drain signal of the write transistor 510b and the gate signal of the write transistor 510b.

[0153] In one embodiment, an electronic device is also provided, comprising one or more semiconductor structures as described in the above embodiments. Examples of electronic devices include data storage devices, copiers, network equipment, household appliances, instruments, mobile phones, computers, and other devices with data storage capabilities. The electronic device may include a housing, a circuit board disposed within the housing, and a memory or data read / write circuit integrated on the circuit board. For the structure of the memory, please refer to the relevant descriptions in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the present embodiments.

[0154] The various technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked first electrode, a dielectric layer, and a second electrode on the substrate, and a through hole that sequentially penetrates the second electrode and the dielectric layer toward the substrate and extends at least to the upper surface of the first electrode; performing oxidation treatment on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole; forming a metal oxide channel layer in the through hole; The materials of the first electrode and the second electrode include metal, the end surfaces of the first electrode and the second electrode include metal oxide containing the metal formed by oxidation treatment, and an ohmic contact is formed between the metal oxide channel layer and the metal oxide.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the metal oxide channel layer, an oxidation treatment is performed on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole using a plasma process.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The end surface of the first electrode and the end surface of the second electrode are oxidized by using a plasma process containing O2 or O3 gas.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The step of performing oxidation treatment on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole comprises: While the metal oxide channel layer is being formed, an oxidation treatment is performed on the end surface of the first electrode and the end surface of the second electrode exposed by the through hole.

5. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a first electrode and a second electrode on the substrate includes: forming a first conductive film layer made of indium and / or tin on the substrate, and performing a patterning process on the first conductive film layer to form the first electrode; forming a second conductive film layer made of indium and / or tin on the substrate, and performing a patterning process on the second conductive film layer to form the second electrode; The end surface of the first electrode and the end surface of the second electrode are made of metal oxide containing indium and / or tin.

6. The method for preparing a semiconductor structure according to claim 1 or 5, characterized in that: The forming of a metal oxide channel layer in the through hole comprises: A metal oxide channel layer containing at least one of indium, gallium, zinc and tin is formed in the through hole.

7. A semiconductor structure, characterized in that include: substrate; a first electrode, a second electrode, and a dielectric layer structure, wherein the first electrode is located on the substrate, the second electrode is stacked with the first electrode and spaced apart in a direction perpendicular to the substrate, and the dielectric layer structure includes a dielectric layer located between the first electrode and the second electrode and a dielectric layer located above the second electrode; a through hole, penetrating the second electrode and each of the dielectric layers and extending at least to the upper surface of the first electrode; a metal oxide channel layer, located in the through hole and contacting end surfaces of the first electrode and the second electrode exposed in the through hole; The materials of the first electrode and the second electrode include metal, the end surfaces of the first electrode and the second electrode include metal oxide of the metal, and there is ohmic contact between the metal oxide channel layer and the metal oxide.

8. The semiconductor structure according to claim 7, wherein: The metal material of the metal oxide channel layer is selected from one or more of indium, gallium, zinc, and tin.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The materials of the first electrode and the second electrode include at least one of indium and tin.

10. The semiconductor structure according to claim 7, wherein: The semiconductor structure includes a read transistor and a write transistor stacked on the substrate, and at least one of the read transistor and the write transistor includes the first electrode, the second electrode, and the metal oxide channel layer.

11. The semiconductor structure according to claim 7, wherein: The through holes have the same aperture in different regions perpendicular to the substrate.

12. The semiconductor structure according to claim 7, wherein: The oxygen concentration of the metal oxide channel layer in a region in contact with end surfaces of the first electrode and the second electrode is consistent with the oxygen concentration of the channel region between the first electrode and the second electrode.

13. An electronic device comprising the semiconductor structure according to any one of claims 7 to 12.

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