Nanostructured field effect transistor devices and methods of forming same

Abstract

Nanostructured field effect transistor devices and methods of forming the same are provided. A method of forming a semiconductor device includes forming a fin structure protruding higher than a substrate, where the fin structure includes a fin and a layer stack overlying the fin, where the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure over the fin structure; forming a source / drain opening in the fin structure at an opposite side of the gate structure; replacing a first end of the first semiconductor material exposed by the source / drain opening with an internal spacer; after the replacement, performing an ion implantation process in which the ion implantation process implants a first dopant into a second end of the second semiconductor material exposed by the source / drain opening; and forming a source / drain region in the source / drain opening after performing the ion implantation process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a nanostructured field effect transistor device and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric, conductive, and semiconducting layers of material onto a semiconductor substrate and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] In one aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure comprises a fin and a layer stack overlying the fin, wherein the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure above the fin structure; forming a source / drain opening in the fin structure on an opposite side of the gate structure; replacing a first end portion of the first semiconductor material exposed by the source / drain opening with an internal spacer; after the replacement, performing an ion implantation process, wherein the ion implantation process implants a first dopant into a second end portion of the second semiconductor material exposed by the source / drain opening; and after performing the ion implantation process, forming a source / drain region in the source / drain opening.

[0005] In one aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure comprises a fin and alternating layers of a first semiconductor material and a second semiconductor material above the fin; forming a dummy gate structure above the fin structure; forming a source / drain opening in the fin structure on an opposite side of the dummy gate structure; forming an internal spacer between adjacent layers of the second semiconductor material; after forming the internal spacer, implanting a first dopant into an end portion of the second semiconductor material exposed by the source / drain opening; after implanting the first dopant, forming a source / drain region in the source / drain opening, wherein the source / drain region is formed to have a second dopant; forming a dielectric layer around the dummy gate structure; and replacing the dummy gate structure with a replacement gate structure.

[0006] In one aspect, an embodiment of the present application provides a semiconductor device comprising: a substrate; a fin protruding above the substrate; a gate structure located above the fin; a source / drain region located above the fin on the opposite side of the gate structure; and a nanostructure located between the source / drain regions and below the gate structure, wherein the nanostructure is a channel region of the semiconductor device and comprises a doped region contacting the source / drain region and an undoped region between the doped regions, wherein the doped region comprises a channel material and a first dopant in the channel material, wherein a dopant concentration in the doped region increases along a first direction perpendicular to a main upper surface of the substrate, wherein the first direction extends from an uppermost nanostructure away from the substrate toward a lowermost nanostructure closest to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 、 Figures 3A to 3C 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C 、 6A to 6D 、 Figure 7A 、 Figure 7B 、 Figures 8A to 8D 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A and Figure 12B are cross-sectional views of a nanostructured field effect transistor (NSFET) device at various stages of fabrication according to an embodiment.

[0010] Figure 13 A flow chart illustrating a method of forming a semiconductor device in some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0012] In addition, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to easily describe the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly. Throughout the discussion herein, unless otherwise described, the same or similar reference numerals in different figures represent the same or similar components formed by the same or similar formation process, using the same or similar materials. In addition, figures having the same numbers but different letters (e.g., Figures 5A to 5C ) shows different views of a NSFET device at the same processing stage.

[0013] According to some embodiments, during the process of forming an NSFET device, after the source / drain openings are formed, an ion implantation process is performed to implant dopants into the ends of each semiconductor material layer in the layer stack, where these ends are exposed by the source / drain openings. Each semiconductor material layer in the layer stack will form the channel region of the NSFET device in subsequent processing. The dopant is implanted into the doped region of the semiconductor material. The doped region has higher carrier mobility and lower resistance than the undoped region of the semiconductor material. Therefore, by forming the doped region in each semiconductor material layer, the resistance of the channel region of the formed NSFET device is reduced, and the electrical performance of the NSFET device is improved.

[0014] Figure 1An example of a nanostructure field effect transistor (NSFET) device 30 according to some embodiments is shown in a three-dimensional view. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) that protrudes above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed above the fin, while source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed above the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed to surround the nanostructures 54. The gate electrode 122 is located above and surrounds the gate dielectric layer 120.

[0015] Figure 1 Reference cross sections used in subsequent figures are also shown. Section AA is along the longitudinal axis of the gate electrode 122 and is, for example, perpendicular to the direction of current flow between the source / drain regions 112 of the NSFET device 30. Section BB is perpendicular to section AA and along the longitudinal axis of the fins 90 and is, for example, in the direction of current flow between the source / drain regions 112 of the NSFET device. Section CC is parallel to section BB and is between two adjacent fins 90. Section DD is parallel to section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, subsequent figures may refer to these reference cross sections.

[0016] Figure 2 、 Figures 3A to 3C 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C 、 6A to 6D 、 Figure 7A 、 Figure 7B 、 Figures 8A to 8D 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A and Figure 12B are cross-sectional views of a nanostructured field effect transistor (NSFET) device 100 at various stages of fabrication according to an embodiment.

[0017] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate (typically a silicon substrate or a glass substrate). Other substrates (e.g., multilayer or gradient substrates) may also be used. In some embodiments, the semiconductor material of the substrate 50 includes silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination of the foregoing.

[0018] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 , the layers formed of the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, and 54C. Figure 2 The number of layers of the first semiconductor material and the second semiconductor material shown is merely a non-limiting example. Other numbers of layers are possible and are fully intended to be included within the scope of the present disclosure.

[0019] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming a channel region of a p-type FET, such as silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming the channel region of an n-type FET, such as silicon. In some embodiments, the second semiconductor material 54 (e.g., silicon) can be used to form an n-type or p-type FET, while the first semiconductor material 52 serves as a sacrificial material that is later removed. The multilayer stack 64 (which can also be referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET in subsequent processing. In particular, the multilayer stack 64 will be patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), wherein the channel region of the resulting NSFET includes a plurality of horizontal nanostructures.

[0020] The multilayer stack 64 can be formed by an epitaxial growth process that can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors for selectively growing the first semiconductor material 52 and then to a second set of precursors for selectively growing the second semiconductor material 54. The first set of precursors includes precursors for a first semiconductor material (e.g., silicon germanium), and the second set of precursors includes precursors for a second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanium), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously flowing the silicon precursor to the growth chamber and then performing the following operations: (1) enabling the germanium precursor to flow to the growth chamber when growing the first semiconductor material 52; and (2) disabling the germanium precursor from flowing to the growth chamber when growing the second semiconductor material 54. The cyclic exposure can be repeated until the target number of layers is formed.

[0021] Figure 2 、 Figures 3A to 3C 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C 、 6A to 6D 、 Figure 7A 、 Figure 7B 、 Figures 8A to 8D 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A and Figure 12B is a cross-sectional view of NSFET device 100 at a subsequent stage of fabrication in accordance with an embodiment. Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 6D 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8D 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A It is along Figure 1 Cross-sectional view of section BB in FIG. Figure 3B 、 Figure 3C 、 Figure 4B 、 Figure 5C 、 Figure 6C 、 Figure 8C 、 Figure 9B 、 Figure 10B 、 Figure 11B and Figure 12B It is along Figure 1Cross-sectional view of section AA in FIG. Figure 5B 、 Figure 6B and Figure 8B It is along Figure 1 The number of fins and the number of gate structures shown in the figures are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0022] exist Figure 3A and Figure 3B In the embodiment of the present invention, fin structures 91 are formed to protrude higher than substrate 50. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a stack 92 overlying the semiconductor fin 90. The stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0023] The fin structure 91 can be patterned by any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). Typically, the double patterning process or the multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the created pattern to have a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern, for example, the fin structure 91.

[0024] In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. Mask 94 can be a single-layer mask, or can be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed from a dielectric material (e.g., silicon oxide, silicon nitride, a combination thereof, etc.) and can be deposited or thermally grown according to a suitable technique. The first mask layer 94A and the second mask layer 94B are different materials with high etching selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. Mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. Mask 94 can then be used as an etching mask to etch the substrate 50 and the multilayer stack 64. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multilayer stack 64 forms a stack 92, and the patterned substrate 50 forms a fin 90, as shown in FIG. Figure 3A and Figure 3B Thus, in the illustrated embodiment, the layer stack 92 further includes alternating layers of the first semiconductor material 52 and the second semiconductor material 54 , and the fin 90 is formed of the same material as the substrate 50 (eg, silicon).

[0025] Figure 3B The fin 90 and layer stack 92 in FIG. 1 are shown as having sloped sidewalls (eg, having a trapezoidal cross-section). Due to the characteristics of the anisotropic etching process used to form the fin 90 and layer stack 92, Figure 3B The sloped sidewalls shown can be formed. For example, the etching capability of the anisotropic etching process can be along Figure 3B The downward vertical direction decreases, which can result in inclined side walls. Figure 3B The shapes of the fins 90 and layer stacks 92 shown in FIG are merely non-limiting examples. The fins 90 and stacks 92 may have substantially vertical sidewalls, such as Figure 3C For ease of illustration, the fin 90 and layer stack 92 may be shown in subsequent figures as having vertical sidewalls, it being understood that the sidewalls may be as shown in FIG. Figure 3B Tilt shown.

[0026] Next, in Figure 4A and Figure 4B , a shallow trench isolation (STI) region 96 is formed on the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed on the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing for converting it to another material (e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. An annealing process can be performed after the insulating material is formed.

[0027] In some embodiments, the insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structure 91, and a filler material (such as those discussed above) is formed over the liner. In some embodiments, the liner is omitted.

[0028] Next, a removal process is applied to the insulating material to remove excess insulating material above fin structure 91. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc.) may be used. The planarization process exposes layer stack 92 so that the top surfaces of layer stack 92 and the insulating material are flush after the planarization process is completed. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed so that layer stack 92 protrudes from between adjacent STI regions 96. The top portions of semiconductor fins 90 may also protrude from between adjacent STI regions 96. In addition, the top surfaces of STI regions 96 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surfaces of STI regions 96 may be formed to be flat, convex, and / or concave by appropriate etching. STI regions 96 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the insulating material (e.g., an etching process that etches the insulating material at a faster rate than the material of fin 90 and layer stack 92)). For example, chemical oxide removal with a suitable etchant such as dilute hydrofluoric acid (dHF) may be used.

[0029] Still refer to Figure 4A and Figure 4B , dummy dielectric layer 97 is formed over layer stack 92 and over STI regions 96. Dummy dielectric layer 97 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. In one embodiment, a silicon layer is conformally formed over layer stack 92 and over the upper surface of STI regions 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as dummy dielectric layer 97.

[0030] Next, in Figures 5A to 5C , a dummy gate 102 is formed on the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed on the dummy dielectric layer 97. The dummy gate layer can be deposited on the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials with high etching selectivity compared to the STI region 96.

[0031] A mask 104 is then formed over the dummy gate layer. Mask 104 can be formed from silicon nitride, silicon oxynitride, combinations thereof, or the like, and can be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form dummy gate 102, and then transferred to the dummy dielectric layer using an acceptable etching technique to form dummy gate dielectric 97. Dummy gate 102 covers the corresponding channel region of stack 92. The pattern of mask 104 can be used to physically separate each dummy gate 102 from an adjacent dummy gate. Dummy gate 102 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of fin structure 91. In some embodiments, dummy gate 102 and dummy gate dielectric 97 are collectively referred to as a dummy gate structure.

[0032] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108 includes multiple sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, while a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0033] Figure 5B and Figure 5C Shown respectively Figure 5A The NSFET device 100 along Figure 5A Cross-sectional view of section EE and section FF in FIG. Section EE and section FF correspond to Figure 1 Section DD and section AA in.

[0034] Next, in Figures 6A to 6C , the gate spacer layer 108 is etched by an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove horizontal portions of the gate spacer layer 108 (e.g., portions above the STI region 96 and the dummy gate 102), while the remaining vertical portions of the gate spacer layer 108 (e.g., portions along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) form the gate spacer 108.

[0035] After forming the gate spacers 108, an implantation of lightly doped source / drain (LDD) regions (not shown) may be performed. Impurities of an appropriate type (e.g., p-type or n-type) may be implanted into the exposed layer stack 92 and / or semiconductor fins 90. The n-type impurity may be any suitable n-type impurity, such as phosphorus, arsenic, antimony, etc., and the p-type impurity may be any suitable p-type impurity, such as boron, BF2, indium, etc. The lightly doped source / drain regions may have a density of about 1E15 / cm 3 and about 1E16 / cm 3 The annealing process can be used to activate the implanted impurities.

[0036] Next, openings 110 (which may also be referred to as recesses or source / drain openings) are formed in layer stack 92. Openings 110 may extend through layer stack 92 and to fin 90. Openings 110 may be formed by an anisotropic etching process using, for example, dummy gate 102 and gate spacers 108 as an etch mask.

[0037] After the opening 110 is formed, a selective etching process is performed to recess the end portion of the first semiconductor material 52 exposed by the opening 110 without substantially attacking the second semiconductor material 54. After the selective etching process, a recess (also referred to as a sidewall recess) is formed in the first semiconductor material 52 at the location where the removed end portion was located.

[0038] Next, an inner spacer layer is formed (e.g., conformally) in the opening 110. The inner spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The inner spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc., formed by a suitable deposition method (e.g., PVD, CVD, atomic layer deposition (ALD), etc.). Next, an etching process (e.g., an anisotropic etching process) is performed to remove the portion of the inner spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the inner spacer layer (e.g., the portion disposed within the sidewall recesses of the first semiconductor material 52) forms the inner spacer layer 55. As Figure 6A As shown, the opening 110 exposes the sidewalls of the second semiconductor material 54 and exposes the upper surface 90U of the fin 90 at the bottom of the opening 110 .

[0039] Figure 6B and Figure 6C Shown respectively Figure 6A FIG. 1 is a cross-sectional view of the NSFET device 100 along section EE and section FF. Figure 6BIn the embodiment, portions of the gate spacer layer 108 disposed on the upper surfaces of the STI regions 96 between adjacent fins 90 are completely removed by the anisotropic etching process used to form the gate spacers 108. In some embodiments, portions of the gate spacer layer 108 on the upper surfaces of the STI regions 96 between adjacent fins 90 are left (e.g., remain). Since a small distance between adjacent fins 90 reduces the efficiency of the anisotropic etching process, the anisotropic etching process discussed above may not completely remove the gate spacer layer 108 disposed between adjacent fins 90, and those portions of the gate spacer layer 108 may therefore be left.

[0040] It should be noted that for ease of explanation, Figure 6A The opening 110 in FIG. 5 is shown as having vertical sidewalls (eg, perpendicular to the major upper surface of the substrate 50). The opening 110 may actually have sloped sidewalls, such as Figure 6D and Figure 7B In some embodiments, each opening 110 has sloped sidewalls such that the width of the opening 110 measured between opposite sidewalls of the opening 110 decreases as the opening 110 extends toward the substrate 50 (see, for example, Figure 7B ). In other words, the opening 110 may have a trapezoidal cross section. As a result, Figure 6A The structure below each dummy gate 102 (the structure including the layers of the first semiconductor material 52 , the layers of the second semiconductor material 54 , and the internal spacers 55 ) may also have a trapezoidal cross-section. Figure 6D Shown Figure 6A An enlarged view of area 135 in FIG.

[0041] exist Figure 6D In the example of FIG. 5 , each layer of the second semiconductor material 54 has an inclined sidewall 54S (e.g., a trapezoidal cross-section). In addition, the length L1 of each layer of the second semiconductor material 54 (the length measured between adjacent openings 110 at the midpoint between the upper and lower surfaces of the layer of the second semiconductor material 54) decreases along the depth direction of the opening 110 toward the substrate 50 (e.g., Figure 6D In some embodiments, the angle θ between the inclined sidewall 54S of the second semiconductor material 54 and the vertical direction 51 is between about 0.5 degrees and about 30 degrees, for example, between about 5 degrees and about 25 degrees, or between about 10 degrees and about 20 degrees. Figure 6D In the example shown, each internal spacer 55 also has a trapezoidal cross-section with one inclined side wall and one vertical side wall. Figure 6D In the embodiment, each layer of the first semiconductor material 52 has a rectangular cross-section, and a length L2 of each layer of the first semiconductor material 52 increases along a vertical direction 51 toward the substrate 50 .

[0042] It should be noted that for ease of explanation, Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A Vertical sidewalls (eg, perpendicular to the main upper surface of the substrate 50) are shown for some sidewalls of, for example, the second semiconductor material 54, the inner spacer 55, the opening 110, and the source / drain region 112. It should be understood that inclined sidewalls (eg, Figure 6D 、 Figure 7B and Figure 8D sidewalls (those shown) are formed in the NSFET device 100 .

[0043] Next, in Figure 7A In the embodiment shown, an ion implantation process 130 is performed to implant a first dopant into the end of the second semiconductor material 54 exposed by the opening 110. The first dopant can be an n-type dopant or a p-type dopant, depending on the type of device being formed. In the embodiment shown, the first dopant is of the same type (e.g., n-type or p-type) as the second dopant in the subsequently formed source / drain regions 112. In other words, the first dopant is of the same type (e.g., n-type or p-type) as the NSFET being formed. The first dopant can be any suitable n-type impurity (e.g., P, Sb, or As) or p-type impurity (e.g., B, Al, Ga, or In) used in the ion implantation process 130.

[0044] In some embodiments, the ion implantation process 130 is performed at a temperature between about -100° C. and about 300° C. The tilt angle of the ion implantation process 130 may be between about 0 degrees and about 45 degrees. The energy of the ion implantation process 130 may be between about 0.2 kiloelectronvolts (KeV) and about 20 KeV. The dose of the ion implantation process 130 may be about 1E16 / cm 2 and about 1E20 / cm 2 In some embodiments, after the ion implantation process 130 is completed, a thermal treatment (eg, an annealing process) is performed to activate the first dopant implanted into the end portion of the second semiconductor material 54 .

[0045] Figure 7B After the ion implantation process 130 and the heat treatment to activate the first dopant are completed, Figure 7A An enlarged view of region 131 in FIG. Figure 7B, doped regions 56 of the second semiconductor material 54 are shown, which are regions of the second semiconductor material 54 that include the first dopant. For each doped region 56, a boundary 57 (e.g., an interface) between the doped region 56 and an undoped portion of the second semiconductor material 54 is shown in dashed lines. The boundary 57 may also be referred to as a junction 57.

[0046] exist Figure 7B In the example shown, due to the sloped sidewalls 54S of the second semiconductor material 54 and the ion beam divergence (and / or the larger tilt angle of the ion beam), the lower layers of the second semiconductor material 54 (e.g., closer to the substrate 50) receive (e.g., are implanted with) more of the first dopant. As a result, the concentration of the first dopant in the doped regions 56 increases along the depth of the opening 110 toward the substrate 50. In other words, the closer the doped regions 56 are to the substrate 50, the higher the concentration of the first dopant in the doped regions 56. In some embodiments, the concentration of the first dopant in the lowest doped regions 56 (e.g., closest to the substrate 50) is between about two times and about five times the concentration in the highest doped regions 56 (e.g., farthest from the substrate 50).

[0047] Once implanted into the end of the second semiconductor material 54 and activated, the first dopant also diffuses further toward the center of the second semiconductor material 54. Figure 7B Each doped region 56 in includes a region having an implanted first dopant and a region having a diffused first dopant. Figure 7B In the example of FIG, the width D1 of the doped region 56 (eg, the maximum width measured between the sloped sidewall 54S of the second semiconductor material 54 and the corresponding boundary 57 of the doped region 56 ) decreases along the depth direction of the opening 110 toward the substrate 50 (eg, Figure 7B In other words, the lower the doped region 56 is, the larger the width D1 of the doped region 56 is. In some embodiments, a larger width D1 indicates a larger volume of the doped region 56.

[0048] In some embodiments, after the thermal treatment to activate the first dopant, the first dopant (e.g., boron ions) in the doped region 56 replaces atoms (e.g., silicon atoms) in the lattice structure of the second semiconductor material 54 (e.g., silicon), thereby being disposed in a replacement position in the lattice structure. The doped region 56 has increased carrier mobility and lower resistance. Because the second semiconductor material 54 forms the channel region of the NSFET device 100 in subsequent processing, the larger doped region 56 (e.g., having a larger width D1 and / or a larger volume) in the second semiconductor material 54 reduces the resistance of the channel region of the formed NSFET device, thereby improving the electrical performance of the NSFET device.

[0049] Next, in Figures 8A to 8C , source / drain regions 112 are formed in the openings 110. In the discussion herein, the source / drain regions 112 may be referred to individually or collectively as a source or a drain, depending on the context. In the illustrated embodiment, the source / drain regions 112 are formed of epitaxial material(s) and, therefore, may also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the openings 110 to apply stress to the corresponding channel region of the formed NSFET device, thereby improving performance. In some embodiments, the epitaxial source / drain regions 112 are formed such that the dummy gate 102 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 112. In some embodiments, gate spacers 108 are used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance so that the epitaxial source / drain regions 112 do not short to a subsequently formed gate of the resulting NSFET device.

[0050] Epitaxial source / drain regions 112 are epitaxially grown in openings 110. Epitaxial source / drain regions 112 can include any acceptable material, such as a material suitable for n-type or p-type devices. For example, when an n-type device is formed, epitaxial source / drain regions 112 can include a material that imparts tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when a p-type device is formed, epitaxial source / drain regions 112 can include a material that imparts compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 112 can have surfaces that are raised from corresponding surfaces of the fins 90 and can have facets.

[0051] The epitaxial source / drain regions 112 and / or the fins 90 may be implanted with a second dopant (e.g., an n-type impurity or a p-type impurity) to form the source / drain regions (similar to the process previously discussed for forming lightly doped source / drain regions), followed by annealing. The source / drain regions may have a density of about 1E19 / cm 3 and about 1E21 / cm 3 The impurity concentration (also referred to as dopant concentration) between 1 and 2. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 112 can be in-situ doped during growth. As described above, the first dopant in the doped regions 56 and the second dopant in the source / drain regions 112 are of the same type (e.g., n-type or p-type). The first dopant can be the same as the second dopant, or can be different from the second dopant but of the same type.

[0052] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 90. In the embodiment shown, adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed (see FIG. Figure 8B ). In other embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 112 of the same NSFET.

[0053] Figure 8D Shown Figure 8A An enlarged view of region 133 in FIG. Figure 8D In the example shown, source / drain region 112 includes a first layer of source / drain material 112A and a second layer of source / drain material 112B. In some embodiments, source / drain region 112 is formed by selectively forming first layer of source / drain material 112A on sloped sidewalls 54S of second semiconductor material 54 and upper surface 90U of fin 90 exposed by opening 110, and then forming second layer of source / drain material 112B on first layer of source / drain material 112A to fill opening 110. In some embodiments, first layer of source / drain material 112A is selectively formed on sloped sidewalls 54S and upper surface 90U because epitaxial source / drain material does not grow on the surface of inner spacer 55. Once first layer of source / drain material 112A is formed, second layer of source / drain material 112B is grown on first layer of source / drain material 112A to fill opening 110.

[0054] The epitaxial growth process for growing the source / drain regions 112 and / or the implantation process for implanting the second dopant in the source / drain regions 112 can be adjusted to achieve different concentrations of the second dopant in the first layer of source / drain material 112A and the second layer of source / drain material 112B. In some embodiments, the concentration of the second dopant (e.g., n-type impurity or p-type impurity) in the first layer of source / drain material 112A is lower than the concentration of the second dopant in the second layer of source / drain material 112B. For example, the concentration of the second dopant in the first layer of source / drain material 112A can be about 1E19 / cm 3 and about 3E21 / cm 3 The concentration of the second dopant in the second source / drain material 112B may be between about 1E20 / cm 3 and about 5E21 / cm 3 between.

[0055] In some embodiments, the concentration of the first dopant in the doped region 56 of the uppermost (e.g., furthest from the substrate 50) second semiconductor material 54 is equal to or higher than the concentration of the second dopant in the first layer of source / drain material 112A. In some embodiments, because the concentration of the first dopant in the doped region 56 increases in the vertical direction toward the substrate 50, this means that the concentration of the first dopant in other lower-doped regions 56 (e.g., regions disposed closer to the substrate 50 than the uppermost doped region 56 furthest from the substrate 50) is higher than the concentration of the second dopant in the first layer of source / drain material 112A.

[0056] In the embodiment shown, the second dopant in the source / drain regions 112 diffuses into the doped regions 56 of the second semiconductor material 54, which will Figure 7B The junction 57 in the second semiconductor material 54 is pushed further toward the middle portion of the second semiconductor material 54. In other words, the diffused second dopant increases the width of the doped region in the second semiconductor material 54. The doped region with the implanted first dopant, the diffused first dopant, and the diffused second dopant is Figure 8D The doped region 58 is marked in FIG. 5 , and a boundary 59 (eg, an interface) between the doped region 58 and the undoped portion of the second semiconductor material 54 is marked in FIG. Figure 8D The boundary 59 may also be referred to as a junction 59.

[0057] like Figure 8D As shown, due to the contribution of the diffused second dopant, the width D2 of each doped region 58 (eg, the maximum width measured between the inclined sidewall 54S of the second semiconductor material 54 and the corresponding boundary 59 of the doped region 58) is greater than Figure 7B The width D1 of the corresponding doped region 56 in the substrate 50 (for example, at the same vertical distance from the substrate 50) is greater than that of the corresponding doped region 56 in the substrate 50. In addition, due to the diffused second dopant, each doped region 58 includes the first dopant and the second dopant, and the total concentration of the first dopant and the second dopant in the doped region 58 can be higher than the concentration of the first dopant in the corresponding doped region 56. Figure 7B similar, Figure 8D The total concentration of the first dopant and the second dopant in the doping region 58 in FIG. 5 shows a gradient. In particular, the total concentration of the first dopant and the second dopant in the doping region 58 increases along the vertical direction toward the substrate 50 .

[0058] The doped region 58 has higher carrier mobility and lower resistance than the undoped region of the second semiconductor material 54 (e.g., silicon), so having a large doped region 58 reduces the channel area of ​​the formed NSFET device (see, e.g., Figure 10A 、 Figure 11A and Figure 12AThe method disclosed herein achieves a large doped region 58 and avoids some performance issues of existing methods.

[0059] To understand the advantages of the presently disclosed method, consider a reference method in which the ion implantation process 130 is omitted. Specifically, after the opening 110 is formed, the reference method performs an etching process to recess the end portion of the second semiconductor material 54 exposed by the opening 110, thereby forming a sidewall recess in the sidewall of the second semiconductor material 54 facing the opening 110. Next, the source / drain region 112 is formed in the opening 110. Portions of the source / drain region 112 may protrude into the sidewall recess of the second semiconductor material 54. The portion of the source / drain region 112 protruding into the sidewall recess and the portion of the second semiconductor material 54 containing the second dopant diffused from the source / drain region 112 can be collectively considered as the doped region of the reference method. However, the reference method has some performance issues. For example, due to process limitations, the depth of the sidewall recess may be limited. In addition, without the ion implantation process 130, the concentration of the dopant in the doped region of the reference method may be limited. In addition, the etching process used to recess the ends of the second semiconductor material 54 may roughen the surface of the inner spacer 55 and the sidewalls of the second semiconductor material 54 exposed to the opening 110. The rough surface may be detrimental to the epitaxial process used to grow the source / drain regions 112 and may reduce the quality of the epitaxial source / drain regions 112, thereby limiting device performance. The present disclosure achieves high dopant concentrations and large sizes (e.g., width and / or volume) of the doped regions 56 / 58 by using the ion implantation process 130 and by controlling the process conditions of the ion implantation process 130, while avoiding the etching process and the performance issues associated with the roughness of the surface of the inner spacer 55 and the sidewalls of the second semiconductor material 54 caused by the etching process. It should be noted that the doped regions 56 of the present disclosure can be regarded as replacing the protruding portions of the source / drain regions 112 in the reference method. Therefore, the concentration of the first dopant in the doped regions 56 should be comparable to (e.g., equal to or higher than) the concentration of the second dopant in the first layer of source / drain material 112A.

[0060] Still refer to Figures 8A to 8CA contact etch stop layer (CESL) 116 is formed (e.g., conformally) over the source / drain regions 112 and over the dummy gate 102, and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114 and may be formed of silicon nitride using PECVD, but other dielectric materials (e.g., silicon oxide, silicon oxynitride, combinations thereof, etc.) and alternative techniques for forming the CESL 116 (e.g., low-pressure CVD (LPCVD), PVD, etc.) may be used instead.

[0061] The first ILD 114 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material of the first ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. Figure 8B and Figure 8C Shown are the Figure 8A Section EE and Section FF Figure 8A 1 is a cross-sectional view of a NSFET device 100 .

[0062] Next, in Figure 9A and Figure 9B In the embodiment of the present invention, the dummy gate 102 and the dummy gate dielectric 97 are removed. Figure 9B Shown Figure 9A A cross-sectional view of the NSFET device 100 along section FF.

[0063] To remove the dummy gate 102, a planarization process (eg, CMP) is performed to level the top surfaces of the first ILD 114 and the CESL 116 with the top surfaces of the dummy gate 102 and the gate spacers 108. The planarization process may also remove the mask 104 on the dummy gate 102 (see FIG. Figure 8A ), and portions of the gate spacers 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gate 102, the gate spacers 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0064] Next, the dummy gate 102 is removed in an etching step(s) such that the recess 103 is formed. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gas(es) that selectively etches the dummy gate 102 without etching the first ILD 114 or the gate spacers 108. During the removal of the dummy gate 102, the dummy gate dielectric 97 may serve as an etch stop layer when the dummy gate 102 is etched. The dummy gate dielectric 97 may then be removed after the dummy gate 102 is removed. An etching process (e.g., an isotropic etching process) may be performed to remove the dummy gate dielectric 97. In one embodiment, an isotropic etching process using an etching gas including HF and NH3 is performed to remove the dummy gate dielectric 97. As Figure 9A and Figure 9B As shown, the recess 103 exposes the channel region of the NSFET device. The channel region is disposed between adjacent pairs of epitaxial source / drain regions 112.

[0065] Next, in Figure 10A and Figure 10B In the embodiment of the present invention, the first semiconductor material 52 (e.g., the portion exposed by the recess 103) is removed to release the second semiconductor material 54. After the first semiconductor material 52 is removed, the second semiconductor material 54 (e.g., the portion below the dummy gate 102 before the dummy gate 102 is removed) forms a plurality of nanostructures 54 extending horizontally (e.g., parallel to the main upper surface of the substrate 50). The nanostructures 54 can be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Figure 10A As shown, gaps 53 (eg, empty spaces) are formed between nanostructures 54 by removing first semiconductor material 52. In some embodiments, nanostructures 54 are nanosheets or nanowires, depending on, for example, the dimensions of nanostructures 54 (eg, size and / or aspect ratio).

[0066] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate thereto), such that the first semiconductor material 52 is removed without substantially attacking the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process is performed using an etching gas and (optionally) a carrier gas. In some embodiments, the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, a combination thereof, or the like.

[0067] Figure 10A1 shows a cross-sectional view of the NSFET device 100 along the longitudinal axis of the fin (eg, along the direction of current flow in the fin), and Figure 10B A cross-sectional view of NSFET device 100 along section FF is shown, which is a cross section along a direction perpendicular to the longitudinal axis of the fin and passing through a middle portion of nanostructure 54 .

[0068] like Figure 10A As shown, each nanostructure 54 has a rectangular cross-section along the longitudinal axis of the fin. Figure 10B In FIG. 5 , each nanostructure 54 has a rectangular cross-section in a cross-section along a direction perpendicular to the longitudinal axis of the fin and passing through a middle portion of the nanostructure 54 .

[0069] Next, in Figure 11A and Figure 11B In some embodiments, nanostructure 54 is reshaped by a nanostructure reshaping process (e.g., an isotropic etching process). In some embodiments, nanostructure 54 is reshaped by a selective etching process using an etchant that is selective to the material of nanostructure 54 (e.g., second semiconductor material 54), such that nanostructure 54 is etched without substantially attacking other materials in NSFET device 100, such as oxide, silicon nitride, and low-K dielectric material.

[0070] The nanostructure reshaping process thins the middle portion of each nanostructure 54 while the ends of the nanostructure 54 (covered by the inner spacer 55 and the gate spacer 108) remain substantially unchanged, thereby producing Figure 11A In addition, the nanostructure reshaping process removes the sharp edges of the nanostructure 54 (see, for example, Figure 10B 90 degree edges of the nanostructures 54 in FIG), thereby producing rounded edges of each nanostructure 54 (see FIG. Figure 11B ), as described in more detail below.

[0071] like Figure 11A As shown, after the nanostructure reshaping process, each nanostructure 54 has a dumbbell shape in a cross section along the longitudinal axis of the fin, wherein the thickness (along the cross section) of the end portion of the nanostructure 54 (e.g., the portion physically contacting the source / drain region 112) is less than 0. Figure 11A The thickness of the middle part (e.g., the half part between the ends) is greater than the thickness of the middle part (e.g., the half part between the ends). Figure 11AIn the example shown, the upper and lower surfaces of the middle portion of each nanostructure 54 are shown as flush surfaces (e.g., flat surfaces). Of course, this is merely a non-limiting example. In some embodiments, the upper and lower surfaces of the middle portion of each nanostructure 54 are curved, for example, curved toward the horizontal center axis of the nanostructure 54. In addition, Figure 11B In the cross section of , each nanostructure 54 has a stadium shape (which may also be referred to as a racetrack shape, a disc-shaped rectangular shape, an oblong shape, or a sausage shape). Figure 11B In a cross section of FIG, the corners of each nanostructure 54 are rounded (e.g., curved). In some embodiments, the thickness T (also referred to as the sheet thickness) of the nanostructure 54 (e.g., nanosheet) is between about 1 nm and about 20 nm, and the length L1 of the nanostructure 54 (see FIG. Figure 6D ) is between about 1 nm and about 50 nm. As an example, the number of nanostructures 54 in the NSFET can be between 1 and 10, but any other suitable number can also be used.

[0072] As feature sizes continue to shrink in advanced process nodes, the distance between adjacent nanostructures 54 may become so small that it may be difficult to form layers (e.g., gate dielectric layers, work function layers) surrounding the nanostructures 54 in subsequent processing. By reshaping the nanostructures 54 (e.g., thinning the middle portion of the nanostructures 54), the distance between adjacent nanostructures 54 increases, thereby making it easier to form, for example, a gate dielectric layer 120 (see FIG. 1 ) surrounding the nanostructures 54. Figure 12A and Figure 12B Furthermore, because the thickness T of the nanostructures 54 forming the channel region 93 of the NSFET device 100 is reduced by the nanostructure reshaping process, it is easier to control (e.g., turn on or off) the NSFET device 100 by applying a gate control voltage to a metal gate formed in a subsequent process.

[0073] In some embodiments, the Figure 11A and Figure 11B In the subsequent figures, the channel region 93 of the NSFET device 100 is shown as having Figure 11A and Figure 11B It should be understood that the channel region 93 may have a cross section Figure 10A and Figure 10B cross-section (e.g., when the nanostructure reshaping process is omitted).

[0074] Next, in Figure 12A and Figure 12B, a gate dielectric material 120 and a gate electrode material 122 are formed to form a replacement gate. The gate dielectric material 120 is conformally deposited in the recess 103 (e.g., on the top surface and sidewalls of the semiconductor fin 90 and on the sidewalls of the gate spacer 108). The gate dielectric material 120 may also be formed on the top surface of the first ILD 114. Notably, the gate dielectric material 120 is formed to surround the nanostructure 54. According to some embodiments, the gate dielectric material 120 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric material 120 is formed of a high-k dielectric material, and in these embodiments, the gate dielectric material 120 may have a k value greater than approximately 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. Methods for forming the gate dielectric material 120 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0075] Next, a gate electrode material 122 is deposited over and around the gate dielectric material 120, filling the remaining portion of the recess 103. The gate electrode material 122 may include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, while a single layer of gate electrode material 122 is shown, the gate electrode material 122 may include any number of liner layers (e.g., barrier layers), any number of work function tuning layers, and filler materials (e.g., filler metals, conductive materials). After filling the gate electrode material 122, a planarization process (e.g., CMP) may be performed to remove the gate dielectric material 120 and any excess portion of the gate electrode material 122 above the top surface of the first ILD 114. The remaining portions of the gate electrode material 122 and the gate dielectric material 120 thus form the gate electrode 122 and the gate dielectric layer 120, respectively, of the replacement gate of the resulting NSFET device 100. Each gate electrode 122 and corresponding gate dielectric layer 120 may be collectively referred to as a gate stack 123 , a replacement gate structure 123 , a metal gate structure 123 , or a gate structure 123 . Each gate structure 123 extends around a corresponding nanostructure 54 .

[0076] As one of ordinary skill in the art will readily appreciate, additional processing may be performed to complete the fabrication of the NSFET device 100, and therefore the details are not discussed herein. For example, a second ILD may be formed over the first ILD 114, and source / drain contacts may be formed extending through the second ILD and the first ILD 114 to electrically couple to the source / drain regions 112. A gate contact may be formed extending through the second ILD to electrically couple to the gate structure 123. Additionally, interconnect structures including conductive lines and vias may be formed during back-end-of-line (BEOL) processing to interconnect electrical components formed in / on the substrate 50, thereby forming functional circuits.

[0077] Embodiments can achieve multiple advantages. The disclosed method and structure provide large doped regions 56 / 58 with high dopant concentrations in the nanostructures 54, which reduces the resistance of the channel region of the formed NSFET device and improves the electrical performance of the NSFET device. Compared to a reference method that omits the ion implantation process 130 and uses an etching process to recess the second semiconductor material 54, the disclosed method avoids performance issues associated with roughness sources caused by the etching process. In addition, the sloped sidewalls 54S of the second semiconductor material 54 facilitate the implantation of the first dopant into the second semiconductor material 54 and achieve a higher dopant concentration in the doped region.

[0078] Figure 13 1 is a flow chart of a method 1000 for forming a semiconductor device according to some embodiments. It should be understood that Figure 13 The embodiment methods shown are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Figure 13 The various steps shown.

[0079] refer to Figure 13 At box 1010, a fin structure is formed that protrudes above a substrate, wherein the fin structure includes a fin and a layer stack overlying the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material. At box 1020, a gate structure is formed over the fin structure. At box 1030, source / drain openings are formed in the fin structure on an opposite side of the gate structure. At box 1040, a first end portion of the first semiconductor material exposed by the source / drain opening is replaced with an internal spacer. At box 1050, after the replacement, an ion implantation process is performed, wherein the ion implantation process implants a first dopant into a second end portion of the second semiconductor material exposed by the source / drain opening. At box 1060, after performing the ion implantation process, a source / drain region is formed in the source / drain opening.

[0080] In an embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack overlying the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure above the fin structure; forming a source / drain opening in the fin structure on an opposite side of the gate structure; replacing a first end portion of the first semiconductor material exposed by the source / drain opening with an internal spacer; after the replacement, performing an ion implantation process, wherein the ion implantation process implants a first dopant into a second end portion of the second semiconductor material exposed by the source / drain opening; and after performing the ion implantation process, forming a source / drain region in the source / drain opening. In an embodiment, the method further includes, after forming the source / drain region: forming a dielectric layer over the source / drain region surrounding the gate structure; and replacing the gate structure with a replacement gate structure. In one embodiment, replacing the gate structure includes: removing the gate structure to form a recess in the dielectric layer, wherein the recess exposes a first portion of a first semiconductor material and a second portion of a second semiconductor material; after removing the gate structure, selectively removing the first portion of the first semiconductor material, wherein the second portion of the second semiconductor material remains after the selective removal to form a plurality of nanostructures; forming a gate dielectric material around the plurality of nanostructures; and forming a gate electrode material around the gate dielectric material. In one embodiment, the source / drain openings are formed with sloped sidewalls such that the width of the source / drain openings decreases as the source / drain openings extend toward the substrate. In one embodiment, a first dopant is implanted into the second end of the second semiconductor material to form a doped region in the second semiconductor material, wherein a concentration of the first dopant in the doped region increases along a depth direction from the source / drain opening toward the substrate. In one embodiment, the first doped region in the uppermost layer of the second semiconductor material distal from the substrate has a first concentration of the first dopant, while the second doped region in the lowermost layer of the second semiconductor material closest to the substrate has a second concentration of the first dopant, wherein the second concentration is between approximately two times and approximately five times the first concentration. In one embodiment, the method further comprises: performing a thermal treatment to activate the first dopant after performing the ion implantation process. In one embodiment, forming the source / drain region comprises: selectively forming a first layer of source / drain material on the second end of the second semiconductor material and on the upper surface of the fin exposed by the source / drain opening; and after selectively forming the first layer of source / drain material, forming a second layer of source / drain material to fill the source / drain opening, wherein the source / drain region is formed to have the second dopant, wherein a first concentration of the second dopant in the first layer of source / drain material is lower than a second concentration of the second dopant in the second layer of source / drain material.In one embodiment, a first doped region in the uppermost layer of the second semiconductor material distal from the substrate has a first concentration of a first dopant, wherein the first concentration of the first dopant is equal to or greater than the first concentration of a second dopant in the first layer of the source / drain material. In one embodiment, the second dopant and the first dopant are the same n-type or p-type. In one embodiment, the second dopant in the source / drain region diffuses into the doped region of the second semiconductor material, wherein the diffused second dopant increases the volume of the doped region.

[0081] In an embodiment, a method of forming a semiconductor device includes: forming a fin structure that protrudes above a substrate, wherein the fin structure includes a fin and alternating layers of a first semiconductor material and a second semiconductor material above the fin; forming a dummy gate structure above the fin structure; forming a source / drain opening in the fin structure on an opposite side of the dummy gate structure; forming an internal spacer between adjacent layers of a second semiconductor material; after forming the internal spacer, implanting a first dopant into ends of the second semiconductor material exposed by the source / drain opening; after implanting the first dopant, forming a source / drain region in the source / drain opening, wherein the source / drain region is formed to have a second dopant; forming a dielectric layer around the dummy gate structure; and replacing the dummy gate structure with a replacement gate structure. In one embodiment, replacing the dummy gate structure includes: removing the dummy gate structure to form a recess in the dielectric layer, wherein the recess exposes a first portion of the first semiconductor material and a second portion of the second semiconductor material; after removing the dummy gate structure, selectively removing the first portion of the first semiconductor material, wherein the second portion of the second semiconductor material remains after the selective removal to form a nanostructure; forming a gate dielectric material around the nanostructure; and forming a gate electrode material around the gate dielectric material. In one embodiment, the nanostructure is formed to have oppositely sloping sidewalls facing the source / drain region, wherein a length of the nanostructure measured between the oppositely sloping sidewalls of the nanostructure increases along a depth direction from the source / drain opening toward the substrate. In one embodiment, the first dopant and the second dopant are the same n-type or p-type, wherein the second dopant is diffused into the nanostructure, wherein the first dopant and the second dopant in the nanostructure are disposed in a doped region of the nanostructure. In one embodiment, a total concentration of the first dopant and the second dopant in the doped region of the nanostructure increases along a depth direction from the source / drain opening toward the substrate.

[0082] In an embodiment, a semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; a source / drain region located over the fin on an opposite side of the gate structure; and a nanostructure between the source / drain regions and below the gate structure, wherein the nanostructure is a channel region of the semiconductor device and includes a doped region in contact with the source / drain region and an undoped region between the doped regions, wherein the doped region includes a channel material and a first dopant in the channel material, wherein a dopant concentration in the doped region increases along a first direction perpendicular to a major upper surface of the substrate, wherein the first direction extends from an uppermost nanostructure farther from the substrate toward a lowermost nanostructure closest to the substrate. In an embodiment, a first doped region in a first one of the nanostructures has a first width, and a second doped region in a second one of the nanostructures has a second width greater than the first width, wherein the second nanostructure is closer to the substrate than the first nanostructure, wherein the first width and the second width are measured along a direction of current flow in the channel region. In an embodiment, the nanostructure has opposite sloping sidewalls facing the source / drain region, wherein a width of the nanostructure measured between the opposite sloping sidewalls of the nanostructure increases along a first direction. In an embodiment, the source / drain region includes a second dopant, wherein the doped region of the nanostructure further includes the second dopant, and wherein a concentration of the dopant in the doped region is a total concentration of the first dopant and the second dopant in the doped region.

[0083] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure comprises a fin and a layer stack overlying the fin, wherein the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure on the fin structure; forming source / drain openings in the fin structure on opposite sides of the gate structure; replacing a first end portion of the first semiconductor material exposed by the source / drain opening with an internal spacer; After the replacing, performing an ion implantation process, wherein the ion implantation process implants a first dopant into a second end portion of the second semiconductor material exposed by the source / drain opening; and After performing the ion implantation process, source / drain regions are formed in the source / drain openings.

2. The method according to claim 1 , further comprising, after forming the source / drain regions: forming a dielectric layer over the source / drain regions surrounding the gate structure; and The gate structure is replaced with a replacement gate structure.

3. The method according to claim 2, wherein: Replacing the gate structure includes: removing the gate structure to form a recess in the dielectric layer, wherein the recess exposes a first portion of the first semiconductor material and a second portion of the second semiconductor material; selectively removing the first portion of the first semiconductor material after removing the gate structure, wherein the second portion of the second semiconductor material remains after the selective removal to form a plurality of nanostructures; forming a gate dielectric material around the plurality of nanostructures; and A gate electrode material is formed around the gate dielectric material.

4. The method according to claim 1, wherein The source / drain openings are formed with sloped sidewalls such that a width of the source / drain openings decreases as the source / drain openings extend toward the substrate.

5. The method according to claim 4, wherein The first dopant is implanted into the second end of the second semiconductor material to form a doped region in the second semiconductor material, wherein a concentration of the first dopant in the doped region increases along a depth direction of the source / drain opening toward the substrate.

6. The method according to claim 5, wherein: A first doped region in the uppermost layer of the second semiconductor material away from the substrate has a first concentration of the first dopant, and a second doped region in the lowermost layer of the second semiconductor material closest to the substrate has a second concentration of the first dopant, wherein the second concentration is between approximately two times and approximately five times the first concentration.

7. The method according to claim 5, further comprising: After performing the ion implantation process, a heat treatment is performed to activate the first dopant.

8. The method according to claim 5, wherein Forming the source / drain region includes: selectively forming a first layer of source / drain material on the second end of the second semiconductor material and on the upper surface of the fin exposed by the source / drain opening; and After selectively forming the first layer of source / drain material, a second layer of source / drain material is formed to fill the source / drain opening, wherein the source / drain region is formed to have a second dopant, wherein a first concentration of the second dopant in the first layer of source / drain material is lower than a second concentration of the second dopant in the second layer of source / drain material.

9. A method of forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure comprises a fin and alternating layers of a first semiconductor material and a second semiconductor material over the fin; forming a dummy gate structure on the fin structure; forming source / drain openings in the fin structure on an opposite side of the dummy gate structure; forming an internal spacer between adjacent layers of the second semiconductor material; After forming the inner spacer, implanting a first dopant into the end portion of the second semiconductor material exposed by the source / drain opening; forming a source / drain region in the source / drain opening after implanting the first dopant, wherein the source / drain region is formed to have a second dopant; forming a dielectric layer around the dummy gate structure; and The dummy gate structure is replaced with a replacement gate structure.

10. A semiconductor device comprising: substrate; a fin protruding above the substrate; a gate structure located above the fin; a source / drain region located on the fin on an opposite side of the gate structure; as well as A nanostructure is located between the source / drain regions and below the gate structure, wherein the nanostructure is a channel region of the semiconductor device and includes a doped region in contact with the source / drain region and an undoped region between the doped regions, wherein the doped region includes a channel material and a first dopant in the channel material, wherein a dopant concentration in the doped region increases along a first direction perpendicular to the main upper surface of the substrate, wherein the first direction extends from an uppermost nanostructure away from the substrate toward a lowermost nanostructure closest to the substrate.

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