Super-junction MOSFET device and preparation method thereof

Abstract

The invention provides a super-junction MOSFET device and a preparation method, a super-junction structure of the super-junction MOSFET device comprises a second conductive type column, the second conductive type column extends from a first main surface to a second main surface, the second conductive type column comprises a first P column arranged in a primitive cell region and a second P column arranged in a terminal region, and the first P column is connected with the second P column. The extension lengths of the first P column and the second P column in the epitaxial layer are different. The length of the first P column and the length of the second P column are set to be different, and the breakdown voltage of the primitive cell region and the terminal region can be adjusted, so that the avalanche tolerance consistency of the super-junction MOSFET device is adjusted, and meanwhile, the unit area conduction resistance is not increased.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor device technology, and specifically to a super junction MOSFET device and a preparation method thereof. Background Art

[0002] Superjunction MOSFET devices can achieve electric field modulation with the same breakdown voltage using lower-resistivity epitaxial materials. They feature high integration, low on-resistance, fast switching speeds, and low switching losses, making them widely used in various power supplies, energy storage, and on-board charging applications. As application requirements become increasingly sophisticated, so too do the demands on the reliability of superjunction MOSFET devices.

[0003] Due to its structure and manufacturing process, super-junction MOSFET devices have lower avalanche resistance per unit area and poorer consistency than planar high-voltage VDMOS devices. Summary of the Invention

[0004] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a super junction MOSFET device and a preparation method thereof.

[0005] An embodiment of a first aspect of the present disclosure provides a super junction MOSFET device, comprising:

[0006] A semiconductor substrate having a first main surface and a second main surface opposite to each other, an epitaxial layer of a first conductivity type being disposed between the first main surface and the second main surface, the epitaxial layer comprising a unit cell epitaxial layer and a terminal epitaxial layer, the terminal epitaxial layer being connected to the unit cell epitaxial layer along a circumferential direction of the unit cell epitaxial layer;

[0007] a well layer of a second conductivity type, the well layer being formed on a side of the unit cell epitaxial layer away from the second main surface;

[0008] a super junction structure located within the epitaxial layer, the super junction structure including a second conductive type column extending from the first main surface toward the second main surface, the second conductive type column including a first P column and a second P column, the first P column being located in the unit cell region, the second P column being located in the terminal region, and the first P column and the second P column being different in length;

[0009] a source region of a first conductivity type, wherein the source region is located in the well layer;

[0010] A gate is provided in a gate conductive polysilicon trench of the outer epitaxial layer, and the gate is isolated from the source region.

[0011] In some embodiments of the present disclosure, the length of the first P-pillar is smaller than the length of the second P-pillar.

[0012] In some embodiments of the present disclosure, the super junction MOSFET device further includes:

[0013] an insulating dielectric layer, the insulating dielectric layer being provided on a side of the epitaxial layer facing away from the second main surface;

[0014] A metal lead penetrates the insulating dielectric layer along a thickness direction of the insulating dielectric layer, and the metal lead contacts the source region and the well layer respectively.

[0015] In some embodiments of the present disclosure, the super junction MOSFET device further includes:

[0016] A passivation layer is provided on a side of the insulating dielectric layer facing away from the second main surface.

[0017] In some embodiments of the present disclosure, the source region and the gate are both located between two adjacent first P columns.

[0018] In some embodiments of the present disclosure, the source region is arranged along the circumference of the gate.

[0019] In some embodiments of the present disclosure, a gate oxide layer is provided between the gate and the source region, between the gate and the cell epitaxial layer, and between the gate and the well layer.

[0020] In some embodiments of the present disclosure, the gate is gate conductive polysilicon.

[0021] A second aspect of the present disclosure provides a method for preparing a super junction MOSFET device, the method comprising:

[0022] a. providing a semiconductor substrate having a first main surface and a second main surface opposite to each other, wherein an epitaxial layer of a first conductivity type is provided between the first main surface and the second main surface;

[0023] b. depositing a hard mask layer on the first main surface of the semiconductor substrate, forming a photoresist, defining a terminal region where a deep trench needs to be formed by photolithography, removing the hard mask layer and photoresist in the terminal region by etching, and forming a hard mask window for trench etching in the terminal region on the first main surface of the semiconductor substrate;

[0024] c. using the hard mask window in the terminal region to dry-etch the semiconductor substrate on the first main surface to form a shallow trench above the unit cell epitaxial layer of the first conductivity type;

[0025] d. forming a photoresist on the first main surface of the semiconductor substrate, defining a region where a deep trench needs to be formed in the primary cell region by photolithography, removing the hard mask layer in the terminal region by etching, removing the photoresist, and forming a hard mask window for etching the primary cell region trench on the first main surface of the semiconductor substrate;

[0026] e. using the hard mask windows in the terminal region and the primary cell region, dry-etching the semiconductor substrate on the first main surface to form a first deep trench in the primary cell region and a second deep trench in the terminal region;

[0027] f. removing the hard mask layer, depositing a second conductive type epitaxial layer on the first main surface of the semiconductor substrate to fill the first deep trench and the second deep trench to form a first P column and a second P column, and removing excess second conductive type epitaxial layer by chemical mechanical polishing;

[0028] g. growing a first oxide layer on the first main surface of the semiconductor substrate, forming a photoresist, performing well region photolithography, and implanting impurity ions of the second conductivity type. After removing the photoresist, forming a well region of the second conductivity type by well driving;

[0029] h. depositing a hard mask layer on the first main surface of the semiconductor substrate, preparing a photoresist, defining a unit cell trench region by photolithography, and removing excess hard mask layer by etching to form a unit cell trench hard mask window;

[0030] i. using the primary cell trench hard mask window, dry-etching the semiconductor substrate on the first main surface to form a gate conductive polysilicon trench in the primary cell region;

[0031] j. growing a sacrificial oxide layer on the first main surface of the semiconductor substrate, removing the sacrificial oxide layer by a wet method, growing a gate oxide layer, depositing gate conductive polysilicon, preparing a photoresist, defining an area where the gate conductive polysilicon needs to be removed by photolithography, and then removing the gate conductive polysilicon in the designated area by etching;

[0032] k. Forming a photoresist on the first main surface of the semiconductor substrate, performing photolithography on the source region, and implanting first conductive type impurity ions. After removing the photoresist, forming a first conductive type source region by well driving;

[0033] 1. depositing an insulating dielectric layer on the first main surface of the semiconductor substrate;

[0034] m. performing photolithography and etching on the insulating dielectric layer to form contact holes on both sides of the gate conductive polysilicon;

[0035] n. Depositing a first metal layer on the insulating dielectric layer, wherein the first metal layer covers the insulating dielectric layer and fills the contact hole to form a metal connection; the metal connection is in ohmic contact with the first conductive type source region and the second conductive type well layer.

[0036] In some embodiments of the present disclosure, after step m, the method further includes:

[0037] o. Depositing a passivation layer on the metal connection line, forming a photoresist on the passivation layer to define a metal lead window, and forming the metal lead window by dry etching the passivation layer.

[0038] According to the superjunction MOSFET device and fabrication method of the embodiments of the present disclosure, the superjunction structure includes a second-conductivity-type pillar, which extends from the first main surface toward the second main surface. The second-conductivity-type pillar includes a first P-pillar provided in the primary cell region and a second P-pillar provided in the terminal region, and the first P-pillar and the second P-pillar have different extension lengths within the epitaxial layer. By setting the lengths of the first P-pillar and the second P-pillar to different lengths, the breakdown voltage of the primary cell region and the terminal region can be adjusted, thereby adjusting the consistency of the avalanche resistance of the superjunction MOSFET device, while not increasing the unit area on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a top view of a super junction MOSFET device according to an embodiment of the present disclosure;

[0040] Figure 2 for Figure 1 A cross-sectional view of a super junction MOSFET device shown;

[0041] Figure 3 A comparison diagram of the breakdown voltages of the cell region and the terminal region of a super junction MOSFET device in the prior art;

[0042] Figure 4 3 is a comparison diagram of the breakdown voltages of the primary cell region and the terminal region of the super junction MOSFET device of this embodiment.

[0043] The reference numerals in the accompanying drawings represent the following:

[0044] 100. Super junction MOSFET devices;

[0045] 10. Substrate; 20. Epitaxial layer; 30. Well layer; 40. Super junction structure; 41. First P column; 41. Second P column; 50. Source region; 60. Gate; 61. Gate oxide layer; 70. Insulating dielectric layer; 80. Metal lead; 90. Passivation layer; 201. Cell region; 202. Terminal region. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of the stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The control method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0048] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates otherwise, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0049] For ease of description, spatially relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures, such as "inside," "outside," "inside," "outside," "below," "beneath," "above," and the like. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "below" another element or feature would then be oriented as "above" or "above" another element or feature. Thus, the example term "below" can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

[0050] like Figure 1 and Figure 2 As shown, an embodiment of the first aspect of the present disclosure provides a super junction MOSFET device 100, comprising: a semiconductor substrate, a well layer 30 of a second conductivity type, a super junction structure 40, a source region 50 of a first conductivity type, and a gate 60. Specifically, the semiconductor substrate has a first main surface and a second main surface relative to each other, an epitaxial layer 20 of a first conductivity type is included between the first main surface and the second main surface, the epitaxial layer 20 includes a unit cell epitaxial layer 21 and a terminal epitaxial layer 22, the terminal epitaxial layer 22 is connected to the unit cell epitaxial layer 21 along the circumference of the unit cell epitaxial layer 21, the well layer 30 of the second conductivity type is formed on the side of the unit cell epitaxial layer 21 away from the second main surface, the super junction structure 40 is located in the epitaxial layer 20, the source region 50 of the first conductivity type is located in the well layer 30, the gate 60 is arranged in a gate conductive polysilicon trench of the outer unit cell epitaxial layer 21, and the gate 60 is isolated from the source region 50. Among them, the super junction structure 40 includes a second conductive type column, which extends from the first main surface to the second main surface. The second conductive type column includes a first P column 41 and a second P column 42. The first P column 41 is arranged in the original cell area 201, and the second P column 42 is arranged in the terminal area 202. The lengths of the first P column 41 and the second P column 42 are different.

[0051] According to the superjunction MOSFET device 100 of the embodiment of the present disclosure, the superjunction structure 40 includes second-conductivity-type pillars, which extend from the first main surface toward the second main surface. The second-conductivity-type pillars include a first P-pillar 41 provided in the primary cell region 201 and a second P-pillar 42 provided in the terminal region 202. The first P-pillar 41 and the second P-pillar 42 extend to different lengths within the epitaxial layer 20. By setting the lengths of the first P-pillar 41 and the second P-pillar 42 to different lengths, the breakdown voltage of the primary cell region 201 and the terminal region 202 can be adjusted, thereby adjusting the consistency of the avalanche withstand capability of the superjunction MOSFET device 100, while not increasing the unit area on-resistance.

[0052] In some embodiments of the present disclosure, both the first P column and the second P column extend from the side of the epitaxial layer 20 away from the second main surface toward the inside of the epitaxial layer 20, that is, the starting positions of the first P column and the second P column are in the same plane. The length of the first P column 41 is less than the length of the second P column 42. By setting the length of the first P column 41 in the original cell area 201 to be less than the length of the second P column 42 in the terminal area 202, the breakdown voltage of the terminal area 202 can be stably higher than the breakdown voltage of the original cell area 201, thereby improving the avalanche resistance consistency of the super junction MOSFET device 100, and at the same time, it will not increase the on-resistance per unit area. The super junction MOSFET device 100 of this embodiment, Figure 3 A comparison diagram of the breakdown voltages of the cell region and the terminal region of a super junction MOSFET device in the prior art; Figure 4 : is a comparison diagram of the breakdown voltage of the primary cell region and the terminal region of the super junction MOSFET device of this embodiment, Figure 3 and Figure 4 The horizontal axis is the N / P dose ratio, that is, the dose ratio of the N column doping ions to the P column doping ions, and the vertical axis is the BV breakdown voltage. Figure 3 and Figure 4 By comparison, it can be seen that the breakdown voltage of the terminal region 202 is stably higher than the breakdown voltage of the original cell region 201.

[0053] In some embodiments of the present disclosure, the superjunction MOSFET device 100 further includes an insulating dielectric layer 70 and a metal lead 80. The insulating dielectric layer 70 is disposed on a side of the epitaxial layer 20 facing away from the second main surface, and covers the epitaxial layer 20. The metal lead 80 penetrates the insulating dielectric layer 70 along the thickness direction of the insulating dielectric layer 70, and contacts the source region 50 and the well layer 30, respectively.

[0054] In some embodiments of the present disclosure, the super junction MOSFET device 100 further includes a passivation layer 90 . The passivation layer 90 is disposed on a side of the insulating dielectric layer 70 facing away from the second main surface, and the passivation layer 90 covers the insulating dielectric layer 70 .

[0055] In some embodiments of the present disclosure, the source region 50 and the gate 60 are both located between two adjacent first P-pillars 41, and the source region 50 is arranged along the circumference of the gate 60. Specifically, the source region 50 is provided in the well layer 30, and the gate 60 is located in a gate conductive polysilicon trench of the unit cell epitaxial layer 21. The gate conductive polysilicon trench extends from the source region 50 through the well layer 30 to the unit cell region 201, and the gate 60 is located between two adjacent first P-pillars 41.

[0056] In some embodiments of the present disclosure, a gate oxide layer 61 is provided between the gate 60 and the source region 50, a gate oxide layer 61 is provided between the gate 60 and the cell epitaxial layer 21, and a gate oxide layer 61 is provided between the gate 60 and the well layer 30. The gate oxide layer 61 isolates the gate 60 from the source region 50, the cell epitaxial layer 21, and the well layer 30 respectively.

[0057] In some embodiments of the present disclosure, the gate 60 is gate conductive polysilicon.

[0058] A second aspect of the present disclosure provides a method for preparing a super junction MOSFET device, the method comprising:

[0059] a. providing a semiconductor substrate having a first main surface and a second main surface opposite to each other, wherein a first conductivity type epitaxial layer is provided between the first main surface and the second main surface;

[0060] b. depositing a hard mask layer on the first main surface of the semiconductor substrate, forming a photoresist, defining a terminal region where a deep trench needs to be formed by photolithography, removing the hard mask layer and photoresist in the terminal region by etching, and forming a hard mask window for trench etching in the terminal region on the first main surface of the semiconductor substrate;

[0061] c. using the hard mask window in the terminal region to dry-etch the semiconductor substrate on the first main surface to form a shallow trench above the first conductive type unit cell epitaxial layer;

[0062] d. forming a photoresist on the first main surface of the semiconductor substrate, defining a region where a deep trench needs to be formed in the primary cell region by photolithography, removing the hard mask layer in the terminal region by etching, removing the photoresist, and forming a hard mask window for etching the primary cell region trench on the first main surface of the semiconductor substrate;

[0063] e. using the hard mask windows in the terminal region and the primary cell region, dry-etching the semiconductor substrate on the first main surface to form a first deep trench in the primary cell region and a second deep trench in the terminal region;

[0064] f. removing the hard mask layer, depositing a second conductive type epitaxial layer on the first main surface of the semiconductor substrate to fill the first deep trench and the second deep trench to form a first P column and a second P column, and removing excess second conductive type epitaxial layer by chemical mechanical polishing;

[0065] g. growing a first oxide layer on the first main surface of the semiconductor substrate, forming a photoresist, performing well region photolithography, and implanting second conductivity type impurity ions. After removing the photoresist, forming a second conductivity type well region by well driving;

[0066] h. depositing a hard mask layer on the first main surface of the semiconductor substrate, preparing a photoresist, defining a unit cell trench region by photolithography, and removing excess hard mask layer by etching to form a unit cell trench hard mask window;

[0067] i. using the primary cell trench hard mask window, dry-etching the semiconductor substrate on the first main surface to form a gate conductive polysilicon trench in the primary cell region;

[0068] j. growing a sacrificial oxide layer on the first main surface of the semiconductor substrate, removing the sacrificial oxide layer by a wet method, growing a gate oxide layer, depositing gate conductive polysilicon, preparing a photoresist, defining an area where the gate conductive polysilicon needs to be removed by photolithography, and then removing the gate conductive polysilicon in the designated area by etching;

[0069] k. Forming a photoresist on the first main surface of the semiconductor substrate, performing photolithography on the source region, and implanting first conductive type impurity ions. After removing the photoresist, forming a first conductive type source region by well driving;

[0070] 1. depositing an insulating dielectric layer on the first main surface of the semiconductor substrate;

[0071] m. performing photolithography and etching on the insulating dielectric layer to form contact holes on both sides of the gate conductive polysilicon;

[0072] n. Depositing a first metal layer on the insulating dielectric layer, wherein the first metal layer covers the insulating dielectric layer and fills the contact hole to form a metal connection; the metal connection is in ohmic contact with the first conductive type source region and the second conductive type well layer.

[0073] In some embodiments of the present disclosure, after step m, the method further includes:

[0074] o. Depositing a passivation layer on the metal connection line, forming a photoresist on the passivation layer to define a metal lead window, and forming the metal lead window by dry etching the passivation layer.

[0075] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A super junction MOSFET device, characterized in that: include: A semiconductor substrate having a first main surface and a second main surface opposite to each other, an epitaxial layer of a first conductivity type being disposed between the first main surface and the second main surface, the epitaxial layer comprising a unit cell epitaxial layer and a terminal epitaxial layer, the terminal epitaxial layer being connected to the unit cell epitaxial layer along a circumferential direction of the unit cell epitaxial layer; a well layer of a second conductivity type, the well layer being formed on a side of the unit cell epitaxial layer away from the second main surface; a super junction structure located within the epitaxial layer, the super junction structure including a second conductive type column extending from the first main surface toward the second main surface, the second conductive type column including a first P column and a second P column, the first P column being located in the unit cell region, the second P column being located in the terminal region, and the first P column and the second P column being different in length; a source region of a first conductivity type, wherein the source region is located in the well layer; A gate is provided in a gate conductive polysilicon trench of the outer epitaxial layer, and the gate is isolated from the source region.

2. The super junction MOSFET device according to claim 1, wherein: The length of the first P-pillar is smaller than the length of the second P-pillar.

3. The super junction MOSFET device according to claim 1, wherein: The super junction MOSFET device further comprises: an insulating dielectric layer, the insulating dielectric layer being provided on a side of the epitaxial layer facing away from the second main surface; A metal lead penetrates the insulating dielectric layer along a thickness direction of the insulating dielectric layer, and the metal lead contacts the source region and the well layer respectively.

4. The super junction MOSFET device according to claim 3, wherein: The super junction MOSFET device further comprises: A passivation layer is provided on a side of the insulating dielectric layer facing away from the second main surface.

5. The super junction MOSFET device according to claim 1, wherein: The source region and the gate are both located between two adjacent first P columns.

6. The super junction MOSFET device according to claim 5, characterized in that: The source region is arranged along the circumference of the gate.

7. The super junction MOSFET device according to claim 5, characterized in that: A gate oxide layer is provided between the gate and the source region, between the gate and the cell epitaxial layer, and between the gate and the well layer.

8. The super junction MOSFET device according to claim 1, wherein: The gate is gate conductive polysilicon.

9. A method for preparing a super junction MOSFET device, characterized in that: The preparation method comprises: a. providing a semiconductor substrate having a first main surface and a second main surface opposite to each other, wherein a first conductivity type epitaxial layer is provided between the first main surface and the second main surface; b. depositing a hard mask layer on the first main surface of the semiconductor substrate, forming a photoresist, defining a terminal region where a deep trench needs to be formed by photolithography, removing the hard mask layer and photoresist in the terminal region by etching, and forming a hard mask window for trench etching in the terminal region on the first main surface of the semiconductor substrate; c. using the hard mask window in the terminal region to dry-etch the semiconductor substrate on the first main surface to form a shallow trench above the unit cell epitaxial layer of the first conductivity type; d. forming a photoresist on the first main surface of the semiconductor substrate, defining a region where a deep trench needs to be formed in the primary cell region by photolithography, removing the hard mask layer in the terminal region by etching, removing the photoresist, and forming a hard mask window for etching the primary cell region trench on the first main surface of the semiconductor substrate; e. using the hard mask windows in the terminal region and the primary cell region, dry-etching the semiconductor substrate on the first main surface to form a first deep trench in the primary cell region and a second deep trench in the terminal region; f. removing the hard mask layer, depositing a second conductive type epitaxial layer on the first main surface of the semiconductor substrate to fill the first deep trench and the second deep trench to form a first P column and a second P column, and removing excess second conductive type epitaxial layer by chemical mechanical polishing; g. growing a first oxide layer on the first main surface of the semiconductor substrate, forming a photoresist, performing well region photolithography, and implanting second conductivity type impurity ions. After removing the photoresist, forming a second conductivity type well region by well driving; h. depositing a hard mask layer on the first main surface of the semiconductor substrate, preparing a photoresist, defining a unit cell trench region by photolithography, and removing excess hard mask layer by etching to form a unit cell trench hard mask window; i. using the primary cell trench hard mask window, dry-etching the semiconductor substrate on the first main surface to form a gate conductive polysilicon trench in the primary cell region; j. growing a sacrificial oxide layer on the first main surface of the semiconductor substrate, removing the sacrificial oxide layer by a wet method, growing a gate oxide layer, depositing gate conductive polysilicon, preparing a photoresist, defining an area where the gate conductive polysilicon needs to be removed by photolithography, and then removing the gate conductive polysilicon in the designated area by etching; k. Forming a photoresist on the first main surface of the semiconductor substrate, performing photolithography on the source region, and implanting first conductive type impurity ions. After removing the photoresist, forming a first conductive type source region by well driving; 1. depositing an insulating dielectric layer on the first main surface of the semiconductor substrate; m. performing photolithography and etching on the insulating dielectric layer to form contact holes on both sides of the gate conductive polysilicon; n. Depositing a first metal layer on the insulating dielectric layer, wherein the first metal layer covers the insulating dielectric layer and fills the contact hole to form a metal connection; the metal connection is in ohmic contact with the source region of the first conductivity type and the well layer of the second conductivity type.

10. The method for preparing a super junction MOSFET device according to claim 9, wherein: After step m, the method further includes: o. Depositing a passivation layer on the metal connection line, forming a photoresist on the passivation layer to define a metal lead window, and forming the metal lead window by dry etching the passivation layer.

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