Self-aligned bigrid MOSFET and manufacturing process thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a self-aligned bigrid MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is composed of a plurality of MOS cells which are connected in parallel, each MOS cell sequentially comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode from bottom to top, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P + layer, a P-type doped region is formed inside the N drift layer and below the grid electrode through ion implantation, and the P-type doped region is in ohmic contact with the grid electrode. According to the invention, the P-type doped region is constructed below the grid electrode and ohmic contact is realized, so that the contact resistance of the grid electrode is obviously reduced; and meanwhile, a self-aligned N-type doped gate is deposited in the P-type region, so that the gate control structure is accurately aligned with the channel position. According to the design, the control capability of the grid electrode on a channel carrier is improved, the conduction loss is synchronously reduced, and the switch response speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a self-aligned dual-gate MOSFET and a manufacturing process thereof. Background Art

[0002] Current high-voltage MOSFET devices, in their pursuit of high withstand voltage and low conduction losses, often face challenges such as insufficient gate control capability, uneven electric field distribution in the drift region, and complex manufacturing processes. Conventional structures suffer from high gate contact resistance, leading to increased switching losses. The lack of effective charge balancing in the drift region can easily lead to localized electric field concentration, reducing breakdown voltage. Furthermore, the existing dual-gate process relies on multiple photolithography alignments, which can easily introduce overlay errors, limiting device performance and increasing manufacturing costs.

[0003] An existing patent discloses a self-aligned dual-trench MOSFET structure and its manufacturing method (publication number CN115513288A). After forming a first semiconductor layer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type on a substrate, the structure utilizes different etch selectivities between first to fourth hard masks, combined with a spacer process, to form an array of self-aligned gate and source trenches in an alternating pattern within the first semiconductor layer. This existing patent relies on a trench spacer process to achieve gate / source trench self-alignment. While this reduces the number of photolithography steps, it fails to optimize gate contact resistance and electric field distribution, resulting in high switching losses and limited withstand voltage. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a self-aligned dual-gate MOSFET and its manufacturing process, which solves the problem that the comparative documents cannot take into account low loss, high voltage resistance and high frequency response at the same time.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a self-aligned dual-gate MOSFET is provided, comprising a plurality of MOS cells connected in parallel. Each MOS cell comprises, from bottom to top, a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer, and a P+ layer. A P-type doped region is formed by ion implantation within the N drift layer and below the gate. The P-type doped region is in ohmic contact with the gate. A plurality of N-type doped gates are deposited in parallel inside the P-type doped region.

[0006] Furthermore, a heavily doped N+ layer is formed inside the N drift layer by ion implantation.

[0007] Furthermore, the cross-sectional profile of the heavily doped N+ layer is in a "U" shape, and two ends of the heavily doped N+ layer are in contact with the P-well layers on both sides respectively.

[0008] Furthermore, the N-drift layer further includes a semicircular drift layer, which is located below the P-well layer and in contact with the P-well layer.

[0009] Furthermore, a semicircular P- layer is provided inside the N drift layer and below the P well layer and the P+ layer, and the top of the semicircular P- layer is in direct contact with both the P well layer and the P+ layer.

[0010] Furthermore, a plurality of mutually parallel P-type doped gates are provided inside the N-drift layer and below the P-well layer, and the tops of the P-type doped gates are in direct contact with the P-well layer.

[0011] Furthermore, the P-type doped gate is located inside the semicircular P-layer.

[0012] A manufacturing process for a self-aligned dual-gate MOSFET, specifically comprising: S1. Provide an N-type substrate and epitaxially grow an N drift layer on the surface thereof; S2. Forming a P-type doped region, a semicircular P-layer, and a P-type doped gate in the N-drift layer through photolithography and ion implantation processes, wherein the semicircular P-layer is located below a predetermined region of the P-well layer, and the P-type doped gate is embedded in the semicircular P-layer; S3, epitaxially growing an N-well layer on the surface of the N-drift layer; S4, forming a P-well layer and a P+ layer on the N-well layer in sequence, and opening a groove above the semicircular P-layer by photolithography and etching processes to expose the top of the P-type doped gate; S5, depositing an N-type doped gate inside the P-type doped region so as to be self-aligned with the gate position; S6. Deposit drain, source and gate metal layers in sequence to complete ohmic contact and interconnection.

[0013] Furthermore, the ion implantation energy of the P-type doping region in step S2 is 50-200 keV; the implantation angle of the semicircular P-layer is 7°-30°, so as to achieve lateral diffusion and contact with the bottom of the P-well layer.

[0014] The present invention provides a self-aligned dual-gate MOSFET and a manufacturing process thereof. Compared with the prior art, the present method achieves the following effects: 1. This invention significantly reduces gate contact resistance by constructing a P-type doped region beneath the gate and achieving ohmic contact. Simultaneously, a self-aligned N-type doped gate is deposited within the P-type region, allowing the gate-controlled structure to precisely align with the channel. This design not only enhances the gate's ability to control channel carriers, but also simultaneously reduces conduction losses and enhances switching response speed.

[0015] 2. This invention utilizes a U-shaped heavily doped N+ layer that penetrates the N-drift layer and connects the P-well layers on either side, forming a low-resistance conductive path. Its unique U-shaped cross-sectional design expands the cross-sectional area for carrier flow, effectively suppressing the parasitic JFET effect, thereby significantly improving the device's conduction characteristics and enhancing its current-carrying capacity.

[0016] 3. This invention optimizes the vertical and lateral electric field distribution by introducing a semicircular drift layer and a semicircular P-layer, making the depletion region more uniform. This structure effectively alleviates electric field concentration at the device edge, significantly improving breakdown voltage and avalanche resistance while reducing leakage risk and ensuring reliability under high-voltage conditions.

[0017] 4. The present invention provides a vertically penetrating P-type doped gate beneath the P-well layer to form a high-speed carrier extraction channel. This structure accelerates hole extraction during the turn-off phase, significantly shortening switching time and reducing switching losses, making it particularly suitable for high-frequency applications.

[0018] 5. The present invention's manufacturing process utilizes a triple-mask integrated technique to simultaneously form multiple doped regions, reducing the number of photolithography steps. Combining tilted implantation with self-aligned deposition allows for precise control of key structures. This process not only improves superjunction charge balance accuracy but also significantly reduces parameter dispersion, enhancing mass production yield and device consistency.

[0019] 6. The nested design of the semicircular P-layer and the internal P-type doped gate in this invention creates a synergistic optimization: the semicircular layer improves longitudinal electric field uniformity, while the P-type gate provides a lateral carrier path. This combination effectively reduces dynamic resistance, and the exposed contact terminals through the slots improve ohmic connection reliability, further enhancing latch-up resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of Example 1 of the present invention; Figure 2 This is a schematic diagram of Example 2 of the present invention; Figure 3 This is a schematic diagram of Example 3 of the present invention; Figure 4 This is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of Example 5 of the present invention; Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0021] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N substrate layer; 5. N drift layer; 6. N well layer; 7. P well layer; 8. P+ layer; 9. P-type doped region; 10. N-type doped gate; 11. Heavily doped N+ layer; 12. Semicircular P- layer; 13. P-type doped gate; 51. Semicircular drift layer. DETAILED DESCRIPTION

[0022] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 6 As shown, a manufacturing process of a self-aligned dual-gate MOSFET specifically includes: Step 1: Provide an N-type substrate 4 and epitaxially grow an N-drift layer 5 on its surface. Selecting a low-defect-density N-type single-crystalline silicon substrate provides a perfect lattice-matching foundation for the subsequent epitaxial layers. Using a hydrogen-reduced silane method, the N-drift layer 5 is grown at 1050°C with a controllable thickness (concentration gradient ≤ ±5%), improving breakdown voltage consistency to over 98% while minimizing the risk of leakage due to lattice mismatch.

[0024] Step 2: Through photolithography and ion implantation processes, a P-type doped region 9, a semicircular P-layer 12 and a P-type doped gate 13 are formed in the N-drift layer 5, wherein the semicircular P-layer 12 is located below a predetermined region of the P-well layer, and the P-type doped gate 13 is embedded in the semicircular P-layer 12; in step S2, the ion implantation energy of the P-type doped region 9 is 50-200 keV; the implantation angle of the semicircular P-layer 12 is 7°-30° to achieve lateral diffusion and contact with the bottom of the P-well layer 7.

[0025] A triple-mask integrated process is used to simultaneously form three P-type structures, reducing the number of photolithography steps by 30%. Energy gradient implantation is used to control the vertical junction depth of the P-type doped region 9 (0.5-2μm), combined with 7°-30° tilted implantation to achieve lateral diffusion of the semicircular P-layer 12 (width deviation <0.1μm), reducing device parameter dispersion to less than 5%, significantly improving mass production yield.

[0026] Step 3: Epitaxially grow an N-well layer 6 on the surface of the N-drift layer 5. This high-purity N-well layer 6 is grown epitaxially under low temperature (900°C) and low pressure (100 Torr). This process suppresses the re-diffusion of impurities in the P-type region 9 caused by high temperatures, maintains the doping steepness (transition region <0.05μm), ensures superjunction charge balance accuracy of over 99.3%, and reduces leakage current by an order of magnitude.

[0027] Step 4: forming a P-well layer 7 and a P+ layer 8 on the N-well layer 6 in sequence, and opening a groove above the semicircular P-layer 12 by photolithography and etching to expose the top of the P-type doped gate 13; Boron / indium co-implantation forms a concentration-gradient P-well layer 7, and reactive ion etching is used to create a groove above the P-layer 12. The groove depth is controlled to within ±5nm, precisely exposing the top of the P-type doped gate 13, reducing the trap density at the contact interface and lowering the contact resistance by 40%.

[0028] Step 5: depositing an N-type doped gate 10 inside the P-type doped region 9 so that it is self-aligned with the gate 3; An N-type doped gate 10 is selectively grown within the P-type doped region 9 using LPCVD. A self-aligned process minimizes the positional deviation between the gate 3 and the channel by less than 50nm. This step eliminates the overlay errors associated with traditional photolithography, improving transconductance by 25% and reducing switching delay to the 5ns level.

[0029] Step 6: Deposit drain 1, source 2 and gate 3 metal layers in sequence to complete ohmic contact and interconnection.

[0030] A low-resistance ohmic contact is formed using a multilayer metal deposition process of Ti / TiN / W (thickness ratio of 100:50:200nm) combined with rapid thermal annealing (650°C / 30s). This improves thermal stability to over 300°C, increasing device power density by 35% and extending device lifetime by three times.

[0031] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a self-aligned dual-gate MOSFET is provided, which is composed of a plurality of MOS cells connected in parallel. A single MOS cell includes, from bottom to top, a drain 1, a semiconductor epitaxial layer, a gate 3, and a source 2. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7, and a P+ layer 8. It is characterized in that: a P-type doped region 9 is formed by ion implantation inside the N drift layer 5 and below the gate 3. The P-type doped region 9 is in ohmic contact with the gate 3; and a plurality of N-type doped gates 10 are deposited inside the P-type doped region 9 and are arranged in parallel.

[0032] The P-type doped region 9 forms an ohmic contact with the gate 3, significantly reducing gate contact resistance. Simultaneously, an N-type doped gate 10 is deposited within the P-type region, and a self-aligned process allows the N-type gate to be precisely positioned below the channel, enhancing gate control capability. This structure maintains low gate resistance while improving switching response speed and reducing conduction losses by over 15%.

[0033] Example 2 like Figure 2 As shown, a heavily doped N+ layer 11 is formed inside the N drift layer 5 by ion implantation. The cross-sectional profile of the heavily doped N+ layer 11 is in a "U" shape, and the two ends of the heavily doped N+ layer 11 are in contact with the P well layers 7 on both sides respectively.

[0034] A U-shaped heavily doped N+ layer 11 penetrates the N-drift layer 5 and connects the P-well layers 7 on either side, forming a low-resistance current path. The U-shaped cross-section increases the conductive cross-sectional area, reducing on-resistance by 20%. The contact between the N+ layer and the P-well suppresses the parasitic JFET effect, increasing current density to 1.5 times that of traditional MOSFETs.

[0035] Example 3 like Figure 3 As shown, the N-drift layer 5 further includes a semicircular drift layer 51 . The semicircular drift layer 51 is located below the P-well layer 7 and contacts the P-well layer 7 .

[0036] The semicircular drift layer 51 is embedded in the N-drift layer 5 and directly contacts the P-well layer 7. Its arc profile optimizes the electric field distribution. This structure makes the depletion region more uniform laterally, raising the breakdown voltage to over 650V while reducing reliability risks caused by electric field concentration at the device edges.

[0037] Example 4 like Figure 4 As shown, a semicircular P- layer 12 is provided inside the N drift layer 5 and below the P well layer 7 and the P+ layer 8 . The top of the semicircular P- layer 12 is in direct contact with both the P well layer 7 and the P+ layer 8 .

[0038] The semicircular P-layer 12 is located below the P-well layer 7 and P+ layer 8, and is laterally diffused by angled ion implantation. Its top contacts the P-well or P+ layer to form a charge-balancing layer, suppressing premature breakdown of the N-drift layer 5, reducing leakage current by an order of magnitude, and improving avalanche resistance by 30%.

[0039] Example 5 like Figure 5 As shown, a plurality of mutually parallel P-type doped gates 13 are provided inside the N-drift layer 5 and below the P-well layer 7 , and the tops of the P-type doped gates 13 are in direct contact with the P-well layer 7 .

[0040] The P-type doped gate 13 vertically penetrates the N-drift layer 5 and directly connects to the P-well layer 7, forming a high-speed carrier extraction channel. This structure accelerates hole extraction during shutdown, shortening the turn-off time to less than 15ns and reducing switching losses by 40%, making it particularly suitable for high-frequency applications.

[0041] Example 6 like Figure 6 As shown, a semicircular P-layer 12 is provided inside the N drift layer 5 and below the P well layer 7 and the P+ layer 8. The top of the semicircular P-layer 12 is in direct contact with the P well layer 7 and the P+ layer 8. A plurality of mutually parallel P-type doped gates 13 are provided inside the N drift layer 5 and below the P well layer 7. The top of the P-type doped gate 13 is in direct contact with the P well layer 7. The P-type doped gate 13 is located inside the semicircular P-layer 12.

[0042] The semicircular P-layer 12 and the internal P-type doped gate 13 form a synergistic structure: the semicircular layer optimizes the longitudinal electric field, while the P-type gate provides a lateral carrier path. This combination reduces dynamic resistance by 25%. Furthermore, the S4 step, during which the top of the P-type gate is exposed, ensures ohmic contact reliability and improves the device's latch-up resistance.

[0043] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A self-aligned dual-gate MOSFET, comprising a plurality of MOS cells connected in parallel, wherein each MOS cell comprises, from bottom to top, a drain (1), a semiconductor epitaxial layer, a gate (3), and a source (2), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7), and a P+ layer (8), and is characterized in that: A P-type doping region (9) is formed inside the N-drift layer (5) and below the gate (3) by ion implantation, and the P-type doping region (9) is in ohmic contact with the gate (3); A plurality of mutually parallel N-type doped gates (10) are deposited inside the P-type doped region (9).

2. The self-aligned dual-gate MOSFET according to claim 1, wherein: A heavily doped N+ layer (11) is formed inside the N drift layer (5) by ion implantation.

3. The self-aligned dual-gate MOSFET according to claim 2, wherein: The cross-sectional profile of the heavily doped N+ layer (11) is in a "U" shape, and two ends of the heavily doped N+ layer (11) are in contact with the P-well layers (7) on both sides respectively.

4. The self-aligned dual-gate MOSFET according to claim 1, wherein: The N drift layer (5) further includes a semicircular drift layer (51), which is located below the P well layer (7) and in contact with the P well layer (7).

5. The self-aligned dual-gate MOSFET according to claim 1, wherein: A semicircular P-layer (12) is provided inside the N drift layer (5) and below the P well layer (7) and the P+ layer (8), and the top of the semicircular P-layer (12) is in direct contact with both the P well layer (7) and the P+ layer (8).

6. The self-aligned dual-gate MOSFET according to claim 1, wherein: A plurality of mutually parallel P-type doped gates (13) are provided inside the N drift layer (5) and below the P well layer (7), and the tops of the P-type doped gates (13) are in direct contact with the P well layer (7).

7. The self-aligned dual-gate MOSFET according to claim 5 or 6, wherein: The P-type doped gate (13) is located inside the semicircular P-layer (12).

8. A process for manufacturing a self-aligned dual-gate MOSFET, characterized in that: The self-aligned dual-gate MOSFET according to claim 7, wherein the manufacturing process of the self-aligned dual-gate MOSFET specifically comprises: S1, providing an N-type substrate (4), and epitaxially growing an N-drift layer (5) on the surface thereof; S2. Forming a P-type doped region (9), a semicircular P-layer (12), and a P-type doped gate (13) in the N-drift layer (5) through photolithography and ion implantation processes, wherein the semicircular P-layer (12) is located below a predetermined region of the P-well layer, and the P-type doped gate (13) is embedded in the semicircular P-layer (12); S3, epitaxially growing an N well layer (6) on the surface of the N drift layer (5); S4, forming a P-well layer (7) and a P+ layer (8) on the N-well layer (6) in sequence, and opening a groove above the semicircular P-layer (12) by photolithography and etching processes to expose the top of the P-type doped gate (13); S5, depositing an N-type doped gate (10) inside the P-type doped region (9) so as to be self-aligned with the gate (3); S6. Depositing drain (1), source (2) and gate (3) metal layers in sequence to complete ohmic contact and interconnection.

9. The process for manufacturing a self-aligned dual-gate MOSFET according to claim 8, wherein: The ion implantation energy of the P-type doping region (9) in step S2 is 50-200 keV; the implantation angle of the semicircular P-layer (12) is 7°-30°, so as to achieve lateral diffusion and contact with the bottom of the P-well layer (7).

Images