Super junction MOSFET and manufacturing method thereof

Abstract

The invention discloses a super junction MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a first epitaxial layer comprises a first conductive type doped first epitaxial sub-layer and an undoped second epitaxial sub-layer, and the second epitaxial sub-layer has a first thickness. A plurality of second conductive type columns are formed in the first epitaxial layer. The super-junction MOSFET comprises an active region, a transition region and a terminal region; a first well region and a second well region which are deeper than the second epitaxial sub-layer are formed in the active region and the transition region. In the terminal region, the first conductive type column comprises a second epitaxial sub-layer, and the first thickness is set according to the requirement of a first relation curve between the terminal breakdown voltage of the super junction structure of the terminal region and the first doping concentration of the second conductive type column; the doping concentration of the second conductive type column is set to be central doping or slightly light doping on the first relation curve, and it is guaranteed that the terminal breakdown voltage is larger than or equal to the breakdown voltage required value. The invention further discloses a manufacturing method of the super junction MOSFET. The invention can enlarge the process window and improve the consistency of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; the present invention also relates to a method for manufacturing a super junction MOSFET. Background Art

[0002] Compared to traditional VDMOS, superjunction MOSFETs (superjunction MOSFETs) have been widely used in various electronic and power fields due to their superior device characteristics. The unique N- and P-pillars in the superjunction MOSFET structure compensate for each other, expanding the area of ​​the PN built-in electric field and enabling high breakdown voltages in dense N-type epitaxial (NEPI) structures. This results in low on-resistance and high breakdown voltages that exceed the limits of silicon.

[0003] The main manufacturing processes for super-junction MOSFET devices currently include two main types. One is a multiple epitaxial doping process, which forms a voltage-resistant layer through multiple epitaxy and forms P-type or PN doping types in each epitaxial layer, ultimately forming a structure in which P-type columns 103 and N-type columns are arranged alternately. The other is a deep trench filling process, which forms a structure in which multiple P-type columns 103 and N-type columns are arranged alternately through deep trench etching and trench filling on a thick first epitaxial layer 102. In the multiple epitaxial doping process, the epitaxial thickness is relatively fixed each time, and the number of epitaxies increases with the increase of breakdown voltage, which leads to higher costs. Relatively speaking, the existing deep trench filling process is easier to achieve a smaller aspect ratio. At the same time, the doping distribution of the super-junction N and P regions formed is more uniform, which is conducive to reducing Rsp. More importantly, the process is simpler and less expensive.

[0004] In existing deep trench technology, the breakdown voltage (BV) of a superjunction MOSFET's active region is borne by the longitudinal electric field formed by PN column depletion. In the device's terminal region, the breakdown voltage is borne by the surface electric field formed by PN column depletion. During device design and fabrication, it is often difficult to align the relationship between the lateral BV of the terminal region and the P-type impurity concentration with the relationship between the BV of the active region and the P-type impurity concentration. This results in a loss of the device's critical process window and compromises device BV consistency. The current solution is to increase the terminal BV—to a value greater than or close to the active region BV—to minimize avalanche breakdown within the device, rather than on the surface, thereby improving the device's overall withstand voltage. Another challenge with superjunction MOSFETs is poor reverse recovery characteristics. Due to the large PN junction area of ​​superjunction MOSFETs, the parasitic body diode injects a large amount of minority carrier charge when turned on. Furthermore, the lateral depletion of the N and P columns is rapid, easily causing current overshoot. Therefore, the reverse recovery characteristics of superjunction MOSFET are manifested as a larger reverse recovery charge (larger reverse recovery current and longer reverse recovery time) and a harder reverse recovery curve, which ultimately increases the power consumption of the device and reduces the application reliability.

[0005] Superjunction MOSFETs fabricated using deep trench technology are categorized into planar gate superjunction devices and trench gate superjunction devices, depending on the location of the gate. The gate of a planar gate superjunction device is a planar gate grown on the surface of the first epitaxial layer 102. The gate of a trench gate superjunction device is formed by etching the first epitaxial layer 102 to form a trench gate within the first epitaxial layer 102. The following uses a trench gate as an example for illustration:

[0006] like Figure 1 The figure below is a schematic diagram of the structure of an existing super junction MOSFET. The following also takes the N-type super junction MOSFET as an example. The vertical direction is defined as the Y direction, the horizontal direction is defined as the X direction, and the coordinates composed of the X axis and the Y axis are also shown in Figure 1 For ease of description, the active region, transition region, and terminal region are represented by corresponding curly brackets 101a, 101b, and 101c, respectively. The active region 101a is also the current flow area, and the terminal region 101c is used to withstand lateral voltage; the transition region 101b is located between the active region 101a and the terminal region 101c, with gate connection metal and field plate metal arranged on the top, marked as transition region 101b. The terminal structure of the device is formed in the transition region 101b and the terminal region 101c. Figure 1 It can be seen that N-type super junction MOSFET includes:

[0007] Semiconductor substrate 101 is N-type, highly doped, or N+ doped, with doping atoms including phosphorus (P) or arsenic (As). The concentration is generally above 1e19 cm⁻³ to reduce substrate resistance. As atoms are commonly used for substrate doping, which reduces interface state density and the diffusion of impurities from semiconductor substrate 101 into the voltage-resistant layer, or subsequent epitaxial layer 102, during subsequent thermal processes. The thinned semiconductor substrate 101 serves as a drain region, with a back metal layer 116 formed on the back side of the drain region, which then forms the drain electrode.

[0008] The N-type doped first epitaxial layer 102 is formed on the semiconductor substrate 101. The resistivity of the first epitaxial layer 102 is generally 0.5 to 5 ohm*cm. It belongs to the N-drift region of the device. Its thickness determines the breakdown voltage of the device. In addition, the first epitaxial layer 102 can be divided into single-layer epitaxial, double-layer epitaxial, multi-layer epitaxial and gradient epitaxial according to the change of doping concentration. The relationship between the resistivity of different first epitaxial layers 102 and the thickness of the epitaxial layer is as follows: Figures 2A to 2D As shown, Bottom represents the bottom of the first epitaxial layer 102, i.e., the junction between the semiconductor substrate 101 and the first epitaxial layer 102, and Top represents the top of the first epitaxial layer 102, i.e., the junction between the first epitaxial layer 102 and the dielectric layer 108. The doping ion species of the first epitaxial layer 102 include phosphorus (P) or arsenic (As).

[0009] The P-type column 103 and the N-type column composed of the first epitaxial layer 102 between the two P-type columns 103 form a PN alternating superjunction structure. The P column, i.e., the P-type column 103, and the N column, i.e., the N-type column, can compensate for each other's depletion at higher doping concentrations. This impurity compensation, on the one hand, makes the superjunction roughly regarded as intrinsic in the withstand voltage direction, with a rectangular built-in electric field, thereby improving the withstand voltage when turned off; on the other hand, it can increase the doping concentration by orders of magnitude, reduce the specific on-resistance, thereby breaking through the traditional silicon limit and achieving Rsp,on∝BV 1.32 In addition, an N-type buffer layer of a certain thickness is required below the P-type pillar 103 in the first epitaxial layer 102. The main purpose is to prevent the highly doped semiconductor substrate 101 from diffusing into the N-type pillar of the superjunction structure during the subsequent process heat treatment, thereby preventing the breakdown voltage of the device from being affected.

[0010] The gate dielectric layer 104, such as the gate oxide layer, is generally SiO2 and has a thickness of 500-1500 angstroms. Its thickness determines the gate's withstand voltage and also affects the gate capacitance. The thickness of the gate oxide layer should be designed based on specific characteristic requirements.

[0011] The gate conductive material layer 105 is generally composed of polysilicon, which is then connected to the front metal layer 113 to form the device gate. Polysilicon floating field plates 105b or fixed potential field plates 105a are also appropriately designed in the transition region 101b and the terminal region 101c to improve the terminal's withstand voltage.

[0012] The P-type well region 106 in the active region 101a overlaps the side of the gate conductive material layer 105 and is used to form an inversion layer channel. The doping concentration of the P-type well region 106 is generally between 1e11 and 1e14 cm⁻³. The higher the concentration of the P-type well region 106, the higher the threshold voltage of the device. The second well region 106a refers to the P-type well region 106 in the transition region 101b. The second well region 106a can be formed by ion implantation simultaneously with the P-type well region 106, or by independent ion implantation using a mask. The width of the second well region 106a can cover part of the transition region 101b, or cover the entire transition region 101b.

[0013] The source region 107 is an N-type heavily doped region with a doping concentration generally above 1e15 cm-3. Together with the contact hole and the top front metal layer 113, it forms the source of the device.

[0014] The dielectric layers 108 and 109 generally include SiO2 and BPSG, and are generally 8k-12k angstroms thick.

[0015] The contact hole includes a contact region 110 formed by contact hole ion implantation, a barrier layer 111, and a metal fill layer 112 for the contact hole. The contact hole ion implantation typically involves implanting BF2 and B. The barrier layer 111 is typically composed of Ti and TiN. The metal fill layer 112 is typically made of tungsten.

[0016] The electrodes formed by the front metal layer 113 include the source and gate. Common materials for the front metal layer 113 include Al, which is connected to the source and gate electrodes through contact holes. The back metal layer 116, commonly made of TiNiAg, is deposited directly on the N+ semiconductor substrate 101 and serves as the drain. The front metal layer 113 also forms a floating metal field plate for the terminal, improving its withstand voltage.

[0017] The passivation layer 114 and the protective layer 115 are made of silicon dioxide and polyimide, and are mainly deposited in the transition region 101b, the terminal region 101c and part of the active region 101a of the device to improve the reliability of the device. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide a superjunction MOSFET that can improve the consistency of the relationship curve between the breakdown voltage of the active region and the doping concentration of the second conductivity type column and the relationship curve between the terminal breakdown voltage and the doping concentration of the second conductivity type column, thereby expanding the process window and improving device consistency. It can also enhance the device's EAS capability, optimize the device's threshold voltage, improve the channel carrier mobility, and improve the device's reverse recovery characteristics. To this end, the present invention also provides a method for manufacturing the superjunction MOSFET.

[0019] To solve the above technical problems, the present invention provides a super junction MOSFET comprising:

[0020] A first epitaxial layer is formed on the top surface of a semiconductor substrate heavily doped with a first conductivity type, the first epitaxial layer comprising a first epitaxial sublayer doped with the first conductivity type and an undoped second epitaxial sublayer located on the top surface of the first epitaxial sublayer, the second epitaxial sublayer having a first thickness.

[0021] A plurality of second conductive type columns are formed in the first epitaxial layer, each second conductive type column passes through the second epitaxial sublayer and the bottom surface of the second conductive type column is higher than the top surface of the semiconductor substrate, the first epitaxial layer between each second conductive type column constitutes a first conductive type column, and the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.

[0022] The super junction MOSFET includes an active region, a transition region and a terminal region; the terminal region surrounds the circumference of the active region, and the transition region is located between the active region and the terminal region.

[0023] A device unit structure of a super junction MOSFET is formed in the active region, and the device unit structure includes:

[0024] A first well region doped with the second conductivity type, a gate structure, and a source region heavily doped with the first conductivity type.

[0025] The first well region is formed in the surface region of the first epitaxial layer and the depth of the first well region is greater than the depth of the second epitaxial sublayer; the first well region covered by the gate structure serves as a channel region; the source region is formed in the surface region of the first well region.

[0026] A second well region doped with a second conductive type is formed in the transition region. The second well region is formed in a surface region of the first epitaxial layer and has a depth greater than a depth of the second epitaxial sub-layer.

[0027] In the terminal area, the first conductive type column includes the second epitaxial sublayer, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure in the terminal area and the first doping concentration of the second conductive type column. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column; the doping concentration of the second conductive type column is set to the central doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

[0028] A further improvement is that the threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region, and under the condition of keeping the threshold voltage unchanged, the greater the first thickness, the smaller the doping concentration of the first well region.

[0029] A further improvement is that the second well region and the first well region have the same process structure and are formed simultaneously; or, the second well region is formed independently of the first well region.

[0030] A further improvement is that the gate structure is a planar gate or a trench gate.

[0031] The gate structure includes a gate dielectric layer and a gate conductive material layer.

[0032] A further improvement is that field oxide is formed on the surface of the first epitaxial layer in the transition region and the terminal region.

[0033] A first field plate is formed on the surface of the field oxide. The material of the first field plate is the same as that of the gate conductive material layer. The first field plate is connected to the gate or is floating.

[0034] A further improvement is that the drain region of the super junction MOSFET is composed of the semiconductor substrate after back-thinning or the semiconductor substrate after back-thinning and back-ion implantation with heavy doping of the first conductivity type.

[0035] A further improvement is that the first epitaxial sublayer is single-doped or multi-layer graded-doped or has a doping pattern that varies linearly with thickness.

[0036] A further improvement is that the second conductive type column includes a second epitaxial layer doped with the second conductive type and filled in the super junction trench.

[0037] To solve the above technical problems, the present invention provides a method for manufacturing a super junction MOSFET, comprising the following steps:

[0038] A semiconductor substrate heavily doped with a first conductivity type is provided and a first epitaxial layer is grown on the top surface of the semiconductor substrate, comprising: first growing a first epitaxial sublayer doped with the first conductivity type, and then growing an undoped second epitaxial sublayer of a first thickness on the top surface of the first epitaxial sublayer.

[0039] A plurality of second conductive type columns are formed in the first epitaxial layer, each second conductive type column passes through the second epitaxial sublayer and the bottom surface of the second conductive type column is higher than the top surface of the semiconductor substrate, the first epitaxial layer between each second conductive type column constitutes a first conductive type column, and the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.

[0040] A gate structure of each device unit structure of a super junction MOSFET is formed, wherein the gate structure is located in the active area, the terminal area surrounds the peripheral side of the active area, and the transition area is located between the active area and the terminal area.

[0041] Field oxide is formed on surfaces of the first epitaxial layer in the transition region and the termination region.

[0042] A first well region doped with a second conductive type is formed in the surface region of the first epitaxial layer in the active region, and a second well region doped with a second conductive type is formed in the surface region of the first epitaxial layer in the transition region; the depth of the first well region is greater than the depth of the second epitaxial sublayer; the first well region covered by the gate structure serves as a channel region; the depth of the second well region is greater than the depth of the second epitaxial sublayer.

[0043] Ion implantation with heavy doping of the first conductivity type is performed to form a source region of each of the device unit structures in a surface area of ​​the first well region of the active region.

[0044] In the terminal area, the first conductive type column includes the second epitaxial sublayer, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure in the terminal area and the first doping concentration of the second conductive type column. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column; the doping concentration of the second conductive type column is set to the central doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

[0045] A further improvement is that the threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region, and under the condition of keeping the threshold voltage unchanged, the greater the first thickness, the smaller the doping concentration of the first well region.

[0046] A further improvement is that the second well region and the first well region have the same process structure and are formed simultaneously; or, the second well region is formed independently of the first well region.

[0047] A further improvement is that the gate structure is a planar gate or a trench gate;

[0048] The gate structure includes a gate dielectric layer and a gate conductive material layer.

[0049] Further improvements include:

[0050] A first field plate is formed on the surface of the field oxide. The material of the first field plate is the same as that of the gate conductive material layer. The first field plate is connected to the gate or is floating.

[0051] Further improvements include:

[0052] Thinning the back side of the semiconductor substrate, so that the drain region of the super junction MOSFET is formed from the semiconductor substrate after the back side thinning;

[0053] Alternatively, after the semiconductor substrate is thinned, back ion implantation with heavy doping of the first conductivity type is performed, and the drain region is formed by the semiconductor substrate with the back side thinned and heavily doped with the first conductivity type through the back ion implantation.

[0054] A further improvement is that the first epitaxial sublayer is single-doped or multi-layer graded-doped or has a doping pattern that varies linearly with thickness.

[0055] A further improvement is that the second conductive type column includes a second conductive type doped second epitaxial layer filled in the super junction trench, and the steps of forming the second conductive type column include:

[0056] Etching is performed to form a plurality of super junction trenches.

[0057] The second epitaxial layer is filled in the super junction trench.

[0058] A further improvement is that the first epitaxial sublayer and the second epitaxial sublayer are grown continuously, and when growing the first epitaxial sublayer, the process gas includes a doping gas, and the doping gas provides first conductive type doping impurities; when growing the second epitaxial sublayer, the doping gas is turned off.

[0059] The present invention sets the top layer of the first epitaxial layer as an undoped second epitaxial sublayer, and the characteristics of the first relationship curve between the terminal breakdown voltage and the first doping concentration of the second conductive type column can be adjusted by the thickness of the second epitaxial sublayer to realize the required first relationship curve by setting the thickness of the second epitaxial sublayer. When the doping concentration of the second conductive type column is set according to the first relationship curve and the terminal breakdown voltage is ensured to be greater than or equal to the required breakdown voltage value, compared with the existing structure without the second epitaxial sublayer, the first relationship curve of the present invention will move toward the direction of the lighter doping of the second conductive type column. Therefore, compared with the existing structure, the doping concentration of the second conductive type column of the super junction structure of the present invention can be obtained. Reduced, while ensuring that the terminal breakdown voltage meets the requirements; and after the first doping concentration of the second conductive type column is reduced, it will be closer to the center doping of the relationship curve between the breakdown voltage of the active area and the first doping concentration of the second conductive type column, and can also make the gap between the terminal breakdown voltage and the breakdown voltage of the active area smaller, and the breakdown voltage consistency of the device can be improved. Therefore, the present invention can improve the consistency of the relationship curve between the breakdown voltage of the active area and the doping concentration of the second conductive type column and the relationship curve between the terminal breakdown voltage and the doping concentration of the second conductive type column, thereby expanding the process window and improving the consistency of the device; after the breakdown voltage consistency of the device is improved, the EAS capability of the device can also be improved.

[0060] For the active area, the present invention sets an undoped second epitaxial sublayer so that the doping concentration of the first well region corresponding to the channel region can be reduced when the same threshold voltage is reached. After the doping concentration of the first well region is reduced, the scattering degree of channel carriers and ionized impurities will be reduced, thereby improving the mobility of channel carriers, thereby reducing the on-resistance of the device and reducing the conduction loss.

[0061] In addition, reducing the doping concentration of the first well region can also reduce the number of minority carriers injected into the body diode when it is turned on, thereby reducing the reverse recovery charge and improving the reverse recovery characteristics, and finally reducing the power consumption of the device and improving the application reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0063] Figure 1 It is a schematic diagram of the structure of an existing super junction MOSFET;

[0064] Figure 2A-2D Schematic diagram of the longitudinal doping distribution curves of the first epitaxial layer of four first conductivity type dopings of the existing superjunction MOSFET;

[0065] Figure 3 2 is a schematic structural diagram of a super junction MOSFET according to an embodiment of the present invention;

[0066] Figures 4A-4D Schematic diagram of longitudinal doping distribution curves of the first epitaxial layer doped with four first conductivity types of the superjunction MOSFET according to an embodiment of the present invention;

[0067] Figure 5 yes Figure 4B Corresponding simulation diagram;

[0068] Figure 6 is a first relationship curve between the terminal breakdown voltage of the super junction structure of the terminal region and the first doping concentration of the second conductivity type column at various first thicknesses of the super junction MOSFET according to an embodiment of the present invention;

[0069] Figure 7 is an enlarged view of a first relationship curve of a selected first thickness of a super junction MOSFET according to an embodiment of the present invention, and a corresponding relationship curve between a breakdown voltage of a super junction structure in an active region and a first doping concentration of a second conductivity type column;

[0070] Figure 8 1 is the electric field intensity distribution curve along line AA' of the existing super junction MOSFET and the super junction MOSFET of the embodiment of the present invention;

[0071] Figure 9 : is the electric field intensity distribution curve along line BB' of the existing super junction MOSFET and the super junction MOSFET of the embodiment of the present invention;

[0072] Figure 10 3 is a comparison diagram of reverse recovery simulation curves of the existing super junction MOSFET and the super junction MOSFET according to the embodiment of the present invention. DETAILED DESCRIPTION

[0073] like Figure 3 FIG. 1 is a schematic diagram of the structure of a super junction MOSFET according to an embodiment of the present invention. The super junction MOSFET according to an embodiment of the present invention includes:

[0074] A first epitaxial layer is formed on the top surface of a semiconductor substrate 101 heavily doped with a first conductive type, the first epitaxial layer including a first epitaxial sublayer 102a doped with the first conductive type and an undoped second epitaxial sublayer 102b located on the top surface of the first epitaxial sublayer 102a, the second epitaxial sublayer 102b having a first thickness.

[0075] Multiple second conductive type columns 103 are formed in the first epitaxial layer, each second conductive type column 103 passes through the second epitaxial sublayer 102b and the bottom surface of the second conductive type column 103 is higher than the top surface of the semiconductor substrate 101. The first conductive type column is composed of the first epitaxial layer between each second conductive type column 103, and the first conductive type column and the second conductive type column 103 are alternately arranged to form a super junction structure.

[0076] In an embodiment of the present invention, the second conductivity type pillar 103 includes a second epitaxial layer doped with the second conductivity type filled in the super junction trench. In some embodiments, the second conductivity type pillar 103 may further include a dielectric layer and an ion implantation region doped with the second conductivity type formed at the bottom of the super junction trench.

[0077] The super junction MOSFET includes an active region 101a, a transition region 101b and a terminal region 101c; the terminal region 101c surrounds the active region 101a, and the transition region 101b is located between the active region 101a and the terminal region 101c. Figure 3 It can be seen that second conductive type pillars 103 are formed in the active area 101a, the transition area 101b and the terminal area 101c, wherein the outer side of the terminal area 101c also includes a region where the second conductive type pillars 103 are not formed.

[0078] The device unit structure of the super junction MOSFET is formed in the active region 101a, and the device unit structure includes:

[0079] A first well region 106 doped with the second conductivity type, a gate structure, and a source region 107 heavily doped with the first conductivity type.

[0080] The first well region 106 is formed in the surface region of the first epitaxial layer and the depth of the first well region 106 is greater than the depth of the second epitaxial sublayer 102b; the first well region 106 covered by the gate structure serves as a channel region; the source region 107 is formed in the surface region of the first well region 106.

[0081] A second well region 106a doped with the second conductivity type is formed in the transition region 101b. The second well region 106a is formed in the surface region of the first epitaxial layer and has a depth greater than that of the second epitaxial sublayer 102b.

[0082] In the terminal area 101c, the first conductive type column includes a second epitaxial sublayer 102b, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure of the terminal area 101c and the first doping concentration of the second conductive type column 103. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column 103; the doping concentration of the second conductive type column 103 is set to the center doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

[0083] In the embodiment of the present invention, the threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region. While maintaining the threshold voltage constant, the greater the first thickness, the lower the doping concentration of the first well region 106. Reducing the doping concentration of the first well region 106 can improve various aspects of device performance:

[0084] First, the scattering of channel carriers can be reduced, thereby increasing the mobility of channel carriers and thereby reducing the channel resistance.

[0085] Secondly, it can reduce minority carrier injection when the body diode is turned on, thereby improving the reverse recovery characteristics.

[0086] In the embodiment of the present invention, the second well region 106 a and the first well region 106 have the same process structure and are formed simultaneously. In other embodiments, the second well region 106 a can also be formed independently of the first well region 106 .

[0087] In the embodiment of the present invention, the gate structure is a trench gate. In other embodiments, the gate structure can also be a planar gate.

[0088] The gate structure includes a gate dielectric layer 104 and a gate conductive material layer 105. In some embodiments, the gate dielectric layer 104 is a gate oxide layer, and the gate conductive material layer 105 is a polysilicon gate.

[0089] Field oxide 108 is formed on the surface of the first epitaxial layer in the transition region 101b and the termination region 101c. The inner surface of the field oxide 108 fully opens the active region 101a and partially opens the transition region 101b to form a protective epoxy layer.

[0090] A first field plate is formed on the surface of the field oxide 108 . The material of the first field plate is the same as that of the gate conductive material layer 105 . The first field plate is connected to the gate or is floating. Figure 3 In FIG. 1 , the first field plate connected to the gate is denoted by 105 a , and the floating first field plate is denoted by 105 b .

[0091] The drain region of the super junction MOSFET is composed of a semiconductor substrate 101 after back-thinning or a semiconductor substrate 101 after back-thinning and back-ion implantation with heavily doped first conductivity type.

[0092] In the embodiment of the present invention, the first epitaxial sub-layer 102a is single-doped or multi-layer graded-doped or has a doping pattern that varies linearly with thickness.

[0093] In the embodiment of the present invention, a cutoff region 107 a heavily doped with the first conductivity type is further included on the outermost side of the terminal region 101 c . The cutoff region 107 a is usually formed simultaneously with the source region 107 using the same process.

[0094] The front side structure of the super junction MOSFET further includes a contact hole passing through the interlayer film 109 and a source and a gate formed by patterning the front side metal layer 113 .

[0095] Corresponding contact holes are formed on the source region 107, the cutoff region 107a, the gate conductive material layer 105, and the top of the first field plate 105a. The contact holes on the source region 107 and the top of the cutoff region 107a are connected to the source electrode, while the contact holes on the top of the gate conductive material layer 105 and the top of the first field plate 105a are connected to the gate electrode. Figure 3 The corresponding cross section does not show the contact hole on the top of the gate conductive material layer 105 .

[0096] The contact hole includes a barrier layer 111 formed on the inner surface of the contact hole opening and a metal fill layer 112. The contact hole opening corresponding to the source region 107 also passes through the source region 107 and forms a heavily doped contact region 110 of the second conductivity type at the bottom. In some embodiments, the barrier layer 111 includes Ti and TiN, and the metal fill layer 112 includes W.

[0097] In the embodiment of the present invention, a passivation layer 114 and a protective layer 115 are further formed on top of the transition region 101 b and the terminal region 101 c . The material of the passivation layer 114 includes silicon oxide, and the material of the protective layer 115 includes polyimide.

[0098] A drain electrode composed of a back metal layer 116 is formed on the back side of the drain region.

[0099] In an embodiment of the present invention, the superjunction MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. Preferably, the semiconductor substrate 101 is doped with As, as opposed to phosphorus (P), As can reduce the diffusion of N-type impurities into the first epitaxial layer. In other embodiments, the superjunction MOSFET can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0100] like Figures 4A to 4D 1 is a schematic diagram of longitudinal doping distribution curves of the first epitaxial layer doped with four first conductivity types of the super junction MOSFET according to an embodiment of the present invention; Figure 4A Shows single doping, where the longitudinal direction is Figure 3 In the y-axis direction, Figure 3 The doping distribution at AA' in FIG, wherein bottom is the interface between the semiconductor substrate 101 and the first epitaxial sublayer 102a, and top represents the top surface of the second epitaxial sublayer 102b. Figure 4A In the single doping, the first epitaxial sublayer 102a is single doped, and the second epitaxial sublayer 102b is undoped; Figure 4B , the first epitaxial sublayer 102a is double-doped and the doping concentration increases successively, and the second epitaxial sublayer 102b is undoped; Figure 4C , the first epitaxial sublayer 102a is multi-layer doped and the doping concentration increases sequentially, and the second epitaxial sublayer 102b is undoped; Figure 4D , the first epitaxial sublayer 102 a is doped with a linearly increasing doping concentration, and the second epitaxial sublayer 102 b is undoped.

[0101] like Figure 5 As shown, Figure 4B Corresponding simulation diagram; Figure 5 The existing superjunction MOSFET is also shown in Figure 2B Corresponding simulation diagram; Figure 5 , 0 microns corresponds to Figure 4B The top position in the figure; curve 201 corresponds to the simulation diagram of the doping concentration distribution of the first epitaxial layer of the existing super junction MOSFET, and curve 202 corresponds to the simulation diagram of the doping concentration distribution of the first epitaxial layer of the super junction MOSFET according to the embodiment of the present invention. It can be seen that in the top area in the y direction, that is, the area of ​​the second epitaxial sublayer 102b corresponding to the embodiment of the present invention, the doping concentration of the first epitaxial layer is reduced.

[0102] like Figure 6 3. The first relationship curve of the terminal breakdown voltage of the super junction structure of the terminal region of the super junction MOSFET of the embodiment of the present invention under various first thicknesses and the first doping concentration of the second conductive type column is shown in FIG. 3. The first thickness corresponding to the curve 301 is 0 microns, that is, Figure 1 Corresponding to the first relationship curve of the existing super junction structure, curve 301 is the benchmark curve, that is, the curve corresponding to the BSL; curves 302, 303 to 307 correspond to the first relationship curves when the first thickness of the embodiment of the present invention is set to 0.25 microns, 0.5 microns, 1 micron, 2 microns, 3 microns and 4 microns respectively; it can be seen that as the first thickness increases, the first relationship curve will move to the left, that is, move toward the direction of the lighter doping of the second conductive type column 103. In the embodiment of the present invention, the second conductive type column 103 is a P-type column, that is, a P column.

[0103] Generally, the maximum breakdown voltage of the curve 301 will meet the breakdown voltage requirement value. Therefore, when the terminal breakdown voltage of the embodiment of the present invention is greater than or equal to the maximum breakdown voltage of the curve 301, the breakdown voltage requirement value will be met. Figure 6 As can be seen from the figure, the maximum breakdown voltages of curves 302 and 303 are both greater than or equal to the maximum breakdown voltage of curve 301 , so the final value of the first thickness can be selected from the first thickness values ​​corresponding to curves 302 and 303 .

[0104] like Figure 7The figure shows an enlarged view of a first relationship curve for a selected first thickness of a super-junction MOSFET according to an embodiment of the present invention, along with a corresponding relationship curve between the breakdown voltage of the super-junction structure in the active region and the first doping concentration of the second conductivity type pillar. It can be seen that the endpoint breakdown voltage corresponding to the center concentration of the P-pillar doping concentration in curve 302 is the maximum breakdown voltage of curve 302. It can be seen that the maximum breakdown voltage of curve 302 is greater than that of curve 301, while the maximum breakdown voltage of curve 303 is almost equal to that of curve 301. Therefore, the optimal first thickness is 0.25 microns, corresponding to curve 302.

[0105] Figure 7 In the figure, curve 401 corresponds to the relationship between the breakdown voltage of the superjunction structure in the active region of a conventional superjunction MOSFET and the first doping concentration of the second conductivity type pillars, while curve 402 corresponds to the relationship between the breakdown voltage of the superjunction structure in the active region of a superjunction MOSFET according to an embodiment of the present invention and the first doping concentration of the second conductivity type pillars. It can be seen that curves 401 and 402 substantially overlap. Therefore, in the active region 101a, since the depth of the first well region 106 is greater than the depth of the second epitaxial sublayer 102b, the second epitaxial sublayer 102b substantially does not affect the relationship between the breakdown voltage of the superjunction structure in the active region and the first doping concentration of the second conductivity type pillars. Furthermore, the center doping concentration of the second conductivity type pillar corresponding to the maximum breakdown voltage of the superjunction structure in the active region is substantially aligned with the center doping concentration of the second conductivity type pillars in curve 303, and the difference between the center doping concentration of the second conductivity type pillars in curve 302 and curve 302 is also smaller than the difference between the center doping concentration of the second conductivity type pillars in curve 301. This improves the consistency of the BV and P-type doping concentrations in the terminal region BV and the active region.

[0106] like Figure 8 As shown, the electric field strength distribution curves along the AA' line of the existing super junction MOSFET and the super junction MOSFET of the embodiment of the present invention are shown; curve 501 corresponds to the electric field strength distribution curve along the AA' line of the existing super junction MOSFET, and curve 502 corresponds to the electric field strength distribution curve along the AA' line of the super junction MOSFET of the embodiment of the present invention, wherein the first thickness is set to 0.25 microns; in curve 501, the electric field strength in the surface area will increase, and the electric field strength distribution in the entire longitudinal direction is uneven; while in curve 502, the electric field strength distribution in the entire longitudinal direction is uniform, which can improve the EAS (surge resistance) capability of the device.

[0107] like Figure 9As shown, the electric field intensity distribution curves along the BB' line of the existing super junction MOSFET and the super junction MOSFET of the embodiment of the present invention are shown; curve 503 corresponds to the electric field intensity distribution curve along the BB' line of the existing super junction MOSFET, and curve 504 corresponds to the electric field intensity distribution curve along the BB' line of the super junction MOSFET of the embodiment of the present invention. It can be seen that in the active region and the transition region, curves 503 and 504 basically coincide with each other, but in the terminal region, the electric field intensity corresponding to curve 504 is greatly increased compared with the electric field intensity of curve 503.

[0108] like Figure 10 , which is a comparison of reverse recovery simulation curves for a conventional superjunction MOSFET and a superjunction MOSFET according to an embodiment of the present invention. Curve 505 corresponds to the reverse recovery simulation curve for the conventional superjunction MOSFET, while curve 506 corresponds to the reverse recovery simulation curve for the superjunction MOSFET according to an embodiment of the present invention. By integrating curves 505 and 506, it can be seen that the reverse recovery charge corresponding to curve 505 is reduced, thereby improving the reverse recovery characteristic.

[0109] In the embodiment of the present invention, the top layer of the first epitaxial layer is set as an undoped second epitaxial sublayer 102b, and the characteristics of the first relationship curve between the terminal breakdown voltage and the first doping concentration of the second conductive type column 103 can be adjusted through the thickness of the second epitaxial sublayer 102b. The required first relationship curve is set by the thickness of the second epitaxial sublayer 102b. When the doping concentration of the second conductive type column 103 is set according to the first relationship curve and the terminal breakdown voltage is ensured to be greater than or equal to the required breakdown voltage value, compared with the existing structure without the second epitaxial sublayer 102b, the first relationship curve of the embodiment of the present invention will move toward the direction of the lighter doping of the second conductive type column 103. Therefore, compared with the existing structure, the doping of the second conductive type column 103 of the super junction structure of the embodiment of the present invention is The concentration can be reduced while ensuring that the terminal breakdown voltage meets the requirements; and after the first doping concentration of the second conductive type column 103 is reduced, it will be closer to the center doping of the relationship curve between the breakdown voltage of the active area 101a and the first doping concentration of the second conductive type column 103, and can also make the gap between the terminal breakdown voltage and the breakdown voltage of the active area 101a smaller, and the breakdown voltage consistency of the device can be improved. Therefore, the embodiment of the present invention can improve the consistency of the relationship curve between the breakdown voltage of the active area 101a and the doping concentration of the second conductive type column 103 and the relationship curve between the terminal breakdown voltage and the doping concentration of the second conductive type column 103, thereby expanding the process window and improving the consistency of the device; after the breakdown voltage consistency of the device is improved, the EAS capability of the device can also be improved.

[0110] For the active area 101a, the present invention sets an undoped second epitaxial sublayer 102b, so that the doping concentration of the first well region 106 corresponding to the channel region can be reduced when the same threshold voltage is reached. After the doping concentration of the first well region 106 is reduced, the scattering degree of channel carriers and ionized impurities will be reduced, thereby improving the mobility of channel carriers, thereby reducing the on-resistance of the device and reducing the conduction loss.

[0111] In addition, the reduction in the doping concentration of the first well region 106 can also reduce the number of minority carriers injected into the body diode when it is turned on, thereby reducing the reverse recovery charge and improving the reverse recovery characteristics, ultimately reducing the power consumption of the device and improving the application reliability of the device.

[0112] The method for manufacturing a super junction MOSFET according to an embodiment of the present invention comprises the following steps:

[0113] Step 1: Provide a semiconductor substrate 101 heavily doped with a first conductivity type and grow a first epitaxial layer on the top surface of the semiconductor substrate 101, including: first growing a first epitaxial sublayer 102a doped with the first conductivity type, and then growing an undoped second epitaxial sublayer 102b of a first thickness on the top surface of the first epitaxial sublayer 102a.

[0114] In the method of the embodiment of the present invention, the first epitaxial sub-layer 102a is single-doped or multi-layer graded-doped or has a doping pattern that varies linearly with thickness.

[0115] The first epitaxial sublayer 102a and the second epitaxial sublayer 102b are grown continuously. When growing the first epitaxial sublayer 102a, the process gas includes a doping gas, and the doping gas provides first conductive type doping impurities. When growing the second epitaxial sublayer 102b, the doping gas is turned off.

[0116] Step 2: Form a plurality of second conductive type columns 103 in the first epitaxial layer, wherein each second conductive type column 103 passes through the second epitaxial sublayer 102b and the bottom surface of the second conductive type column 103 is higher than the top surface of the semiconductor substrate 101. The first conductive type column is composed of the first epitaxial layer between each second conductive type column 103, and the first conductive type column and the second conductive type column 103 are alternately arranged to form a super junction structure.

[0117] In the method of the embodiment of the present invention, the second conductive type pillar 103 includes a second conductive type doped second epitaxial layer filled in the super junction trench. The steps of forming the second conductive type pillar 103 include:

[0118] Etching is performed to form a plurality of super junction trenches.

[0119] The second epitaxial layer is filled in the super junction trench.

[0120] Step 3: Form the gate structure of each device unit structure of the super junction MOSFET. The gate structure is located in the active area 101a, the terminal area 101c surrounds the active area 101a, and the transition area 101b is located between the active area 101a and the terminal area 101c.

[0121] In the embodiment of the present invention, the gate structure is a trench gate. In other embodiments, the gate structure may be a planar gate or a trench gate.

[0122] The gate structure includes a gate dielectric layer 104 and a gate conductive material layer 105. In some embodiments, the gate dielectric layer 104 is a gate oxide layer, and the gate conductive material layer 105 is a polysilicon gate.

[0123] Step 4: forming a field oxide 108 on the surface of the first epitaxial layer in the transition region 101b and the termination region 101c.

[0124] The method of the embodiment of the present invention further includes:

[0125] A first field plate is formed on the surface of the field oxide 108. The material of the first field plate is the same as that of the gate conductive material layer 105. The first field plate is connected to the gate or is floating. Figure 3 In the embodiment, the first field plate connected to the gate is individually denoted by reference numeral 105a, and the floating first field plate is individually denoted by reference numeral 105b. In some embodiments, the first field plate is a polysilicon field plate.

[0126] Step 5. Form a first well region 106 doped with the second conductivity type in the surface region of the first epitaxial layer of the active region 101a, and form a second well region 106a doped with the second conductivity type in the surface region of the first epitaxial layer of the transition region 101b; the depth of the first well region 106 is greater than the depth of the second epitaxial sublayer 102b; the first well region 106 covered by the gate structure serves as a channel region; the depth of the second well region 106a is greater than the depth of the second epitaxial sublayer 102b.

[0127] In the embodiment of the present invention, the threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region. Under the condition of keeping the threshold voltage unchanged, the greater the first thickness, the lower the doping concentration of the first well region 106.

[0128] In the embodiment of the present invention, the second well region 106a and the first well region 106 have the same process structure and are formed simultaneously. In other embodiments, the second well region 106a can also be formed independently of the first well region 106.

[0129] Step 6: Perform ion implantation of heavily doped first conductivity type ions to form source regions 107 of each device unit structure in the surface area of ​​the first well region 106 of the active region 101 a .

[0130] When the source region 107 is formed, a stop region 107 a is also formed at the outermost side of the termination region 101 c .

[0131] In the terminal area 101c, the first conductive type column includes a second epitaxial sublayer 102b, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure of the terminal area 101c and the first doping concentration of the second conductive type column 103. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column 103; the doping concentration of the second conductive type column 103 is set to the center doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

[0132] like Figure 6 As shown, a first relationship curve corresponding to various values ​​of the first thickness can be obtained first.

[0133] Then, according to the terminal breakdown voltage and the first doping concentration corresponding to each first relationship curve, a first relationship curve whose terminal breakdown voltage is greater than or equal to the required breakdown voltage value is selected; the selected first relationship curve is as follows: Figure 7 As shown in curves 302 and 303. Comparing curves 302 and 303, it can be seen that curve 302 has a higher terminal breakdown voltage. Therefore, under optimal conditions, the first thickness value corresponding to curve 302, i.e., 0.25 microns, can be selected. Of course, the method of the embodiment of the present invention can also select the first thickness value as 0.5 microns or any other value between 0.5 microns and 0.25 microns.

[0134] After that, the following front processes are also included:

[0135] An interlayer film 109 is formed.

[0136] Contact holes are formed through the interlayer film 109, and corresponding contact holes are formed on the source region 107, the cutoff region 107a, the gate conductive material layer 105, and the top of the first field plate 105a. The contact holes on the source region 107 and the cutoff region 107a are connected to the source electrode, while the contact holes on the gate conductive material layer 105 and the top of the first field plate 105a are connected to the gate electrode. Figure 3 The corresponding cross section does not show the contact hole at the top of the gate conductive material layer 105. The steps of forming the contact hole include:

[0137] A contact hole opening is formed. The contact hole opening corresponding to the source region 107 also passes through the source region 107;

[0138] Afterwards, the method further includes forming a second conductive type heavily doped contact region 110 at the bottom of the contact hole opening corresponding to the source region 107 .

[0139] The inner surface of the contact hole opening is formed into a barrier layer 111. In some embodiments, the barrier layer 111 includes Ti and TiN.

[0140] The contact hole opening is filled with a metal filling layer 112. In some embodiments, the metal filling layer 112 is made of W.

[0141] Later also includes:

[0142] A passivation layer 114 is formed and patterned so that the passivation layer 114 is located only in the transition region 101b and the terminal region 101c. The material of the passivation layer 114 includes silicon oxide.

[0143] A protective layer 115 is formed and patterned so that the protective layer 115 is located only in the transition region 101b and the terminal region 101c. The material of the protective layer 115 includes polyimide.

[0144] The following back-end processes are also included:

[0145] The back side of the semiconductor substrate 101 is thinned, and the drain region of the superjunction MOSFET is formed from the back-thinned semiconductor substrate 101. Alternatively, after the semiconductor substrate 101 is thinned, back-side ion implantation with a heavy first conductivity type doping is performed, and the drain region is formed from the back-thinned and heavily first conductivity type doped semiconductor substrate 101.

[0146] A back metal layer 116 is formed on the back side of the drain region, and the back metal layer 116 forms a drain electrode.

[0147] In the embodiment of the present invention, Figure 3 As shown, the top of the first epitaxial layer in the terminal region 101c has an undoped portion, namely the second epitaxial sublayer 102b, and the P-type column 103 and the N-type column need to compensate for each other's depletion, which will cause the center concentration of the P-type impurity in the terminal region 101c to move toward a lighter direction. This will reduce the difference between the BV of the terminal region 101c in the lateral direction and the BV of the active region and the center of the P-type impurity concentration. In addition, when the top of the first epitaxial layer is undoped, the P column is light or in the center, but it is still relatively concentrated relative to the first epitaxial layer. Due to the charge compensation principle, the depletion region of the first epitaxial layer will be expanded and enhanced at this time. Therefore, the embodiment of the present invention will increase the BV of the light concentration and the center concentration of the P column in the terminal region 101c. This will improve the key process window of the device, and improve the voltage resistance and BV consistency of the device.

[0148] Furthermore, because the active region 101a of the device according to the present invention utilizes an undoped top first epitaxial layer structure, namely, a second epitaxial sublayer 102b, a lower doping concentration in the P-type well region, namely, the first well region 106, can achieve the same threshold voltage as existing structures. The lower doping concentration in the first well region 106 reduces the scattering of channel electrons and ionized impurities, thereby improving channel mobility and lowering on-resistance. It also reduces the injected charge into the device's body diode, lowering the reverse recovery charge of the body diode and optimizing the reverse recovery characteristics. This reduces device power consumption and improves device reliability.

[0149] To more clearly illustrate the embodiment of the present invention, the embodiment of the present invention is further described below with reference to specific parameters. Taking a 600V N-type deep trench superjunction MOSFET as an example, the wafer manufacturing process is as follows:

[0150] First, a high-resistivity first epitaxial layer is grown on a low-resistivity N-type semiconductor substrate 101. The thickness of this first epitaxial layer is 45-50 μm. Low-resistivity semiconductor substrate 101, or semiconductor substrate 101, is doped with As (arsenic) to reduce the interface state density and the diffusion of impurities from the semiconductor substrate 101 into the voltage-resistant layer during subsequent thermal processes. The doping concentration of semiconductor substrate 101 is above 1e19 cm⁻³, indicating heavy N-type doping, to reduce substrate resistance. The first epitaxial layer typically adopts a double-layer epitaxial structure, with a top resistivity of 0.85 ohm.cm and a bottom resistivity of 1.05 ohm.cm, indicating light N-type doping. The doping atom in the first epitaxial layer is P (phosphorus). The resistivity variation of the first epitaxial layer, the specific doping concentration, and the interrelationships between dopant atom types in actual production designs can be simulated and designed using computer-aided design software (TCAD).

[0151] The first epitaxial layer process of the embodiment of the present invention is different from the existing epitaxial layer process. Based on the above conventional superjunction MOSFET first epitaxial layer structure, in this example, N-type doping is not performed within a certain thickness range in the Y direction at the top of the first epitaxial layer, that is, the second epitaxial sublayer 102b is not doped. The specific undoped thickness of the top of the first epitaxial layer, that is, the first thickness, varies according to different process platforms and device designs, and can be assisted in design by TCAD. The actual growth method of the first epitaxial layer can be that when the first epitaxial layer grows to a certain range at the top, the gas doped with N-type impurities is turned off, and the residual gas is used to complete the epitaxial growth within the remaining certain thickness range, that is, the growth of the second epitaxial sublayer 102b. Through simulation software, it can be obtained that the final doping concentration distribution curve of the first epitaxial layer after the device undergoes various thermal processes is as shown in FIG. Figure 5 As shown in Figure 2, the phosphorus doping concentration within a certain range on the top of the first epitaxial layer can be reduced from 5.4e15 cm-2 to 2.8e15 cm-2.

[0152] Typically, the superjunction trench width for a 600V superjunction product is 3.2μm, with a spacing of 3.8μm between each superjunction trench. A dielectric film is then deposited on the first epitaxial layer, and several trenches with a specific aspect ratio, known as superjunction trenches, are etched into the first epitaxial layer using photolithography. These trenches are distributed throughout the active area 101a, the transition region 101b, and part of the termination region 101c. The trench depth ranges from 40 to 47μm. The trench width and spacing can be adjusted based on the product's characteristics and the choice of epitaxial substrate (semiconductor substrate 101). For this type of superjunction product, assuming a first epitaxial layer thickness of 50μm, the trench depth will not exceed 47μm. A buffer layer of sufficient thickness is required at the bottom of the trenches to improve the device's current surge resistance. After the trench topography is etched, a dielectric film, either an oxide film or a SiN film, with a thickness of approximately 0.1 to 0.2 μm, is left at the bottom of the trenches. Some processes also implant P-type ions at the bottom of the trench to increase BVdss. Boron is commonly used, with an energy of 90-180 keV and a dose of 1.0E12 to 2.0E12 cm⁻². P-type silicon, or the second epitaxial layer, is then epitaxially filled within the trench. The doping concentration of the P-type silicon depends on the doping concentration and structure of the first epitaxial layer of the substrate. Chemical mechanical polishing is then used for planarization. Filling the superjunction trench as described above forms P-type pillars, or the second conductivity type pillars 103.

[0153] Then, several shallow trenches, namely gate trenches, are formed on the first epitaxial layer by photolithography and etching. The depth of the gate trenches is generally 2 to 4 μm. A gate dielectric layer 104, such as a thermal oxide layer, is deposited. Then, polysilicon is deposited and etched to form the device's gate conductive material layer 105. Polysilicon field plates 105a and 105b are also deposited in the transition region 101b and the terminal region 101c. Field plate 105b is a floating structure that reduces the peak electric field on the device surface, optimizes the electric field distribution, and increases the breakdown voltage at the device terminal.

[0154] After that, a layer of thickness is formed on the surface of the silicon wafer, i.e., the semiconductor substrate 101, by CVD deposition. The oxide film, also known as field oxide, protects the device from high voltage breakdown. Generally, the higher the BV of the device, the thicker the oxide film required. This oxide film only covers the transition region 101b and the terminal region 101c. The oxide film in the charge flow area, the active region 101a, needs to be etched away.

[0155] Next, photolithography and ion implantation are used to form a first well region 106 and a second well region 106a in the device cell region, namely the active region 101a and the transition region 101b. Boron is typically implanted, with an energy of 60 to 180 keV and a dose of 1e11 cm⁻² to 1e14 cm⁻². In routine production, the device threshold voltage can be affected by product characteristics, such as whether the product is irradiated or non-irradiated, as well as other process adjustments. This can be achieved by adjusting the implantation dose or energy of the first well region 106.

[0156] Then, the source region 107 is formed by photolithography and ion implantation of N-type impurities. Common N-type impurities include phosphorus and arsenic.

[0157] The current metal electrode process primarily involves depositing the interlayer film 109, etching and filling the contact holes, and depositing the front metal layer 113. The metal fill layer 112 that forms the contact hole and the doped region at the bottom form a semiconductor-metal ohmic contact. In typical metal electrode processes, in the device current flow region, the contact hole will etch away silicon in the N-type high-concentration region, or source region 107, with an etching depth of 2000 to 4000 angstroms. In the transition region 101b, the contact hole only needs to penetrate the interlayer film 109 and the protective epoxy film, or field oxide 108, with the silicon etching depth in this region not exceeding 500 angstroms. Subsequently, BF2 or B, or both, is implanted into the bottom of the contact hole (CT) trench to form the P+ contact region 110. A Ti-TiN barrier layer 111 is then deposited to prevent Si from dissolving in the AlCu, forming a spike, and annealing is performed. Then, metal tungsten, i.e., a metal filling layer 111, is deposited to fill the contact hole trench, i.e., the opening. The thickness of W is 4000 angstroms. After that, the surface metal is removed, and 4-5 μm AlCu is deposited, where the Cu content accounts for 0.5%, to form metal electrodes, including the source and gate.

[0158] Next comes the preparation of the passivation layer 114 and protective layer 115. Typically, a high-density silicon oxide layer is deposited under plasma as the passivation layer 114, followed by a thicker polyimide film as the protective layer 115. Photolithography and development are then used to form a protective pattern covering the terminal area 101c and part of the active area 101a. After baking, the polyimide layer has a thickness of 4 to 10 μm.

[0159] Some devices require electron irradiation. This can be performed after the passivation layer 114 process, followed by the polyimide process. However, processes such as polyimide baking may affect the effectiveness of the electron irradiation. Alternatively, electron irradiation can be introduced after the polyimide process, followed by setting an appropriate dose and annealing conditions. For example, a typical dose is 60-300 kGY, and annealing conditions are 300-380°C for 30-300 minutes to further improve the device's body diode reverse recovery characteristics. Platinum implantation can also be performed after the CT process to adjust the device's body diode reverse recovery characteristics.

[0160] In the present invention, the active region 101a and the terminal region 101c are simulated using TCAD simulation software to determine the optimal undoped thickness of the top of the first epitaxial layer, i.e., the first thickness. First, by varying the undoped thickness of the top of the first epitaxial layer, different terminal structures are constructed. The doping concentration distribution curves of the terminal region along the AA' position of this embodiment and the existing superjunction device are shown in FIG. Figure 5 . Figure 5 The curve of the doping concentration distribution of the first epitaxial layer at AA' after thermal annealing is shown in Figure 1. The curve of the breakdown voltage of the top undoped first epitaxial layer device changes with the doping concentration of the P-type column, that is, the second conductive type column 103 is shown in Figure 1. Figure 6 . In the direction where the doping concentration of the P-type column 103 is relatively light, the BV value in the direction of relatively light can be significantly improved when the first epitaxial layer is undoped. At the same time, as the thickness of the undoped top of the first epitaxial layer increases, the center concentration of the doping of the terminal P-type column 103 will gradually move toward the light direction. When it is undoped at 0.25μm, the BV corresponding to the center concentration of the doping of the P-type column 103 is higher than that of the BSL device, that is, the existing superjunction MOSFET. When it is undoped at 0.5μm, the BV corresponding to the center concentration of the doping of the P-type column 103 is almost equal to that of the BSL device. In this example, the optimal undoped thickness of the first epitaxial layer can be set to 0.25μm.

[0161] 0.25 μm undoped first epitaxial layer super junction device and Figure 1 The electric field intensity distribution curve of the terminal region of the existing super junction device at the AA' position in the direction of the P column being doped lightly is shown in FIG. Figure 8 . The embodiment of the present invention 0.25μm undoped first epitaxial layer super junction device and Figure 1 The electric field intensity distribution curve of the existing super junction device terminal region at the BB' position in the direction of the P column doping is shown in FIG. Figure 9. At the AA' position, the terminal electric field strength increases from 100V / cm to 1e5V / cm. Moreover, the largest BV of the BSL device is located in the surface area of ​​the device. After optimizing the first epitaxial layer, the BV distribution in the overall AA direction is more uniform. This can improve the EAS (surge resistance) capability of the device. At the BB' position, it can be seen that at the outermost circle 100μm of the terminal, the electric field strength increases from 1.1e4V / cm to 2.1e5V / cm. From the simulation results, it can be seen that after adopting the first epitaxial layer with no doping on the top, the PN column depletion region at the outermost edge of the terminal is enhanced and expanded. The reason is that when the top of the first epitaxial layer is not doped, the P column is relatively light or the center concentration is still relatively high relative to the first epitaxial layer. Due to the charge compensation principle, the depletion region of the first epitaxial layer will be expanded and enhanced at this time. Therefore, the optimization of the first epitaxial layer proposed in the present invention can improve the BV of the terminal area 101cP column with a light concentration and a center concentration.

[0162] In addition, due to the presence of an undoped region at the top of the first epitaxial layer in the terminal region 101c, and the need for mutual depletion compensation between the P-type column 103 and the N-type column (i.e., the first conductivity type column), the P epitaxial center of the terminal region 101c shifts toward a lighter color. As the undoped thickness of the first epitaxial layer increases, the corresponding Pepi, i.e., the center concentration of the P-type column 103, gradually shifts toward a lighter color due to charge balance. When the undoped thickness of the top of the first epitaxial layer is greater than 0.5μm, i.e., 1μm, 2μm, 3μm, and 4μm, the BV corresponding to the center concentration of the P-type column 103 doping is lower than that of the BSL device.

[0163] Then, the device structure of the active region with 0.25μm undoped and 0.5μm undoped top of the first epitaxial layer and BSL conditions was constructed through simulation, and the BV curves of the corresponding structures at different PEPI doping concentrations were obtained. The simulation results are shown in Figure 7 The dotted line in the figure is the BV simulation curve of the active area, and the solid line is the BV simulation curve of the terminal area. From the data, it can be seen that the adjustment of the first epitaxial layer in the embodiment of the present invention will hardly affect the breakdown voltage of the active area. This is mainly because the undoped part of the top of the first epitaxial layer in the active area will be completely neutralized by the ion implantation of the first well region 106, and the undoped first epitaxial layer at the top will not form a depletion region with the P column. In addition, from Figure 7 It can also be seen that when the top undoped first epitaxial layer is used, the doping concentration at the center of the P-pillar of the device is closer to the doping concentration at the center of the P-pillar in the active area. This will increase the breakdown voltage of the entire device, expand the overall process window of the device, and improve consistency.

[0164] Furthermore, in the active region, the excess P-type boron doping after neutralizing the top first epitaxial layer directly affects the device's threshold voltage. Therefore, when the ion implantation concentration of the P-well, or first well region 1066, is the same, a device using an undoped top first epitaxial layer will have a higher threshold voltage than a BSL device. Therefore, the P-well boron dose can be reduced to achieve the target threshold voltage. The P-well boron dose in the BSL device is relatively high at 1.5e13 cm⁻². In the present embodiment, the dose can be reduced to 1.45e13 cm⁻². The reduction in the P-well boron dose is related to the thickness of the undoped top first epitaxial layer. The greater the thickness of the undoped top first epitaxial layer, the greater the reduction in the P-well boron dose. When the optimized device and the BSL device maintain the same threshold voltage of 4V, simulations show that the channel electron mobility in the BSL device is approximately 949 cm⁻² / (V*s), while the electron mobility in the optimized device is increased to 953 cm⁻² / (V*s). This is mainly because the boron doping concentration of the P-well in the optimized device is reduced, and the degree of scattering of channel electrons and ionized impurities is reduced, thereby improving the channel mobility. Electron mobility is inversely proportional to the on-resistance. The higher the mobility, the faster the electrons move in the channel, and a larger current can be conducted at the same voltage, thereby reducing resistance. Therefore, the optimization of the first epitaxial layer proposed in the embodiment of the present invention helps to improve the channel electron mobility, reduce the on-resistance of the device, and reduce conduction loss. The body diode reverse recovery simulation results of the other two are shown in Figure 10 During the reverse recovery process, the total amount of minority carrier charge stored in the PN junction that can be extracted is the reverse recovery charge Qrr, which is the integral of the reverse recovery current Irr and the reverse recovery time trr:

[0165] Simulation data indicates that the optimized device, namely the super-junction MOSFET according to an embodiment of the present invention, has a lower reverse recovery charge than the BSL device. Specifically, the reverse recovery charge Qrr of the BSL device is approximately 3.81e-6C, while the Qrr of the optimized device is approximately 3.65e-6C, a 4.2% reduction in reverse recovery charge. This is because the reduced boron dose injected into the P-well reduces the number of holes injected into the body diode, thereby reducing the reverse recovery charge of the body diode, lowering device power consumption, and improving device reliability.

[0166] Therefore, the super-junction MOSFET according to the embodiment of the present invention can achieve the following technical results:

[0167] The embodiments of the present invention improve the BVDSS of the terminal by optimizing the structure of the first epitaxial layer of the device, and improve the consistency between the BV of the terminal region 101c and the BV of the active region and the P-type impurity concentration, thereby improving the BVDSS of the entire device, expanding the process window, improving device consistency, and enhancing the EAS capability of the device. At the same time, this optimization can improve the VTH of the device, so the target threshold voltage of the device can be met by reducing the injection concentration of the P well. This will lead to a reduction in the degree of scattering between channel electrons and ionized impurities, thereby improving the channel electron mobility, reducing the on-resistance of the device, and reducing conduction losses; it will also lead to a reduction in the injected holes in the body diode of the device, reducing the reverse recovery charge, and improving the reverse recovery characteristics. This can reduce the power consumption of the device and improve the reliability of the device application.

[0168] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A super junction MOSFET, characterized in that: include: A first epitaxial layer is formed on a top surface of a semiconductor substrate heavily doped with a first conductivity type, the first epitaxial layer comprising a first epitaxial sublayer doped with the first conductivity type and an undoped second epitaxial sublayer located on a top surface of the first epitaxial sublayer, the second epitaxial sublayer having a first thickness; A plurality of second conductivity type pillars are formed in the first epitaxial layer, each second conductivity type pillar passes through the second epitaxial sublayer and a bottom surface of the second conductivity type pillar is higher than a top surface of the semiconductor substrate, the first epitaxial layer between each second conductivity type pillar constitutes a first conductivity type pillar, and the first conductivity type pillars and the second conductivity type pillars are alternately arranged to form a super junction structure; The super junction MOSFET includes an active region, a transition region and a terminal region; the terminal region surrounds the active region, and the transition region is located between the active region and the terminal region; A device unit structure of a super junction MOSFET is formed in the active region, and the device unit structure includes: a first well region doped with the second conductivity type, a gate structure, and a source region heavily doped with the first conductivity type; The first well region is formed in a surface region of the first epitaxial layer and has a depth greater than a depth of the second epitaxial sublayer; the first well region covered by the gate structure serves as a channel region; the source region is formed in a surface region of the first well region; A second well region doped with a second conductivity type is formed in the transition region, the second well region is formed in a surface region of the first epitaxial layer and has a depth greater than a depth of the second epitaxial sublayer; In the terminal area, the first conductive type column includes the second epitaxial sublayer, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure in the terminal area and the first doping concentration of the second conductive type column. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column; the doping concentration of the second conductive type column is set to the central doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

2. The superjunction MOSFET according to claim 1, wherein: The threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region. Under the condition of keeping the threshold voltage unchanged, the greater the first thickness, the smaller the doping concentration of the first well region.

3. The super junction MOSFET according to claim 2, wherein: The second well region and the first well region have the same process structure and are formed simultaneously; or, the second well region is formed independently of the first well region.

4. The superjunction MOSFET according to claim 1, wherein: The gate structure is a planar gate or a trench gate; The gate structure includes a gate dielectric layer and a gate conductive material layer.

5. The super junction MOSFET according to claim 4, wherein: Field oxide is formed on the surface of the first epitaxial layer in the transition region and the termination region; A first field plate is formed on the surface of the field oxide. The material of the first field plate is the same as that of the gate conductive material layer. The first field plate is connected to the gate or is floating.

6. The super junction MOSFET according to claim 1, wherein: The drain region of the super junction MOSFET is composed of the semiconductor substrate after back-thinning or the semiconductor substrate after back-thinning and back-ion implantation with heavy doping of the first conductivity type.

7. The super junction MOSFET according to claim 1, wherein: The first epitaxial sublayer is single doped or multi-layer graded doped or has a doping pattern that varies linearly with thickness.

8. The super junction MOSFET according to claim 1, wherein: The second conductive type column includes a second conductive type doped second epitaxial layer filled in the super junction trench.

9. A method for manufacturing a super junction MOSFET, characterized in that: The steps include: Providing a semiconductor substrate heavily doped with a first conductivity type and growing a first epitaxial layer on a top surface of the semiconductor substrate, comprising: first growing a first epitaxial sublayer doped with the first conductivity type, and then growing an undoped second epitaxial sublayer of a first thickness on a top surface of the first epitaxial sublayer; forming a plurality of second conductivity type pillars in the first epitaxial layer, wherein each second conductivity type pillar passes through the second epitaxial sublayer and a bottom surface of the second conductivity type pillar is higher than a top surface of the semiconductor substrate; the first epitaxial layer between each second conductivity type pillar constitutes a first conductivity type pillar; and the first conductivity type pillars and the second conductivity type pillars are alternately arranged to form a super junction structure; forming a gate structure of each device unit structure of a super junction MOSFET, wherein the gate structure is located in the active area, the terminal area surrounds the circumference of the active area, and the transition area is located between the active area and the terminal area; forming a field oxide on the surface of the first epitaxial layer in the transition region and the termination region; A first well region doped with a second conductivity type is formed in a surface region of the first epitaxial layer in the active region, and a second well region doped with a second conductivity type is formed in a surface region of the first epitaxial layer in the transition region; the depth of the first well region is greater than the depth of the second epitaxial sublayer; the first well region covered by the gate structure serves as a channel region; the depth of the second well region is greater than the depth of the second epitaxial sublayer; Performing ion implantation of a heavily doped first conductivity type ion into a surface region of the first well region of the active region to form a source region of each of the device unit structures; In the terminal area, the first conductive type column includes the second epitaxial sublayer, and the first thickness is set according to the requirements of the first relationship curve between the terminal breakdown voltage of the super junction structure in the terminal area and the first doping concentration of the second conductive type column. The larger the first thickness, the more the first relationship curve moves toward the direction of the lighter doping of the second conductive type column; the doping concentration of the second conductive type column is set to the central doping or lighter doping on the first relationship curve and ensures that the terminal breakdown voltage is greater than or equal to the required breakdown voltage value.

10. The method for manufacturing a super junction MOSFET according to claim 9, wherein: The threshold voltage of the device unit structure is determined by the net doping concentration of the second conductivity type in the channel region. Under the condition of keeping the threshold voltage unchanged, the greater the first thickness, the smaller the doping concentration of the first well region.

11. The method for manufacturing a super junction MOSFET according to claim 10, wherein: The second well region and the first well region have the same process structure and are formed simultaneously; or, the second well region is formed independently of the first well region.

12. The method for manufacturing a super junction MOSFET according to claim 9, wherein: The gate structure is a planar gate or a trench gate; The gate structure includes a gate dielectric layer and a gate conductive material layer.

13. The method for manufacturing a super junction MOSFET according to claim 12, wherein: Also includes: A first field plate is formed on the surface of the field oxide. The material of the first field plate is the same as that of the gate conductive material layer. The first field plate is connected to the gate or is floating.

14. The method for manufacturing a super junction MOSFET according to claim 9, wherein: Also includes: Thinning the back side of the semiconductor substrate, so that the drain region of the super junction MOSFET is formed from the semiconductor substrate after the back side thinning; Alternatively, after the semiconductor substrate is thinned, back ion implantation with heavy doping of the first conductivity type is performed, and the drain region is formed by the semiconductor substrate with the back side thinned and heavily doped with the first conductivity type through the back ion implantation.

15. The method for manufacturing a super junction MOSFET according to claim 9, wherein: The first epitaxial sublayer is single doped or multi-layer graded doped or has a doping pattern that varies linearly with thickness.

16. The method for manufacturing a super junction MOSFET according to claim 9, wherein: The second conductive type column includes a second conductive type doped second epitaxial layer filled in the super junction trench, and the steps of forming the second conductive type column include: Performing etching to form a plurality of super junction trenches; The second epitaxial layer is filled in the super junction trench.

17. The method for manufacturing a super junction MOSFET according to claim 9, wherein: The first epitaxial sublayer and the second epitaxial sublayer are grown continuously. When growing the first epitaxial sublayer, the process gas includes a doping gas, and the doping gas provides first conductive type doping impurities; when growing the second epitaxial sublayer, the doping gas is turned off.

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