Integrated device and application thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an integrated device and application thereof.The integrated device comprises a substrate, a sub-collector layer, a plurality of transistor units, a first dielectric layer, a plurality of metal supporting structures, a passivation layer and a metal column, the sub-collector layer is arranged on the substrate, the transistor units are arranged on the sub-collector layer, and the first dielectric layer is arranged on the substrate; the first dielectric layer covers the transistor units and the sub-collector layer, the metal supporting structures are arranged on the first dielectric layer, the passivation layer covers the first dielectric layer and is provided with a first opening, and the metal column is arranged on the passivation layer and is electrically connected with the transistor units through the first opening. The metal support structure is located outside the transistor unit. By means of the arrangement, the metal supporting structure can provide effective supporting for the metal columns, and the reliability of the integrated device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an integrated device, a radio frequency amplifier including the integrated device, and a communication device including the radio frequency amplifier. Background Art

[0002] Semiconductor integrated circuits, due to their high frequency and high efficiency, are widely used in communications, radar, and optoelectronics. The reliability of semiconductor integrated circuits is a key indicator of their ability to operate stably and long-term under specified conditions, directly impacting the lifespan, safety, and market competitiveness of electronic products.

[0003] Currently, the copper pillars used in integrated devices are directly pressed onto a polymer layer. Due to the inherent softness of the polymer, the copper pillars lack support, failing to provide effective and reliable support, severely impacting device reliability. Therefore, effectively improving the reliability of integrated devices has become a pressing technical challenge for those skilled in the art.

[0004] It should be noted that the information disclosed in this background technology section is only intended to increase understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The present invention provides an integrated device comprising a substrate, a subcollector layer, multiple transistor units, a first dielectric layer, multiple metal support structures, a passivation layer, and metal pillars. The subcollector layer is disposed on the substrate, the multiple transistor units are disposed on the subcollector layer, the first dielectric layer covers the multiple transistor units and the subcollector layer, the multiple metal support structures are disposed on the first dielectric layer, the passivation layer covers the first dielectric layer, the passivation layer has a first opening, and the metal pillars are disposed on the passivation layer and electrically connect the multiple transistor units through the first opening. When viewed from above, the metal support structures are located outside the transistor units.

[0006] The present invention also provides a radio frequency amplifier and a communication device. The radio frequency amplifier includes the aforementioned integrated device. The communication device includes the aforementioned radio frequency amplifier.

[0007] The present invention provides an integrated device and its application, which improves the reliability of the integrated device by arranging a metal support structure for supporting metal pillars in a passivation layer, so that the metal support structure can provide effective support for the metal pillars; and does not require an additional mask process, which facilitates production and reduces process complexity.

[0008] Other features and beneficial effects of the present invention will be described in the following description, and some of the technical features and beneficial effects can be obviously derived from the description or understood by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 This is a schematic diagram of the layout of a traditional HBT integrated device; Figure 2 It is a schematic diagram of the structure of a traditional HBT integrated device; Figure 3 is a schematic top view of the integrated device provided in the first embodiment of the present invention; Figure 4 is a schematic structural diagram of an integrated device provided by a first embodiment of the present invention; Figure 5 is a schematic top view of the integrated device provided in the second embodiment of the present invention; Figure 6 is a schematic top view of the integrated device provided in the third embodiment of the present invention; Figure 7 is a schematic top view of the integrated device provided in the fourth embodiment of the present invention; Figure 8 is a schematic top view of the integrated device provided in the fifth embodiment of the present invention; Figure 9 is a schematic structural diagram of an integrated device provided by a sixth embodiment of the present invention; Figure 10 is a schematic top view of the integrated device provided by the seventh embodiment of the present invention; Figure 11 is a schematic structural diagram of an integrated device provided by a seventh embodiment of the present invention; Figure 12 is a schematic structural diagram of an integrated device provided by an eighth embodiment of the present invention; Figure 13 3 is a schematic top view of the integrated device provided in the ninth embodiment of the present invention.

[0011] Reference numerals: 10-substrate; 12-subcollector layer; 14-first dielectric layer; 16-metal support structure; 161-first metal layer; 162-second metal layer; 163-third metal layer; 18-passivation layer; 181-first opening; 182-second opening; 20-metal pillar; 22-collector layer; 24-base layer; 26-emitter layer; 28-collector; 30-base; 32-emitter; 34-metal connection layer; 36-second dielectric layer; 50-transistor unit; 51-first interconnect metal layer; 52-second interconnect metal layer; 60-epitaxial structure; S1-minimum spacing between the metal support structure and the transistor unit; W1-width of the metal support structure. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0013] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0014] See also Figure 3 and Figure 4 , Figure 3 is a schematic top view of the integrated device provided in the first embodiment of the present invention, Figure 4is a schematic structural diagram of an integrated device provided in a first embodiment of the present invention. To achieve at least one of the aforementioned advantages, or other advantages, the first embodiment of the present invention provides an integrated device, which is an integrated device integrating a transistor unit 50. As shown in the figure, the integrated device may include a substrate 10, a subcollector layer 12, a plurality of transistor units 50, a first dielectric layer 14, a plurality of metal support structures 16, a passivation layer 18, and a metal pillar 20.

[0015] The material of the substrate 10 may include GaAs, Si, SiC, GaN, sapphire, etc., mainly serving as a supporting material.

[0016] The sub-collector layer 12 is disposed on the substrate 10. The sub-collector layer 12 may be a highly doped N-type layer, such as N+GaAs, to reduce contact resistance and improve heat conduction.

[0017] A plurality of transistor units 50 are provided on the sub-collector layer 12. In the figure, the positions of the transistor units 50 are indicated by dashed boxes. Figure 2 There are three transistor units 50. The transistor unit 50 may refer to a group of unit structures having a collector 28, a base 30, and an emitter 32 integrated. Specifically, each transistor unit 50 may include a collector layer 22, a base layer 24, an emitter layer 26, a collector 28, a base 30, and an emitter 32. The collector layer 22 is disposed on the sub-collector layer 12, the base layer 24 is disposed on the collector layer 22, the emitter layer 26 is disposed on the base layer 24, the collector 28 is disposed on the sub-collector layer 12, the base 30 is connected to the base layer 24, and the emitter 32 is connected to the emitter layer 26.

[0018] The collector layer 22 and base layer 24 can be made of GaAs. The emitter layer 26 can be made of InGaP. The base 30 can be made of a narrow-bandgap material such as GaAs or SiGe, with P-type doping to help form a heterojunction barrier and reduce carrier transit time. The collector 28 can be made of a material such as InGaP, with low N-type doping to increase breakdown voltage and facilitate carrier collection.

[0019] The first dielectric layer 14 covers the plurality of transistor units 50 and the sub-collector layer 12. The first dielectric layer 14 is made of an insulating material, such as silicon nitride, silicon oxide, and the like.

[0020] A plurality of metal support structures 16 are disposed on the first dielectric layer 14. The metal support structures 16 are made of metal materials such as Ti, Pt, Ni, Au, Al, and the like.

[0021] The passivation layer 18 covers the first dielectric layer 14 and has a first opening 181 that exposes the transistor unit 50. The passivation layer 18 is made of a polymer, such as polyimide. The passivation layer 18 also has a second opening 182 located above the metal support structure 16. The metal pillar 20 fills the second opening 182.

[0022] The metal pillar 20 is disposed on the passivation layer 18 and electrically connects the plurality of transistor units 50 through the first opening 181. The material of the metal pillar 20 may include metal such as Cu or Au.

[0023] refer to Figure 1 and Figure 2 In the conventional HBT integrated device shown, the copper pillars are directly pressed against the polymer layer. Due to the relatively soft nature of the polymer, the copper pillars are weakly supported, failing to provide effective and reliable support, severely impacting device reliability. In contrast, this embodiment incorporates a metal support structure 16 within the passivation layer 18 for supporting the metal pillars 20. From a top view, the metal support structure 16 is positioned outside the transistor unit 50, effectively supporting the metal pillars 20 and improving the reliability of the integrated device. Furthermore, the embodiment eliminates the need for additional photomask processing, facilitating manufacturing and reducing process complexity.

[0024] In some embodiments, the width W1 of the metal support structure 16 is greater than 0.5 μm to enhance the support strength of the metal support structure 16 , thereby improving the reliability of the integrated device.

[0025] In some embodiments, when viewed from above, the minimum spacing S1 between the metal support structure 16 and the transistor unit 50 is greater than 0.5 μm to enhance the support strength of the metal support structure 16 and thus improve the reliability of the integrated device.

[0026] In some embodiments, when viewed from above, the area of ​​the metal support structure 16 accounts for 1% to 90% of the area of ​​the substrate 10, for example, 1% to 80%, 1% to 50%, 10% to 90%, etc., to enhance the support strength of the metal support structure 16 and thereby improve the reliability of the integrated device. However, the present invention is not limited to this, and the area ratio can be designed according to the structural requirements of different devices to meet the needs of different customers.

[0027] In some embodiments, in a top view, a portion of the metal support structure 16 is disposed at the boundary of the substrate 10 to enhance the support strength of the metal support structure 16 , thereby improving the reliability of the integrated device.

[0028] In some embodiments, a portion of the metal support structure 16 is disposed between two adjacent transistor units 50 in a top view to enhance the support strength of the metal support structure 16 , thereby improving the reliability of the integrated device.

[0029] In some embodiments, the metal support structure 16 is square, circular, or rectangular in shape when viewed from above. However, the present invention is not limited thereto, and the metal support structure 16 can also be shaped in any other manner according to actual deployment requirements.

[0030] In some embodiments, the integrated device further includes a metal connection layer 34, which is disposed on the upper surfaces of the collector 28, the base 30, and the emitter 32. The metal support structure 16 includes a first metal layer 161, a second metal layer 162, and a third metal layer 163 stacked in sequence on the first dielectric layer 14. By stacking multiple metal layers, the stacking height is increased, so that the morphology after the metal pillar 20 is plated is smoother, thereby improving the overall structural stability. In some embodiments, the widths of the first metal layer 161, the second metal layer 162, and the third metal layer 163 may be different, for example, the width of the first metal layer 161 decreases in sequence to the width of the third metal layer 163, thereby improving the structural stability. However, the present invention is not limited to this, and the structural shapes of the multiple metal layers can be adjusted accordingly according to actual support requirements. In some embodiments, the first metal layer 161 can be prepared together with the collector 28 in the same process, the second metal layer 162 can be prepared together with the metal connection layer 34 in the same process, and the third metal layer 163 can be prepared together with the metal layer subsequently used to electrically connect the two transistor units 50.

[0031] See also Figures 5 to 8 , Figure 5 is a schematic top view of the integrated device provided by the second embodiment of the present invention, Figure 6 is a schematic top view of the integrated device provided in the third embodiment of the present invention, Figure 7 is a schematic top view of the integrated device provided in the fourth embodiment of the present invention, Figure 8 3 is a schematic top view of the integrated device provided in the fifth embodiment of the present invention. Figures 5 to 8 It is used to illustrate the different morphologies of multiple metal support structures 16, such as Figure 5 Compared to Figure 3 As far as the top view is concerned, the long strip metal support structure 16 is added on the upper and lower sides; Figure 6 Compared to Figure 3 As for the embodiment, the metal support structure 16 between two adjacent transistor units 50 is removed, and the long strip metal support structures 16 located on the upper and lower sides are added; Figure 7 Compared to Figure 3As for the embodiment, the metal support structure 16 between two adjacent transistor units 50 is removed, and square metal support structures 16 located on the upper and lower sides are added; Figure 8 Compared to Figure 3 In the embodiment of the present invention, the metal support structure 16 between two adjacent transistor units 50 is removed, and circular metal support structures 16 located on the upper side and the lower side are added.

[0032] In some embodiments, as Figure 9 As shown, the integrated device further includes a second dielectric layer 36. The second dielectric layer 36 covers the metal support structure 16 and is made of an insulating material, such as silicon nitride or silicon oxide. The second dielectric layer 36 not only provides insulation protection but also further enhances overall structural stability.

[0033] See also Figure 10 and Figure 11 , Figure 10 is a schematic top view of the integrated device provided in the seventh embodiment of the present invention, Figure 11 is a schematic diagram of the structure of the integrated device provided by the seventh embodiment of the present invention. Figure 3 Compared with the integrated device of the first embodiment, the difference of this embodiment is mainly that the integrated device further includes a first interconnect metal layer 51 and a second interconnect metal layer 52. The first interconnect metal layer 51 covers the transistor unit 50 and the passivation layer 18. The second interconnect metal layer 52 covers the first interconnect metal layer 51. The first interconnect metal layer 51 and the second interconnect metal layer 52 are connected to the metal support structure 16. The first interconnect metal layer 51 can be prepared together with the second metal layer 162 in the same process. The second interconnect metal layer 52 can be prepared together with the third metal layer 163 in the same process. The first opening 181 of the passivation layer 18 no longer exposes the metal connection layer 34 above the emitter 32, but exposes the metal connection layer 34 above the base 30, so that the first interconnect metal layer 51 is connected to the metal connection layer 34 above the base 30. The first metal layer 161 is also provided in other places and extends outward to form an overhanging pattern.

[0034] See also Figure 12 , Figure 12 FIG. 1 is a schematic diagram of the structure of an integrated device provided by the eighth embodiment of the present invention. Figure 11 As for the integrated device of the seventh embodiment, the main difference of this embodiment is that an epitaxial structure 60 is also provided under the metal support structure 16. The epitaxial structure 60 is, for example, an epitaxial structure including a collector layer 22 and a base layer 24, which provides effective support for the metal column 20, thereby improving the reliability of the integrated device.

[0035] See also Figure 13 , Figure 13Schematic diagram of the top view of the integrated device provided by the ninth embodiment of the present invention. Figure 10 The difference between the integrated device of the seventh embodiment and this embodiment lies in that the first interconnect metal layer 51 is connected to the collector 28 and the shape of the overhang pattern formed is also different. In addition, in some embodiments, an epitaxial structure 60 may be provided below the metal support structure 16.

[0036] In summary, the present invention provides an integrated device and its application, which, by setting a metal support structure 16 for supporting the metal column 20 in the passivation layer 18, enables the metal support structure 16 to provide effective support for the metal column 20, thereby improving the reliability of the integrated device; and there is no need to add additional mask processes, which facilitates production and manufacturing and reduces process complexity.

[0037] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated device, characterized in that: The integrated device comprises: substrate; a subcollector layer, disposed on the substrate; a plurality of transistor units, disposed on the sub-collector layer; a first dielectric layer, covering the plurality of transistor units and the sub-collector layer; a plurality of metal support structures, disposed on the first dielectric layer; a passivation layer covering the first dielectric layer, wherein the passivation layer has a first opening; a metal pillar, disposed on the passivation layer and electrically connected to the plurality of transistor units through the first opening; In a top view, the metal support structure is located outside the transistor unit.

2. The integrated device according to claim 1, wherein: The metal support structure includes a first metal layer, a second metal layer and a third metal layer sequentially stacked on the first dielectric layer.

3. The integrated device according to claim 1, wherein: The width of the metal support structure is greater than 0.5 μm.

4. The integrated device according to claim 2, wherein: The first metal layer and the collector are prepared together in the same process, the second metal layer and the metal connection layer are prepared together in the same process, and the third metal layer and the metal layer for electrically connecting two transistor units are prepared together.

5. The integrated device according to claim 1, wherein: In a top view, the minimum distance between the metal support structure and the transistor unit is greater than 0.5 μm.

6. The integrated device according to claim 1, wherein: In a top view, the area of ​​the metal support structure accounts for 1% to 50% of the area of ​​the substrate.

7. The integrated device according to claim 1, wherein: Each of the transistor units includes a collector layer, a base layer, an emitter layer, a collector, a base and an emitter, the collector layer is arranged on the sub-collector layer, the base layer is arranged on the collector layer, the emitter layer is arranged on the base layer, the collector is arranged on the sub-collector layer, the base is connected to the base layer, and the emitter is connected to the emitter layer.

8. The integrated device according to claim 1, wherein: In a top view, part of the metal support structure is disposed between two adjacent transistor units, and part of the metal support structure is disposed at the boundary of the substrate.

9. The integrated device according to claim 1, wherein: When viewed from above, the metal support structure is square or circular.

10. The integrated device according to claim 1, wherein: The integrated device further includes a first interconnect metal layer and a second interconnect metal layer, wherein the first interconnect metal layer covers the transistor unit and the passivation layer, the second interconnect metal layer covers the first interconnect metal layer, and the first interconnect metal layer and the second interconnect metal layer are connected to the metal support structure.

11. The integrated device according to claim 1, wherein: An epitaxial structure is also provided below the metal support structure.

12. A radio frequency amplifier, characterized in that: The radio frequency amplifier comprises the integrated device according to any one of claims 1 to 11.

13. A communication device, characterized in that: The communication device comprises the radio frequency amplifier according to claim 12.

Images