Light emitting device and display panel

Abstract

The invention provides a light-emitting device and a display panel, and belongs to the technical field of photoelectron manufacturing. The light-emitting device comprises a substrate, a first passivation layer, a second passivation layer, a driving chip, a pixel chip and a bonding pad, the pixel chip is located on the plate surface of the substrate, the first passivation layer is located on the plate surface of the substrate and covers the pixel chip, the driving chip is located on the surface, away from the substrate, of the first passivation layer, and at least part of the orthographic projection of the pixel chip on the substrate is located in the orthographic projection of the driving chip on the substrate; the second passivation layer is located on the surface, away from the substrate, of the first passivation layer and covers the driving chip, the multiple bonding pads are all located on the surface, away from the substrate, of the second passivation layer, and the multiple bonding pads are electrically connected with pins of the driving chip through through holes penetrating through the second passivation layer; and at least part of the bonding pad is electrically connected with an electrode of the pixel chip through a through hole penetrating through the second passivation layer and the first passivation layer. The problem that many electronic components are arranged on the circuit board can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting device and a display panel. Background Art

[0002] In the emerging display industry, display panels typically consist of a circuit board and light-emitting elements. The light-emitting elements are typically LED packages or LED chips, mounted on a circuit board with driver and control functions. The circuit board drives the array of light-emitting elements to emit light, generating a display image.

[0003] Because LED packaging components or LED chips lack inherent control and driving functions, a driver chip often needs to be designed on the circuit board. This results in a large number of driver and control components being placed on the display panel's circuit board, further complicating the design. Furthermore, the horizontal integration of the LED chip and driver IC can create significant height differences between the driver IC and LED chip, leading to issues such as the driver IC obstructing the LED chip's light output. Summary of the Invention

[0004] The disclosed embodiments provide a light-emitting device and display panel that can not only alleviate the problem of having too many electronic components on a circuit board and simplify the circuit board, but also address the difficulties of rewiring and IC shading caused by the large height differences in horizontally integrated ICs and LEDs. Furthermore, vertical packaging can reduce the area of ​​a single pixel device and save costs. The technical solution is as follows:

[0005] An embodiment of the present disclosure provides a light-emitting device, which includes: a substrate, a first passivation layer, a second passivation layer, a driver chip, a plurality of pixel chips and a plurality of pads; the plurality of pixel chips are located on the board surface of the substrate, the first passivation layer is located on the board surface of the substrate and covers the plurality of pixel chips, the driver chip is located on the surface of the first passivation layer away from the substrate, and at least part of the orthographic projections of the plurality of pixel chips on the substrate are located within the orthographic projection of the driver chip on the substrate; the second passivation layer is located on the surface of the first passivation layer away from the substrate and covers the driver chip, the plurality of pads are all located on the surface of the second passivation layer away from the substrate, and the plurality of pads are electrically connected to the pins of the driver chip through through holes penetrating the second passivation layer, and at least part of the pads are electrically connected to the electrodes of the pixel chip through through holes penetrating the second passivation layer and the first passivation layer.

[0006] In another implementation of the embodiment of the present disclosure, the multiple pixel chips include: a first pixel chip, a second pixel chip and a third pixel chip, and the luminous colors of the first pixel chip, the second pixel chip and the third pixel chip are all different; the light-emitting device also includes a first redistribution layer, the first redistribution layer is located on the surface of the first passivation layer away from the substrate, the first redistribution layer includes a first metal trace, a second metal trace, a third metal trace and a fourth metal trace, one end of the first metal trace is connected to the first pixel chip through a through hole, one end of the second metal trace is connected to the second pixel chip through a through hole, one end of the third metal trace is connected to the third pixel chip through a through hole, and one end of the fourth metal trace is respectively connected to the first pixel chip, the second pixel chip and the third pixel chip through a through hole, the other end of the first metal trace, the other end of the second metal trace, the other end of the third metal trace and the other end of the fourth metal trace all have electrode blocks; at least part of the pads are connected to the electrode blocks through through holes passing through the second passivation layer.

[0007] In another implementation of the embodiment of the present disclosure, the light-emitting device also includes a second redistribution layer and an insulating layer, the second redistribution layer is located on the surface of the second passivation layer away from the substrate, the insulating layer is located on the surface of the second passivation layer away from the substrate and covers the second redistribution layer, a part of the second redistribution layer is connected to the pin of the driving chip through a through hole, and another part of the second redistribution layer is connected to the electrode block through a through hole; the soldering pad is located on the surface of the insulating layer away from the substrate, and the soldering pad is connected to the second redistribution layer through a through hole penetrating the insulating layer.

[0008] In another implementation of the embodiment of the present disclosure, the second redistribution layer includes a first connecting trace, a second connecting trace, a third connecting trace, a fourth connecting trace, a fifth connecting trace, a sixth connecting trace, a seventh connecting trace and an eighth connecting trace; the driving chip has a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin, one end of the first connecting trace is connected to the first pin through a through hole, one end of the second connecting trace is connected to the second pin through a through hole, one end of the third connecting trace is connected to the third pin through a through hole, one end of the fourth connecting trace is connected to the fourth pin through a through hole, one end of the fifth connecting trace is connected to the fifth pin through a through hole, and the One end of the six connecting traces is connected to the sixth pin through a through hole, one end of the seventh connecting trace is connected to the seventh pin through a through hole, one end of the eighth connecting trace is connected to the eighth pin through a through hole, and the four connecting traces in the second redistribution layer are also connected to the four electrode blocks respectively through through holes; the soldering pad includes a first solder point, a second solder point, a third solder point and a fourth solder point, the first solder point is connected to the other end of the first connecting trace through a through hole, and the first solder point is also connected to the other end of the seventh connecting trace, the second solder point is connected to the other end of the fifth connecting trace through a through hole, the third solder point is connected to the other end of the eighth connecting trace through a through hole, and the fourth solder point is connected to the other end of the sixth connecting trace through a through hole.

[0009] In another implementation of the embodiment of the present disclosure, the first pin is a negative pin, the second pin, the third pin and the fourth pin are all positive pins, the fifth pin is a clock signal pin, the sixth pin is a power pin, the seventh pin is an empty pin, and the eighth pin is an input pin; the first connecting trace is also connected to the electrode block of the fourth metal trace through a through hole, the second connecting trace is also connected to the electrode block of the first metal trace through a through hole, the third connecting trace is also connected to the electrode block of the second metal trace through a through hole, and the fourth connecting trace is also connected to the electrode block of the third metal trace through a through hole.

[0010] In another implementation of the embodiment of the present disclosure, the insulating layer includes an organic material layer or an inorganic material layer.

[0011] In another implementation of the embodiment of the present disclosure, the thickness of the first passivation layer is greater than or equal to the thickness of the pixel chip.

[0012] In another implementation of the embodiment of the present disclosure, the thickness of the second passivation layer is greater than or equal to the thickness of the driver chip.

[0013] In another implementation of the embodiment of the present disclosure, the thickness of the pixel chip is less than 10 μm, and the side length of the pixel chip is less than 50 μm; the thickness of the driver chip is less than 150 μm, and the side length of the driver chip is less than 200 μm.

[0014] An embodiment of the present disclosure provides a display panel, which includes a circuit board and a plurality of light-emitting devices as described above, wherein the plurality of light-emitting devices are located on the circuit board, and the solder pads of the light-emitting devices are electrically connected to the circuit board.

[0015] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0016] In the light-emitting device provided in the embodiments of the present disclosure, a pixel chip is arranged on a substrate surface and covered with a first passivation layer. A driver chip is also disposed on the first passivation layer, with at least a portion of the pixel chip's orthographic projection on the substrate located within the driver chip's orthographic projection on the substrate. That is, the pixel chip and driver chip are stacked perpendicular to the substrate. A second passivation layer is also disposed on the first passivation layer, covering the driver chip, thereby packaging the pixel chip and driver chip together.

[0017] Furthermore, multiple pads on the second passivation layer are electrically connected to the pins of the driver chip via through-holes penetrating the second passivation layer. Some pads are also electrically connected to the electrodes of the pixel chip via through-holes penetrating the second passivation layer and the first passivation layer. This not only allows power to be supplied to the driver chip and pixel chip via the pads, but also allows the driver chip to control the pixel chip, thereby forming a light-emitting device with control and drive functions. This eliminates the need for numerous drive and control components on the circuit board, thus simplifying the circuit board. Furthermore, vertical packaging can solve the problems of height inconsistency, difficulty in wiring electrode connections, and shading of the driver IC caused by horizontal packaging. Vertical packaging also saves area per pixel device, saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a structural schematic diagram of a light-emitting device provided by an embodiment of the present disclosure;

[0020] Figure 2 This is a hierarchical schematic diagram of a pixel chip arranged on a substrate provided by an embodiment of the present disclosure;

[0021] Figure 3 yes Figure 2 A top view of a pixel chip is provided;

[0022] Figure 4 is a hierarchical schematic diagram of a light-emitting device provided by an embodiment of the present disclosure;

[0023] Figure 5 yes Figure 4 A top view of a light emitting device is provided.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. Substrate;

[0026] 21. First passivation layer; 22. Second passivation layer; 23. Insulation layer; 24. First organic material bonding layer; 25. Second organic material bonding layer; 26. Light absorption layer;

[0027] 30. Driver chip; 31. First pin; 32. Second pin; 33. Third pin; 34. Fourth pin; 35. Fifth pin; 36. Sixth pin; 37. Seventh pin; 38. Eighth pin;

[0028] 40. Pixel chip; 41. First pixel chip; 42. Second pixel chip; 43. Third pixel chip;

[0029] 50, soldering pad; 51, first soldering point; 52, second soldering point; 53, third soldering point; 54, fourth soldering point;

[0030] 60. First redistribution layer; 61. First metal trace; 62. Second metal trace; 63. Third metal trace; 64. Fourth metal trace; 65. Electrode block;

[0031] 70. Second redistribution layer; 71. First connecting trace; 72. Second connecting trace; 73. Third connecting trace; 74. Fourth connecting trace; 75. Fifth connecting trace; 76. Sixth connecting trace; 77. Seventh connecting trace; 78. Eighth connecting trace. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] In related art, light-emitting elements and driver chips are horizontally arranged and sealed together to create a light-emitting device with driving and control functions. Because the LED chips in the light-emitting elements are very thin, only a few microns thick, and the driver chips are at least tens of microns thick, lining up and sealing the LED and driver chips, with their significant thickness differences, requires a thick passivation layer for rewiring. Furthermore, the LED chip's electrodes are very small, making the creation of through-holes and the fabrication of the conductive layer for the through-holes challenging, making the fabrication of the rewiring electrodes difficult.

[0035] Furthermore, the significant height difference can cause the driver chip to block the light emitted by the LED chip, resulting in a decrease in brightness at wide viewing angles. Furthermore, sealing the LED chip and driver chip side by side can increase the size of the encapsulated light-emitting device, increasing its manufacturing cost.

[0036] To this end, an embodiment of the present disclosure provides a light emitting device. Figure 1 Schematic diagram of the structure of a light emitting device provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting device includes: a substrate 10 , a first passivation layer 21 , a second passivation layer 22 , a driving chip 30 , a plurality of pixel chips 40 and a plurality of pads 50 .

[0037] like Figure 1As shown, multiple pixel chips 40 are located on the surface of the substrate 10, the first passivation layer 21 is located on the surface of the substrate 10 and covers the multiple pixel chips 40, the driving chip 30 is located on the surface of the first passivation layer 21 away from the substrate 10, and at least part of the orthographic projection of the multiple pixel chips 40 on the substrate 10 is located within the orthographic projection of the driving chip 30 on the substrate 10.

[0038] like Figure 1 As shown, the second passivation layer 22 is located on the surface of the first passivation layer 21 away from the substrate 10 and covers the driving chip 30. Multiple pads 50 are located on the surface of the second passivation layer 22 away from the substrate 10, and the multiple pads 50 are electrically connected to the pins of the driving chip 30 through through holes passing through the second passivation layer 22. At least some of the pads 50 are electrically connected to the electrodes of the pixel chip 40 through through holes passing through the second passivation layer 22 and the first passivation layer 21.

[0039] In the light-emitting device provided in the embodiments of the present disclosure, a pixel chip 40 is arranged on the surface of a substrate 10 and is covered by a first passivation layer 21. A driver chip 30 is also disposed on the first passivation layer 21. At least a portion of the orthographic projection of the pixel chip on the substrate 10 is located within the orthographic projection of the driver chip 30 on the substrate 10. That is, the pixel chip and the driver chip 30 are stacked in a direction perpendicular to the substrate 10. A second passivation layer 22 is also disposed on the first passivation layer 21 to cover the driver chip 30, thereby packaging the pixel chip and the driver chip 30 together.

[0040] Furthermore, multiple pads 50 on the second passivation layer 22 are electrically connected to the pins of the driver chip 30 via through-holes penetrating the second passivation layer 22. Some pads 50 are also electrically connected to the electrodes of the pixel chip via through-holes penetrating the second passivation layer 22 and the first passivation layer 21. This not only allows power to be supplied to the driver chip 30 and the pixel chip via the pads 50, but also allows the driver chip 30 to control the pixel chip, thereby forming a light-emitting device with both control and drive functions. This eliminates the need for numerous drive and control components on the circuit board, thus simplifying the circuit board.

[0041] At the same time, compared with the method of horizontally stacking the driver chip 30 and the pixel chip, the embodiment of the present disclosure adopts the method of vertically stacking the driver chip 30 on the pixel chip, which can solve the problems of difficulty in rewiring and light blocking caused by the large height difference between the pixel chip and the driver chip 30 in the horizontal stacking method, and can also reduce the horizontal size of the light-emitting device and reduce the preparation cost of the light-emitting device.

[0042] Alternatively, as Figure 1As shown, the plurality of pixel chips 40 include: a first pixel chip 41 , a second pixel chip 42 and a third pixel chip 43 , and the first pixel chip 41 , the second pixel chip 42 and the third pixel chip 43 all emit light of different colors.

[0043] In the embodiment of the present disclosure, the plurality of pixel chips include a first pixel chip 41 emitting red light, a second pixel chip 42 emitting green light, and a third pixel chip 43 emitting blue light.

[0044] The difference between the first pixel chip 41 , the second pixel chip 42 and the third pixel chip 43 lies in the different luminescent colors of the epitaxial layers.

[0045] For the first pixel chip 41, the epitaxial layer is a red epitaxial layer. For the second pixel chip 42, the epitaxial layer is a green epitaxial layer. For the third pixel chip 43, the epitaxial layer is a blue epitaxial layer.

[0046] The red epitaxial layer includes a first p-type layer, a first light-emitting layer and a first n-type layer stacked in sequence.

[0047] In the red epitaxial layer, the first p-type layer includes a p-type AlInP layer.

[0048] The first light-emitting layer includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The first light-emitting layer may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0049] The first n-type layer includes an n-type AlGaInP current spreading layer.

[0050] In the embodiment of the present disclosure, the green epitaxial layer includes a second p-type layer, a second light-emitting layer, and a second n-type layer stacked in sequence.

[0051] In the green epitaxial layer, the second p-type layer includes a p-type GaN layer.

[0052] The second light-emitting layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The second light-emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0053] The second n-type layer includes an n-type GaN layer.

[0054] In the embodiment of the present disclosure, the blue epitaxial layer includes a third p-type layer, a third light-emitting layer, and a third n-type layer stacked in sequence.

[0055] In the blue epitaxial layer, the third p-type layer includes a p-type GaN layer.

[0056] The third light-emitting layer may include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The third light-emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0057] The third n-type layer includes an n-type GaN layer.

[0058] Optionally, the pixel chip has a thickness of 2 μm to 10 μm.

[0059] Exemplarily, the thickness of the red epitaxial layer is 5 μm, the thickness of the green epitaxial layer is 8 μm, and the thickness of the blue epitaxial layer is 6 μm.

[0060] Figure 2 FIG. 1 is a hierarchical diagram of a pixel chip arranged on a substrate 10 according to an embodiment of the present disclosure. Figure 2 As shown, the light emitting device further includes a first redistribution layer 60 . The first redistribution layer 60 is located on a surface of the first passivation layer 21 away from the substrate 10 .

[0061] Figure 3 yes Figure 2 A top view of a pixel chip is provided. Figure 3 As shown, the first redistribution layer 60 includes a first metal trace 61, a second metal trace 62, a third metal trace 63 and a fourth metal trace 64. One end of the first metal trace 61 is connected to the first pixel chip 41 through a through hole, one end of the second metal trace 62 is connected to the second pixel chip 42 through a through hole, one end of the third metal trace 63 is connected to the third pixel chip 43 through a through hole, and one end of the fourth metal trace 64 is connected to the first pixel chip 41, the second pixel chip 42 and the third pixel chip 43 through a through hole respectively. The other end of the first metal trace 61, the other end of the second metal trace 62, the other end of the third metal trace 63 and the other end of the fourth metal trace 64 all have an electrode block 65.

[0062] In the above implementation, the first redistribution layer 60 is set to four metal lines, three of which are respectively connected to the first electrodes of the first pixel chip 41, the second pixel chip 42 and the third pixel chip 43, and the fourth metal line 64 is simultaneously connected to the second electrodes of the first pixel chip 41, the second pixel chip 42 and the third pixel chip 43.

[0063] like Figure 3 As shown, the other ends of the four metal traces are provided with electrode blocks with a width greater than the line width of the metal traces, so that the metal traces can be more easily connected to other components by expanding the area.

[0064] At the same time, even if the electrode block is arranged at the edge area of ​​the first passivation layer 21, the electrode block can be connected to the corresponding pixel chip through the metal wiring, which can effectively avoid the electrode block being set in the center position to block and absorb more light.

[0065] like Figure 1 As shown, at least part of the pads 50 are connected to the electrode blocks 65 via through-holes penetrating the second passivation layer 22. In this way, the pads 50 disposed on the second passivation layer 22 can inject current into the pixel chip via the electrode blocks of the first redistribution layer 60, thereby energizing the pixel chip.

[0066] In this way, the driver chip 30 is stacked on the pixel chip, which not only reduces the horizontal size of the light-emitting device, but also the first redistribution layer 60 extends the electrode block to the edge area of ​​the first passivation layer 21, thereby facilitating digging holes in the second passivation layer 22 so that the pad 50 can be connected downward to the pixel chip, solving the redistribution difficulty caused by the large height difference between the pixel chip and the driver chip 30, and reducing the preparation cost of the light-emitting device.

[0067] Alternatively, as Figure 1 As shown, the light-emitting device also includes a second redistribution layer 70 and an insulating layer 23. The second redistribution layer 70 is located on the surface of the second passivation layer 22 away from the substrate 10. The insulating layer 23 is located on the surface of the second passivation layer 22 away from the substrate 10, and the insulating layer 23 covers the second redistribution layer 70. A portion of the second redistribution layer 70 is connected to the pin of the driving chip 30 through a through hole, and another portion of the second redistribution layer 70 is connected to the electrode block through a through hole.

[0068] like Figure 1 As shown, the pad 50 is located on the surface of the insulating layer 23 away from the substrate 10 , and the pad 50 is connected to the second redistribution layer 70 via a through hole penetrating the insulating layer 23 .

[0069] In the embodiment of the present disclosure, a second redistribution layer 70 is provided and the pins of the driver chip 30 are connected to the second redistribution layer 70, and the second redistribution layer 70 is extended to the area opposite to the first redistribution layer 60. In this way, when a hole is opened on the second passivation layer 22, the opened through hole can be a vertical hole without the need for bending and twisting, thereby reducing the difficulty of opening the hole and improving the preparation efficiency.

[0070] An insulating layer 23 is further provided on the surface of the second passivation layer 22 . The insulating layer 23 covers the second redistribution layer 70 to prevent the second redistribution layer 70 from contacting other film layers and causing a short circuit.

[0071] Optionally, the insulating layer 23 includes an organic material layer or an inorganic material layer.

[0072] For example, the insulating layer 23 may be a polyimide layer. Polyimide has good dielectric properties, and thus the insulating layer 23 made of polyimide has good insulation effect.

[0073] For example, the insulating layer 23 may be a distributed Bragg reflector (DBR) layer, so that the insulating layer 23 can reflect light, thereby effectively increasing the amount of light emitted by the pixel chip and improving the brightness of the light-emitting device.

[0074] The DBR layer includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0075] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0076] Figure 4 It is a hierarchical schematic diagram of a light-emitting device provided in an embodiment of the present disclosure. Figure 5 yes Figure 4 A top view of a light emitting device is provided. Figure 4 、 5 As shown, the second redistribution layer 70 includes a first connection line 71 , a second connection line 72 , a third connection line 73 , a fourth connection line 74 , a fifth connection line 75 , a sixth connection line 76 , a seventh connection line 77 and an eighth connection line 78 .

[0077] like Figure 5 As shown, the driver chip 30 has a first pin 31 , a second pin 32 , a third pin 33 , a fourth pin 34 , a fifth pin 35 , a sixth pin 36 , a seventh pin 37 and an eighth pin 38 .

[0078] Exemplarily, the first pin 31 is a positive power supply pin (VDD). The positive power supply pin is used to connect to the positive electrode of the pixel chip. In the embodiment of the present disclosure, the positive power supply pin can be connected to a common electrode in each pixel chip.

[0079] Exemplarily, the second pin 32 , the third pin 33 and the fourth pin 34 are all cathode pins, which are used to be connected to the cathodes of the first pixel chip 41 , the second pixel chip 42 and the third pixel chip 43 , respectively.

[0080] Exemplarily, the fifth pin 35 is a clock signal pin (Clock).

[0081] Exemplarily, the sixth pin 36 is a negative power supply pin (VSS), which is used to be connected to a power source and to control the negative electrode of each pixel chip.

[0082] Exemplarily, the seventh pin 37 is a non-connected pin (NC).

[0083] Exemplarily, the eighth pin 38 is an input pin (DI). The input pin is a data transmission pin used to receive a data signal to control and drive the pixel chip.

[0084] like Figure 4 、 5 As shown, one end of the first connecting trace 71 is connected to the first pin 31 through a through hole, one end of the second connecting trace 72 is connected to the second pin 32 through a through hole, the other end of the second connecting trace 72 is connected to the electrode block 65 connected to the first metal trace 61 through a through hole, one end of the third connecting trace 73 is connected to the third pin 33 through a through hole, the other end of the third connecting trace 73 is connected to the electrode block 65 connected to the second metal trace 62 through a through hole, one end of the fourth connecting trace 74 is connected to the fourth pin 34 through a through hole, the other end of the fourth connecting trace 74 is connected to the electrode block 65 connected to the third metal trace 63 through a through hole, one end of the fifth connecting trace 75 is connected to the fifth pin 35 through a through hole, one end of the sixth connecting trace 76 is connected to the sixth pin 36 through a through hole, one end of the seventh connecting trace 77 is connected to the electrode block 65 connected to the fourth metal trace 64 through a through hole, and one end of the eighth connecting trace 78 is connected to the eighth pin 38 through a through hole.

[0085] In the embodiment of the present disclosure, eight connecting lines corresponding to the pins of the driver chip 30 are set, and the connecting lines are extended to the area opposite to the electrode block of the first redistribution layer 60. In this way, some pins of the driver chip 30 can be connected to the electrodes of the pixel chip through the connecting lines, so as to achieve the purpose of the driver chip 30 controlling and driving the pixel chip.

[0086] like Figure 4 、 5 As shown, the pad 50 includes a first solder point 51, a second solder point 52, a third solder point 53, and a fourth solder point 54. The first solder point 51 is connected to the other end of the first connection trace 71 through a through hole, and the first solder point 51 is also connected to the other end of the seventh connection trace 77. In this way, the positive electrode pin of the driving power supply and the common positive electrode of the three pixel chips can be connected through the first solder point 51.

[0087] The second solder joint 52 is connected to the other end of the fifth connection trace 75 through a through hole, the third solder joint 53 is connected to the other end of the eighth connection trace 78 through a through hole, and the fourth solder joint 54 is connected to the other end of the sixth connection trace 76 through a through hole.

[0088] In the embodiment of the present disclosure, the solder pad 50 includes four solder points corresponding to the connecting traces, and each solder point is arranged in the edge area of ​​the insulating layer 23 and is opposite to the other end of each connecting trace. In this way, when a hole is opened on the insulating layer 23, the opened through hole can be a vertical hole without the need for bending and twisting, thereby reducing the difficulty of opening the hole and improving the preparation efficiency.

[0089] In the disclosed embodiment, the fourth metal trace 64 is connected to the positive electrodes of the three pixel chips. The first connecting trace 71 is connected to the first pin 31, which is the positive power supply pin. Therefore, the first connecting trace 71 electrically connects the positive power supply pin of the driver chip 30 to the positive electrodes of each pixel chip.

[0090] Alternatively, as Figure 4 、 5 As shown, the second connection trace 72 is also connected to the electrode block of the first metal trace 61 through a through hole.

[0091] In the disclosed embodiment, the first metal trace 61 is connected to the cathode of the first pixel chip 41. The second connection trace 72 is connected to the second pin 32, which is a cathode pin. Therefore, the second connection trace 72 electrically connects the cathode power pin of the driver chip 30 to the cathode of the first pixel chip 41.

[0092] Alternatively, as Figure 4 、 5 As shown, the third connecting trace 73 is also connected to the electrode block of the second metal trace 62 through a through hole.

[0093] In the disclosed embodiment, the second metal trace 62 is connected to the cathode of the second pixel chip 42. The third connection trace 73 is connected to the third pin 33, which is a cathode pin. Therefore, the third connection trace 73 electrically connects the negative power supply pin of the driver chip 30 to the cathode of the second pixel chip 42.

[0094] Alternatively, as Figure 4 、 5 As shown, the fourth connecting trace 74 is also connected to the electrode block of the third metal trace 63 through a through hole.

[0095] In the disclosed embodiment, the third metal trace 63 is connected to the cathode of the third pixel chip 43. The fourth connection trace 74 is connected to the fourth pin 34, which is a cathode pin. Therefore, the fourth connection trace 74 electrically connects the negative power supply pin of the driver chip 30 to the cathode of the third pixel chip 43.

[0096] In the embodiments disclosed herein, a three-color RGB pixel chip is used as an example for description. However, the actual situation is not limited to a three-color RGB pixel chip. For example, the pixel chip can be single-color, dual-color, or even four-color. The actual circuit connections on the driver IC are also not limited.

[0097] In one implementation, a separate cathode pin is provided on the driver IC, so that the driver IC is electrically connected to the cathode of the pixel chip through the cathode pin.

[0098] In some other implementations, a positive electrode pin may also be separately provided on the driver IC, so that the driver IC is electrically connected to the positive electrode of the pixel chip through the positive electrode pin.

[0099] The specific pin type to be used can be set according to actual conditions and is not limited in the embodiments of the present disclosure.

[0100] Optionally, the thickness of the first passivation layer 21 is greater than or equal to the thickness of the pixel chip, so as to ensure that the first passivation layer 21 can completely cover the pixel chip, thereby avoiding the problem of short circuit caused by other film layers being connected to the electrodes of the pixel chip.

[0101] Exemplarily, the thickness of the pixel chip is less than 10 μm, and the side length of the pixel chip is less than 50 μm. For example, when the thickness of the pixel chip is 3 μm, the thickness of the first passivation layer 21 may be 5 μm.

[0102] Exemplarily, the first passivation layer 21 may be at least one of a silicon oxide layer, a titanium oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0103] Alternatively, as Figure 1 As shown, the light emitting device may further include a light absorbing layer 26 .

[0104] For example, Figure 1 As shown, the light absorption layer 26 fills the gaps between the pixel chips to absorb the side light emitted between adjacent pixel chips.

[0105] Exemplarily, the first passivation layer 21 is stacked on the light absorption layer 26 , so that the insulating protection layer formed by the light absorption layer 26 and the first passivation layer 21 is more planarized, which is beneficial to the formation of subsequent film layers.

[0106] For example, the light-absorbing layer includes a silicon oxide layer and carbon particles filled in the silicon oxide layer. This makes the light-absorbing layer appear black, absorbing the side light emitted by each pixel chip and preventing light crosstalk between adjacent pixel chips.

[0107] Optionally, the thickness of the second passivation layer 22 is greater than or equal to the thickness of the driver chip 30. This ensures that the second passivation layer 22 can completely cover the driver chip 30 to avoid short circuits caused by other film layers being connected to the pins of the driver chip 30.

[0108] For example, the thickness of the driver chip 30 is less than 150 μm, and the side length of the driver chip 30 is less than 200 μm. For example, when the thickness of the driver chip 30 is 120 μm, the thickness of the second passivation layer 22 may be 200 μm.

[0109] Exemplarily, the second passivation layer 22 may be at least one of a silicon oxide layer, a titanium oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0110] Optionally, the substrate 10 may be a sapphire substrate or a glass substrate.

[0111] Optionally, the thickness of the substrate 10 is greater than 10 μm, the area of ​​the substrate 10 is greater than the sum of the areas of the three pixel chips, and the area of ​​the substrate 10 is also greater than the area of ​​the driver chip 30. This ensures that the pixel chips or the driver chip 30 do not protrude from the edge of the substrate 10 after being stacked.

[0112] Optionally, a first organic material bonding layer 24 may be further provided between the substrate 10 and the pixel chip 40 to enhance the connection reliability between the pixel chip and the substrate 10 .

[0113] Exemplarily, the first organic material bonding layer is a transparent organic material, and the light transmittance of the first organic material bonding layer is greater than 50%.

[0114] Optionally, a second organic material bonding layer 25 may be further provided between the first passivation layer 21 and the driving chip 30 to enhance the connection reliability between the driving chip 30 and the first passivation layer 21 .

[0115] Illustratively, the second organic material bonding layer may be a transparent material, or a non-transparent material or a semi-transparent material.

[0116] An embodiment of the present disclosure provides a display panel, which includes a circuit board and a plurality of light-emitting devices as described above. The plurality of light-emitting devices are located on the circuit board, and the pads of the light-emitting devices are electrically connected to the circuit board.

[0117] Among them, the pads of the driver chip in the light-emitting device are electrically connected to the drive traces on the circuit board. This not only reduces the number of electronic components for controlling and driving the pixel chip on the circuit board and simplifies the circuit board, but also solves the wiring difficulties existing in horizontal integration, the large area occupied by the driver IC, and the light shading problems of the driver IC.

[0118] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make slight changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A light emitting device, characterized in that: The light emitting device comprises: a substrate (10), a first passivation layer (21), a second passivation layer (22), a driving chip (30), a plurality of pixel chips (40) and a plurality of pads (50); The plurality of pixel chips (40) are located on the surface of the substrate (10); the first passivation layer (21) is located on the surface of the substrate (10) and covers the plurality of pixel chips (40); the driving chip (30) is located on a surface of the first passivation layer (21) away from the substrate (10); and at least part of the orthographic projections of the plurality of pixel chips (40) on the substrate (10) is located within the orthographic projection of the driving chip (30) on the substrate (10); The second passivation layer (22) is located on a surface of the first passivation layer (21) away from the substrate (10) and covers the driver chip (30); the plurality of pads (50) are located on a surface of the second passivation layer (22) away from the substrate (10); and the plurality of pads (50) are electrically connected to the pins of the driver chip (30) through through holes penetrating the second passivation layer (22); and at least some of the pads (50) are electrically connected to the electrodes of the pixel chip (40) through through holes penetrating the second passivation layer (22) and the first passivation layer (21).

2. The light emitting device according to claim 1, wherein The plurality of pixel chips (40) include: a first pixel chip (41), a second pixel chip (42), and a third pixel chip (43); the first pixel chip (41), the second pixel chip (42), and the third pixel chip (43) all emit different colors of light; The light emitting device further comprises a first redistribution layer (60), the first redistribution layer (60) being located on a surface of the first passivation layer (21) away from the substrate (10), the first redistribution layer (60) comprising a first metal trace (61), a second metal trace (62), a third metal trace (63) and a fourth metal trace (64), one end of the first metal trace (61) being connected to the first pixel chip (41) via a through hole, and one end of the second metal trace (62) being connected to the second pixel chip (41) via a through hole. (42), one end of the third metal trace (63) is connected to the third pixel chip (43) through a through hole, one end of the fourth metal trace (64) is connected to the first pixel chip (41), the second pixel chip (42) and the third pixel chip (43) through a through hole, and the other end of the first metal trace (61), the other end of the second metal trace (62), the other end of the third metal trace (63) and the other end of the fourth metal trace (64) all have an electrode block (65); At least part of the pad (50) is connected to the electrode block (65) via a through hole penetrating the second passivation layer (22).

3. The light emitting device according to claim 2, characterized in that The light-emitting device further comprises a second redistribution layer (70) and an insulating layer (23), wherein the second redistribution layer (70) is located on a surface of the second passivation layer (22) away from the substrate (10), and the insulating layer (23) is located on a surface of the second passivation layer (22) away from the substrate (10) and covers the second redistribution layer (70), a portion of the second redistribution layer (70) is connected to a pin of the driver chip (30) through a through hole, and another portion of the second redistribution layer (70) is connected to the electrode block through a through hole; The pad (50) is located on a surface of the insulating layer (23) away from the substrate (10), and the pad (50) is connected to the second redistribution layer (70) via a through hole penetrating the insulating layer (23).

4. The light emitting device according to claim 3, characterized in that The second redistribution layer (70) includes a first connecting line (71), a second connecting line (72), a third connecting line (73), a fourth connecting line (74), a fifth connecting line (75), a sixth connecting line (76), a seventh connecting line (77) and an eighth connecting line (78); The driver chip (30) has a first pin (31), a second pin (32), a third pin (33), a fourth pin (34), a fifth pin (35), a sixth pin (36), a seventh pin (37) and an eighth pin (38); one end of the first connecting wire (71) is connected to the first pin (31) through a through hole; one end of the second connecting wire (72) is connected to the second pin (32) through a through hole; one end of the third connecting wire (73) is connected to the third pin (33) through a through hole; and the fourth connecting wire (74) is connected to the 4) is connected to the fourth pin (34) through a through hole, one end of the fifth connecting wire (75) is connected to the fifth pin (35) through a through hole, one end of the sixth connecting wire (76) is connected to the sixth pin (36) through a through hole, one end of the seventh connecting wire (77) is connected to the seventh pin (37) through a through hole, one end of the eighth connecting wire (78) is connected to the eighth pin (38) through a through hole, and the four connecting wires in the second redistribution layer (70) are also connected to the four electrode blocks respectively through through holes; The soldering pad (50) includes a first soldering point (51), a second soldering point (52), a third soldering point (53) and a fourth soldering point (54), wherein the first soldering point (51) is connected to the other end of the first connecting trace (71) through a through hole, and the first soldering point (51) is also connected to the other end of the seventh connecting trace (77), the second soldering point (52) is connected to the other end of the fifth connecting trace (75) through a through hole, the third soldering point (53) is connected to the other end of the eighth connecting trace (78) through a through hole, and the fourth soldering point (54) is connected to the other end of the sixth connecting trace (76) through a through hole.

5. The light emitting device according to claim 4, characterized in that The first pin (31) is a negative pin, the second pin (32), the third pin (33) and the fourth pin (34) are all positive pins, the fifth pin (35) is a clock signal pin, the sixth pin (36) is a power pin, the seventh pin (37) is a free pin, and the eighth pin (38) is an input pin; The first connecting trace (71) is also connected to the electrode block of the fourth metal trace (64) through a through hole, the second connecting trace (72) is also connected to the electrode block of the first metal trace (61) through a through hole, the third connecting trace (73) is also connected to the electrode block of the second metal trace (62) through a through hole, and the fourth connecting trace (74) is also connected to the electrode block of the third metal trace (63) through a through hole. The light emitting device according to claim 3 , wherein: The insulating layer (23) comprises an organic material layer or an inorganic material layer.

7. The light emitting device according to any one of claims 1 to 6, characterized in that: The thickness of the first passivation layer (21) is greater than or equal to the thickness of the pixel chip.

8. The light emitting device according to any one of claims 1 to 6, characterized in that: The thickness of the second passivation layer (22) is greater than or equal to the thickness of the driving chip (30).

9. The light emitting device according to any one of claims 1 to 6, characterized in that: The thickness of the pixel chip is less than 10 μm, and the side length of the pixel chip is less than 50 μm; The thickness of the driving chip (30) is less than 150 μm, and the side length of the driving chip (30) is less than 200 μm.

10. A display panel, characterized in that: The display panel includes a circuit board and a plurality of light-emitting devices according to any one of claims 1 to 9, wherein the plurality of light-emitting devices are located on the circuit board, and pads of the light-emitting devices are electrically connected to the circuit board.

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