Display panel and electronic device including the same

Abstract

The invention discloses a display panel and electronic equipment comprising the display panel. The display panel includes: pixels; a signal line electrically connected to the pixel; and a signal pad connected to the signal line. The signal pad includes: a first conductive pattern connected to an end of the signal line; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern disposed between the first conductive pattern and the second conductive pattern. A first via is defined in the first conductive pattern. The insulating pattern extends into the first via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0033810 filed on March 11, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure herein relate to a display panel and an electronic device including the display panel, and more particularly, to a display panel including a pad area and an electronic device including the display panel. Background Art

[0004] The display device includes a display area that is activated in response to an electrical signal. The display device can detect input applied from the external environment through the display area. The display device can also display various images to provide visual information to the user.

[0005] The display device includes a display panel and a circuit board. The display panel can be electrically connected to the mainboard via the circuit board. A driver chip can be mounted on the display panel. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display panel having improved bonding reliability and an electronic device including the display panel.

[0007] According to an embodiment of the present invention, a display panel includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line. The signal pad includes: a first conductive pattern connected to an end of the signal line; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern disposed between the first and second conductive patterns. A first through-hole is defined in the first conductive pattern. The insulating pattern extends into the first through-hole.

[0008] In an embodiment, the entirety of the insulating pattern may be disposed in a plane inside each of the first and second conductive patterns.

[0009] In an embodiment, the second conductive pattern may be in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern in plane and a top surface of the insulating pattern.

[0010] In an embodiment, the first through hole may overlap with the insulating pattern in plane.

[0011] In embodiments, the insulating pattern may include a polymer.

[0012] In an embodiment, the display panel may further include: a pad insulating layer disposed between an end portion of the signal line and the first conductive pattern; a second through hole extending from the first through hole may be defined in the pad insulating layer; and the insulating pattern may extend into the first through hole.

[0013] In an embodiment, the first through hole may be provided in plural.

[0014] According to an embodiment of the present invention, a display panel includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line. The signal pad includes: a first conductive pattern connected to an end of the signal line; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern, the entire insulating pattern being disposed within each of the first and second conductive patterns in a planar manner. The insulating pattern includes: a first portion disposed between the first and second conductive patterns; and a second portion protruding from the first portion in a direction away from an upper surface of the second conductive pattern.

[0015] In an embodiment, a first via hole may be defined in the first conductive pattern, and the second portion of the insulating pattern may be disposed inside the first via hole.

[0016] In an embodiment, the second conductive pattern may be in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern in plane and a top surface of the insulating pattern.

[0017] In embodiments, the insulating pattern may include a polymer.

[0018] In an embodiment, the first through hole may overlap with the insulating pattern in plane.

[0019] In an embodiment, the display panel may further include: a pad insulating layer disposed between an end portion of the signal line and the first conductive pattern. A second through hole extending from the first through hole may be defined in the pad insulating layer, and the second portion of the insulating pattern may extend into the second through hole.

[0020] In an embodiment, the first through hole may be provided in plural.

[0021] According to an embodiment of the present inventive concept, an electronic device includes: a display panel including a signal pad; an electronic component electrically connected to the display panel; and an adhesive layer bonding the display panel and the electronic component to each other. The signal pad includes: a first conductive pattern having a first through-hole defined therein; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern disposed between the first and second conductive patterns. The first through-hole overlaps the insulating pattern in planar view.

[0022] In embodiments, the insulation pattern may extend into the first via hole.

[0023] In an embodiment, the entirety of the insulating pattern may be disposed inside each of the first and second conductive patterns on a plane, and the insulating pattern may include a polymer.

[0024] In an embodiment, the second conductive pattern may be in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern in plane and a top surface of the insulating pattern.

[0025] In an embodiment, the display panel may further include: a pad insulating layer disposed below the first conductive pattern; a second through hole extending from the first through hole may be defined in the pad insulating layer; and the insulating pattern may extend into the second through hole.

[0026] In an embodiment, the first through hole may be provided in plural. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings:

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the inventive concept;

[0029] Figure 2A and Figure 2B Each is an exploded perspective view of a display device according to an embodiment of the inventive concept;

[0030] Figure 3 is a cross-sectional view of a display module according to an embodiment of the inventive concept;

[0031] Figure 4 is a plan view of a display panel according to an embodiment of the inventive concept;

[0032] Figure 5 is a cross-sectional view of a display panel illustrating a pixel according to an embodiment of the inventive concept;

[0033] Figure 6 is an enlarged exploded perspective view of a pad region of a display device according to an embodiment of the inventive concept;

[0034] Figure 7A is a schematic plan view of a pad region according to an embodiment of the inventive concept;

[0035] Figure 7B and Figure 7C each being a cross-sectional view of a pad region according to an embodiment of the inventive concept;

[0036] Figure 8 is a cross-sectional view illustrating a coupling structure of a display device according to an embodiment of the inventive concept; and

[0037] Figures 9A to 9E Each is a cross-sectional view of a pad region according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0038] It will be understood that in this specification, when an element (or region, layer, section, etc.) is referred to as being "on," "connected to," or "coupled to" another element, it may be directly disposed on, directly connected to, or coupled to the other element, or a third element may be disposed between the elements. When an element (or region, layer, section, etc.) is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there may be no intervening elements.

[0039] The same reference numerals or symbols always refer to the same elements. In addition, in the drawings, the thickness, ratio and size of each element may be exaggerated in order to effectively describe the technical content. The term "and / or" includes one or more combinations that the relevant elements can define.

[0040] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the teachings of the present invention, and similarly, a second element may be referred to as a first element. As used herein, the singular is intended to include the plural, unless the context clearly indicates otherwise.

[0041] In addition, terms such as "below," "below," "upper," and "above" are used to explain the relationship between elements shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0042] It will be further understood that when used herein, terms such as “include” or “have” indicate the presence of recited features, numbers, steps, operations, elements, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts or combinations thereof.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0044] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0045] Figure 1 is a perspective view of a display device DD according to an embodiment of the inventive concept. Figure 2A and Figure 2B Each is an exploded perspective view of a display device DD according to an embodiment of the present invention. As an example, Figure 2B The diagram shows the Figure 2A The display device DD is in a state where the bending area BA shown in the figure is bent.

[0046] refer to Figure 1 , a mobile phone terminal is illustrated as an example of a display device DD. The display device DD according to an embodiment of the present inventive concept can be applied to large electronic devices such as televisions or monitors, and can also be applied to small and medium-sized electronic devices such as tablet computers, vehicle navigation units, game consoles, or smart watches.

[0047] In an embodiment, the display device DD may have a rectangular shape on a plane having relatively long sides extending in a first direction DR1 and relatively short sides extending in a second direction DR2 intersecting the first direction DR1. However, embodiments of the present inventive concept are not necessarily limited thereto, and the display device DD may have various shapes on a plane (e.g., in a plan view), such as a circular shape and other polygonal shapes.

[0048] Hereinafter, a direction substantially perpendicularly crossing a plane defined by the first and second directions DR1 and DR2 is defined as a third direction DR3. The description "when viewed on a plane" or "in a plan view" herein may mean a state viewed in the third direction DR3.

[0049] The display device DD may be rigid or flexible. The term "flexible" refers to the property of being able to bend and may include any structure ranging from a fully foldable structure to a structure that can bend at the level of a few nanometers. For example, in an embodiment, a flexible display device DD may include a curved display device, a rollable display device, and a foldable display device.

[0050] The display device DD can display an image IM via a display surface DD-IS. Figure 1 In the embodiment of the present invention, the image IM is a software application icon and a clock, temperature, and calendar window. However, the embodiments of the present inventive concept are not necessarily limited thereto, and the image IM can be a variety of different themes. The display surface DD-IS can be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0051] The display surface DD-IS may include a display area DD-DA that displays an image IM and a non-display area DD-NDA adjacent to the display area DD-DA (e.g., in the first direction DR1 and / or the second direction DR2). The non-display area DD-NDA may be an area that does not display the image IM. However, embodiments of the present inventive concept are not necessarily limited thereto, and the non-display area DD-NDA may be adjacent to only one side of the display area DD-DA, or may be omitted.

[0052] refer to Figure 2A and Figure 2B , the display device DD may include a window WM, a display module DM and a receiving member BC.

[0053] The window WM can be arranged above the display module DM (for example, in the third direction DR3) and transmit the image provided from the display module DM to the outside (for example, the external environment). In an embodiment, the window WM may include a base layer and a functional layer provided on the base layer. In an embodiment, the functional layer may include a protective layer and an anti-fingerprint layer, etc. In an embodiment, the base layer of the window WM may be made of glass, sapphire or plastic, etc. The base layer of the window WM may include an optically transparent insulating material. For example, the base layer of the window WM may include glass or a plastic film, or include a glass substrate and a plastic film connected to each other by an adhesive.

[0054] The window WM may include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may be aligned with (eg, in the third direction DR3) the transmissive area TA. Figure 1 The non-transmission area NTA may overlap with the display area DD-DA shown in FIG. 1 and have a shape corresponding to the shape of the display area DD-DA. The non-transmission area NTA may overlap with the display area DD-DA (for example, in the third direction DR3). Figure 1, and has a shape corresponding to that of the non-display area DD-NDA. The non-transmission area NTA may be a region having a relatively low light transmittance compared to the transmission area TA. In an embodiment, the non-transmission area NTA may be defined in a portion of the base layer of the window WM by a border pattern, and the region where the border pattern is not provided may be defined as the transmission area TA. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, the non-transmission area NTA may be omitted.

[0055] In an embodiment, an anti-reflection layer may be provided between the window WM and the display module DM (e.g., in the third direction DR3). The anti-reflection layer may reduce the reflectivity of external light incident from outside the display device DD. In an embodiment, the anti-reflection layer may include a color filter. The color filter may have a predetermined arrangement. For example, the color filter may be arranged taking into account the emission colors of the pixels included in the display panel DP, which will be described later. In addition, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0056] According to an embodiment of the inventive concept, the display module DM may include a display panel DP and an input sensor ISU.

[0057] In an embodiment, the display panel DP may be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot light-emitting display panel. However, the embodiments of the present inventive concept are not necessarily limited thereto. Hereinafter, for ease of explanation, the display panel DP will be described as an organic light-emitting display panel.

[0058] In embodiments, the input sensor ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. In embodiments, the input sensor ISU may be formed on the display panel DP through a continuous process, or may be separately manufactured and subsequently attached to the upper side of the display panel DP via an adhesive layer. However, the input sensor ISU is not necessarily limited to any one embodiment.

[0059] The display device DD may further include a driver chip DC disposed on the display panel DP. The display device DD may further include a circuit board PB disposed on the display panel DP. In an embodiment, the circuit board PB may be a flexible circuit board. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP to the mainboard.

[0060] The driving chip DC may include driving elements such as a data driving circuit for driving pixels of the display panel DP. Figure 2A The diagram illustrates a structure in which the driver chip DC is mounted on the display panel DP. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, the driver chip DC may be mounted on the circuit board PB. In this embodiment, the driver chip DC and the circuit board PB, which are directly mounted on the display panel DP, may be collectively referred to as electronic components.

[0061] In an embodiment, the display panel DP may include a bending area BA and first and second non-bending areas NBA1 and NBA2 arranged to be spaced apart from each other in the first direction DR1 with the bending area BA therebetween.

[0062] The bending area BA can be defined as an area in which the display panel DP can be bent along a virtual bending axis BX extending in the second direction DR2. The first non-bending area NBA1 can be defined as an area overlapping with the transmissive area TA (for example, in the third direction DR3), and the second non-bending area NBA2 can be defined as an area to which the circuit board PB is connected (for example, mounted). When the bending area BA is bent about the bending axis BX, the circuit board PB and the driver chip DC can be bent in a direction toward the rear surface of the display panel DP, thereby being disposed below the rear surface of the display panel DP. In an embodiment, the display device DD may include additional components for compensating for the height difference between the circuit board PB and the rear surface of the display panel DP that may be generated due to the bending area BA.

[0063] According to an embodiment, the width of the first non-bending area NBA1 in the second direction DR2 can be greater than the width of each of the bending area BA and the second non-bending area NBA2 in the second direction DR2. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, the width of the bending area BA in the second direction DR2 can gradually decrease from the first non-bending area NBA1 toward the second non-bending area NBA2, and is not necessarily limited to any one embodiment.

[0064] like Figure 2B As illustrated in FIG, since a portion of the display panel DP is bent, the circuit board PB electrically coupled to the display panel DP may be disposed on the rear surface of the display panel DP.

[0065] The receiving member BC may receive the display module DM and may be coupled to the window WM. The circuit board PB may be provided at one end of the display panel DP and may be electrically connected to the reference Figure 3 The circuit element layer DP-CL is described. For example, Figure 2AAs shown in FIG, the circuit board PB may be disposed at the lower end of the display panel DP in the first direction DR1. In an embodiment, the display device DD may further include a main board and an electronic module, a camera module, a power module, etc. mounted on the main board.

[0066] Although a mobile phone terminal is described above as an example of a display device DD, the display device DD may be various other electronic devices including two or more combined electronic components. For example, in an embodiment, the display panel DP and the driver chip DC mounted on the display panel DP may correspond to electronic components different from each other, and only these components may constitute the display device DD. The display panel DP and the circuit board PB connected to the display panel DP may also correspond to electronic components different from each other, and only these components may constitute the display device DD. Alternatively, only the main board and the electronic module mounted on the main board may constitute the display device DD. Hereinafter, the display device DD according to an embodiment conceived by the present invention will be described mainly with respect to the combined structure of the display panel DP and the driver chip DC mounted on the display panel DP.

[0067] Figure 3 is a cross-sectional view of a display module DM according to an embodiment of the inventive concept.

[0068] refer to Figure 3 In an embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL. The input sensor ISU may be disposed on (eg, directly disposed on) the upper insulating layer TFL.

[0069] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. In an embodiment, the display area DP-DA of the display panel DP may be Figure 1 The display area DD-DA shown in the figure or Figure 2A The non-display area DP-NDA may correspond to the transmission area TA shown in FIG. Figure 1 The non-display area DD-NDA shown in the figure or Figure 2A Corresponding to the non-transmitting area NTA shown in FIG.

[0070] The base layer BL may include at least one plastic film. In an embodiment, the base layer BL may be a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like.

[0071] The circuit element layer DP-CL may include circuit elements and at least one intermediate insulating layer. In an embodiment, the intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements may include signal lines and pixel driving circuits, etc. In an embodiment, the insulating layer, the semiconductor layer, and the conductive layer are formed by processes such as coating or deposition. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. are formed by these processes. Patterns set in the same layer are formed by the same process. Hereinafter, patterns formed by the same process mean that the patterns include the same material and have the same stacking structure.

[0072] The display element layer DP-OLED may include a plurality of light emitting elements. In an embodiment, the display element layer DP-OLED may further include an organic layer such as a pixel defining film.

[0073] The upper insulating layer TFL may seal the display element layer DP-OLED. The upper insulating layer TFL may be disposed (e.g., directly disposed) on the display element layer DP-OLED. The upper insulating layer TFL may overlap with the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL may overlap with at least a portion of the non-display area DP-NDA. As an example, the upper insulating layer TFL may include a thin film encapsulation layer. In an embodiment, the thin film encapsulation layer may include a stacked structure of an inorganic layer / organic layer / inorganic layer. The upper insulating layer TFL may protect the display element layer DP-OLED from moisture, oxygen, and foreign matter such as dust particles. However, the embodiments of the present invention are not necessarily limited thereto, and in addition to the thin film encapsulation layer, the upper insulating layer TFL may further include an additional insulating layer. For example, an optical insulating layer for controlling the refractive index may be further included.

[0074] In an embodiment of the present inventive concept, an encapsulation substrate may be provided instead of the upper insulating layer TFL. In this embodiment, the encapsulation substrate may be opposite to the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may be disposed between the encapsulation substrate and the base layer BL (e.g., in the third direction DR3).

[0075] In an embodiment, the input sensor ISU may be disposed directly on the display panel DP. Herein, "component A is disposed directly on component B" means that no separate layer (e.g., an intermediate layer) is disposed between component A and component B. In this embodiment, the input sensor ISU may be manufactured together with the display panel DP through a continuous process. However, embodiments of the present inventive concept are not necessarily limited thereto, and the input sensor ISU may be provided as a separate panel to be coupled to the display panel DP via an adhesive layer. Alternatively, as an example, the input sensor ISU may be omitted.

[0076] Figure 4 is a plan view of a display panel DP according to an embodiment of the inventive concept.

[0077] refer to Figure 4 In an embodiment, the display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of signal pads DP-PD.

[0078] The pixels PX may be arranged in the display area DP-DA. Each of the pixels PX includes a light-emitting element and a pixel driving circuit connected to the light-emitting element. In an embodiment, the light-emitting element may be an organic light-emitting element. However, the embodiments of the present invention are not necessarily limited thereto. The gate driving circuit GDC sequentially outputs gate signals to a plurality of gate lines GL to be described later. In an embodiment, the transistors of the gate driving circuit GDC may be formed by the same process as the transistors of the pixels PX (e.g., a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process). The display panel DP may further include another driving circuit that provides an emission control signal to the pixels PX.

[0079] In an embodiment, the signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel PX among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel PX among the pixels PX. The power lines PL may be connected to the pixels PX. The control signal lines CSL may provide control signals to the gate drive circuit GDC.

[0080] The signal lines SGL may overlap the display area DP-DA and the non-display area DP-NDA (e.g., in the third direction DR3). Each of the signal lines SGL may include a line portion LP. In an embodiment, each of the signal lines SGL may further include a pad portion. The line portion LP may overlap the display area DP-DA and the non-display area DP-NDA (e.g., in the third direction DR3). The pad portion may be connected to an end of the line portion LP.

[0081] In an embodiment, the plurality of signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The area where the first and second pads PD1 and PD2 are disposed may be defined as a first pad area PA1, and the area where the third pad PD3 is disposed may be defined as a second pad area PA2.

[0082] The first pad area PA1 may be Figure 2AThe first pad area PA1 may include an area overlapping with the driver chip DC in the display area, and the second pad area PA2 may be an area overlapping with the circuit board PB. In an embodiment, the first pad area PA1 may include a first area B1 in which the first pad PD1 is provided and a second area B2 in which the second pad PD2 is provided. The first pad area PA1 and the second pad area PA2 may be provided within the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in the first direction DR1. Although an example in which one pad row is provided in the first pad area PA1 is illustrated, embodiments of the present inventive concept are not necessarily limited thereto, and a plurality of pad rows may be provided in the first pad area PA1.

[0083] In an embodiment, each of the first pads PD1 may be connected to a corresponding data line among the data lines DL. The first pads PD1 and the second pads PD2 may be electrically connected to each other. The second pads PD2 may be connected to the third pads PD3 through connection signal lines SCLn, respectively.

[0084] The circuit board PB may include a plurality of plate bump electrodes PB-BP. In an embodiment, the plurality of plate bump electrodes PB-BP may be arranged in the second direction DR2. In an embodiment, the plate bump electrodes PB-BP of the circuit board PB may directly contact the third pads PD3 of the second pad area PA2 to be electrically connected to the third pads PD3.

[0085] Figure 5 is a cross-sectional view of the display panel DP illustrating a pixel PX according to an embodiment of the inventive concept.

[0086] refer to Figure 5 , the display area DP-DA may include an emission area PXA and a non-emission area NPXA. Each of the pixels PX may include a light-emitting element OLED and a pixel driving circuit connected to the light-emitting element OLED. For example, the pixel PX may include a transistor TR and a light-emitting element OLED.

[0087] As an example, in Figure 5 , one transistor TR is illustrated. However, embodiments of the present inventive concept are not necessarily limited thereto. In an embodiment, a pixel PX according to an embodiment may include seven transistors and at least one capacitor, and the seven transistors and the capacitor may be electrically connected to each other. However, the number of each of the transistors and capacitors constituting the pixel PX is not necessarily limited to any one embodiment and may vary.

[0088] In embodiments, the display panel DP may include semiconductor patterns, conductive patterns, signal lines, and multiple insulating layers. The insulating layers, semiconductor layers, and conductive layers may be formed through processes such as coating or deposition. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned through photolithography and etching processes. These processes may form the semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED.

[0089] The base layer BL may include a synthetic resin film. The base layer BL may have a multilayer structure. For example, in an embodiment, the base layer BL may have a three-layer structure comprising a synthetic resin layer, an inorganic layer, and a synthetic resin layer. For example, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. Alternatively, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0090] In embodiments, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, first to sixth insulating layers 10 to 60 , a transistor TR, a connection signal line SCLd, an upper electrode UE, first and second connection electrodes CNE1 and CNE2 .

[0091] At least one inorganic layer is disposed on (e.g., directly disposed on) the top surface of the base layer BL. The inorganic layer may be provided in a multilayer structure. The barrier layer BRL may be disposed on the base layer BL (e.g., directly disposed thereon in the third direction DR3). The buffer layer BFL may be disposed on the barrier layer BRL (e.g., directly disposed thereon in the third direction DR3). The barrier layer BRL and the buffer layer BFL may be inorganic layers.

[0092] The semiconductor pattern is disposed on the buffer layer BFL (e.g., directly thereon in the third direction DR3). In an embodiment, the semiconductor pattern may include polysilicon. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, the semiconductor pattern may include amorphous silicon or metal oxide.

[0093] Figure 5 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may be further arranged in other areas of the pixel PX on a plane. For example, the semiconductor pattern may be arranged across multiple pixels PX according to a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region and a second region. The first region may be doped with an n-type dopant or a p-type dopant. The p-type transistor includes a doped region doped with a p-type dopant.

[0094] The first region may have a higher conductivity than that of the second region and may function substantially as an electrode or signal line. The second region may be a region having a low doping concentration or being undoped and may substantially correspond to an active portion (e.g., a channel) of a transistor. For example, a portion of the semiconductor pattern may be the active portion of the transistor, another portion thereof may be the source or drain of the transistor, and yet another portion thereof may be a connection electrode or a connection signal line SCLd.

[0095] like Figure 5 As illustrated in , the source S, the active portion A, and the drain D of the transistor TR may be provided by a semiconductor pattern.

[0096] Figure 5 A portion of a connection signal line SCLd provided by the semiconductor pattern is illustrated. In an embodiment, the connection signal line SCLd may be electrically connected to a drain of one of the transistors in the pixel PX.

[0097] The first insulating layer 10 is disposed on the buffer layer BFL (for example, directly thereon in the third direction DR3). The first insulating layer 10 may cover the semiconductor pattern. In an embodiment, the first insulating layer 10 may overlap with the plurality of pixels PX in common. The gate G may be disposed on the first insulating layer 10 (for example, directly thereon in the third direction DR3). In an embodiment, the gate G may be part of the metal pattern. The gate G may overlap with the active portion A (for example, in the third direction DR3). In an embodiment, the gate G may be used as a mask in a process of doping the semiconductor pattern.

[0098] The second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10 (e.g., directly thereon in the third direction DR3). In an embodiment, the second insulating layer 20 may overlap with a plurality of pixels PX in common. The upper electrode UE may be disposed on the second insulating layer 20 (e.g., directly thereon in the third direction DR3). The upper electrode UE may overlap with the gate G of the transistor TR (e.g., in the third direction DR3). In an embodiment, the upper electrode UE may be part of a metal pattern. In an embodiment, a portion of the gate G and the upper electrode UE overlapping the portion may define a capacitor.

[0099] The third insulating layer 30 covering the upper electrode UE may be disposed on the second insulating layer 20 (e.g., directly thereon in the third direction DR3). In an embodiment, the first connection electrode CNE1 disposed on the third insulating layer 30 may be connected to (e.g., directly connected to) the connection signal line SCLd through a contact hole CNT-1 passing through the first to third insulating layers 10 to 30.

[0100] The fourth insulating layer 40 covering the first connection electrode CNE1 may be disposed on the third insulating layer 30 (eg, directly thereon in the third direction DR3 ). The first to fourth insulating layers 10 to 40 may be inorganic and / or organic layers and may have a single-layer or multi-layer structure.

[0101] In embodiments, the first connection electrode CNE1 may be disposed on the fourth insulating layer 40 and may be covered by the fifth insulating layer 50. Alternatively, embodiments may include both of the first connection electrode disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 and the first connection electrode disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50.

[0102] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 (e.g., directly thereon in the third direction DR3). The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50 (e.g., directly thereon in the third direction DR3). In embodiments, the second connection electrode CNE2 may be connected (e.g., directly connected) to the first connection electrode CNE1 via a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0103] The sixth insulating layer 60 covering the second connection electrode CNE2 may be disposed on the fifth insulating layer 50 (e.g., directly thereon in the third direction DR3). The sixth insulating layer 60 may be an organic layer. The first electrode AE ​​may be disposed on the sixth insulating layer 60 (e.g., directly thereon in the third direction DR3). In embodiments, the first electrode AE ​​may be connected to (e.g., directly connected to) the second connection electrode CNE2 via a contact hole CNT-3 passing through the sixth insulating layer 60.

[0104] The circuit element layer DP-CL may include a plurality of connection electrodes connected to each transistor, and some of these plurality of connection electrodes may be provided at different layers. In an embodiment, the first connection electrode CNE1 may extend to connect to the transistor TR. However, the positions of the plurality of connection electrodes are not necessarily limited to any one embodiment.

[0105] The display element layer DP-OLED may include a pixel defining film PDL and a light-emitting element OLED. A pixel opening portion OPN may be defined in the pixel defining film PDL. The pixel opening portion OPN of the pixel defining film PDL may expose at least a portion of the first electrode AE ​​(e.g., a central portion of the first electrode AE). In this embodiment, the emission area PXA may be defined as a portion of the first electrode AE ​​exposed by the pixel opening portion OPN.

[0106] In an embodiment, the hole control layer HCL may be commonly disposed in the emission region PXA and the non-emission region NPXA. The hole control layer HCL may include a hole transport layer and / or a hole injection layer. The emission layer EML may be disposed on the hole control layer HCL (for example, directly thereon in the third direction DR3). In an embodiment, the emission layer EML may be disposed in an area corresponding to the pixel opening portion OPN. For example, an emission layer EML may be provided separately in each of the plurality of pixels PX. However, the embodiments of the present invention are not necessarily limited thereto, and the emission layer EML may be provided commonly in the plurality of pixels PX by using an open mask.

[0107] In an embodiment, the electron control layer ECL may be disposed on the emission layer EML (for example, directly thereon in the third direction DR3). The electron control layer ECL may include an electron transport layer and / or an electron injection layer. The hole control layer HCL and the electron control layer ECL may be provided in common in a plurality of pixels PX by using an open mask. The second electrode CE may be disposed on the electron control layer ECL (for example, directly thereon in the third direction DR3). The second electrode CE may have an integral shape and be commonly disposed in a plurality of pixels PX. The upper insulating layer TFL may be disposed on the second electrode CE (for example, directly thereon in the third direction DR3). The upper insulating layer TFL may include a plurality of thin films.

[0108] Figure 6 is an enlarged exploded perspective view of pad areas PA1 and PA2 of a display device DD according to an embodiment of the inventive concept. As an example, Figure 6 The driving chip DC and the circuit board PB are illustrated as being separate from the display panel DP. Figure 6 The first pad PD1, the second pad PD2, the connection signal line SCLn and the third pad PD3 are respectively connected to Figure 4 The first pad PD1, the second pad PD2, the connection signal line SCLn, and the third pad PD3 in FIG. 1 are the same and thus will not be described again or will be described briefly.

[0109] refer to Figure 4 and Figure 6 In an embodiment, the driver chip DC may be bonded to the first pad area PA1 via a first adhesive layer CF1. The circuit board PB may be bonded to the second pad area PA2 via a second adhesive layer CF2. In an embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may each include a synthetic resin having adhesive properties. Each of the first adhesive layer CF1 and the second adhesive layer CF2 may be a non-conductive film. For example, each of the first adhesive layer CF1 and the second adhesive layer CF2 may include only a synthetic resin having adhesive properties without including conductive balls.

[0110] The driver chip DC may include a driver integrated circuit D-IC and chip bump electrodes DC-BP mounted in the driver chip DC. The driver integrated circuit D-IC may include a top surface DC-US and a bottom surface DC-DS opposite to the top surface DC-US (e.g., in a third direction DR3), and the bottom surface DC-DS may be a surface facing the first and second pads PD1 and PD2. The chip bump electrodes DC-BP may be provided on the bottom surface DC-DS of the driver integrated circuit D-IC.

[0111] In an embodiment, the chip bump electrode DC-BP may include first bumps BP1 electrically connected to the first pads PD1 and second bumps BP2 electrically connected to the second pads PD2. In an embodiment, the first bumps BP1 may be arranged in the second direction DR2, and the second bumps BP2 may be spaced apart from the first bumps BP1 in the first direction DR1 and arranged in the second direction DR2.

[0112] In an embodiment, the driver chip DC may receive a first signal from the outside (e.g., an external device) through the second pad PD2 and the second bump BP2. The driver chip DC may provide a second signal generated based on the first signal to the first pad PD1 through the first bump BP1. For example, the driver chip DC may include a data driving circuit. The first signal may be an image signal that is a digital signal applied from the outside (e.g., an external device), and the second signal may be a data signal that is an analog signal. In an embodiment, the driver chip DC may generate an analog voltage corresponding to the grayscale value of the image signal. The data signal may be generated by Figure 4 The data lines DL illustrated in FIG. 8 are provided to the pixels PX.

[0113] In an embodiment, each of the first bump BP1 and the second bump BP2 may have a shape protruding from the bottom surface DC-DS of the driver integrated circuit D-IC to be exposed to the outside (e.g., the external environment). When the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed in a contact state, and the second pad PD2 and the second bump BP2 may be fixed in a contact state.

[0114] In an embodiment, the circuit board PB may include a base layer P-BS and a board bump electrode PB-BP installed in the circuit board PB. The base layer P-BS may include a top surface PB-US and a bottom surface PB-DS, and the bottom surface PB-DS may be a surface facing the third pad PD3 (for example, in the third direction DR3). The board bump electrode PB-BP may be provided on the bottom surface PB-DS of the base layer P-BS. The board bump electrodes PB-BP may be electrically connected to the third pad PD3, respectively. The board bump electrodes PB-BP may be arranged in the second direction DR2. The circuit board PB may provide image signals, driving voltages, and other control signals to the driver chip DC.

[0115] In an embodiment, the plate bump electrode PB-BP may have a shape protruding from the bottom surface PB-DS of the base layer P-BS to be exposed to the outside (e.g., the external environment). When the second adhesive layer CF2 is cured, the third pad PD3 and the plate bump electrode PB-BP may be fixed in a contact state.

[0116] The electronic component may include a substrate and a bump electrode disposed below the substrate. In an embodiment where the electronic component corresponds to a driver chip DC, the substrate may correspond to a driver integrated circuit D-IC of the driver chip DC, and the bump electrode may correspond to a chip bump electrode DC-BP. Alternatively, in an embodiment where the electronic component corresponds to a circuit board PB, the substrate may correspond to a base layer P-BS of the circuit board PB, and the bump electrode may correspond to a board bump electrode PB-BP.

[0117] Figure 7A is a schematic plan view of pad areas PA1 and PA2 according to an embodiment of the inventive concept. Figure 7B and Figure 7C Each is a cross-sectional view of pad areas PA1 and PA2 according to an embodiment of the inventive concept. Figure 7B The pad area PA1 and PA2 are Figure 7A The cross-sectional view corresponding to the line AA' in FIG. Figure 7C The pad area PA1 and PA2 are Figure 7A The cross-sectional view corresponding to the line BB' in FIG. Figure 8 is a cross-sectional view illustrating a coupling structure of a display device DD according to an embodiment of the inventive concept.

[0118] Figures 7A to 8 The signal pad DP-PD (eg, signal pad structure) shown in FIG. Figure 4 and Figure 6 As an example of a signal line, any one of the first to third pads PD1 to PD3 described. Figure 7AThe data line DL is illustrated as including an end portion DL-E and a line portion DL-S having different widths from each other. However, embodiments of the present invention are not necessarily limited thereto. Here, the width may refer to the length or width of the end portion DL-E or the line portion DL-S in the second direction DR2. The signal line may be a signal line other than the data line DL and may have a uniform width regardless of the end portion DL-E and the line portion DL-S. The end portion DL-E may correspond to the above reference numeral 1. Figure 4 described in the pad section.

[0119] Hereinafter, the pad areas PA1 and PA2 will be described mainly in terms of the first pad area PA1 in which the data line DL is disposed. Figure 4 The same description of the first pad area PA1 may be applied to the second pad area PA2, except that the data line DL is replaced by a 12A .

[0120] refer to Figure 7A In an embodiment, the signal pad DP-PD may include a first conductive pattern CL1, a second conductive pattern CL2, and at least one insulating pattern SP. In an embodiment, the first conductive pattern CL1 may be connected to the end DL-E of the data line DL through at least one contact hole OP-C. As an example, Figure 7A The embodiment shown in FIG illustrates the signal pad DP-PD including seven contact holes OP-C and six insulating patterns SP. However, the number of the contact holes OP-C and the number of the insulating patterns SP are not necessarily limited thereto.

[0121] The end portion DL-E may have a shape extending longitudinally in the first direction DR1 on a plane. For example, the length or width of the end portion DL-E in the first direction DR1 may be greater than the length or width in the second direction DR2.

[0122] The contact hole O-C may overlap with the end portion DL-E in a plane. In an embodiment, the contact holes O-C may be arranged in the first direction DR1. For example, each of the contact holes O-C may be arranged to be spaced apart from each other in the first direction DR1. A portion of the first conductive pattern CL1 may overlap with the contact hole OP-C in a plane.

[0123] The insulating pattern SP may overlap the second conductive pattern CL2 in a plane. The insulating pattern SP may be arranged to be spaced apart from the contact hole OP-C in a plane. For example, the insulating pattern SP may be spaced apart from the contact hole OP-C in the first direction DR1. In an embodiment, the insulating pattern SP may be arranged in the first direction DR1. For example, the insulating patterns SP may be spaced apart from each other in the first direction DR1.

[0124] In an embodiment, each of the insulating patterns SP may be disposed between the contact holes OP-C adjacent thereto. As an example, Figure 7A The six insulating patterns SP are illustrated as being respectively provided in six planes between the seven contact holes O-C However, the arrangement relationship of the insulating patterns SP with respect to the contact holes O-C is not necessarily limited thereto.

[0125] As an example, Figure 7A The insulating patterns SP are shown as each having a circular shape in a plan view. However, embodiments of the present inventive concept are not necessarily limited thereto. The shape of the insulating pattern SP in a plan view may be changed to a polygonal shape, an elliptical shape, or the like. Furthermore, the shapes of the insulating patterns SP are not limited to being identical to one another. For example, one or more insulating patterns SP (e.g., in a plan view) may have a different shape from the remaining insulating patterns SP.

[0126] refer to Figure 7B and Figure 7C The end portion DL-E may be disposed on the first insulating layer 10 (eg, directly thereon in the third direction DR3). Figure 5 The gate G shown in FIG. 1 is provided in the same layer. In an embodiment, the end portion DL-E may be formed by the same process as the gate G. The end portion DL-E may include the same material as the gate G.

[0127] However, the embodiments of the present inventive concept are not necessarily limited thereto, and the position of the end portion DL-E may be changed. For example, in an embodiment, the end portion DL-E may be Figure 5 The upper electrode UE shown in FIG is provided in the same layer, includes the same material and has the same stacking structure. Alternatively, in an embodiment, some of the plurality of signal lines may be connected to the gate G (see FIG. Figure 5 ) is formed by the same process, and the other signal lines can be connected to the upper electrode UE (see Figure 5 ) are formed by the same process.

[0128] In an embodiment, the data line DL may be provided in one layer to have an integral shape. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, one data line DL may include multiple portions provided in different layers. For example, the line portion DL-S may include two or more portions.

[0129] The first conductive pattern CL1 may be disposed on the fourth insulating layer 40 (e.g., directly thereon in the third direction DR3). The first conductive pattern CL1 may be connected to (e.g., directly connected to) the end portion DL-E through a contact hole OP-C passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. For example, the first conductive pattern CL1 may be in direct contact with the end portion DL-E through the contact hole OP-C. In an embodiment, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be respectively connected to the end portion DL-E. Figure 5 The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 of the display area DP-DA shown in FIG are formed by the same process. In this specification, the insulating layer disposed between the end portion DL-E and the first conductive pattern CL1 (for example, in the third direction DR3) may be defined as a pad insulating layer IL-P. For example, Figure 7B In the embodiment shown in FIG, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be defined as a pad insulating layer IL-P. However, embodiments of the present inventive concept are not necessarily limited thereto, and the stacking structure of the pad insulating layer IL-P may be configured according to the circuit element layer DP-CL (see FIG. Figure 5 For example, in an embodiment, the contact hole O-C may be defined by an additional insulating layer in addition to the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40, or may be defined by fewer insulating layers than the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40.

[0130] The first conductive pattern CL1 and the end portion DL-E may be distinguished by the pad insulating layer IL-P (eg, the second insulating layer 20 , the third insulating layer 30 , and the fourth insulating layer 40 ) disposed therebetween.

[0131] The second conductive pattern CL2 may be disposed (e.g., directly disposed) on the first conductive pattern CL1. A region (e.g., a first portion) of the second conductive pattern CL2 that does not overlap with the insulating pattern SP (e.g., in a plane) may be in direct contact with the first portion of the first conductive pattern CL1. A region (e.g., a second portion) of the second conductive pattern CL2 that overlaps with the insulating pattern SP may be in direct contact with the insulating pattern SP and may be spaced apart from the second portion of the first conductive pattern CL1 by the insulating pattern SP that overlaps with the second portion of the first conductive pattern CL1 in a plane.

[0132] In an embodiment, the first conductive pattern CL1 may be Figure 5 The first connection electrode CNE1 described above is formed by the same process, and the second conductive pattern CL2 can be formed by the same process as that described above. Figure 5The second connection electrode CNE2 is formed by the same process as described above. The first conductive pattern CL1 may be formed with the first connection electrode CNE1 (see Figure 5 ) include the same material, and the second conductive pattern CL2 may be connected to the second connection electrode CNE2 (see Figure 5 ) include the same materials. As an example, Figure 7B and Figure 7C Each illustrates an embodiment in which the first conductive pattern CL1 is disposed on (e.g., directly disposed on) the fourth insulating layer 40. However, embodiments of the present invention are not necessarily limited thereto. For example, in an embodiment, the first conductive pattern CL1 may be disposed on (e.g., directly disposed on) the third insulating layer 30, and in this embodiment, the fourth insulating layer 40 may not be disposed in the pad areas PA1 and PA2. However, embodiments of the present invention are not necessarily limited thereto, and may be configured according to the circuit element layer DP-CL (see Figure 5 ) stacking structure to differently select a combination of connection electrodes formed by the same process as the first conductive pattern CL1 and the second conductive pattern CL2, respectively, as long as the combination can provide the first conductive pattern CL1 and the second conductive pattern CL2 in different layers from each other.

[0133] As an example, in Figure 7B and Figure 7C , an embodiment is illustrated in which the second conductive pattern CL2 has a surface area larger than that of the first conductive pattern CL1 in a plan view, and the second conductive pattern CL2 has an edge disposed outside the edge of the first conductive pattern CL1 and covers the edge of the first conductive pattern CL1. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in an embodiment, the second conductive pattern CL2 (e.g., in a plan view) may have a surface area substantially the same as that of the first conductive pattern CL1, and the edge of the second conductive pattern CL2 may be substantially aligned with the edge of the first conductive pattern CL1.

[0134] A portion of the second conductive pattern CL2 may include a portion overlapping with the insulating pattern SP in a plan view. The insulating pattern SP may be disposed between the first conductive pattern CL1 and the second conductive pattern CL2 in a cross-sectional view (e.g., in the third direction DR3). The insulating pattern SP may be disposed (e.g., directly) on the first conductive pattern CL1 and may be covered by the second conductive pattern CL2. The second conductive pattern CL2 may cover the top surface of the insulating pattern SP. The insulating pattern SP may be disposed within each of the first conductive pattern CL1 and the second conductive pattern CL2 in a plan view. For example, the entire insulating pattern SP may be disposed within each of the first conductive pattern CL1 and the second conductive pattern CL2 in a plan view.

[0135] In an embodiment, the second conductive pattern CL2 may have a multilayer structure. For example, in an embodiment, the second conductive pattern CL2 may have a three-layer structure in which a first layer, a second layer, and a third layer are sequentially stacked (e.g., in the third direction DR3). The second layer may have a higher electrical conductivity than each of the first and third layers. For example, in an embodiment, the first and third layers may be titanium (Ti), and the second layer may be aluminum (Al).

[0136] A through hole HL1 may be defined in the first conductive pattern CL1. A through hole HL2 may also be defined in the pad insulating layer IL-P. The through hole HL1 passing through the first conductive pattern CL1 may be referred to as a first through hole, and the through hole HL2 passing through the pad insulating layer IL-P may be referred to as a second through hole.

[0137] In an embodiment where the through hole HL1 is defined only in the first conductive pattern CL1 and the through hole HL2 is not defined in the pad insulating layer IL-P, the through hole HL may include only the first through hole HL1. In an embodiment where the through holes HL1 and HL2 are defined in the first conductive pattern CL1 and the pad insulating layer IL-P, respectively, the through hole HL may include both the first through hole HL1 and the second through hole HL2.

[0138] The second through-hole HL2 may extend from (eg, directly extend from) the first through-hole HL1 to be provided integrally with the first through-hole HL1 . Figure 7C The embodiment in which the second through hole HL2 is defined in all of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 included in the pad insulating layer IL-P is illustrated. However, embodiments of the present inventive concept are not necessarily limited thereto. For example, in some embodiments, the second through hole HL2 may be defined only in the fourth insulating layer 40, or may be defined only in the third insulating layer 30 and the fourth insulating layer 40.

[0139] The through-hole HL may be defined in a portion that overlaps the insulating pattern SP in a plane. The through-hole HL may be filled with a portion of the insulating pattern SP. For example, in an embodiment, the insulating pattern SP may extend into the first through-hole HL1 and the second through-hole HL2. In an embodiment in which the insulating pattern SP is disposed on the first conductive pattern CL1 and fills the through-hole HL, the contact area between the insulating pattern SP and the layers disposed below the insulating pattern SP (e.g., the first conductive pattern CL1 and the pad insulating layer IL-P) may be increased compared to a comparative embodiment in which the insulating pattern SP is disposed on the first conductive pattern CL1 without the through-hole HL. Accordingly, the insulating pattern SP may be fixed and prevented from leaking from the layers disposed below the insulating pattern SP.

[0140] The top surface of the insulating pattern SP may be defined as a surface on which the insulating pattern SP is in direct contact with the second conductive pattern CL2. The bottom surface of the insulating pattern SP may be defined as all surfaces of the insulating pattern SP except the top surface of the insulating pattern SP. The bottom surface of the insulating pattern SP may include a surface in direct contact with the top surface of the first conductive pattern CL1 and a surface surrounding a portion filled inside the through hole HL.

[0141] In an embodiment, the insulating pattern SP may include a first portion SP1 and a second portion SP2. The first portion SP1 may be a portion disposed between the first conductive pattern CL1 and the second conductive pattern CL2 (eg, in the third direction DR3). Figure 7C In the embodiment shown in , the first portion SP1 may be a portion having a semicircular shape in a cross-sectional view. The second portion SP2 may refer to a portion protruding from the first portion SP1 in a direction away from the upper surface of the second conductive pattern CL2 and toward the base layer BL. The second portion SP2 may be referred to as a protrusion. The second portion SP2 may be a portion filled with the through hole HL. In an embodiment, the first portion SP1 and the second portion SP2 may have a unitary shape and may be integral with each other.

[0142] The insulating pattern SP may have a shape in which a semicircular shape and a protruding shape protruding from the semicircular shape are combined in a cross-sectional view. In a cross-sectional view in which the top surface of the insulating pattern SP is curved, the semicircular shape may be a semicircular shape. The protruding shape may be a shape protruding from a non-circular surface of the semicircular shape. However, embodiments of the present inventive concept are not necessarily limited thereto, and the insulating pattern SP may have a shape in which a trapezoidal shape, a rectangular shape, or an inverted trapezoidal shape and a protruding shape protruding from them are combined in a cross-sectional view (for example, a form integrated with each other).

[0143] The insulating pattern SP may include a polymer. In an embodiment, the insulating pattern SP may include a thermosetting polymer. However, embodiments of the present inventive concept are not necessarily limited thereto, and in some embodiments, the insulating pattern SP may include a thermoplastic polymer. The first portion SP1 and the second portion SP2 may include the same material and be formed by the same process.

[0144] In an embodiment, the insulating pattern SP may be aligned with the fifth insulating layer 50 (see Figure 5 ) are formed by the same process. However, the embodiments of the present inventive concept are not necessarily limited thereto, and may be formed according to the circuit element layer DP-CL (see Figure 5) stacked structure to select different combinations of connection electrodes formed by the same process as the first conductive pattern CL1 and the second conductive pattern CL2. Accordingly, the insulating layer formed by the same process as the insulating pattern SP can also be selected differently.

[0145] The portion of the second conductive pattern CL2 that overlaps the insulating pattern SP may protrude from the first conductive pattern CL1 in the third direction DR3 compared to the remaining portion of the second conductive pattern CL2. The protruding portion of the second conductive pattern CL2 may be referred to as a protrusion CL2-T. The second conductive pattern CL2 may be in direct contact with each of the top surface of the first conductive pattern CL1 (e.g., in the third direction DR3) that does not overlap with the insulating pattern SP and the top surface of the insulating pattern SP. The protrusion CL2-T of the second conductive pattern CL2 may correspond to a portion that is in direct contact with the top surface of the insulating pattern SP.

[0146] As an example, Figure 8 A driver chip DC is illustrated as an electronic component. Figure 8 The chip bump electrodes DC-BP (see Figure 6 ) of the first bump BP1 and the first pad PD1 (see Figure 6 ) is in direct contact with the first pad PD1 (see Figure 6 )exist Figure 8 It is shown as signal pad DP-PD in the figure.

[0147] The first bump BP1 of the driver chip DC can pass through the first adhesive layer CF1 to directly contact the second conductive pattern CL2 of the signal pad DP-PD through a bonding process. Because the display device DD according to an embodiment of the present inventive concept does not include conductive balls, even if the signal pads DP-PD are densely arranged, short circuit defects caused by the conductive balls and / or electrical conduction defects when no conductive balls are provided between the signal pad DP-PD and the bump electrode can be prevented. Accordingly, a high-resolution display panel can be realized.

[0148] Generally, as the height of the insulating pattern SP increases, the risk of the insulating pattern SP being lost increases. However, as in the embodiments of the present inventive concept, by increasing the fixing force of the insulating pattern SP, the height of the insulating pattern SP can be designed to be relatively large. In embodiments in which the height of the insulating pattern SP is designed to be relatively large, the contact reliability with the first bump BP1 can be improved.

[0149] Even in the case where the adhesive layer CF1 / CF2 is peeled off from the signal pad DP-PD during the process to reattach the adhesive layer CF1 / CF2, since the fixing force of the insulating pattern SP is increased, the display panel DP including the signal pad DP-PD (see FIG. Figure 6 ) may not be damaged, and therefore, the display panel DP (see Figure 6 ) can be reused.

[0150] Figures 9A to 9E Each is a cross-sectional view of pad areas PA1 and PA2 according to an embodiment of the inventive concept. Figures 9A to 9E The diagram shows Figure 7A Other examples of cross-sectional views corresponding to the line BB' in FIG. Figure 7A The shape of the through hole HL shown in FIG is different. Figures 7A to 8 The same things described can be applied to Figures 9A to 9E , and to simplify the explanation, repeated descriptions of similar or identical elements may be omitted.

[0151] refer to Figure 9A In an embodiment, the through hole HLa may be defined only in the first conductive pattern CL1a, and the through hole HLa may not be defined in the pad insulating layer IL-P. Accordingly, the first portion SP1a of the insulating pattern SPa may be Figure 7C The first part SP1 has the same shape as Figure 7C Unlike the second portion SP2 in the first conductive pattern CL1a, the second portion SP2a may be a protrusion filling only the through hole HLa defined in the first conductive pattern CL1a.

[0152] On a plane, Figure 9A The shape and / or surface area of ​​the through hole HLa in Figure 7A The shapes and / or surface areas of the through holes HL in FIG. 5 may be the same or may be different and may not necessarily be limited to any shape and / or surface area.

[0153] refer to Figure 9B and Figure 9C In an embodiment, each of the through holes HLb and HLc may be provided in plural. Figure 9B In the embodiment shown in FIG, two through holes HLb may be defined. The first portion SP1b of the insulating pattern SPb may be aligned with Figure 7C The first portion SP1 has the same shape as the second portion SP2b. Figure 7C The second portion SP2 in has the same shape but can be configured as two protrusions. Figure 9C In the embodiment shown in FIG, three through holes HLc may be defined. The first portion SP1c of the insulating pattern SPc may be Figure 7C The first portion SP1 has the same shape as the second portion SP2c. Figure 7CThe second portion SP2 in has the same shape but may be configured as three protrusions.

[0154] In an embodiment, on a plane, Figure 9B and Figure 9C The shape and / or surface area of ​​each of the through holes HLb and HLc in Figure 7A The shapes and / or surface areas of the through holes HL in FIG. 5 may be the same or may be different and may not necessarily be limited to any shape and / or surface area. Figure 9B and Figure 9C The through holes HLb and HLc are illustrated as passing through all of the first conductive patterns CL1b and CL1c and the pad insulating layer IL-P. However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiments, the through holes HLb and HLc may pass through only the first conductive patterns CL1b and CL1c.

[0155] refer to Figure 9D and Figure 9E , a case where the shapes of the through holes HLd and HLe in the cross-sectional view are not rectangular is illustrated as an example. Figure 9D As illustrated in FIG, in an embodiment, the shape of the through hole HLd in the cross-sectional view may be an inverted trapezoidal shape. Accordingly, the first portion SP1d of the insulating pattern SPd may be Figure 7C The first portion SP1 in FIG has the same shape, but the second portion SP2d may correspond to the through hole HLd to have an inverted trapezoidal shape in a cross-sectional view. Figure 9E As shown in FIG, in an embodiment, the shape of the through hole HLe in the cross-sectional view may be a trapezoidal shape. Accordingly, the first portion SP1e of the insulating pattern SPe may be Figure 7C The first portion SP1 in FIG. 5 has the same shape, but the second portion SP2e may correspond to the through-hole HLe to have a trapezoidal shape in a cross-sectional view.

[0156] Figure 9D and Figure 9E The through holes HLd and HLe are illustrated as passing through all of the first conductive patterns CL1d and CL1e and the pad insulating layer IL-P. However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiments, the through holes HLd and HLe may pass through only the first conductive patterns CL1d and CL1e.

[0157] According to the above description, as the coupling area of ​​the insulation pattern increases, the display panel according to the embodiment of the inventive concept can reduce the risk of insulation pattern leakage and increase the height of the insulation pattern, and the display panel can be reused.

[0158] Furthermore, a display device including a display panel according to an embodiment of the inventive concept may increase a contact area, and thus, may improve bonding reliability.

[0159] Although non-limiting embodiments of the present invention have been described, it should be understood that the present invention should not be limited to the described embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the present invention. Therefore, the technical scope of the embodiments of the present invention is not limited to the embodiments described in the detailed description of the specification.

Claims

1. A display panel, comprising: Pixels; a signal line electrically connected to the pixel; as well as Signal pads, connected to the signal lines, Wherein, the signal pad includes: a first conductive pattern connected to an end portion of the signal line; a second conductive pattern, disposed on the first conductive pattern; and an insulating pattern, disposed between the first conductive pattern and the second conductive pattern, wherein a first through hole is defined in the first conductive pattern, and Wherein, the insulating pattern extends into the first through hole.

2. The display panel according to claim 1, wherein The entirety of the insulating pattern is disposed in a plane inside each of the first conductive pattern and the second conductive pattern.

3. The display panel according to claim 1, wherein: The second conductive pattern is in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern in plane and a top surface of the insulating pattern.

4. The display panel according to claim 1, wherein: The first through hole overlaps with the insulating pattern in a plane.

5. The display panel according to claim 1, wherein: The insulating pattern includes a polymer.

6. The display panel according to claim 1, further comprising: a pad insulating layer provided between the end of the signal line and the first conductive pattern, wherein a second through hole extending from the first through hole is defined in the pad insulating layer, and Wherein, the insulating pattern extends into the second through hole.

7. The display panel according to any one of claims 1 to 6, wherein: The first through hole is provided in plural.

8. A display panel comprising: Pixels; a signal line electrically connected to the pixel; as well as Signal pads, connected to the signal lines, Wherein, the signal pad includes: a first conductive pattern connected to an end portion of the signal line; a second conductive pattern, disposed on the first conductive pattern; and an insulating pattern, wherein the entirety of the insulating pattern is disposed in a plane inside each of the first conductive pattern and the second conductive pattern, Wherein, the insulating pattern includes: a first portion disposed between the first conductive pattern and the second conductive pattern; and The second portion protrudes from the first portion in a direction away from the upper surface of the second conductive pattern.

9. The display panel according to claim 8, wherein: A first through hole is defined in the first conductive pattern, and The second portion of the insulation pattern is disposed inside the first through hole.

10. The display panel according to claim 8, wherein: The second conductive pattern is in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern on the plane and a top surface of the insulating pattern.

11. The display panel according to claim 8, wherein: The insulating pattern includes a polymer.

12. The display panel according to claim 9, wherein: The first through hole overlaps the insulation pattern on the plane.

13. The display panel according to claim 9, further comprising: a pad insulating layer provided between the end of the signal line and the first conductive pattern, wherein a second through hole extending from the first through hole is defined in the pad insulating layer, and The second portion of the insulation pattern extends into the second through hole.

14. The display panel according to any one of claims 9 to 13, wherein: The first through hole is provided in plural.

15. An electronic device comprising: a display panel including a signal pad; an electronic component electrically connected to the display panel; as well as an adhesive layer bonding the display panel and the electronic component to each other, Wherein, the signal pad includes: a first conductive pattern having a first through hole defined therein; a second conductive pattern, disposed on the first conductive pattern; and an insulating pattern, disposed between the first conductive pattern and the second conductive pattern, The first through hole overlaps with the insulating pattern in a plane.

16. The electronic device according to claim 15, wherein The insulation pattern extends into the first through hole.

17. The electronic device according to claim 15, wherein: The entirety of the insulating pattern is disposed inside each of the first conductive pattern and the second conductive pattern on the plane, and The insulating pattern includes a polymer.

18. The electronic device according to claim 15, wherein The second conductive pattern is in direct contact with a first portion of the first conductive pattern that does not overlap with the insulating pattern on the plane and a top surface of the insulating pattern.

19. The electronic device according to claim 15, wherein The display panel further comprises: a pad insulating layer, disposed below the first conductive pattern, wherein a second through hole extending from the first through hole is defined in the pad insulating layer, and Wherein, the insulating pattern extends into the second through hole.

20. The electronic device according to any one of claims 15 to 19, wherein: The first through hole is provided in plural.

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