Silicon super junction structure for increased yield

Abstract

Super junction elements with increased manufacturing yields may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Rather than etching a trench having a sufficiently large aspect ratio to reliably fill with a doped P-type material, the aspect ratio of the trench may be reduced to reduce the size of the element. This smaller trench may then be lined with a relatively thin (e.g., about 1 m to about 2 m) P-type liner, rather than fully filling the trench with a P-type material. Filling the trench with the passive fill material may occur at relatively high temperatures within a few minutes, thereby being likely to result in voids or seams being formed within the passive fill material. However, since the passive fill material does not affect the operation of the element, this type of defect may be present in the element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. patent application Ser. No. 18 / 171,119, filed on February 17, 2023, entitled “SILICON SUPER JUNCTION STRUCTURES FOR INCREASED THROUGHPUT,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present technology relates to semiconductor systems, processes, and apparatus, and more particularly, to processes and systems for improving scaling of high aspect ratio power devices. Background Art

[0004] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Producing patterned materials on substrates requires controlled methods for forming and removing materials. As device sizes continue to decrease, features within integrated circuits may become smaller, and the aspect ratios of structures may increase, and maintaining the dimensions of these structures during processing operations may become challenging. Some processes may result in recessed features in the material that may have uneven or tapered sidewalls due to increased exposure during processing. Developing materials with straight sidewalls may become more difficult. Additionally, backfilling recessed features with material without any seams and / or voids may also become more difficult.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high-quality components and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0006] In some embodiments, a superjunction component may include a first N-type region extending orthogonally upward from a substrate. The substrate may form a first contact region for the component. The component may also include a second N-type region extending orthogonally upward from the substrate to a second contact region of the component. The component may further include a trench between the first N-type region and the second N-type region. The trench may be lined with a P-type liner along its sidewalls. The P-type liner may contact a third contact region of the component. The trench may be filled with a passive filler material between the P-type liner.

[0007] In some embodiments, a superjunction device may include a silicon substrate forming a drain region for the device, a gate region, a source region, an N-type region extending upward from the silicon substrate to the gate region, a P-type region extending upward from the silicon substrate to the source region, and a passive filler material extending upward to the source region. The P-type region may be between the passive filler material and the N-type region. The passive filler material may include a void or seam within the passive filler material.

[0008] In some embodiments, a method of forming a superjunction device may include forming an N-type material on a substrate and etching a trench in the N-type material. The trench may extend from a top surface of the N-type material downward to at least the top surface of the substrate to form a first N-type region and a second N-type region. The method may also include forming a P-type liner in the trench and filling the trench with a passive fill material.

[0009] In any embodiment, any or all of the following features may be implemented in any combination and without limitation. The height of the P-type liner may be greater than or approximately 40 μm. The width of the P-type liner may be less than or approximately 200 nm. The first contact region may include a drain of a superjunction transistor, the second contact region may include a gate of the superjunction transistor, and the third contact region may include a source of the superjunction transistor. The superjunction transistor may have a breakdown voltage greater than or approximately 650 V. The width of the trench may be less than or approximately 2 μm. The doping concentration of the P-type liner may be higher than the doping concentration of the second N-type region. The gap or seam may be at least 1 μm from the bottom of the passive fill material, and the gap or seam may be at least 1 μm from the top of the passive fill material. The aspect ratio of the P-type region and the area occupied by the passive fill material may be greater than or approximately 20. The aspect ratio of the P-type region and the area occupied by the passive fill material may be greater than or approximately 40. The trench may be filled with the passive fill material in less than 15 minutes. The trench may be filled with the passive fill material without one or more growth-etch cycles. The passive fill material may include undoped silicon. The trench may be filled with the passive fill material at a temperature greater than or about 900°C. The method may also include planarizing the top surface of the element after filling the trench with the passive fill material to remove excess passive fill material. The trench may be etched below the top surface of the substrate. A P-type liner may be grown on the sidewalls of the trench as a P-type doped epitaxial silicon liner. The doping concentration of the N-type material may be about 1e14 dopant / cm 3 With about 1e16 dopants / cm 3 and the doping concentration of the P-type liner may be more than about 8 times the doping concentration of the N-type material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of the various embodiments may be achieved by referring to the remainder of the specification and drawings, wherein the same reference numerals are used throughout the several drawings to represent similar components. In some cases, a sub-label is associated with a reference numeral to represent one of multiple similar components. When a reference numeral is referenced to an existing sub-label without explanation, it is intended to represent all such multiple similar components.

[0011] Figure 1 A top plan view of one embodiment of a processing system is shown that may include or be configured with deposition, etch, bake, and cure chambers in accordance with some embodiments of the present technology.

[0012] Figure 2 A superjunction device according to some embodiments is depicted.

[0013] Figure 3 A flow chart is depicted of a method of forming a superjunction device that allows for reduced pitch and faster trench fill, according to some embodiments.

[0014] Figures 4A to 4E Depicted is an incremental structure for forming a superjunction device according to some embodiments. DETAILED DESCRIPTION

[0015] Superjunction devices with increased manufacturing yields can be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Rather than etching a trench with a sufficiently large aspect ratio to reliably fill it with doped P-type material, the trench's aspect ratio can be reduced to reduce the size of the device. This smaller trench can then be lined with a relatively thin (e.g., approximately 1 µm to approximately 2 µm) P-type liner, rather than completely filling the trench with P-type material. Within the P-type liner, the trench can then be filled with a passive fill material. Filling the trench with the passive fill material can be performed over a period of several minutes at relatively high temperatures, which can potentially result in the formation of voids or seams within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

[0016] As device sizes continue to shrink, the thickness and size of many material layers may decrease to allow for device scaling. The size of features within semiconductor structures may decrease, and the aspect ratio of the features may increase. As the aspect ratio of features increases, patterning operations may have difficulty uniformly etching features without tapering the feature's sidewalls or compromising feature size or integrity due to increased exposure closer to the surface of the substrate material being processed. Furthermore, refilling features with higher aspect ratios may become increasingly difficult due to pinching off at the top of the feature, which may prevent the feature from being filled without seams and / or voids.

[0017] In forming power device structures, conventional techniques are limited in their ability to scale features for increased aspect ratios due to the natural effects of long etching and deposition operations. For example, in superjunction structures, p-type silicon pillars are formed by filling trenches etched into n-type silicon with p-type material. In these structures, on-resistance is controlled by the spacing or width of the different materials. Resistance can be increased by reducing the width of the p-type silicon pillars. Scaling of the p-type silicon pillars is limited by the etching and the ability to fill the trenches seamlessly and / or without gaps. For example, increasing the aspect ratio with conventional etching can result in pitch degradation and tapered features due to the prolonged exposure of the upper region of the feature being formed. Additionally, filling operations for high aspect ratio features can result in pinching off before filling the deeper regions of the feature. Consequently, conventional techniques have been limited to lower aspect ratio or shorter structures to limit performance impacts or device failures. Consequently, many conventional techniques are limited in their ability to prevent structural defects in the final device or improve upon legacy designs.

[0018] The present technology overcomes these problems by redefining how pillars are formed in the base material. By forming smaller features with a thin epitaxial liner before backfilling, the pillars of material can be maintained at a much smaller width compared to conventional techniques. More specifically, the width of the pillars of material can be defined by the width of the epitaxial liner rather than by the width of the recessed feature. Additionally, the recessed features can be made smaller than conventional techniques and backfilled quickly with passive fill material because voids or seams in the passive fill material do not affect the operation of the device. By changing the formation process itself, the present technology can provide features with much larger aspect ratios and can also significantly increase yield when manufacturing multiple devices.

[0019] While the remainder of the disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, the technology should not be considered limited to use with the described etching or deposition processes alone. Before describing the systems and methods or operations of exemplary process sequences according to some embodiments of the technology, this disclosure will discuss one possible system that may be used with the technology. It should be understood that the technology is not limited to the described apparatus and that the processes discussed may be performed in any number of processing chambers and systems.

[0020] Figure 1A top plan view of one embodiment of a processing system 100 that may include or be configured with deposition, etching, baking, and curing chambers according to some embodiments of the present technology is shown. In this figure, a pair of front-opening modular chambers 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low-pressure holding area 106 before being placed into one of the substrate processing chambers 108a-108f positioned in series 109a-109c. A second robot 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-108f and back. Each substrate processing chamber 108a-108f can be configured to perform a variety of substrate processing operations, including the dry etching process described herein, in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes.

[0021] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing, and / or etching a film of material on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) may be used to deposit material on a substrate, and a third pair of processing chambers (e.g., 108a-108b) may be used to cure, anneal, or otherwise treat the deposited film. In another configuration, all three pairs of chambers (e.g., 108a-108f) may be configured to deposit and cure films on a substrate. Any one or more of the processes described may be performed in additional chambers separate from the manufacturing system shown in various embodiments. It will be appreciated that system 100 contemplates additional configurations of chambers for depositing, etching, annealing, and curing material films. Furthermore, the present technology may utilize any number of other processing systems that may incorporate chambers for performing any particular operation. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various portions (such as the holding and transfer areas) can allow operations to be performed in multiple chambers while maintaining a specific vacuum environment between discrete processes.

[0022] The system 100, or more specifically, a chamber incorporated into the system 100 or other processing systems, may be used to produce structures according to some embodiments of the present technology. Figure 2 A super junction device 200 according to some embodiments is depicted. Figure 2 The element 200 in FIG. 1 is shown by way of example as a superjunction transistor, such as a superjunction MOSFET. However, the principles described herein can be used to form any superjunction element, and the description is not limited to superjunction transistors.

[0023] Component 200 may include a number of different electrical contacts. Component 200 may include a source contact 206 electrically coupled to an N+ source region 207 formed within a P-type well 205. Collectively, source contact 206, N+ source region 207, and P-type well 205 may be referred to as the "source region" of component 200. The component may be formed on a silicon substrate 226. Silicon substrate 226 may form the drain region of component 200. Although in Figure 2 Although not explicitly shown, the drain region formed by substrate 226 may include a conductive contact similar to source contact 206. Component 200 may also include a gate region including gate contact 202 and gate oxide 209. Each of the source, drain, and gate regions may include Figure 2 Other layers or regions not explicitly shown in the diagram. Additionally, in this disclosure, these contacts may also be more generally referred to as "first," "second," and "third" contacts to distinguish one contact from the other contacts in a non-transistor-specific manner. For example, in this transistor implementation, the drain region may be referred to as the first contact region, the gate region may be referred to as the second contact region, and the source region may be referred to as the third contact region.

[0024] The internal region of the component 200 may include multiple N-type doped regions and / or P-type doped regions. These regions may also be referred to as "pillars" because these regions generally extend upward from the silicon substrate 226 to the top of the component 200. The component 200 may include a first N-type region 208 extending orthogonally upward from the silicon substrate 226 to the top of the component 200. The component 200 may also include a P-type region 210, which also extends orthogonally upward from the silicon substrate 226 to the source region of the component 200. The component 200 may also include a second N-type region 212, which similarly extends orthogonally upward from the silicon substrate 226 to the gate region. It should be noted that the component 200 may also include additional contact regions, P-type regions (e.g., P-type region 214) and N-type regions (e.g., N-type region 216), some of which are in Figure 2 Shown in the figure.

[0025] Typically, in a standard superjunction device, the width 220 of the P-type region 210 and the width 222 of the second N-type region 212 are substantially the same. A ) and the doping level of the N-type region 212 (N D To function optimally, the charges should be balanced between the second N-type region 212 and the P-type region 210 according to the following equation.

[0026]

[0027] By carefully balancing the charge between the N-type columns in the P-type columns of device 200, these regions can be completely depleted from each other to form a depletion region throughout the bulk of device 200. Complete depletion significantly increases the breakdown voltage of device 200 without reducing the doping concentration. This allows the device to have very high doping concentrations in the N-type regions, as long as the balance is maintained according to equation (1) above.

[0028] The breakdown voltage of device 200 is also a function of its height 224. Generally, the greater the height 224 of device 200, the higher its breakdown voltage. However, when reducing the size of device 200, circuit designers often focus on reducing the width of the N-type pillars within the P-type pillars. Specifically, spacing 228 should be reduced to reduce the size of device 200. A technical problem exists: due to the aspect ratio of features, manufacturing limitations have limited how much the critical dimension, or width, of these features can be reduced within a given height 224 of device 200. Specifically, forming the device typically involves forming N-type material on top of silicon substrate 226. A trench is then etched in the N-type region, leaving an N-type mesa including, for example, N-type region 208 and N-type region 212. The trench is then filled with P-type material to form P-type regions, such as P-type region 210 and P-type region 214. Therefore, for a given height, the trench's aspect ratio limits the trench's width.

[0029] For example, Figure 2 Device 200 in FIG. 2 may be rated for a 650 V device. Specifications for this 650 V device include a height 224 of approximately 40 µm. The width 220 of the P-type region 210 is approximately 2 µm (also known as the critical dimension, or "CD"). This results in the trench etched to form the P-type region 210 having an aspect ratio of 40 / 2 = 20. Spacing 228, which can be defined as the distance between the centers of consecutive N-type regions, is approximately 4 µm. An aspect ratio of 20 has been found to be an acceptable feature size for current etching and filling operations for devices of this size. At this size, an aspect ratio exceeding 20 can cause problems when etching the trench. Specifically, the trench may erode at its top surface, and sloped sidewalls with an ill-defined bottom may develop in the trench. Increasing the aspect ratio can also cause problems when filling the trench. When depositing material in the trench, the material may close off at the top before filling the trench throughout its entire height. This may result in voids or seams in the P-type region that may interfere with the operation of the device 200 .

[0030] At high aspect ratios (such as 20), special procedures are often required to ensure complete trench filling. For example, when filling trenches with P-type epitaxial silicon, the method typically involves a selective epitaxial fill process in high-aspect-ratio trenches. This process utilizes multiple alternating growth-and-etch steps to avoid the formation of voids and / or seams. Specifically, a layer of fill material is grown in the trench, followed by an etchback to prevent pinch-off and maintain a uniform surface. Performing only a single growth step often results in early pinch-off at the top of the trench, thereby preventing the precursor gas from reaching the bottom of the trench for decomposition and epitaxial growth. While this process does produce completely filled trenches, it also takes a considerable amount of time. For example, the high-aspect-ratio trenches described herein can take up to three hours per wafer to complete the filling process. This results in extremely low yields and severely limits the high-volume manufacturing of wafers with superjunction devices. Furthermore, controlling defects in the P-type fill material is very difficult. If not properly monitored and controlled, these defects can negatively impact device characteristics by increasing leakage current and reducing breakdown voltage. Therefore, there are many technical problems in the current superjunction device manufacturing.

[0031] The embodiments described herein address this problem of creating high voltage components by using a liner to create a P-type region rather than etching and filling the trench with a P-type material. The trench is lined with a P-type liner and can then be filled with a passive fill material, such as an undoped silicon material. The passive fill material can be deposited or grown in the trench relatively quickly and may form gaps or seams. However, the passive fill material does not affect the operation of the component, so these gaps or seams are acceptable. Since the trench does not need to be carefully and completely filled, the aspect ratio of the trench can be increased. For example, the width of the trench can be reduced, which in turn reduces the spacing and size of the component.

[0032] Figure 3 A flowchart 300 is shown of a method for forming a superjunction device that allows for reduced pitch and faster trench fill, according to some embodiments. The method of flowchart 300 can be performed in one or more processing chambers, such as the chambers incorporated into system 100 described above. The method of flowchart 300 may or may not include one or more operations prior to the start of the method, including front-end processing, deposition, etching, grinding, cleaning, or any other operations that may be performed prior to the described operations. The method may also include a number of optional operations, as shown in the figure, which may or may not be specifically associated with some embodiments of the method according to the present technology.

[0033] Figures 4A to 4E The method of flowchart 300 describes an incremental structure for forming a superjunction device according to some embodiments. Figures 4A to 4EThe operations are described schematically, and the diagrams thereof will be described in conjunction with the operations of this method. It should be understood that the figures are only partial schematic diagrams with limited detail, and that in some embodiments, the substrate may contain any number of semiconductor portions having aspects as shown in the figures, as well as alternative structural aspects that may still benefit from any aspect of the present technology.

[0034] The method of Flowchart 300 may include forming a first N-type region on a substrate (302). Figure 4A As shown, structure 400 may include a substrate 426. In various embodiments, substrate 426 may have a substantially flat surface or a non-flat surface. Substrate 426 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, a doped or undoped silicon wafer, a patterned or unpatterned wafer, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. As a non-limiting example, in some embodiments, substrate 426 may be or include an N+ material such as N+ silicon. Substrate 426 may have various sizes, such as a 200 mm or 300 mm diameter wafer, and a rectangular or square panel. Substrate 426 may be positioned within a processing region of a semiconductor processing chamber. Although shown as a flat substrate, it should be understood that substrate 426 is included merely to illustrate the underlying structure, which may include any number of layers or features on a wafer or other substrate, and upon which the structures described below may be formed.

[0035] Above substrate 426, structure 400 may include a first N-type material. The first N-type material may be disposed along at least a portion or all of substrate 426. The first N-type material may be N-type silicon and may be doped with phosphorus, arsenic, a combination thereof, or other similar materials. The first N-type material may form first N-type region 408 and second N-type region 412, although mesas or pillars in these regions (and possibly other N-type regions) may not become apparent until after etching one or more trenches in a subsequent operation. The height of the first N-type material and the resulting first N-type region 408 may be greater than or approximately 20 µm, between approximately 20 µm and approximately 30 µm, between approximately 30 µm and approximately 40 µm, between approximately 40 µm and approximately 50 µm, between approximately 50 µm and approximately 60 µm, between approximately 60 µm and approximately 70 µm, between approximately 70 µm and approximately 80 µm, greater than or approximately 80 µm, greater than or approximately 90 µm, and so forth.

[0036] In some embodiments, to facilitate patterning of the first N-type material, a hard mask, photoresist, or any other mask material may be placed along the first N-type material. For example, a first mask may be formed over the first N-type material, and a second mask may be formed over the first mask. In some embodiments, one or both masks may be any number of materials that facilitate structure formation, such as oxides, nitrides, carbides, or some combination of materials. For example, the first mask may be or include silicon nitride, and the second mask may be or include silicon oxide or some other mask material. It is contemplated that the first N-type material and the second mask may be or include silicon nitride. Figure 4A The single mask provided above for the depicted embodiment is only one example structure 400 .

[0037] The method of flowchart 300 may also include etching a trench 433 in the first N-type material (304). Figure 4A As shown, a first mask and / or a second mask may be etched or patterned to form features, such as trenches 433. Any etching process and any etching reagent may be used to etch trenches 433 through the first mask and / or the second mask. In some embodiments, the etching may completely remove the second mask when the pattern is transferred to the underlying N-type material.

[0038] The etching of the first N-type material may form one or more trenches in the material. The trenches 433 may be formed to a depth of greater than or about 10 μm, greater than or about 15 μm, greater than or about 20 μm, greater than or about 25 μm, greater than or about 30 μm, greater than or about 35 μm, greater than or about 40 μm, greater than or about 45 μm, greater than or about 50 μm, greater than or about 55 μm, greater than or about 60 μm, greater than or about 65 μm, greater than or about 70 μm, greater than or about 75 μm, greater than or about 80 μm, greater than or about 85 μm, greater than or about 90 μm, greater than or about 95 μm, greater than or about 100 μm, or greater. Figure 4A As shown, trench 433 can extend all the way down to the top surface of substrate 426. In some embodiments, trench 433 can extend below the top surface of substrate 426, such that trench 433 penetrates substrate 426. As described below, this provides a surface upon which epitaxial silicon can be grown from substrate 426 when trench 433 is filled. This also allows the P-type liner to electrically contact substrate 426. Thus, the height of trench 433 corresponds to any of the heights described above for first N-type region 408, or a higher height. For example, for a 650V device, trench 433 can be approximately 40 μm high or slightly higher when extending into substrate 426.

[0039] The trenches 433 may have an aspect ratio, or depth-to-width ratio, of less than or approximately 50, less than or approximately 40, less than or approximately 30, less than or approximately 25, less than or approximately 20, less than or approximately 15, less than or approximately 10, or less. As described above, for a given height 424, the process allows the trenches to be etched to a smaller width 454. This, in turn, increases the aspect ratio and reduces the pitch 428. For example, the current pitch 428 for standard 650 V components is approximately 7 µm, resulting in a trench 433 width 454 of approximately 3.5 µm. The embodiments described herein can reduce the pitch 428 to less than or approximately 6 µm, less than or approximately 5 µm, less than or approximately 4 µm, less than or approximately 3 µm, or less than or approximately 2 µm. For 650 V components having a height of approximately 40 µm or greater, trenches 433 having a width 454 as small as 1 micron (µm) would not be possible without the methods described herein.

[0040] The method of Flowchart 300 may include forming a P-type liner 450 in the trench 433 ( 306 ). Figure 4B The formation of a P-type liner 450 in trench 433 is depicted in accordance with some embodiments. The deposition or formation can be performed in any number of ways, and in some embodiments, the material can be conformally formed around the trench features. The P-type liner 450, which can be, for example, p-type silicon, can be deposited by atomic layer deposition, epitaxially grown, or produced by any number of other processes to produce conformal coverage about trench 433. The P-type liner 450 can be characterized as having a thickness between about 50 nm and about 100 nm, between about 100 nm and about 150 nm, between about 150 nm and about 200 nm, between about 200 nm and about 250 nm, between about 250 nm and about 300 nm, greater than or about 300 nm, and the like. The P-type liner 450 may also be characterized by a thickness of less than or approximately 200 nm, less than or approximately 150 nm, less than or approximately 100 nm, less than or approximately 90 nm, less than or approximately 80 nm, less than or approximately 70 nm, less than or approximately 60 nm, less than or approximately 50 nm, less than or approximately 40 nm, less than or approximately 30 nm, less than or approximately 20 nm, less than or approximately 10 nm, less than or approximately 5 nm, or less. The P-type liner 450 may be a silicon-containing material doped with boron or other similar materials. In some embodiments, the P-type liner 450 may also include germanium.

[0041] The P-type liner 450 can substantially cover the sidewall portions of the first N-type region 408 in the trench 433. In some embodiments, the P-type liner 450 can also be formed on the bottom of the trench 433. Due to its conformal coverage of the structure, the P-type liner 450 can be free of seams and / or voids, even to a depth of several hundred nanometers. This can provide significant performance improvements for the final device compared to conventional techniques that have reduced or incomplete coverage and the formation of seams or voids at greater depths. However, depending on the formation and thickness, some pores in the P-type liner 450 are expected.

[0042] The method of flowchart 300 may further include filling trench 433 with a passive fill material ( 308 ). Figure 4C The formation of a passive fill material 460 is depicted, according to some embodiments. The passive fill material 460 can fill the trench 433 by backfilling the interior region of the trench 433 between the sidewalls on which the P-type liner 450 has been formed. In some embodiments, the passive fill material 460 can be formed as a single-step process. For example, the passive fill material 460 can be formed without using one or more of the aforementioned growth-etch cycles, which are typically used to uniformly fill the trench 433. Depending on the process, this single-step process can fill the trench 433 with the passive fill material 460 in less than or about 15 minutes, or less than about 20 minutes.

[0043] Various materials can be used for the passive fill material 460. For example, the passive fill material 460 can include undoped silicon, which is electrically neutral compared to the N-type doped silicon and / or P-type doped silicon used elsewhere in the structure 400. Other similar materials can also be used. The P-type liner 450 can surround the passive fill material 460 in the trench 433.

[0044] In some embodiments, the passive fill material 460 can be formed quickly using relatively high temperatures to reduce processing time. For example, the temperature when forming the passive fill material 460 can be elevated to greater than or about 750°, greater than or about 800°, greater than or about 850°, greater than or about 900°, greater than or about 950°, greater than or about 1000°, and the like.

[0045] While generally avoided, such embodiments allow for the formation of gaps or seams, such as Figure 4C Voids 438 are depicted. Voids 453 are permitted in this case because the passive fill material 460 is electrically neutral in the structure 400. Therefore, voids 453 can be tolerated without affecting the performance of the structure 400. In some embodiments, voids 453 can be permitted at least 1 μm from the top of the structure 400 497 and / or at least 1 μm from the bottom of the trench 433 or the top of the substrate 426 458.

[0046] Additional operations may include removing a portion of the passive fill material 460 and any remaining mask material by planarizing the structure, such as by a chemical mechanical polishing operation. Figure 4D A planarized structure with filled trenches is depicted in accordance with some embodiments. At this stage, the P-type liner 450 may alternatively be referred to as the P-type region 410, as it is ready to perform that function in the structure 400. The spacing 428 may be as small as 2 µm, with the width 422 of the first N-type region 408 being approximately 1 µm, the width 457 of the P-type region 410 being approximately 200 nm, and the width 462 of the passive fill material 460 being approximately 800 nm. Note that Figure 4D Not drawn to scale.

[0047] The doping level of the first N-type region 408 can be kept constant. Figure 2 For example, the doping level of the first N-type region 408 may be approximately 1e14 dopant / cm 3 with approximately 1e16 dopants / µm 3 between (e.g., in some embodiments, 7e15 dopant / cm 3 The doping level of the P-type region 410 may be greater than or approximately 8 times, greater than or approximately 9 times, greater than or approximately 10 times, and so on, the doping level of the first N-type region 408. Specifically, the doping level of the P-type region 410 may be increased to balance the above equation (1), such that the product of the doping level of the first N-type region 408 and the width 422 of the first N-type region 408 is equal to the product of the doping level of the P-type region 410 and the width 457 of the P-type region 410 (i.e., the thickness of the P-type liner 450).

[0048] Additional operations may include forming remaining contact areas for structure 400 . Figure 4E A structure 400 with contact regions is depicted, according to some embodiments. Structure 400 may include a gate region 402 and / or a source region 406 to complement the drain region formed by substrate 426. A first N-type region 408 may extend upward orthogonally from substrate 426 or the drain region. A second N-type region 412 may also extend upward orthogonally from substrate 426 to the gate region 402 of structure 400. A trench between first N-type region 408 and second N-type region 412 may be lined with a P-type liner 450 along the sidewalls of the trench to form a P-type region 410. P-type region 410 may contact the drain formed by substrate 426 and may extend upward to contact the source region 406 of the device. Passive fill material 460 may also extend upward to the source region 406. After structure 400 is completed, structure 400 may include a void 453 within passive fill material 460.

[0049] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0050] While some embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Furthermore, many well-known processes and components have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be considered to limit the scope of the technology.

[0051] Where a range of values ​​is provided, it is understood that every intervening value between the upper and lower limits of that range, down to the smallest fraction of the unit of the lower limit, is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any specified value or unspecified intervening value in the stated range and any other specified value or intervening value in that stated range is contemplated. The upper and lower limits of those smaller ranges may independently be included or excluded within that range, and each range in which either limit is included in the smaller range, neither limit is included in the smaller range, or both limits are included in the smaller range is encompassed within the technology, subject to any specifically excluded limits in the stated range. Where the stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0052] As used in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a pillar" includes a plurality of such pillars and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0053] Furthermore, when used in this specification and the following claims, the words “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including” are intended to specify the presence of stated features, integers, components, or operations, but do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

[0054] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It will be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of certain embodiments as set forth in the appended claims.

[0055] In the foregoing description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood that these embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form so as not to obscure the embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0056] Furthermore, it should be noted that individual embodiments may be described as processes depicted as flow charts, process diagrams, data flow diagrams, structure diagrams, or block diagrams. Although a flow chart may depict operations as a sequential process, many operations may be performed in parallel or simultaneously. Additionally, the order of the operations may be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0057] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage elements, optical storage elements, wireless channels, and various other media capable of storing, containing, or carrying (a number of) instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subroutine, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted by any appropriate means, including memory sharing, message passing, token passing, network transmission, etc.

[0058] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments for performing the necessary tasks may be stored in a machine-readable medium. Processor(s) may perform the necessary tasks.

[0059] Additionally, for illustrative purposes, the methods are described in a particular order. It should be understood that, in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the methods described above may be performed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or a logic circuit programmed with the instructions) to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy disk, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. A super junction device, comprising: a first N-type region extending upwardly and perpendicularly from a substrate, wherein the substrate forms a first contact region for the element; a second N-type region, the second N-type region extending perpendicularly upward from the substrate to a second contact region of the element; as well as A trench is provided between the first N-type region and the second N-type region, wherein the trench is lined with a P-type liner along a sidewall of the trench, the P-type liner contacts the third contact region of the element, and the trench is filled with a passive filling material between the P-type liners.

2. The super junction device according to claim 1, wherein a height of the P-type liner is greater than or approximately 40 μm. 3 . The super junction device according to claim 1 , wherein a width of the P-type liner is less than or approximately 200 nm.

4. The super junction device according to claim 1, wherein: The first contact region includes a drain of the superjunction transistor; The second contact region includes a gate of the superjunction transistor; and The third contact region includes a source of the super junction transistor. 5 . The super junction device of claim 4 , wherein the super junction transistor has a breakdown voltage greater than or approximately 650 V.

6. The super junction device of claim 1, wherein a width of the trench is less than or approximately 2 μm. 7 . The super junction device according to claim 1 , wherein a doping concentration of the P-type liner is higher than a doping concentration of the second N-type region.

8. A super junction device, comprising: a silicon substrate forming a drain region for the element; gate region; source region; An N-type region, the N-type region extending upward from the silicon substrate to the gate region; A P-type region, the P-type region extending upward from the silicon substrate to the source region; as well as A passive filling material extends to the source region, wherein the P-type region is between the passive filling material and the N-type region, and the passive filling material includes a gap or seam inside the passive filling material. 9 . The super junction device of claim 8 , wherein the gap or seam is at least 1 μm away from the bottom of the passive filling material, and the gap or seam is at least 1 μm away from the top of the passive filling material. 10 . The super junction device of claim 8 , wherein the aspect ratio of the region occupied by the P-type region and the passive filling material is greater than or approximately 20. 11 . The super junction device of claim 8 , wherein the aspect ratio of the region occupied by the P-type region and the passive filling material is greater than or approximately 40.

12. A method for forming a super junction device, the method comprising: forming an N-type material on a substrate; Etching a trench in the N-type material, wherein the trench extends downward from a top surface of the N-type material to at least one top surface of the substrate to form a first N-type region and a second N-type region; forming a P-type liner in the trench; as well as The trench is filled with a passive fill material.

13. The method of claim 12, wherein the trench is filled with the passive fill material in less than 15 minutes.

14. The method of claim 12, wherein the trench is filled with the passive fill material without one or more growth-etch cycles.

15. The method of claim 12, wherein the passive fill material comprises undoped silicon.

16. The method of claim 12, wherein the trench is filled with the passive fill material at a temperature greater than or about 900°C.

17. The method of claim 12, further comprising: The top surface of the element is planarized after filling the trench with the passive fill material to remove excess passive fill material.

18. The method of claim 12, wherein the trench is etched below the top surface of the substrate.

19. The method of claim 12, wherein the P-type liner is grown on the sidewall of the trench as a P-doped epitaxial silicon liner.

20. The method of claim 12, wherein the doping concentration of the N-type material is about 1e14 dopant / cm 3 With about 1e16 dopants / cm 3 and the doping concentration of the P-type liner is about 8 times or more than the doping concentration of the N-type material.

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