Discrete device interconnects between stacked substrates

Abstract

A stacked substrate package is disclosed that incorporates a surface mount device (SMD) between a substrate and an interposer substrate. An SMD, which may be a passive device (e.g., a capacitor, inductor, resistor, etc.), may be electrically coupled to the power distribution routing layer of the base and / or interposer substrate. In this manner, net power may be provided to devices of a stacked substrate package (e.g., SoC die, memory die, etc.

Description

Technical Field

[0001] The present disclosure relates generally to discrete devices, and more particularly, but not exclusively, to discrete device interconnections between stacked substrates and fabrication techniques thereof. Background Art

[0002] Integrated circuit technology has made significant progress in increasing computing power through the miniaturization of active components. Packaged devices can be found in many electronic devices, including processors, servers, and radio frequency (RF) integrated circuits. Packaging technology becomes more cost-effective for high-pin-count devices and / or high-volume components.

[0003] It is known to stack multiple substrates in a package-on-package (PoP) or stacked substrate package device. In such packages, copper (Cu) core balls are used to hold the stacked substrates. However, Cu core balls can be expensive. In addition, the presence of multiple substrates can make net power distribution difficult.

[0004] Accordingly, a need exists for systems, devices, and methods, including those provided herein, that overcome the shortcomings of conventional stacked substrate packaging. Summary of the Invention

[0005] The following is a simplified summary of one or more aspects and / or examples associated with each device and method disclosed herein. As such, the following summary should not be considered an exhaustive overview of all contemplated aspects and / or examples, nor should it be considered to identify key or decisive elements associated with all contemplated aspects and / or examples or to delineate the scope associated with any particular aspect and / or example. Accordingly, the sole purpose of the following summary is to present certain concepts related to one or more aspects and / or examples of the devices and methods disclosed herein in a simplified form prior to the detailed description given below.

[0006] A stacked substrate package is disclosed. The stacked substrate package may include a base substrate. The stacked substrate package may also include an interposer substrate, which is above the base substrate. The stacked substrate package may further include a plurality of interposer connectors, which are between the base substrate and the interposer substrate. The plurality of interposer connectors may provide an electrical path between the base substrate and the interposer substrate. The stacked substrate package may also include a die, which is between the base substrate and the interposer substrate. The die may be electrically coupled to the base substrate. The stacked substrate package may further include one or more surface mount devices (SMDs), which are between the base substrate and the interposer substrate. Each SMD may be electrically coupled to the base substrate, the interposer substrate, or both.

[0007] A method for manufacturing a stacked substrate package is disclosed. The method may include providing a base substrate. The method may also include providing an interposer substrate on the base substrate. The method may further include forming a plurality of interposer connectors between the base substrate and the interposer substrate. The plurality of interposer connectors may provide an electrical path between the base substrate and the interposer substrate. The method may also include providing a die between the base substrate and the interposer substrate. The die may be electrically coupled to the base substrate. The method may further include providing one or more surface mount devices (SMDs) between the base substrate and the interposer substrate. Each SMD may be electrically coupled to the base substrate, the interposer substrate, or both.

[0008] Other features and advantages associated with the various apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete appreciation of the various aspects of the present disclosure and its many attendant advantages will be readily obtained as the same becomes better understood by reference to the following detailed description considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and do not constitute a limitation of the present disclosure in any way.

[0010] Figure 1 A conventional stacked substrate package is explained.

[0011] Figure 2 A stacked substrate package according to one or more aspects of the present disclosure is illustrated.

[0012] Figure 3 Illustrated is a top view of a stacked substrate package according to one or more aspects of the present disclosure.

[0013] Figure 4A -4F illustrates an example of stages in manufacturing a stacked substrate package according to one or more aspects of the present disclosure.

[0014] Figure 5A -5C illustrates an example of stages in preparing a vertical surface mount device according to one or more aspects of the present disclosure.

[0015] Figure 6 and 7 A flow chart illustrating an example method of manufacturing a stacked substrate package according to one or more aspects of the present disclosure.

[0016] Figure 8 Various electronic devices are illustrated that may utilize one or more aspects of the present disclosure.

[0017] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. As is customary, the features depicted in the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As is customary, certain drawings have been simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Furthermore, similar reference numerals are used throughout the specification and drawings to indicate similar features. DETAILED DESCRIPTION

[0018] Various aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the present teachings. Additionally, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted so as not to obscure the relevant details taught in the present disclosure.

[0019] In some of the described example implementations, examples are identified where various component structures and portions of operations may be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such examples, internal details of known conventional component structures and / or portions of operations may be omitted to help avoid potential confusion of the concepts illustrated in the illustrative embodiments disclosed herein.

[0020] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "having," "includes," and / or "comprising" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] As mentioned above, conventional stacked substrate packaging can be expensive and net power distribution can be problematic. Figure 1 As seen, the conventional stacked substrate package 100 includes a base substrate 110 and an interposer substrate 120. The base substrate 110 may also be referred to as a bottom or main substrate.

[0022] Between the base substrate 110 and the interposer substrate 120, there may be a plurality of copper (Cu) core balls 150. The copper core balls 150 help maintain the stack height or spacing between the base substrate 110 and the interposer substrate 120. A system-on-chip (SoC) die 140 is placed between the base substrate 110 and the interposer substrate 120. The die 140 is electrically coupled to the base substrate 110. Any remaining spacing between the base substrate 110 and the interposer substrate 120 is filled with a molding compound or encapsulant 130. A plurality of solder balls 180 are provided to enable connection to external devices.

[0023] A package-on-package (PoP) memory 160 is placed on top of an interposer substrate 120. A plurality of PoP balls electrically couple the memory 160 to the interposer substrate 120. In this manner, power can be provided to the PoP memory 160 and the die 140 through connections in the base substrate 110, the interposer substrate 120, the core balls 150, and the PoP balls 170. However, providing net power to the die 140 and / or to the memory 160 can be problematic.

[0024] According to various aspects disclosed herein, to address issues associated with conventional stacked substrate packages, a stacked substrate package is proposed in which a power distribution network (PDN) is improved. In one or more aspects, passive devices (e.g., capacitors, inductors, etc.) are provided to achieve net power distribution to active devices.

[0025] Figure 2 A stacked substrate package according to one or more aspects of the present disclosure is illustrated. The stacked substrate package 200 may include a base substrate 210 and an interposer substrate 220. The base substrate 110 may also be referred to as a bottom or main substrate. Although not shown, the base substrate 110 may include one or more routing layers configured to route or otherwise distribute control and data signals. The base substrate 210 may also include one or more routing layers of a power distribution network (PDN) to distribute power (e.g., VDD, VDDQ, VDD2, gnd, etc.). In addition, although not shown, the interposer substrate 220 may similarly include one or more routing layers configured to route or otherwise distribute control and data signals, and may include one or more routing layers of a PDN.

[0026] The stacked substrate package 200 may include one or more interposer connectors 250 between the base substrate 210 and the interposer substrate 220. Each interposer connector 250 may be a solder ball (Pb or Pb-free), a copper core ball, a CCB bump, or the like. The interposer connector 250 may be configured to provide an electrical path between the base substrate 210 and the interposer substrate 220. That is, the interposer connector 250 may electrically couple the signal routing layer of the base substrate 210 with the signal routing layer of the interposer substrate 220, and electrically couple the power routing layer of the base substrate 210 with the power routing layer of the interposer substrate 220. The interposer connector 250 may also be configured to maintain a distance between the base substrate 210 and the interposer substrate 220.

[0027] One or more dies 240 may be placed between the base substrate 210 and the interposer substrate 220. For simplicity, Figure 2 2. A die 240 is illustrated in FIG. The die 240 may be an application processor chip, such as a system-on-chip (SoC) chip. In one aspect, the die 240 may be electrically coupled to the base substrate 210. That is, the die 240 may be connected to signal and power routing layers within the base substrate 210.

[0028] One or more surface mount devices (SMDs) 290, 295 may be placed between the base substrate 210 and the interposer substrate 220. The SMDs 290, 295 may be passive devices such as capacitors, inductors, resistors, etc. Each SMD 290, 295 may be electrically coupled to the base substrate 210, the interposer substrate 220, or both. For example, each SMD 290, 295 may include a first terminal and a second terminal, and the terminals of the SMDs 290, 295 may be coupled to the PDN layer of the base substrate 210 and / or the PDN layer of the interposer substrate 220.

[0029] Each SMD can be a horizontal SMD 290 or a vertical SMD 295. In one aspect, whether an SMD is horizontal or vertical can be determined based on the orientation of the direction from the first terminal to the second terminal of the SMD. Figure 2 As seen in FIG, in horizontal SMD 290, the direction from the first terminal to the second terminal is parallel (more or less) to the orientation of base substrate 210 and / or the orientation of interposer substrate 220. However, in vertical SMD 295, the direction from the first terminal to the second terminal is perpendicular (more or less) to the orientation of base substrate 210 and / or the orientation of interposer substrate 220.

[0030] The horizontal SMD 290 may be electrically coupled to the base substrate 210 and / or the interposer substrate 220. That is, a first terminal of the horizontal SMD 290 may be electrically coupled to a routing layer (e.g., a PDN routing layer) of the base substrate 210, or to a routing layer (e.g., a PDN routing layer) of the interposer substrate 220, or both. Furthermore, a second terminal and a first terminal of the horizontal SMD 290 may be electrically coupled to a routing layer (e.g., a PDN routing layer) of the base substrate 210, or to a routing layer (e.g., a PDN layer) of the interposer substrate 220, or both.

[0031] The vertical SMD 295 may be electrically coupled to the base substrate 210 and the interposer substrate 220. That is, a first terminal of the vertical SMD 295 may be electrically coupled to a routing layer (e.g., a PDN routing layer) of the base substrate 210, and a second terminal of the vertical SMD 295 may be electrically coupled to a routing layer (e.g., a PDN routing layer) of the interposer substrate 220.

[0032] Space not occupied by die 240, SMDs 290, 295, and interposer connector 250 may be filled with molding or encapsulant 230. That is, molding / encapsulant 230 may encapsulate die 240, SMDs 290, 295, and interposer connector 250 between base substrate 210 and interposer substrate 220.

[0033] In one aspect, the SMDs 290, 295 can also be configured to maintain the distance between the base substrate 210 and the interposer substrate 220. This is particularly true for the vertical SMDs 295. In this manner, the SMDs 290, 295 can replace some of the copper core balls 150 of the conventional stacked substrate package 100. That is, the positions previously occupied by the copper core balls 150 in the conventional stacked substrate package 100 can now be occupied by the interposer connectors 250 and the SMDs 290, 295 in the proposed stacked substrate package 200.

[0034] This is Figure 3 Chinese commentary, Figure 3 Explained along the Figure 2 1. A top view of the stacked substrate package 200 along line AA of FIG. Note the placement of the interposer connector 250 and the SMDs 290, 295 on the base substrate 210. For simplicity, the molding 230 is not shown. The keep-out zone (KOZ) is maintained.

[0035] Refer back Figure 2The stacked substrate package 200 may further include a device 260 on the interposer substrate 220, and a plurality of device connectors 270 may electrically couple the device 260 to the interposer substrate 220. In one aspect, the device 260 may be a flip-chip die, such as a memory (e.g., DRAM). In this example, the device connectors 270 may also be referred to as flip-chip connectors 270. In this manner, the chip 240 may communicate with the flip-chip die 260 through the base or bottom substrate 210, the interposer connectors 250, the interposer substrate 220, and the memory connectors 270. If the flip-chip die 260 is a memory, the die 240 may access the memory 260.

[0036] The stacked substrate package 200 may further include external connectors 280 (eg, a ball grid array (BGA)) on the lower surface of the base substrate 210. The external connectors 280 may enable the stacked substrate package 200 to be connected to devices external to the stacked substrate package 200.

[0037] Figure 4A -4F illustrate examples of stages in the manufacture of a stacked substrate package, such as the stacked substrate package 200 , according to one or more aspects of the present disclosure. Specifically, these figures illustrate a process for incorporating a horizontal SMD 290 . Figure 4A Illustrated is a stage where a surface mount technology (SMT) process is performed on the interposer substrate 220. In particular, the horizontal SMD 290 and the interposer connector 250 may be attached to the interposer substrate 220.

[0038] Figure 4B Illustrated is a stage where the die 240 and solder paste 415 are placed on the base substrate 210. The solder paste 415 may be printed in locations on the base substrate 210 corresponding to the locations of the horizontal SMDs 290.

[0039] Figure 4C It is illustrated a stage in which the interposer substrate 220 is turned over and placed on the base substrate 210. Thereafter, reflow may be performed.

[0040] Figure 4D It is illustrated that the stage at which the space between the base substrate 210 and the interposer substrate 220 may be filled with the molding / sealant 230 .

[0041] Figure 4E Illustrated is a stage where external connectors 280 may be attached to the base substrate.

[0042] Figure 4F Illustrated is a stage where a device 260 may be connected to the interposer substrate 220. For example, a PoP process may be performed, such as attaching a flip-chip device (eg, memory) and device connectors 270 to the interposer substrate 220.

[0043] Figure 5A -5C illustrates an example of stages in preparing a vertical SMD 295 according to one or more aspects of the present disclosure. Figure 5A It is illustrated at a stage where solder resist 512 may be applied to the vertical SMD 295. In this way, short circuiting of terminals of the vertical SMD 295 may be prevented.

[0044] Figure 5B Solder 517 is illustrated as being formed on both terminals of the vertical SMD 295. Alternatively, only one terminal may be soldered, such as Figure 5C The prepared vertical SMD 295 can then be incorporated into manufacturing. For example, Figure 4A 、 4B The stages illustrated in 4C may be modified to include vertical SMD 295 .

[0045] Figure 6 A flow chart illustrating an example method 600 of manufacturing a stacked substrate package, such as the stacked substrate package 200 , according to one or more aspects of the present disclosure.

[0046] At block 610, a base substrate 210 may be provided. In one aspect, block 610 may correspond to Figure 4B The stages explained in .

[0047] At block 620, the interposer substrate 220 may be provided over the base substrate 210. In one aspect, block 620 may correspond to Figure 4A –The stages explained in 4C.

[0048] At block 630, a plurality of interposer connectors 250 may be formed between the base substrate 210 and the interposer substrate 220. The plurality of interposer connectors 250 may provide an electrical path between the base substrate 210 and the interposer substrate 220. That is, the interposer connectors 250 may electrically couple the routing layer (signal and / or power) of the base substrate 210 with the routing layer (signal and / or power) of the interposer substrate 220. In one aspect, block 630 may correspond to Figure 4A –The stages explained in 4C.

[0049] At block 640, the die 240 may be provided between the base substrate 210 and the interposer substrate 220. The die 240 may be electrically coupled to the base substrate 210. That is, the connections of the die 240 may be electrically coupled to the routing layers (signal and / or power) of the base substrate 210. In one aspect, block 640 may correspond to Figure 4B –The stages explained in 4C.

[0050] At block 650, one or more surface mount devices (SMDs) 290, 295 may be provided between the base substrate 210 and the interposer substrate 220. Each SMD 290, 295 may be electrically coupled to the base substrate 210, the interposer substrate 220, or both. That is, the terminals of each SMD 290, 295 may be electrically coupled to the routing layer (signal and / or power) of the base substrate 210 and / or the routing layer (signal and / or power) of the interposer substrate 220. In this block, horizontal SMDs 290 and / or vertical SMDs 295 may be provided. In one aspect, block 650 may correspond to Figure 4A –The stages explained in 4C.

[0051] Figure 7 A flow chart illustrating an example method 700 of manufacturing a stacked substrate package, such as the stacked substrate package 200 , according to one or more aspects of the present disclosure. Figure 7 Can be considered as Figure 6 More comprehensive.

[0052] Block 710 may be similar to block 610. That is, at block 710, a base substrate 210 may be provided. In one aspect, block 610 may correspond to Figure 4B The stages explained in .

[0053] Block 720 may be similar to block 620. That is, at block 720, the interposer substrate 220 may be provided over the base substrate 210. In one aspect, block 720 may correspond to Figure 4A –The stages explained in 4C.

[0054] Block 730 may be similar to block 630. That is, at block 730, a plurality of interposer connectors 250 may be formed between the base substrate 210 and the interposer substrate 220. The plurality of interposer connectors 250 may provide an electrical path between the base substrate 210 and the interposer substrate 220. That is, the interposer connectors 250 may electrically couple the routing layer (signal and / or power) of the base substrate 210 with the routing layer (signal and / or power) of the interposer substrate 220. In one aspect, block 730 may correspond to Figure 4A –The stages explained in 4C.

[0055] Block 740 may be similar to block 640. That is, at block 740, the die 240 may be provided between the base substrate 210 and the interposer substrate 220. The die 240 may be electrically coupled to the base substrate 210. That is, the connections of the die 240 may be electrically coupled to the routing layers (signal and / or power) of the base substrate 210. In one aspect, block 740 may correspond to Figure 4B –The stages explained in 4C.

[0056] Block 750 may be similar to block 650. That is, at block 750, one or more surface mount devices (SMDs) 290, 295 may be provided between the base substrate 210) and the interposer substrate 220. Each SMD 290, 295 may be electrically coupled to the base substrate 210, the interposer substrate 220, or both. That is, the terminals of each SMD 290, 295 may be electrically coupled to the routing layer (signal and / or power) of the base substrate 210 and / or the routing layer (signal and / or power) of the interposer substrate 220. In this block, horizontal SMDs 290 and / or vertical SMDs 295 may be provided. In one aspect, block 750 may correspond to Figure 4A –The stages explained in 4C.

[0057] At block 760, the space between the base substrate 210 and the interposer substrate 220 may be filled with the molding / sealant 230. In one aspect, block 760 may correspond to Figure 4D The stages explained in .

[0058] In block 770, a flip chip device 260 (eg, a memory device) may be provided over the interposer substrate 220. In one aspect, block 770 may correspond to Figure 4F The stages explained in .

[0059] In block 780, a plurality of flip chip connectors 270 may be formed to electrically couple the flip chip device 260 to the interposer substrate 220. That is, the connections of the flip chip device 260 may be electrically coupled to the routing layers (signal and / or power) of the interposer substrate. In one aspect, block 780 may correspond to Figure 4F The stages explained in .

[0060] Figure 8 Various electronic devices 800 are illustrated that may be integrated with any of the aforementioned stacked substrate packages in accordance with various aspects of the present disclosure. For example, a mobile phone device 802, a laptop computer device 804, and a fixed location terminal device 806 may each be generally considered user equipment (UE) and may include one or more stacked substrate packages (e.g., stacked substrate package 200) as described herein. Figure 8The devices 802, 804, and 806 illustrated in FIG are merely exemplary. Other electronic devices may also include a die package, such electronic devices including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0061] The devices and functionalities disclosed above can be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all of these files can be provided to a manufacturing facility that manufactures devices based on these files. The resulting products can include semiconductor wafers that are then diced into semiconductor dies and packaged into glass-based antenna devices. The glass-based antenna devices can then be used in the devices described herein.

[0062] Implementation examples are described in the following numbered clauses:

[0063] Item 1: A stacked substrate package comprising: a base substrate; an interposer substrate over the base substrate; a plurality of interposer connectors between the base substrate and the interposer substrate, the plurality of interposer connectors providing an electrical path between the base substrate and the interposer substrate; a die between the base substrate and the interposer substrate, the die being electrically coupled to the base substrate; and one or more surface mount devices (SMDs) between the base substrate and the interposer substrate, wherein each SMD is electrically coupled to the base substrate, the interposer substrate, or both.

[0064] Item 2: The stacked substrate package of Item 1, wherein at least one of the SMDs is a passive device.

[0065] Item 3: The stacked substrate package of Item 2, wherein the at least one SMD is a capacitor.

[0066] Clause 4: The stacked substrate package of any of clauses 1-3, wherein at least one SMD is coupled to the routing layer of the base substrate, or to the routing layer of the interposer substrate, or to both.

[0067] Item 5: The stacked substrate package of Item 4, wherein the routing layer of the base substrate is a power distribution network (PDN) routing layer of the base substrate, or wherein the routing layer of the interposer substrate is a PDN routing layer of the interposer substrate, or both.

[0068] Item 6: A stacked substrate package as in any of Items 4-5, wherein the SMD is a horizontal SMD including a first terminal and a second terminal, wherein the first terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or is electrically coupled to both, and wherein the second terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or is electrically coupled to both.

[0069] Item 7: A stacked substrate package as described in any of items 4-6, wherein the SMD is a vertical SMD including a first terminal and a second terminal, wherein the first terminal of the vertical SMD is electrically coupled to the routing layer of the base substrate, and wherein the second terminal of the vertical SMD is electrically coupled to the routing layer of the interposer substrate.

[0070] Item 8: The stacked substrate package of any of items 1-7, wherein at least one interposer connection is formed of solder.

[0071] Clause 9: The stacked substrate package of any of clauses 1-8, further comprising: a memory over the interposer substrate; and a plurality of memory connectors electrically coupling the memory with the interposer substrate.

[0072] Item 10: A stacked substrate package as in any of items 1-19, wherein the stacked substrate package is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0073] Item 11: A method of manufacturing a stacked substrate package, the method comprising: providing a base substrate; providing an interposer substrate over the base substrate; forming a plurality of interposer connectors between the base substrate and the interposer substrate, the plurality of interposer connectors providing an electrical path between the base substrate and the interposer substrate; providing a die between the base substrate and the interposer substrate, the die being electrically coupled to the base substrate; and providing one or more surface mount devices (SMDs) between the base substrate and the interposer substrate, wherein each SMD is electrically coupled to the base substrate, the interposer substrate, or both.

[0074] Clause 12: The method of clause 11, wherein at least one SMD is a passive device.

[0075] Clause 13: The method of Clause 12, wherein the at least one SMD is a capacitor.

[0076] Clause 14: The method of any of clauses 11-13, wherein at least one SMD is coupled to the routing layer of the base substrate, or to the routing layer of the interposer substrate, or to both.

[0077] Clause 15: The method of clause 14, wherein the routing layer of the base substrate is a power distribution network (PDN) routing layer of the base substrate, or wherein the routing layer of the interposer substrate is a PDN routing layer of the interposer substrate, or both.

[0078] Clause 16: A method as described in any of clauses 14-15, wherein the SMD is a horizontal SMD including a first terminal and a second terminal, wherein the first terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or is electrically coupled to both, and wherein the second terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or is electrically coupled to both.

[0079] Clause 17: The method of any of clauses 14-16, wherein the SMD is a vertical SMD comprising a first terminal and a second terminal, wherein the first terminal of the vertical SMD is electrically coupled to the routing layer of the base substrate, and wherein the second terminal of the vertical SMD is electrically coupled to the routing layer of the interposer substrate.

[0080] Clause 18: The method of any of Clauses 11-17, wherein at least one interposer connection is formed from solder.

[0081] Clause 19: The method of any of clauses 14-15, further comprising: providing a flip chip device over the interposer substrate; and forming a plurality of flip chip connections electrically coupling the flip chip device with the interposer substrate.

[0082] Clause 20: The method of clause 19, wherein the flip chip device is a memory device.

[0083] As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communication device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, devices carried onboard a motor vehicle, and / or devices typically carried by an individual and / or having communication capabilities. Other types of portable electronic devices (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that is capable of receiving wireless communications and / or navigation signals (such as via short-range wireless, infrared, a wired connection, or other connection), regardless of whether satellite signal reception, assistance data reception, and / or positioning-related processing occurs at the device or the other device. In addition, these terms are intended to include all devices, including wireless and wired communication devices, that are capable of communicating with a core network via a radio access network (RAN), and through the core network, the UE is able to connect to external networks (such as the Internet) and to other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as over a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.). The UE can be implemented by any of several types of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired phones, smartphones, tablets, tracking devices, asset tags, etc. The communication link by which the UE can send signals to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link by which the RAN can send signals to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0084] Wireless communication between electronic devices may be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to provide significantly reduced power consumption and cost while maintaining a similar communication range. BLE was incorporated into the main Bluetooth standard in 2010 with the adoption of Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0085] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as preferred over other examples. Likewise, the term "exemplary" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, a particular feature and / or structure may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the method described herein.

[0086] It should be noted that the terms “connect,” “couple,” or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements via which the two elements are “connected” or “coupled” together, unless the connection is explicitly disclosed as a direct connection.

[0087] Any reference to an element herein using designations such as "first," "second," etc. does not limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Likewise, unless otherwise stated, a set of elements may include one or more elements.

[0088] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0089] Nothing described or illustrated in this application is intended to confer upon the public any component, act, feature, benefit, advantage, or equivalent, regardless of whether such component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0090] In the above detailed description, it can be seen that different features are grouped together in the examples. This manner of disclosure should not be understood as reflecting an intention that the claimed examples have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include fewer than all the features of the individual examples disclosed. Therefore, the appended claims should therefore be considered to be incorporated into this description, with each claim itself being a separate example. Although each claim may be a separate example in itself, it should be noted that although a dependent claim in the claims may refer to a specific combination with one or more claims, other examples may also cover or include a combination of the dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly expressed that a specific combination is not the target. In addition, it is intended that features of a claim may be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0091] Furthermore, it should be noted that the methods, systems, and apparatus disclosed in the present description or claims may be implemented by devices that include means for performing the corresponding actions and / or functionalities of the disclosed methods.

[0092] Furthermore, in some examples, an individual action may be subdivided into or include one or more sub-actions. Such sub-actions may be included in and may be part of the disclosure of the individual action.

[0093] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of the present disclosure as defined in the appended claims. The functions and / or actions in the method claims according to the various examples of the present disclosure described herein do not necessarily have to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid obscuring the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural is also contemplated unless explicitly stated to be limited to the singular.

Claims

1. A stacked substrate package, comprising: base substrate; an interposer substrate, the interposer substrate being on the base substrate; a plurality of interposer connectors between the base substrate and the interposer substrate, the plurality of interposer connectors providing an electrical path between the base substrate and the interposer substrate; a die between the base substrate and the interposer substrate, the die being electrically coupled to the base substrate; as well as one or more surface mount devices (SMDs), the one or more SMDs being between the base substrate and the interposer substrate, Each SMD is electrically coupled to the base substrate, the interposer substrate, or both. 2 . The stacked substrate package of claim 1 , wherein at least one SMD is a passive device. The stacked substrate package of claim 2 , wherein the at least one SMD is a capacitor. 4 . The stacked substrate package of claim 1 , wherein at least one SMD is coupled to a routing layer of the base substrate, or coupled to a routing layer of the interposer substrate, or both.

5. The stacked substrate package according to claim 4, wherein the routing layer of the base substrate is a power distribution network (PDN) routing layer of the base substrate, or wherein the routing layer of the interposer substrate is a PDN routing layer of the interposer substrate, or Both of the above.

6. The stacked substrate package according to claim 4, wherein the SMD is a horizontal SMD comprising a first terminal and a second terminal, wherein the first terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or both, and The second terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or both.

7. The stacked substrate package according to claim 4, wherein the SMD is a vertical SMD comprising a first terminal and a second terminal, wherein the first terminal of the vertical SMD is electrically coupled to the routing layer of the base substrate, and Wherein the second terminal of the vertical SMD is electrically coupled to the routing layer of the interposer substrate. 8 . The stacked substrate package of claim 1 , wherein at least one interposer connector is formed of solder.

9. The stacked substrate package according to claim 1 , further comprising: a memory on the interposer substrate; as well as A plurality of memory connections electrically couple the memory with the interposer substrate.

10. The stacked substrate package of claim 1 , wherein the stacked substrate package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

11. A method for manufacturing a stacked substrate package, the method comprising: providing a base substrate; providing an interposer substrate over the base substrate; forming a plurality of interposer connectors between the base substrate and the interposer substrate, the plurality of interposer connectors providing electrical paths between the base substrate and the interposer substrate; providing a die between the base substrate and the interposer substrate, the die being electrically coupled to the base substrate; as well as One or more surface mount devices (SMDs) are provided between the base substrate and the interposer substrate, wherein each SMD is electrically coupled to the base substrate, the interposer substrate, or both.

12. The method of claim 11, wherein at least one SMD is a passive device. The method of claim 12 , wherein the at least one SMD is a capacitor.

14. The method of claim 11, wherein at least one SMD is coupled to a routing layer of the base substrate, or to a routing layer of the interposer substrate, or both.

15. The method according to claim 14, wherein the routing layer of the base substrate is a power distribution network (PDN) routing layer of the base substrate, or wherein the routing layer of the interposer substrate is a PDN routing layer of the interposer substrate, or Both of the above.

16. The method according to claim 14, wherein the SMD is a horizontal SMD comprising a first terminal and a second terminal, wherein the first terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or both, and The second terminal of the horizontal SMD is electrically coupled to the routing layer of the base substrate, or is electrically coupled to the routing layer of the interposer substrate, or both.

17. The method according to claim 14, wherein the SMD is a vertical SMD comprising a first terminal and a second terminal, wherein the first terminal of the vertical SMD is electrically coupled to the routing layer of the base substrate, and Wherein the second terminal of the vertical SMD is electrically coupled to the routing layer of the interposer substrate.

18. The method of claim 11, wherein at least one interposer connector is formed from solder.

19. The method of claim 11, further comprising: providing a flip-chip device on the interposer substrate; as well as A plurality of flip chip connections are formed that electrically couple the flip chip device with the interposer substrate.

20. The method of claim 19, wherein the flip-chip device is a memory device.

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