Electronic device and control method of electronic device

Abstract

The present invention suppresses electromagnetic interference in an electronic device having a built-in antenna and a built-in transmission line. The electronic device includes an antenna, a plurality of transmission lines, and a control unit. Further, in an electronic device equipped with an antenna, a plurality of transmission lines, and a control unit, the plurality of transmission lines transmit signals. Further, in an electronic device equipped with an antenna, a plurality of transmission lines, and a control unit, the control unit controls directivity of electromagnetic waves emitted from the plurality of transmission lines based on reception performance of the antenna.

Description

Technical Field

[0001] The present technology relates to an electronic device, and more particularly, to an electronic device for transmitting signals within the device and a control method for the electronic device. Background Art

[0002] Various known standards are used for signal transmission within electronic devices, such as the Mobile Industry Processor Interface (MIPI) and Peripheral Component Interconnect Express (PCIe). According to the MIPI standard, differential signals are transmitted via each channel acting as a transmission line. For example, a device has been proposed that individually adjusts the delay time of multiple signals comprising a differential signal (e.g., see Patent Document 1).

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: WO 2022 / 130880 A Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] The aforementioned known standards aim to reduce common-mode noise by adjusting the delay times of the multiple signals that make up a differential signal. However, when an internal antenna is located near a transmission line, the transmission line may act as a noise source, causing electromagnetic interference between the transmission line and the antenna. This phenomenon is known as internal electromagnetic compatibility (EMC) or radio frequency interference (RFI). This electromagnetic interference leads to problems such as reduced antenna reception performance.

[0008] The present technology has been proposed in view of such circumstances, and an object of the present technology is to suppress electromagnetic interference in an electronic device having built-in components including an antenna and a transmission line.

[0009] Solution to the problem

[0010] This technology is designed to address the aforementioned issues. In its first aspect, it includes an electronic device and a control method for the electronic device. The electronic device includes an antenna, multiple transmission lines through which signals are transmitted, and a control unit that controls the directivity of electromagnetic waves radiated from the multiple transmission lines based on the antenna's reception performance. This effectively suppresses electromagnetic interference.

[0011] In addition, according to the first aspect, the device may further include a first driving unit that outputs a first output signal, a second driving unit that outputs a second output signal, a first transmission-side delay circuit that delays the output of the first output signal, and a second transmission-side delay circuit that delays the output of the second output signal. The plurality of transmission lines may include a first transmission line that transmits the first output signal and a second transmission line that transmits the second output signal, and the control unit may adjust the delay time of each of the first transmission-side delay circuit and the second transmission-side delay circuit. This achieves the effect of controlling directivity by adjusting the delay time.

[0012] Furthermore, according to the first aspect, the first transmission-side delay circuit and the second transmission-side delay circuit can each include a multi-stage delay element that generates a plurality of delayed signals having different delay times, and a selector that selects and outputs either the clock signal or one of the plurality of delayed signals. This achieves the effect of controlling the delay time of each transmission line.

[0013] Furthermore, according to the first aspect, each of the first transmission-side delay circuit and the second transmission-side delay circuit may include a logic circuit that outputs a signal obtained by delaying a clock signal, a plurality of first transistors connected in parallel between a power supply terminal and a power supply node of the logic circuit, and a plurality of second transistors connected in parallel between a ground terminal and a ground node of the logic circuit, and the control unit may control the number of first transistors that are turned on and the number of second transistors that are turned on. This has the effect of controlling the delay time of each transmission line.

[0014] Furthermore, according to the first aspect, each of the first transmission-side delay circuit and the second transmission-side delay circuit may include a logic circuit that delays and outputs a clock signal, a first transistor placed between a power supply terminal and a power supply node of the logic circuit, a second transistor placed between a ground terminal and a ground node of the logic circuit, a first bias voltage generating circuit that generates a first bias voltage and supplies the first bias voltage to a gate of the first transistor, and a second bias voltage generating circuit that generates a second bias voltage and supplies the second bias voltage to a gate of the second transistor, and the control unit may control each of the first bias voltage and the second bias voltage. This results in an effect of controlling the delay time of each transmission line.

[0015] Furthermore, according to the first aspect, the communication standard applied to the plurality of transmission lines may include the Mobile Industry Processor Interface (MIPI) C-PHY standard. This results in the effect of transmitting differential signals using a clock embedding method.

[0016] Furthermore, according to the first aspect, the system may further include a first receiving-side delay circuit that delays and outputs the first output signal as a first delayed signal, a second receiving-side delay circuit that delays and outputs the second output signal as a second delayed signal, a first receiver circuit that receives the first delayed signal, and a second receiver circuit that receives the second delayed signal. Furthermore, the control unit may further adjust the delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit. This has the effect of resetting the delay time on the receiving side.

[0017] Furthermore, according to the first aspect, the communication standard applied to the plurality of transmission lines may include the MIPI D-PHY standard, which results in the effect of transmitting a clock signal and a data signal.

[0018] Furthermore, according to the first aspect, the control unit may include a transmitting-side control unit and a receiving-side control unit. The transmitting-side control unit adjusts the delay time of each of the first transmitting-side delay circuit and the second transmitting-side delay circuit and provides a control signal related to the delay time. The receiving-side control unit adjusts the delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit based on the control signal. This achieves the effect of adjusting the delay time using the transmitting-side and receiving-side control units.

[0019] Furthermore, according to the first aspect, each of the first reception-side delay circuit and the second reception-side delay circuit may include a delay-locked loop (DLL), which can effectively control the delay time of each transmission line.

[0020] Furthermore, according to the first aspect, an edge inversion determination circuit may be further included. The edge inversion determination circuit determines whether the sign of the phase difference between the edge of the first delay signal and the boundary of the second delay signal is inverted and outputs a determination result. The receiving-side control unit may adjust the delay time of each of the first and second receiving-side delay circuits based on the control signal and the determination result. This achieves the effect of resetting the delay time with high precision.

[0021] Furthermore, according to the first aspect, the communication standards applied to the plurality of transmission lines may include a standard applied to transmission of differential signals or single-ended signals, which brings about an effect of suppressing electromagnetic interference when transmitting differential signals or single-ended signals.

[0022] Furthermore, according to the first aspect, the communication standard used for differential signal transmission may include Peripheral Component Interconnect Express (PCIe), while the communication standard used for single-ended signal transmission may include Double Data Rate (DDR). This has the effect of suppressing electromagnetic interference when using PCIe or DDR.

[0023] Furthermore, according to the first aspect, the plurality of transmission lines may include a predetermined number of first transmission lines for transmitting signals from the first chip to the control unit, and a predetermined number of second transmission lines for transmitting signals from the second chip to the control unit. This has the effect of suppressing electromagnetic interference in a device equipped with multiple chips.

[0024] Furthermore, according to the first aspect, the output timings of signals transmitted via a predetermined number of first transmission lines can be the same, and the output timings of signals transmitted via a predetermined number of second transmission lines can be the same, and the control unit can adjust the delay time of one of the first transmission lines or the second transmission line relative to the output timing of the other transmission line. This results in the effect of appropriately controlling the delay times of the plurality of transmission lines.

[0025] Furthermore, according to the first aspect, the control unit can individually adjust the delay time of the signals transmitted through the predetermined number of first transmission lines and the predetermined number of second transmission lines, which results in an effect of appropriately controlling the delay time of the plurality of transmission lines.

[0026] Furthermore, according to the first aspect, the output timings of the signals transmitted through the predetermined number of second transmission lines can be the same, and the control unit can independently control the delay time of the output timings and the delay time of the signals transmitted through the predetermined number of first transmission lines. This allows for appropriate control of the delay times of the plurality of transmission lines.

[0027] Furthermore, according to the first aspect, the first chip can transmit a first authentication key, the second chip can transmit a second authentication key, and the control unit can authenticate each of the first and second chips based on whether the first and second authentication keys each match a third authentication key, and control the directivity of electromagnetic waves radiated from the transmission line corresponding to the successfully authenticated chip. This enables chips with various configurations to coexist.

[0028] Furthermore, according to the first aspect, a rewritable third storage unit for storing a third authentication key may be further included. The first chip may include a rewritable first storage unit for storing the first authentication key, and the second chip may include a rewritable second storage unit for storing the second authentication key. This enables the addition and updating of authentication keys. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is an example of a rear view of the electronic device according to the first embodiment of the present technology.

[0030] Figure 2 is a plan view illustrating an example of the internal structure of the housing according to the first embodiment of the present technology.

[0031] Figure 3 is a diagram illustrating a configuration example of a camera module according to a first embodiment of the present technology.

[0032] Figure 4 is a block diagram illustrating a configuration example of an electronic device according to the first embodiment of the present technology.

[0033] Figure 5 is a diagram illustrating an example of wiring within each channel according to the first embodiment of the present technology.

[0034] Figure 6 is a block diagram illustrating a configuration example of a sensor chip and a system on chip (SoC) according to the first embodiment of the present technology.

[0035] Figure 7 is a block diagram illustrating a configuration example of a drive unit according to the first embodiment of the present technology.

[0036] Figure 8 is a circuit diagram illustrating a configuration example of a delay circuit according to the first embodiment of the present technology.

[0037] Figure 9 is an example of an enlarged view of a flexible printed circuit (FPC) cable according to the first embodiment of the present technology.

[0038] Figure 10 is a graph showing an example of frequency characteristics of each channel in the initial state according to the first embodiment of the present technology.

[0039] Figure 11 : is a diagram showing an example of a frequency spectrum of each of channels 0 and 1 according to the first embodiment of the present technology.

[0040] Figure 12 : is a diagram showing an example of the frequency spectrum of channel 2 according to the first embodiment of the present technology.

[0041] Figure 13 is a diagram illustrating an example of coordinate axes and a radiation electric field according to the first embodiment of the present technology.

[0042] Figure 14 is a diagram illustrating an example of radiation characteristics of electromagnetic waves at a radio frequency of 750 megahertz (MHz) according to the first embodiment of the present technology.

[0043] Figure 15 : is a diagram showing an example of radiation characteristics of electromagnetic waves at a radio frequency of 1250 megahertz (MHz) according to the first embodiment of the present technology.

[0044] Figure 16: is a diagram showing an example of radiation characteristics of electromagnetic waves at a radio frequency of 1750 megahertz (MHz) according to the first embodiment of the present technology.

[0045] Figure 17 is a diagram illustrating an example of a radiation electric field at each frequency according to the first embodiment of the present technology.

[0046] Figure 18 is a flowchart illustrating an operation example of the electronic device according to the first embodiment of the present technology.

[0047] Figure 19 are diagrams illustrating examples of directivity of electromagnetic waves before and after delay time adjustment according to the first embodiment of the present technology.

[0048] Figure 20 : is a diagram showing an example of the waveform of a differential signal in the initial state according to the first embodiment of the present technology.

[0049] Figure 21 : is a diagram showing an example of the waveform of a differential signal after delay time adjustment according to the first embodiment of the present technology.

[0050] Figure 22 is a circuit diagram illustrating a configuration example of a delay circuit according to a second embodiment of the present technology.

[0051] Figure 23 is a circuit diagram illustrating a configuration example of a delay circuit according to a third embodiment of the present technology.

[0052] Figure 24 is a block diagram illustrating a configuration example of a sensor chip and an SoC according to a fourth embodiment of the present technology.

[0053] Figure 25 is a diagram illustrating an example of delay time on the reception side according to the fourth embodiment of the present technology.

[0054] Figure 26 is a block diagram illustrating a configuration example of a sensor chip and an SoC according to a fifth embodiment of the present technology.

[0055] Figure 27 is a circuit diagram illustrating a configuration example of a delay circuit according to a fifth embodiment of the present technology.

[0056] Figure 28 : is a diagram showing an example of the waveform of a differential signal after delay time adjustment according to the fifth embodiment of the present technology.

[0057] Figure 29 is a diagram illustrating an example of the delay time of the delay circuit on the reception side according to the fifth embodiment of the present technology.

[0058] Figure 30 is a block diagram illustrating a configuration example of a SoC according to a sixth embodiment of the present technology.

[0059] Figure 31 is a block diagram illustrating a configuration example of an edge inversion determination circuit according to a sixth embodiment of the present technology.

[0060] Figure 32 is a circuit diagram illustrating a configuration example of a pulse generating circuit according to a sixth embodiment of the present technology.

[0061] Figure 33 is a flowchart illustrating an operation example of the electronic device according to the sixth embodiment of the present technology.

[0062] Figure 34 is a flowchart illustrating an example of delay time compensation processing according to the sixth embodiment of the present technology.

[0063] Figure 35 is a block diagram illustrating a configuration example of an electronic device according to a seventh embodiment of the present technology.

[0064] Figure 36 is a timing chart illustrating an example of a delay time adjustment method according to the seventh embodiment of the present technology.

[0065] Figure 37 is a timing chart illustrating an example of a delay time adjustment method according to the seventh embodiment of the present technology.

[0066] Figure 38 is a timing chart illustrating an example of a delay time adjustment method according to the seventh embodiment of the present technology.

[0067] Figure 39 is a flowchart illustrating an operation example of the electronic device according to the first modification example of the seventh embodiment of the present technology.

[0068] Figure 40 1 and 2 are block diagrams of a sensor chip and a SoC according to a second modification of the seventh embodiment of the present technology.

[0069] Figure 41 It is a diagram illustrating a case where the SoC according to the second modification example of the seventh embodiment of the present technology transmits an authentication key.

[0070] Figure 42 is a block diagram illustrating a schematic configuration example of a vehicle control system.

[0071] Figure 43 It is an explanatory diagram illustrating an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0072] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The description is given in the following order.

[0073] 1. First embodiment (an example of adjusting the delay time of each channel)

[0074] 2. Second Embodiment (Example of Adjusting the Delay Time of Each Channel by Controlling the Transistor Size)

[0075] 3. Third Embodiment (Example of Adjusting the Delay Time of Each Channel by Controlling the Bias Voltage)

[0076] 4. Fourth Embodiment (Example of Adjusting the Delay Time of Each Channel on the Transmitting Side and Resetting the Delay Time on the Receiving Side)

[0077] 5. Fifth Embodiment (Example of Adjusting the Delay Time of Each Channel Using a Transmitting-Side Control Unit and Resetting the Delay Time on the Receiving Side)

[0078] 6. Sixth Embodiment (Example of Adjusting the Delay Time of Each Channel on the Transmitting Side and Determining Whether to Reverse the Edge Relationship on the Receiving Side)

[0079] 7. Seventh Embodiment (Example of Adjusting the Delay Time of Channels Set Between Multiple Chips)

[0080] 8. Application examples to mobile objects

[0081] <1. First embodiment>

[0082] [Configuration example of electronic equipment]

[0083] Figure 1 1 is an example of a rear view of the electronic device 100 according to the first embodiment of the present technology. For example, a smartphone is taken as an example of the electronic device 100. The electronic device 100 includes a housing 110. The side of the housing 110 on which the display device (not shown) is mounted is defined as the front side of the electronic device 100, and a rear camera including a lens 211 is placed on the rear side opposite to the front side.

[0084] Hereinafter, a predetermined axis parallel to the rear side of the housing 110 is defined as an “X axis”, a predetermined axis orthogonal to the rear side is defined as a “Z axis”, and an axis orthogonal to the X and Z axes is defined as a “Y axis”.

[0085] Figure 2This is a plan view illustrating an example of the internal structure of housing 110 according to the first embodiment of the present technology. Housing 110 houses antenna 120, camera module 200, and mainboard 400. Mainboard 400 includes connector 410, a predetermined number of discrete components 415, and SoC 420. Furthermore, camera module 200 and connector 410 are electrically connected via FPC cable 300.

[0086] The antenna 120 transmits and receives electromagnetic waves to and from the outside. The antenna 120 is placed near the FPC cable 300. In addition, the antenna 120 converts electromagnetic waves received from the outside into electrical signals and transmits the electrical signals to the SoC 420, and converts electrical signals received from the SoC 420 into electromagnetic waves and transmits the electromagnetic waves to the outside.

[0087] The camera module 200 generates image data through photoelectric conversion and provides the image data to the SoC 420 through the FPC cable 300 and a signal line (not shown) in the main board 400 .

[0088] The FPC cable 300 includes a plurality of transmission lines (not shown) for transmitting image data and control signals.

[0089] The SoC 420 controls various devices installed in the electronic device 100 (such as the antenna 120 and the camera module 200 ).

[0090] Note that although a smartphone is given as an example of the electronic device 100, the electronic device 100 is not limited to a smartphone as long as it includes an antenna and a transmission line. The electronic device 100 may be, for example, a laptop computer or an in-vehicle device.

[0091] [Configuration example of camera module]

[0092] Figure 3 1 is a diagram illustrating a configuration example of a camera module 200 according to a first embodiment of the present technology. The camera module 200 includes a module head 201 and a module board 202. On the module head 201, a lens 211 and an actuator (not shown) that drives the lens 211 are placed.

[0093] On the module board 202, a sensor chip 220 and a predetermined number of separate components 210 are placed. The sensor chip 220 functions as a solid-state imaging element, for example, to generate image data and transmit the image data to the SoC 420 through the FPC cable 300.

[0094] Furthermore, in the XY plane, an angle formed by the X-axis and a direction from a predetermined position (e.g., a center position) on the FPC cable 300 to a predetermined position on the antenna 120 located near the FPC cable 300 is represented by φ, and for example, φ is 210°. Furthermore, the height of the antenna 120 from the front side of the housing is approximately equal to the height of the FPC cable 300.

[0095] Figure 4 This is a block diagram illustrating an example configuration of an electronic device 100 according to the first embodiment of the present technology. Transmission lines 310, 320, 330, and 340 are laid between the sensor chip 220 and the SoC 420. An FPC cable 300 includes these transmission lines. Transmission line 310 is used to transmit control signals at a lower communication speed than transmission lines 320, 330, and 340. For example, the Inter-Integrated Circuit (I2C) standard is used as the communication standard applied to transmission line 310.

[0096] The transmission lines 320, 330, and 340 are used to transmit image data at a high communication speed compared to the transmission line 310. As a communication standard applied to these transmission lines 320, 330, and 340, for example, the MIPI C-PHY standard is used.

[0097] According to the MIPI C-PHY standard, transmission lines 320, 330, and 340 are each used as a channel. Each channel transmits signals using a three-wire differential transmission method. Hereinafter, transmission line 320 is represented as channel 0, transmission line 330 is represented as channel 1, and transmission line 340 is represented as channel 2. Furthermore, according to the MIPI C-PHY standard, a clock embedding method is used to transmit data signals with an embedded clock signal.

[0098] Note that the I2C and MIPI C-PHY standards are used for transmission of control signals and image data, respectively, but different communication standards may be used. For example, the MIPI D-PHY standard described later, a different communication standard for transmitting differential signals (such as PCIe), or a communication standard for transmitting single-ended signals (such as Double Data Rate (DDR)) may be used instead of the MIPI C-PHY standard.

[0099] Figure 5 This diagram illustrates an example of wiring within each channel according to the first embodiment of the present technology. In channel 0 (transmission line 320), signal lines 321, 322, and 323 are laid. In channel 1 (transmission line 330), signal lines 331, 332, and 333 are laid. In channel 2 (transmission line 340), signal lines 341, 342, and 343 are laid. The signals transmitted through the three lines in each channel are represented as SIGA, SIGB, and SIGC.

[0100] Note that two of the transmission lines 320 , 330 , and 340 are examples of the first and second transmission lines described in the claims.

[0101] [Chip Configuration Example]

[0102] Figure 6 This is a block diagram illustrating a configuration example of a sensor chip 220 and an SoC 420 according to the first embodiment of the present technology. The sensor chip 220 includes a data generation unit 221, a delay configuration circuit 222, a delay circuit 510, a delay circuit 223, a delay circuit 224, a drive unit 225, a drive unit 226, and a drive unit 227.

[0103] The data generating unit 221 generates parallel data and supplies the parallel data to each of the driving units 225 , 226 , and 227 .

[0104] Delay configuration circuit 222 sets the delay time of each of delay circuits 510, 223, and 224. Delay configuration circuit 222 receives a control signal from SoC 420 via transmission line 310 based on the I2C standard. The control signal includes information indicating the delay time of each of delay circuits 510, 223, and 224. Delay configuration circuit 222 sets the delay time according to the control signal.

[0105] Delay circuit 510 delays clock signal CLK and supplies the resulting signal as clock signal CLK0 to driver unit 225. Delay circuit 223 delays clock signal CLK and supplies the resulting signal as clock signal CLK1 to driver unit 226. Delay circuit 224 delays clock signal CLK and supplies the resulting signal as clock signal CLK2 to driver unit 227. Note that delay circuits 510 and 223 are examples of the first transmission-side delay circuit and the second transmission-side delay circuit described in the claims.

[0106] In synchronization with clock signal CLK0, driver unit 225 converts parallel data into serial data and transmits the serial data to SoC 420 via channel 0 (transmission line 320) using a differential transmission method. In synchronization with clock signal CLK1, driver unit 226 converts parallel data into serial data and transmits the serial data to SoC 420 via channel 1 (transmission line 330) using a differential transmission method. In synchronization with clock signal CLK2, driver unit 227 converts parallel data into serial data and transmits the serial data to SoC 420 via channel 2 (transmission line 340) using a differential transmission method. Note that driver units 225 and 226 are examples of the first driver unit and the second driver unit described in the claims.

[0107] As described above, by delaying the clock signal for each channel, the signal transmitted synchronously with the clock signal can be delayed. In addition, through delay control, SoC 420 can independently control the delay time of each channel. All delay times for channels 0, 1, and 2 can be different, or two of the three delay times can be the same.

[0108] Furthermore, the SoC 420 includes a system control unit 421 , a receiver circuit 422 , a receiver circuit 423 , a receiver circuit 424 , a synchronization circuit 426 , a synchronization circuit 427 , a synchronization circuit 428 , a communication circuit 425 , and a data processing unit 429 .

[0109] The system control unit 421 controls the entire SoC 420. Here, it is assumed that a test mode for delay time adjustment or a normal mode other than the test mode is enabled in the electronic device 100.

[0110] As described above, since the antenna 120 is placed near the three channels, electromagnetic interference (EMI) caused by the electric fields radiated from these channels may couple with the antenna 120. When the antenna 120 receives weak radio waves from the outside, the EMI interferes with the reception of the radio waves. That is, the wireless sensitivity of the antenna 120 is reduced. In particular, the faster the communication speed through the FPC cable 300, or the longer the FPC cable 300, the greater the electromagnetic field radiation. In addition, the shorter the distance between the FPC cable 300 and the antenna 120, the greater the reduction in wireless sensitivity. In addition, since the peak of the radiated electric field may appear in the harmonics of the clock signal used in the MIPI standard, the wireless sensitivity is easily reduced when their frequencies overlap with the frequency band used for wireless communication.

[0111] Therefore, in the test mode, an attempt is made to solve this problem by adjusting the delay time. Note that the delay time adjustment can also be performed in the dynamic normal mode.

[0112] When the test mode is enabled, the system control unit 421 transmits a transmission request of a predetermined test signal to the outside through the communication circuit 425 and the antenna 120 .

[0113] The antenna 120 receives the test signal, and the communication circuit 425 provides the data of the received test signal to the system control unit 421. Based on the received data, the system control unit 421 measures parameters indicating the reception performance of the antenna 120. As parameters, wireless sensitivity, the level of antenna coupling noise, etc. are measured.

[0114] Then, the system control unit 421 uses the control signal to adjust the delay time of each of the delay circuits 510, 223, and 224 individually by a predetermined number of times. As described above, since the MIPI C-PHY standard adopts a clock embedding method, the receiving side can perform normal processing in synchronization with the clock signal regardless of how the delay time difference (in other words, phase difference) between the channels changes.

[0115] The system control unit 421 then determines a delay time combination that minimizes a measured value, such as wireless sensitivity or noise level, and causes the delay configuration circuit 222 to set the delay time to the final configured value. The delay configuration circuit 222 stores data indicating the configured value in an internal register, etc. After the delay time is configured, the electronic device 100 exits test mode and transitions to normal mode. In normal mode, the delay configuration circuit 222 uses the stored data to delay the signal.

[0116] Note that the system control unit 421 adjusts the delay time to minimize the measured value such as wireless sensitivity, but the adjustment is not limited to this control. For example, the system control unit 421 may determine whether the measured value is less than or equal to a predetermined tolerance value each time the delay time is adjusted, and may set the delay time when the measured value becomes less than or equal to the tolerance value.

[0117] As described above, the system control unit 421 adjusts the delay time for each channel to control the directivity of the electromagnetic waves radiated from the three channels based on a principle similar to that of a phased array antenna. Furthermore, the system control unit 421 controls the directivity based on parameters indicating the reception performance of the antenna 120 (such as wireless sensitivity), thereby suppressing electromagnetic interference that affects the antenna 120. Note that the system control unit 421 is an example of the control unit described in the claims.

[0118] The above-mentioned delay time adjustment is performed, for example, at the factory shipment stage. In addition, the delay time adjustment can be performed after factory shipment at a predetermined timing such as when the electronic device 100 is powered on or at the start of communication.

[0119] Receiver circuit 422 receives the differential data signal via channel 0 (transmission line 320) and provides the differential data signal to synchronization circuit 426. Synchronization circuit 426 performs clock data recovery to extract the embedded clock signal from the data signal and provides the data signal to data processing unit 429 in synchronization with the clock signal. Receiver circuit 423 receives the differential data signal via channel 1 (transmission line 330) and provides the differential data signal to synchronization circuit 427. Synchronization circuit 427 performs clock data recovery and provides the data signal to data processing unit 429. Receiver circuit 424 receives the differential data signal via channel 2 (transmission line 340) and provides the differential data signal to synchronization circuit 428. Synchronization circuit 428 performs clock data recovery and provides the data signal to data processing unit 429.

[0120] The communication circuit 425 exchanges analog electrical signals with the antenna 120. The communication circuit 425 performs analog-to-digital (AD) conversion, demodulation processing, and the like on the electrical signals received from the antenna 120, and supplies the resulting data as received data to the system control unit 421. Furthermore, the communication circuit 425 performs modulation processing, digital-to-analog (DA) conversion, and the like on data to be transmitted, and supplies the resulting analog electrical signals to the antenna 120.

[0121] The data processing unit 429 performs various types of processing (image processing, etc.) on the data signals received from each of the synchronization circuits 426 , 427 , and 428 .

[0122] Note that in this figure, SoC 420 adjusts the delay time based on the wireless sensitivity of antenna 120 and antenna coupling noise, but this processing can also be performed by sensor chip 220. In this case, it is only necessary for sensor chip 220 to be equipped with a system control unit, and control information indicating the measurement value such as wireless sensitivity is transmitted from SoC 420 to the system control unit of sensor chip 220.

[0123] In addition, in this figure, the number of channels is 3, but is not limited to 3 and may be 2 or 4.

[0124] [Drive unit configuration example]

[0125] Figure 7 59 is a block diagram illustrating a configuration example of the driving unit 225 according to the first embodiment of the present technology. The driving unit 225 includes driving circuits 590, 595, and 596. The driving circuit 590 includes a serializer 591, a pre-driver 592, and a final driver 593.

[0126] The serializer 591 converts the parallel data PA received from the data generation unit 221 into serial data in synchronization with the clock signal CLK0 received from the delay circuit 510. The serializer 591 provides the serial data to the pre-driver 592. The pre-driver 592 generates an output signal SIGA based on the serial data and provides the output signal SIGA to the final driver 593. The final driver 593 outputs the output signal SIGA to the signal line 321 channel 0 (transmission line 320).

[0127] The driver circuits 595 and 596 are similar in configuration to the driver circuit 590. The driver circuit 595 performs parallel-to-serial conversion in synchronization with the clock signal CLK0 and outputs the output signal SIGB to the signal line 322. The driver circuit 596 performs parallel-to-serial conversion in synchronization with the clock signal CLK0 and outputs the output signal SIGC to the signal line 323.

[0128] Note that by installing a delay circuit for each channel, the delay circuit for each channel can also be controlled independently. In this figure, the delay circuit 510 delays the input clock of the serializer 591, but the present invention is not limited to this configuration as long as the output of the driver circuit 590 can be delayed. For example, the delay circuit 510 can also delay the output of the serializer 591 or the output of the pre-driver 592.

[0129] [Configuration example of delay circuit]

[0130] Figure 8 5 is a circuit diagram illustrating a configuration example of a delay circuit 510 according to the first embodiment of the present technology. The delay circuit 510 includes multiple stages of delay elements such as inverters 511 to 524 and a selector 525. Note that instead of inverters, buffers may be placed as delay elements.

[0131] Inverters 511 to 524 generate a plurality of delayed signals with different delay times. For example, inverters 512 , 514 , 516 , 518 , 520 , 522 , and 524 in even stages each provide seven delayed signals with different delay times to selector 525 .

[0132] Note that a buffer may be placed instead of an inverter. Furthermore, the number of delay elements is not limited to 14, as long as it is at least one. Furthermore, inverters 511 to 524 are examples of delay elements described in the claims.

[0133] The selector 525 selects the clock signal CLK or one of the seven delayed signals according to the control signal T_SET received from the delay configuration circuit 222. The selector 525 provides the selected signal to the driver circuit 590 as the clock signal CLK0.

[0134] Figure 9 This is an example of an enlarged view of an FPC cable 300 according to the first embodiment of the present technology. As illustrated in the figure, in FPC cable 300, a ground line 301, signal lines 321-323 corresponding to channel 0, signal lines 331-333 corresponding to channel 1, and signal lines 341-343 corresponding to channel 2 are laid over a ground line 302.

[0135] Next, we describe the results of a simulation analyzing the changes in directivity caused by delay time adjustment for each channel. The simulation model uses the same physical property values ​​(conductivity, dielectric constant, loss tangent, etc.) as those used for metals and insulating films in the device. Furthermore, for chips and cables, values ​​representing their actual dimensions were used.

[0136] Figure 10 This graph shows an example of the frequency characteristics of each channel in the initial state according to the first embodiment of the present technology. In the initial state, it is assumed that the delay time for all three channels is set to "0." In this graph, the vertical axis represents the levels of the output signals SIGA, SIGB, and SIGC, and the horizontal axis represents the frequency. The signal operation waveform for each channel is obtained and converted into the frequency spectrum shown in the graph, which is used as input data for the simulation model for electrolytic analysis.

[0137] Hereinafter, the transition timing of the delayed differential signal within the period of the clock signal embedded in the differential signal before delay is defined as the phase. The spectrum of each channel when the delay time is adjusted is obtained by simulation and is shown in FIG. Figure 11 and Figure 12 middle.

[0138] Figure 11 : is a diagram showing an example of the frequency spectrum of each of channels 0 and 1 according to the first embodiment of the present technology. When the real part is represented by Re and the imaginary part is represented by Im, the waveform amplitude represented by Ad is represented by the following equation, for example.

[0139] Ad = (Re 2 + IM 2 ) 1 / 2

[0140] In addition, the phase θd is expressed by the following equation, for example.

[0141] θd = tan -1 (IM / Re)

[0142] a of the figure shows Re and IM when the phases of the output signals SIGA, SIGB, and SIGC in channel 0 are adjusted to 0°, 45°, 90°, 135°, and 180°, respectively.

[0143] b of the figure shows Re and IM when the phases of the output signals SIGA, SIGB, and SIGC in channel 1 are adjusted to 0°, 45°, 90°, 135°, and 180°, respectively.

[0144] Figure 12 Re and IM are shown when the phases of the output signals SIGA, SIGB, and SIGC in channel 2 are adjusted to 0°, 45°, 90°, 135°, and 180°, respectively.

[0145] Figure 13 It is a diagram illustrating an example of coordinate axes and radiated electric fields according to the first embodiment of the present technology. Figure a illustrates the coordinate axes (X-axis, Y-axis and Z-axis) of a simulation model for electromagnetic field analysis. Figure b shows an example of a radiated electric field at an observation point at a distance r from the origin of the coordinate axis. The angle formed by the line segment extending from the origin to the observation point and the Z axis is denoted as θ. The angle formed between the line segment obtained by projecting the line segment extending from the origin to the observation point onto the XY plane and the X axis is denoted as φ. At the observation point, the radiated electric field oscillating in the θ direction is defined as the vertically polarized electric field E θ , and the radiated electric field oscillating along the φ direction is defined as the horizontally polarized electric field E φ .

[0146] Then, the radio frequency is set to 750, 1250 and 1750 MHz in sequence, and the combination of the phases of channels 0, 1 and 2 is modified multiple times for each radio frequency. For each combination, θ is fixed at 90°, and the relationship between φ and the vertically polarized electric field E is obtained through simulation. θ The relationship between φ and the horizontal polarization electric field E φ Since describing the radiation characteristics of all combinations will generate a lot of information, Figure 14 、 Figure 15 and Figure 16 Only some of them are shown.

[0147] Figure 14 : is a diagram showing an example of the radiation characteristics of electromagnetic waves when the radio frequency is 750 MHz. In this figure, the horizontal axis represents φ and the vertical axis represents the vertical polarization electric field E θ In addition, white circles represent graphs when the phases of channels 0, 1, and 2 are all set to 0°. Triangles represent graphs when the phases of channels 0, 1, and 2 are set to 0°, 45°, and 0°, respectively. Squares represent graphs when the phases of channels 0, 1, and 2 are set to 0°, 180°, and 0°, respectively.

[0148] As shown in the figure, changing the phase of each channel will cause a significant change in the radiation characteristics. When the antenna orientation is set to 210°, the E in this direction is set to 0°, 45°, and 0°. θ Become the smallest.

[0149] Figure 15 is a diagram showing an example of radiation characteristics of electromagnetic waves when the radio frequency is 1250 megahertz (MHz).

[0150] Figure 16 is a diagram showing an example of radiation characteristics of electromagnetic waves when the radio frequency is 1750 megahertz (MHz).

[0151] like Figures 14 to 16 As shown in , when the radio frequency changes, the radiation characteristics of the electromagnetic waves from each channel also change. Figures 14-16 In the graph shown in , when θ is set to, for example, 90° and φ is set to be equal to the orientation of the antenna (for example, 210°), the vertically polarized electric field E θ Summary Figure 17 middle.

[0152] like Figure 17 As shown in FIG, at a radio frequency of 750 MHz, the vertically polarized electric field E can be made to be 0°, 45°, and 0° in three combinations by setting the phases of channels 0, 1, and 2, respectively. θ minimize.

[0153] Furthermore, in the case of a radio frequency of 1250 or 1750 MHz, the vertically polarized electric field E can be made to θ minimize.

[0154] In addition, when considering the vertical polarization electric field E at each radio frequency θ When the angle is 0°, 45° and 0° are the most suitable.

[0155] Note that although there is no horizontally polarized electric field E in this figure φ However, the electronic device 100 can also adjust the phase to reduce the horizontal polarization electric field E φ In addition, the electronic device 100 can also adjust the phase to reduce the vertical polarization electric field E θ and the horizontally polarized electric field E φ Both.

[0156] [Examples of electronic equipment operation]

[0157] Figure 18This is a flowchart illustrating an example of the operation of the electronic device 100 according to the first embodiment of the present technology. This operation starts when the test mode for delay time adjustment is enabled, for example. Note that the flow illustrated in this figure can also be started when the normal mode is enabled.

[0158] The electronic device 100 receives a test signal (step S901). The electronic device 100 then measures the wireless sensitivity of the antenna 120 (step S902). Note that, as described above, the electronic device 100 may also measure antenna coupling noise instead of wireless sensitivity.

[0159] The electronic device 100 determines whether wireless sensitivity measurement has been completed for all combinations of delay times for each channel (step S903). If measurement has not been completed for all combinations (step S903: No), the electronic device 100 adjusts the delay time for each channel (step S904) and repeats step S901 and subsequent steps.

[0160] On the other hand, when measurement has been completed for all combinations (step S903 : Yes), the electronic device 100 sets the delay time of each channel that minimizes wireless sensitivity to a final value (step S905 ) and completes the operation in the test mode.

[0161] Figure 19 1 is a diagram illustrating an example of the directivity of electromagnetic waves before and after delay time adjustment according to the first embodiment of the present technology. FIG. a illustrates an example of the directivity of electromagnetic waves in an initial state where all channels in the FPC cable 300 have a delay time of 0 nanoseconds (in other words, a phase of 0°).

[0162] In the case where the antenna 120 is located near the left side of the FPC cable 300 as illustrated in a of the figure, the stronger the electric field radiated leftward from the FPC cable 300 is, the larger the coupling noise of the antenna 120 becomes.

[0163] However, as illustrated in b of the figure, the SoC 420 can control the directivity of the radiated electric field toward the right side to suppress the reduction in wireless sensitivity. Figures 14 to 16 As shown in , the radiation characteristics may vary with frequency, or the frequency band used by the electronic device 100 may differ in a manner depending on the target market country. By performing the test signal (or the signal transmitted in the normal mode) received at the frequency used in the target market, Figure 19 The process shown in the diagram can easily set the optimal delay time for the frequency.

[0164] Figure 20This diagram shows an example of a differential signal waveform in the initial state according to the first embodiment of the present technology. Output signals SIGA, SIGB, and SIGC are transmitted through each of channels 0, 1, and 2. The dotted line represents the waveform of output signal SIGA, the solid line represents the waveform of output signal SIGB, and the dot-dash line represents the waveform of output signal SIGC.

[0165] The levels of these signals change to high, medium, or low levels depending on the value of the data to be transmitted. In addition, three types of differential signals are transmitted: a differential signal formed by the output signals SIGA and SIGB, a differential signal formed by the output signals SIGB and SIGC, and a differential signal formed by the output signals SIGC and SIGA.

[0166] Furthermore, each output signal transitions synchronously with the embedded clock signal. For example, the levels of the output signals SIGA, SIGB, and SIGC transition at timings T0, T1, and T2. The intervals between these transitions correspond to the period of the clock signal. If the data rate is 500 million symbols per second (Msps), its period is 2 nanoseconds (ns). In this figure, the delay times of channels 0, 1, and 2 are the same in the initial state, so the transition timings of the channels are the same.

[0167] Figure 21 This figure shows an example of a waveform of a differential signal after delay time adjustment according to the first embodiment of the present technology. (a) of the figure shows a waveform when the delay times of channels 0, 1, and 2 are set to 1, 0, and 0 nanoseconds (ns), respectively. In this case, the phases of channels 0, 1, and 2 are 180°, 0°, and 0°, respectively.

[0168] In addition, b of the figure shows the waveform when the delay times of channels 0, 1, and 2 are set to 0, 0.25, and 0.5 nanoseconds (ns), respectively. Since the period is 2 nanoseconds (ns), the phases of channels 0, 1, and 2 are 0°, 45°, and 90°, respectively.

[0169] As shown in the figure, by intentionally introducing a phase difference for each channel, the propagation direction of the composite electromagnetic field radiated from all channels at a specific frequency can be changed. In addition, the composite electric fields radiated from each channel also have the effect of canceling each other out at a specific frequency, so that the value of the electric field itself can also be reduced. For example, at a specific frequency, by setting the phases of channels 0, 1, and 2 to 0°, 180°, and 180°, respectively, a cancellation effect can be achieved. This means that when the phase of channel 0 is set to 0° and the electric field at a specific point is approximately 1, when the phase of channel 1 is set to 180° and the electric field at the specific point is approximately 0.5, and the phase of channel 2 is set to 180° and the electric field at the specific point is approximately 0.5, the composite electric field at the specific point can be made close to 0.

[0170] As described above, according to the first embodiment of the present technology, the system control unit 421 controls the directivity of electromagnetic waves radiated from 3 channels based on the reception performance of the antenna 120 , so that electromagnetic interference can be suppressed to enhance wireless sensitivity.

[0171] <2. Second embodiment>

[0172] In the first embodiment described above, the delay time adjustment is performed by the delay circuit 510 equipped with a plurality of delay elements and a selector 525, but the present technology is not limited to this circuit configuration. The electronic device 100 according to the second embodiment is different from the first embodiment in that a circuit having a plurality of transistors connected in parallel on the power supply side and the ground side is used as the delay circuit 510.

[0173] Figure 22 1 is a circuit diagram illustrating a configuration example of a delay circuit 510 according to a second embodiment of the present technology. The delay circuit 510 of the second embodiment includes p-channel metal oxide semiconductor (pMOS) transistors 531 to 539, n-channel MOS (nMOS) transistors 540 to 548, and an inverter 549.

[0174] A pMOS transistor 539 and an nMOS transistor 540 are connected in series between the input terminal of the delay circuit 510 and the input terminal of the inverter 549 , with the pMOS transistor 539 being placed on the power supply side.

[0175] The pMOS transistor 539 and the nMOS transistor 540 output a signal obtained by inverting and delaying the clock signal CLK to the inverter 549. The inverter 549 inverts the input signal and outputs the inverted signal as the clock signal CLK0 to the driver circuit 590. Note that the pMOS transistor 539 and the nMOS transistor 540 are examples of the logic circuit described in the claims.

[0176] Furthermore, the pMOS transistors 531 to 538 are connected in parallel between the source of the pMOS transistor 539 and the ground node. The nth bit (n is an integer from 0 to 7) of the 8-bit control signal T_SET_rise received from the delay configuration circuit 222 is input to the gate of the nth pMOS transistor.

[0177] Furthermore, nMOS transistors 541 to 548 are connected in parallel between the source and the power supply node of nMOS transistor 540. The n-th bit of the 8-bit control signal T_SET_fall received from the delay configuration circuit 222 is input to the gate of the n-th nMOS transistor.

[0178] The system control unit 421 can use the delay configuration circuit 222 to adjust the rise time and fall time of the clock signal according to the control signals T_SET_rise and T_SET_fall. In this figure, at least one nMOS transistor and at least one pMOS transistor are controlled to be in the on state. The fewer transistors in the on state, the smaller the total gate width of the parallel MOS transistors (in other words, the transistor size), resulting in a longer delay time.

[0179] Note that although eight pMOS transistors and eight nMOS transistors are connected in parallel, the number of MOS transistors connected in parallel is not limited to eight, and may be two or more.

[0180] As described above, according to the second embodiment of the present technology, the system control unit 421 controls on / off of the pMOS transistor and nMOS transistor connected in parallel so that the delay time can be adjusted according to their sizes (total gate width).

[0181] <3. Third embodiment>

[0182] In the first embodiment described above, the delay time adjustment is performed by the delay circuit 510 equipped with a plurality of delay elements and a selector 525, but the present technology is not limited to this circuit configuration. The electronic device 100 according to the third embodiment differs from the first embodiment in that the bias voltage of the transistor in the delay circuit 510 is controlled.

[0183] Figure 23 1 is a circuit diagram illustrating a configuration example of a delay circuit 510 according to a third embodiment of the present technology. The delay circuit 510 of the third embodiment includes pMOS transistors 538 and 539, nMOS transistors 540 and 541, an inverter 549, a P-channel bias voltage generating unit 550, and an N-channel bias voltage generating unit 551.

[0184] A pMOS transistor 539 and an nMOS transistor 540 are connected in series between the input terminal of the delay circuit 510 and the input terminal of the inverter 549, with the pMOS transistor 539 being placed on the power supply side. The inverter 549 inverts the input signal and outputs the inverted signal as the clock signal CLK0 to the driver circuit 590.

[0185] The pMOS transistor 538 is placed between the source of the pMOS transistor 539 and the power supply node. The nMOS transistor 541 is placed between the source of the nMOS transistor 540 and the ground node.

[0186] The P-channel bias voltage generating unit 550 generates a P-channel bias voltage according to the control signal T_SET_rise received from the delay configuration circuit 222, and supplies the P-channel bias voltage to the gate of the pMOS transistor 538. The N-channel bias voltage generating unit 551 generates an N-channel bias voltage according to the control signal T_SET_fall received from the delay configuration circuit 222, and supplies the N-channel bias voltage to the gate of the nMOS transistor 541. It is assumed that the P-channel bias voltage and the N-channel bias voltage can be switched at multiple levels, that is, at more than two levels.

[0187] Note that the P-channel bias voltage generating unit 550 and the N-channel bias voltage generating unit 551 are examples of the first bias voltage generating unit and the second bias voltage generating unit described in the claims.

[0188] The system control unit 421 can use the delay configuration circuit 222 to control the bias voltage according to the control signals T_SET_rise and T_SET_fall to adjust the rise time and fall time of the clock signal. The higher the P-channel bias voltage or the lower the N-channel bias voltage, the longer the delay time.

[0189] As described above, according to the third embodiment of the present technology, the system control unit 421 controls the bias voltages of the pMOS transistor 538 and the nMOS transistor 541 so that the delay time can be adjusted in accordance with the bias voltages.

[0190] <4. Fourth embodiment>

[0191] In the first embodiment, the MIPI C-PHY standard is used for signal transmission between the sensor chip 220 and the SoC 420, but the present technology is not limited to this standard. The electronic device 100 of the fourth embodiment differs from the first embodiment in that the MIPI D-PHY standard is used.

[0192] Figure 24: This is a block diagram illustrating a configuration example of a sensor chip 220 and an SoC 420 according to a fourth embodiment of the present technology. As the communication standard applied to the transmission lines 320, 330, and 340 of the fourth embodiment, the MIPI D-PHY standard is used. According to the MIPI D-PHY standard, the clock embedding method is not used, and the data signal and the clock signal are transmitted through separate channels. For example, the transmission lines 320, 330, and 340 are used as data channels for transmitting data signals, while the clock signal is transmitted through a clock channel (not shown) different from the data channel. As described above, the clock signal is transmitted through the clock channel, which eliminates the need for clock data recovery on the receiving side.

[0193] Without using the clock embedding method, when the phase is shifted on the transmission side, it is necessary to reset the phase on the reception side. Therefore, in the fourth embodiment, the SoC 420 is further provided with a delay configuration circuit 430 and delay circuits 431 , 432 , and 433 .

[0194] The delay circuit 431 delays the signal transmitted through the channel 0 (transmission line 320) and supplies the resulting signal to the synchronization circuit 426. The delay circuit 432 delays the signal transmitted through the channel 1 (transmission line 330) and supplies the resulting signal to the synchronization circuit 427. The delay circuit 433 delays the signal transmitted through the channel 2 (transmission line 340) and supplies the resulting signal to the synchronization circuit 428.

[0195] The delay configuration circuit 430 sets the delay time of each of the delay circuits 431 , 432 , and 433 under the control of the system control unit 421 .

[0196] Figure 25 This is a diagram illustrating an example of delay time on the receiving side according to the fourth embodiment of the present technology. It is assumed that, similar to the transmitting side, each of the delay circuits 431, 432, and 433 on the receiving side is equipped with multiple stages of delay elements and selectors. Note that delay circuits 431, 432, and 433 are examples of the receiving-side delay circuit described in the claims.

[0197] In addition, the number of delay elements installed in the transmission side delay circuit and the number of delay elements installed in the reception side delay circuit may be different. When the delay times of the delay elements are the same, the number of stages of delay elements on the reception side is preferably greater than that on the transmission side.

[0198] Assume that the period of the clock signal is 2 nanoseconds (ns), and in the default configuration, the delay time of each of the delay circuits 431, 432, and 433 is, for example, 2 nanoseconds (ns). Furthermore, assume that the delay time can be controlled within a range of 0 to 4 nanoseconds (ns). This allows the phase to be adjusted within a range of -180° to +180° on the receiving side.

[0199] Here, it is assumed that the system control unit 421 adjusts the delay times of channels 0, 1, and 2 on the transmitting side to 1, 0, and 0 nanoseconds (ns), respectively. In this case, as illustrated in the figure, the system control unit 421 uses the delay configuration circuit 430 to control the delay time of channel 0 on the receiving side to be 1 nanosecond shorter than the default configuration (i.e., 1 nanosecond), and maintains the delay times of channels 1 and 2 at the default configuration. This allows the phase of channel 0, which is offset on the transmitting side, to be reset on the receiving side. By resetting the phase, the receiving side can normally receive data signals even when using the MIPI D-PHY standard.

[0200] Note that the second embodiment and the third embodiment are each applicable to the fourth embodiment.

[0201] As described above, according to the fourth embodiment of the present technology, the system control unit 421 controls the delay time of the reception side to reset the phase so that the reception side can normally receive the data signal even without using the clock embedding method.

[0202] <5. Fifth embodiment>

[0203] In the fourth embodiment described above, the SoC 420 on the receiving side controls the delay time, but the present technology is not limited to this configuration. The electronic device 100 of the fifth embodiment differs from the fourth embodiment in that the delay time is adjusted on both the transmitting and receiving sides.

[0204] Figure 26 4 is a block diagram illustrating a configuration example of a sensor chip 220 and an SoC 420 according to a fifth embodiment of the present technology. The sensor chip 220 of the fifth embodiment is different from that of the fourth embodiment in further including a system control unit 230.

[0205] In the fifth embodiment, the system control unit 421 on the receiving side of the data signal supplies a control signal indicating a measurement value such as wireless sensitivity to the system control unit 230 on the transmitting side. The system control unit 421 sets the delay time of each channel on the transmitting side based on the measurement value.

[0206] Then, the system control unit 230 supplies a control signal related to the delay time of each channel to the system control unit 421 , and the system control unit 421 sets the delay time on the reception side based on the control signal.

[0207] Here, the system control unit 230 on the transmitting side transmits a control signal indicating, for example, a configuration value for the delay time of each channel itself to the system controller 421 on the receiving side. Alternatively, the system control unit 230 provides a control signal indicating the frequency of a clock signal and the phase of each channel. In this case, the system control unit 421 calculates the delay time of each channel based on the received frequency and phase, and sets this value for each channel.

[0208] Note that the system control unit 230 is an example of a transmission-side control unit described in the claims, and the system control unit 421 is an example of a reception-side control unit described in the claims.

[0209] As illustrated in the figure, by allocating the delay time adjustment function to the sensor chip 220 , the circuit scale and design burden of the SoC 420 can be reduced.

[0210] Figure 27 1 is a circuit diagram illustrating a configuration example of the delay circuit 431 according to the fifth embodiment of the present technology. The delay circuit 431 includes, for example, a delay-locked loop (DLL) 560, a DLL 565, and a DLL 566. These DLLs 560, 565, and 566 delay the output signals SIGA, SIGB, and SIGC, and output the resulting signals as delayed signals SIGA', SIGB', and SIGC' to the synchronization circuit 426.

[0211] The DLL 560 includes, for example, a phase comparator 561, a shift register 562, a variable delay line 563, and a replica delay line 564. DLLs 565 and 566 are similar to the DLL 560 in circuit configuration.

[0212] The phase comparator 561 compares the phase of the input SIGA with the phase of the signal fed back from the replica delay line 564 and provides the comparison result to the shift register 562 .

[0213] The shift register 562 shifts the bit sequence based on the comparison result and supplies the resulting bit sequence to the variable delay line 563. The variable delay line 563 delays SIGA, outputs the resulting signal as SIGA′, and feeds it back to the replica delay line 564. The delay time of the variable delay line 563 is controlled according to the bit sequence supplied from the shift register 562.

[0214] The replica delay line 564 delays SIGA' and provides the resulting signal as a feedback signal to the phase comparator 561. The delay time of the replica delay line 564 is controlled by the control signal T_SET supplied from the delay configuration circuit 430. By shortening the delay time of the replica delay line 564, the delay time of the variable delay line 563 can be extended accordingly.

[0215] Note that the circuit configuration of the DLL 560 is not limited to the example illustrated in the figure. For example, an up / down counter may be provided instead of the shift register 562. Furthermore, a charge pump and a voltage-controlled delay line may be provided instead of the shift register 562 and the variable delay line 563.

[0216] Figure 28 This diagram illustrates an example of a waveform of a differential signal after delay time adjustment according to the fifth embodiment of the present technology. It is assumed that the system control unit 230 on the transmitting side sets the delay times for channels 0, 1, and 2 to 1.75, 0.25, and 0.5 nanoseconds (ns), respectively, based on wireless sensitivity and other factors. Furthermore, the clock signal period is 2 nanoseconds (ns). The phases of channels 0, 1, and 2 are 315°, 45°, and 90°, respectively.

[0217] Figure 29 This diagram illustrates an example of the delay time of the delay circuit on the receiving side according to the fifth embodiment of the present technology. The system control unit 421 on the receiving side sets the delay times of the delay circuits 431, 432, and 433 corresponding to channels 0, 1, and 2 to 0.25, 1.75, and 1.5 nanoseconds (ns), respectively. Their respective phases are 45°, 315°, and 270°, respectively. When the phases on the transmitting and receiving sides are added together, the result is 360°, and the phases are reset accordingly.

[0218] Note that the second embodiment and the third embodiment are applicable to the fifth embodiment.

[0219] As described above, according to the fifth embodiment of the present technology, the system control unit 230 on the transmission side adjusts the delay time, so that the circuit scale and design burden of the SoC 420 can be reduced.

[0220] <6. Sixth embodiment>

[0221] In the fifth embodiment described above, the system control unit 230 on the transmitting side sends a control signal (frequency and phase) related to the delay time to the receiving side, but this configuration makes it difficult for the receiving side to reset the phase. For example, due to changes in process, voltage and temperature (PVT), the actual delay time of the delay circuit may deviate from the design value. Therefore, if the design value of the transmitting side is applied to the receiving side as it is, an error may occur during the reset phase. The electronic device 100 according to the sixth embodiment differs from the fifth embodiment in that the receiving side determines whether the sign of the phase difference between the edges of the two channels has been reversed.

[0222] Figure 301 is a block diagram illustrating a configuration example of a SoC 420 according to a sixth embodiment of the present technology. The SoC 420 of the sixth embodiment differs from the fifth embodiment in that an edge inversion determination circuit 440 is further included.

[0223] Furthermore, when setting the delay time for each channel, the system control unit 230 on the transmitting side sends a control signal to the system controller 421 on the receiving side, indicating the magnitude relationship between the delay times of the channels. For example, if the delay times of channels 0, 1, and 2 are 0.1, 0, and 0 nanoseconds (ns), respectively, a control signal is sent indicating that the delay time of channel 0 is greater than the delay times of channels 1 and 2, and that the delay times of channels 1 and 2 are the same. The system control unit 421 on the receiving side then adjusts the delay time of each channel based on this control signal and the determination result received from the edge inversion determination circuit 440. The details of the delay time adjustment method will be described later.

[0224] The edge inversion determination circuit 440 determines whether the sign of the phase difference between the edge of the delayed signal passing through a specific channel and the edge of the delayed signal passing through another channel is inverted, and transmits the determination result to the system control unit 421. When there are three channels 0, 1, and 2, the determination result between channel 0 and channel 1, the determination result between channel 1 and channel 2, and the determination result between channel 2 and channel 0 are transmitted.

[0225] Figure 31 444 is a block diagram illustrating a configuration example of an edge inversion determination circuit 440 according to a sixth embodiment of the present technology. The edge inversion determination circuit 440 includes pulse generation circuits 450 , 441 , and 442 , and flip-flops 443 , 444 , and 445 .

[0226] Any one of the three delayed signals SIGA′, SIGB′, and SIGC′ supplied from the delay circuit 431 corresponding to channel 0 is input to the pulse generating circuit 450 as L0.

[0227] Furthermore, the three delayed signals supplied from the delay circuit 431 are input to the synchronization circuit 426. Any one of the three delayed signals supplied from the delay circuit 432 corresponding to channel 1 is input as L1 to the pulse generation circuit 441. Furthermore, the three delayed signals supplied from the delay circuit 431 are input to the synchronization circuit 427. Any one of the three delayed signals supplied from the delay circuit 433 corresponding to channel 2 is input as L2 to the pulse generation circuit 442. Furthermore, the three delayed signals supplied from the delay circuit 433 are input to the synchronization circuit 428.

[0228] The pulse generation circuit 450 detects the rising or falling edge of the delayed signal L0 and generates a one-shot pulse. This pulse signal is input as P0 to the D terminal of the flip-flop 443 and the clock terminal of the flip-flop 445. Note that the pulse width of the one-shot pulse must be greater than or equal to the setup time and hold time of the flip-flop 443 and the like.

[0229] The pulse generation circuit 441 detects a rising edge or a falling edge of the delay signal L1 and generates a pulse signal P1 . The pulse signal P1 is input to the D terminal of the flip-flop 444 and the clock terminal of the flip-flop 443 .

[0230] The pulse generation circuit 442 detects a rising edge or a falling edge of the delay signal L2 and generates a pulse signal P2 . The pulse signal P2 is input to the D terminal of the flip-flop 445 and the clock terminal of the flip-flop 444 .

[0231] D flip-flops are used as flip-flops 443, 444, and 445. The judgment result between channels 0 and 1 is output as E_Judge0-1 from the Q terminal of flip-flop 443 to the system control unit 421. The judgment result between channels 1 and 2 is output as E_Judge1-2 from the Q terminal of flip-flop 444 to the system control unit 421. The judgment result between channels 2 and 0 is output as E_Judge2-0 from the Q terminal of flip-flop 445 to the system control unit 421.

[0232] Figure 32 1 is a circuit diagram illustrating a configuration example of a pulse generating circuit 450 according to a sixth embodiment of the present technology. The pulse generating circuit 450 includes an inverting delay line 451, an inverter 452, a delay line 453, a logic AND gate 454, an AND gate 455, and a logic OR gate 456.

[0233] The inverting delay line 451 delays and inverts the delayed signal L0 and supplies the resulting signal to the AND gate 454. The AND gate 454 outputs a logical AND of the input delayed signal L0 and the inverted signal received from the inverting delay line 451 to the OR gate 456 as a rising pulse signal.

[0234] The inverter 452 inverts the delayed signal L0 and supplies the resulting signal to the AND gate 455. The inverting delay line 453 delays and inverts the delayed signal L0 and supplies the resulting signal to the AND gate 455. The AND gate 455 outputs a logical AND of the inverted signal received from the inverter 452 and the signal received from the delay line 453 to the OR gate 456 as a falling pulse signal.

[0235] The OR gate 456 outputs a logical sum of the rising pulse signal and the falling pulse signal received from the AND gates 454 and 455 to the flip-flop 443 as a pulse signal P0 .

[0236] Figure 33 1 is a flowchart illustrating an operation example of the electronic device 100 according to the sixth embodiment of the present technology. The operation of the electronic device 100 of the sixth embodiment is different from that of the first embodiment in that a delay time compensation process is performed after step S905 (step S910).

[0237] Figure 34 This is a flowchart illustrating an example of delay time compensation processing according to the sixth embodiment of the present technology. The system control unit 230 in the sensor chip 220 transmits a control signal to the SoC 420 indicating the magnitude relationship between the delay times of the channels (step S911). Furthermore, the driver unit 225 and other components in the sensor chip 220 perform a switching operation for each channel to invert the signal within the minimum data period throughout the specified phase compensation period (step S912).

[0238] Furthermore, during the phase compensation period, the system control unit 421 within the SoC 420 adjusts the delay time of each channel based on the magnitude relationship between the delay times and the determination result received from the edge inversion determination circuit 440 (step S913). For example, the delay time of channel 0 is shorter than the delay time of channel 1. Assuming that the delay time can be switched at multiple levels, the system control unit 421 performs at least one of control to make the delay time of channel 1 shorter by one level than the default configuration value, or control to make the delay time of channel 0 longer by one level than the default configuration value.

[0239] Then, the system control unit 421 on the receiving side determines whether the determination result indicating the sign of the phase difference between the edges of the two channels has been inverted (step S914 ). If there are three channels, it is determined whether all three determination results have been inverted.

[0240] If any of the determination results have not been reversed (step S914: No), the system control unit 421 repeats step S913 and subsequent steps. From the second time onward, control is performed to change the delay time by a unit time compared to the previous value. By repeating step S913 until the determination result is reversed, the phase difference between the corresponding channels can be reduced to approximately zero.

[0241] On the other hand, if all the determination results are inverted (step S914: Yes), the system control unit 421 sets the delay time for each channel (step S915) and then the sensor chip 220 stops the switching operation (step S916) and completes the delay time compensation process.

[0242] As illustrated in this figure, by adjusting the delay time of each channel on the receiving side based on the determination results of the marginal relationship, the delay time can be reset with high accuracy even when the actual delay time deviates from the designed value due to, for example, variations in PVT. Note that even if a configuration is provided on the transmitting side with a circuit that measures the actual delay time and transmits the measured value to the receiving side, the delay time can be accurately reset. However, this configuration is not preferred because the circuit scale on the transmitting side increases.

[0243] Note that the second embodiment and the third embodiment are applicable to the sixth embodiment.

[0244] As described above, according to the sixth embodiment of the present technology, the system control unit 421 on the reception side adjusts the delay time of each channel based on the determination result of the edge relationship, so that the delay time can be reset with high accuracy.

[0245] <7. Seventh embodiment>

[0246] In the first embodiment described above, the SoC 420 adjusts the delay time of each channel provided between the SoC 420 and the sensor chip 220. However, two or more sensor chips may be installed in the device. The electronic device 100 according to the seventh embodiment differs from the first embodiment in that two or more sensor chips are installed and the delay time of each channel provided between the sensor chips is adjusted.

[0247] Figure 35 1 is a block diagram illustrating a configuration example of an electronic device 100 according to a seventh embodiment of the present technology. The electronic device 100 according to the seventh embodiment includes an antenna 120 , a main board 400 , a sensor chip 220 - 1 , a sensor chip 220 - 2 , and an SoC 420 .

[0248] The sensor chips 220-1 and 220-2 are similar in configuration to the sensor chip 220 of the first embodiment. These chips are implemented on the main board 400 together with the SoC 420, for example. Figure 2 As shown in the diagram, the sensor chips 220 - 1 and 220 - 2 may be placed in a camera module and connected to the mainboard 400 via cables.

[0249] In addition, if Figure 35As shown in the diagram, transmission lines 310-1, 320-1, 330-1, and 340-1 are laid between the sensor chip 220-1 and the SoC 420. Transmission lines 310-2, 320-2, 330-2, and 340-2 are laid between the sensor chip 220-2 and the SoC 420. These transmission lines are similar to the transmission lines 310, 320, 330, and 340 of the first embodiment. In addition, the communication standard applied to the transmission lines 320-1, 330-1, 340-1, 320-2, 330-2, and 340-2 can be the MIPI C-PHY standard as in the first embodiment, or a different standard such as the MIPI D-PHY standard. Note that multiple communication standards can also be combined, for example, the MIPI C-PHY standard can be applied to the sensor chip 220-1, and the MIPI D-PHY standard can be applied to the sensor chip 220-2.

[0250] In the seventh embodiment, the transmission lines 320-1, 330-1, and 340-1 are represented as channels 0-1, 1-1, and 2-1, respectively, and the transmission lines 320-2, 330-2, and 340-2 are represented as channels 0-2, 1-2, and 2-2, respectively.

[0251] Note that the number of chips on the transmission side (sensor chips 220 - 1 and 220 - 2 ) is 2, but may be 3 or more. In this case, transmission lines are further laid between the third and subsequent chips and the SoC 420 .

[0252] Sensor chips 220-1 and 220-2 are examples of the first and second chips described in the claims. Transmission lines 320-1, 330-1, and 340-1 are examples of the first transmission line described in the claims, and transmission lines 320-2, 330-2, and 340-2 are examples of the second transmission line described in the claims.

[0253] The system control unit 421 (not shown) in the SoC 420 can use Figure 36 、 Figure 37 and Figure 38 Delay time adjustment can be performed using any of the methods shown in the diagram. This allows for suppression of electromagnetic interference and enhanced wireless sensitivity, even when two or more chips are present on the transmitter side.

[0254] For example, Figure 36 As shown in the diagram, the output timing of each signal of channels 0-1, 1-1 and 2-1 is represented as T0, and the output timing of each signal of channels 0-2, 1-2 and 2-2 is represented as T1. SIGA, SIGB and SIGC in the figure represent signals transmitted through three lines in each channel.

[0255] In the figure, the system control unit 421 adjusts the delay time of the output timing T1 of the channels 0 - 1 , 1 - 1 , and 2 - 1 relative to the output timing T0 of the channels 0 - 2 , 1 - 2 , and 2 - 2 .

[0256] Or, as Figure 37 As shown in the diagram, the system control unit 421 adjusts the delay time of each channel individually. For example, the delay time dT of channels 0-1, 2-1, 0-2, 1-2, and 2-2 relative to the output timing T0 of the signal of channel 1-1 is 0-1 , dT 2-1 , dT 0-2 , dT 1-2 and dT 2-2 are adjusted individually.

[0257] Or, as Figure 38 As shown in the diagram, the system control unit 421 adjusts the delay time (dT 1-1 or dT 2-1 ) and the delay time dT of the output timing T1 of channels 0-2, 1-2 and 2-2.

[0258] Note that the second to sixth embodiments are each applicable to the seventh embodiment.

[0259] As described above, according to the seventh embodiment of the present technology, the system control unit 421 adjusts the delay time of each transmission line provided between the sensor chips 220 - 1 and 220 - 2 , thereby making it possible to suppress electromagnetic interference by configuring two or more chips on the transmission side.

[0260] [First Modification]

[0261] In the seventh embodiment described above, the system control unit 421 performs delay time adjustment by controlling each of the sensor chips 220-1 and 220-2. However, some sensor chips are incompatible with delay control. The electronic device 100 of the first variation of the seventh embodiment differs from the seventh embodiment in that each chip is authenticated.

[0262] Figure 39 This is a flowchart illustrating an example of the operation of electronic device 100 according to the first variation of the seventh embodiment of the present technology. In the first variation of the seventh embodiment, authentication key K1 is pre-stored in a register or the like within sensor chip 220-1. Furthermore, authentication key K2 is pre-stored in a register or the like within sensor chip 220-2. Authentication key K3 is pre-stored in a register or the like within SoC 420. Note that authentication keys K1, K2, and K3 are examples of the first, second, and third authentication keys described in the claims.

[0263] When the test mode for delay time adjustment is enabled, the sensor chips 220-1 and 220-2 transmit authentication keys K1 and K2 to the SoC 420. These authentication keys are transmitted via, for example, the transmission lines 310-1 and 310-2 using the I2C standard. Note that each sensor chip can also transmit the authentication key via, for example, the transmission lines 320-1, 330-1, and 340-1 or the transmission lines 320-2, 330-2, and 340-2 using the MIPI C-PHY standard.

[0264] Then, the system control unit 421 in the SoC 420 authenticates each of the sensor chips 220 - 1 and 220 - 2 based on whether a corresponding one of the received authentication keys K1 and K2 matches the authentication key K3 (step S921 ).

[0265] like Figure 6 As shown in the configuration illustrated in FIG, if each sensor chip is equipped with delay configuration circuit 222, delay circuit 510, etc. and is compatible with delay control, a key identical to authentication key K3 is stored in the chip, thereby ensuring successful authentication. If the authentication keys do not match or the chip does not transmit the authentication key itself, authentication fails.

[0266] exist Figure 39 In the example, the system control unit 421 within the SoC 420 determines whether at least one chip has been successfully authenticated (step S922). If at least one chip has been successfully authenticated (step S922: Yes), the electronic device 100 receives the test signal (step S901). Then, the electronic device 100 measures the wireless sensitivity of the antenna 120 (step S902).

[0267] The system control unit 421 determines whether wireless sensitivity measurement has been completed for all delay time combinations (step S923). If measurement has not been completed for all combinations (step S923: No), the electronic device 100 adjusts the delay time for each channel (step S924) and repeats step S901 and subsequent steps.

[0268] In these steps S923 and S924, only the channels corresponding to the successfully authenticated chips will have their delay times adjusted. For example, if only one of the sensor chips 220-1 and 220-2 has been successfully authenticated, the system control unit 421 adjusts the delay time of each channel corresponding to that chip, without adjusting the delay time of the other channels. If both the sensor chips 220-1 and 220-2 have been successfully authenticated, the system control unit 421 uses the delay time in Figures 36 to 38As described above, by excluding chips that have failed authentication (ie, chips that are incompatible with delay control) from adjustment targets, chips with various configurations can coexist in the electronic device 100, thereby allowing for enhanced versatility.

[0269] exist Figure 39 In the case where measurement has been completed for all combinations (step S923: Yes), the electronic device 100 sets the delay time that minimizes wireless sensitivity to the final value (step S905). If all chips fail authentication (step S922: No), or after step S905, the electronic device 100 terminates operation in the test mode.

[0270] Note that the second to sixth embodiments are each applicable to the first modification of the seventh embodiment.

[0271] As described above, according to the first modification of the seventh embodiment of the present technology, the system control unit 421 adjusts the delay time of the channel corresponding to the successfully authenticated chip so that chips having various configurations can coexist in the electronic device 100 .

[0272] [Second Modification]

[0273] In the first variant of the seventh embodiment described above, each chip is authenticated using an authentication key pre-stored in the chip, but it may be necessary to add or update the authentication key. For example, a chip that was initially incompatible with delay control may later become compatible through a firmware update or the like. In addition, the SoC 420 uses Figures 36 to 38 Any of the adjustment methods illustrated in the figure may be used, but the adjustment method may be changed later. The electronic device 100 according to the second modification of the seventh embodiment is different from the first modification of the seventh embodiment in that the authentication key is stored in a rewritable register or the like.

[0274] Figure 40 1 is a block diagram illustrating a configuration example of the electronic device 100 according to the second modification of the seventh embodiment of the present technology. The electronic device 100 according to the second modification of the seventh embodiment further includes system control units 230 - 1 and 230 - 2 and registers 231 - 1 , 231 - 2 , and 600 .

[0275] The system control unit 230 - 1 and the register 231 - 1 are placed in the sensor chip 220 - 1 , while the system control unit 230 - 2 and the register 231 - 2 are placed in the sensor chip 220 - 2 . The register 600 is placed in the SoC 420 .

[0276] Registers 231-1, 231-2, and 600 are rewritable and store authentication keys K1, K2, and K3, respectively. As these registers, static random access memory (SRAM) or the like is used. Note that Figure 40 There is no illustration of Figure 6 Various circuits such as the delay circuit 510 shown in the diagram.

[0277] In the test mode, the system control unit 230-1 reads the authentication key K1 from the register 231-1 and transmits the authentication key K1 to the system control unit 421, while the system control unit 230-2 reads the authentication key K2 from the register 231-2 and transmits the authentication key K2 to the system management unit 421. The system control unit 421 reads the authentication key K3 from the register 600 and determines whether the authentication key K3 matches each of the authentication keys K1 and K2.

[0278] As illustrated in this figure, storing the authentication key in a rewritable register allows the authentication key to be updated as needed. Furthermore, the authentication key can be rewritten later under user software control, etc. Note that the authentication key is stored in a register; however, as long as the storage location is rewritable, it is not limited to registers and can also be stored in nonvolatile memory, etc. Furthermore, registers 231-1, 231-2, and 600 are examples of the first, second, and third storage units described in the claims.

[0279] Note that when updating the authentication key, as in Figure 41 As shown in the diagram, the new authentication key may also be sent from the SoC 420 to each sensor chip via transmission lines 310 - 1 and 310 - 2 based on, for example, the I 2 C standard, and the authentication key may be stored in a register within each chip.

[0280] Furthermore, each of the second to sixth embodiments is applicable to the second modification of the seventh embodiment.

[0281] As described above, according to the second modification of the seventh embodiment of the present technology, each chip stores the corresponding authentication key in a rewritable register so that the authentication key can be added or updated.

[0282] <8. Application Examples to Mobile Objects>

[0283] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can also be implemented as a device mounted on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0284] Figure 42is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0285] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Figure 42 In the example illustrated in FIG, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0286] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for driving force generation devices such as an internal combustion engine and a drive motor for generating driving force for the vehicle, a driving force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking system for generating braking force for the vehicle.

[0287] The body system control unit 12020 controls the operation of various devices attached to the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various vehicle lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device serving as a key substitute or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and other functions.

[0288] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, and characters on the road surface, or detect the distance to such objects.

[0289] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information related to the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0290] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver is dozing off.

[0291] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement advanced driver assistance system (ADAS) functions, including vehicle collision avoidance or shock absorption, follow-up driving based on following distance, vehicle speed control, vehicle collision warning, vehicle lane departure warning, etc.

[0292] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism, braking device, etc. based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, and perform collaborative control such as automatic driving to enable the vehicle to travel automatically without relying on the driver's operation.

[0293] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle acquired by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, for example, according to the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0294] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information. Figure 42In the example shown in the diagram, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are illustrated. The display portion 12062 may include, for example, at least one of an onboard display and a head-up display.

[0295] Figure 43 It is a diagram illustrating an example of the installation position of the imaging unit 12031.

[0296] exist Figure 43 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0297] Imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at locations such as the front nose, exterior rearview mirrors, rear bumpers, rear doors, and the upper portion of the windshield within the vehicle compartment of the vehicle 12100. Imaging unit 12101 provided at the front nose and imaging unit 12105 provided at the upper portion of the windshield within the vehicle compartment primarily obtain images in front of the vehicle 12100. Imaging units 12102 and 12103 provided at the exterior rearview mirrors primarily obtain images on both sides of the vehicle 12100. Imaging unit 12104 provided at the rear bumper or rear door primarily obtains images from the rear of the vehicle 12100. Imaging unit 12105 provided at the upper portion of the windshield within the vehicle compartment is primarily used to detect preceding vehicles, pedestrians, obstacles, signal lights, traffic signs, lanes, and the like.

[0298] Notice, Figure 43 The diagram illustrates examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101 positioned on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, positioned on the exterior rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104 positioned on the rear bumper or rear door. For example, by superimposing image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 as viewed from above can be obtained.

[0299] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or an imaging element having pixels for phase difference detection.

[0300] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111-12114, as well as the temporal change in this distance (relative speed to vehicle 12100), thereby extracting the nearest three-dimensional object, particularly one located on the travel path of vehicle 12100 and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the preceding vehicle. Furthermore, microcomputer 12051 can pre-set a following distance to be maintained with the preceding vehicle and perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and other functions. This allows for coordinated control aimed at autonomous driving, such as enabling the vehicle to travel autonomously without relying on driver input.

[0301] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those visually recognizable to the driver of the vehicle 12100 and those visually difficult for the driver of the vehicle 12100 to discern. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating the possibility of a collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062 and initiates forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thus assist in driving to avoid collisions.

[0302] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. This identification of pedestrians is performed, for example, by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the pedestrian is present. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104, thereby identifying the pedestrian, the audio / visual output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. The audio / visual output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0303] In the above, an example of a vehicle control system to which the technology of the present disclosure is applicable is described. The technology of the present disclosure is applicable to the vehicle control system 12000 among the above components, for example. Specifically, Figure 4 The electronic device 100 illustrated in FIG is applicable to a vehicle control system 12000. By applying the technology according to the present disclosure to the vehicle control system 12000, electromagnetic interference can be suppressed to enhance the wireless sensitivity of the antenna, thereby enhancing the reliability and safety of the system.

[0304] Note that the embodiments are described as examples for embodying the present technology, and that the matters in the embodiments correspond to the matters defining the present invention in the claims. Similarly, the matters defining the present invention in the claims correspond to the matters with the same names in the embodiments of the present technology. Note that the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the gist of the present technology.

[0305] Note that the effects described herein are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0306] Note that the present technology can also have the following configurations.

[0307] (1) An electronic device comprising:

[0308] antenna;

[0309] a plurality of transmission lines for transmitting signals; and

[0310] A control unit controls directivity of electromagnetic waves radiated from the plurality of transmission lines based on reception performance of the antenna.

[0311] (2) The electronic device according to (1) above, further comprising:

[0312] a first driving unit that outputs a first output signal;

[0313] a second driving unit that outputs a second output signal;

[0314] a first transmission-side delay circuit that delays output of a first output signal; and

[0315] a second transmission-side delay circuit that delays output of a second output signal, wherein

[0316] The plurality of transmission lines include:

[0317] a first transmission line transmitting a first output signal; and

[0318] a second transmission line transmitting a second output signal, and

[0319] The control unit adjusts the delay time of the first transmission-side delay circuit and the second transmission-side delay circuit.

[0320] (3) The electronic device according to (2) above, wherein

[0321] The first transmission-side delay circuit and the second transmission-side delay circuit each include:

[0322] a multi-stage delay element generating a plurality of delayed signals having different delay times; and

[0323] A selector that selects and outputs a clock signal or one of the plurality of delayed signals.

[0324] (4) The electronic device according to (2) above, wherein

[0325] The first transmission-side delay circuit and the second transmission-side delay circuit each include:

[0326] a logic circuit that outputs a signal obtained by delaying a clock signal;

[0327] a plurality of first transistors connected in parallel between a power supply terminal of the logic circuit and a power supply node; and

[0328] a plurality of second transistors connected in parallel between a ground terminal of the logic circuit and a ground node, and

[0329] The control unit controls the number of the first transistors that are in the on state and the number of the second transistors that are in the on state.

[0330] (5) The electronic device according to (2) above, wherein

[0331] The first transmission-side delay circuit and the second transmission-side delay circuit each include:

[0332] A logic circuit that delays and outputs a clock signal;

[0333] a first transistor interposed between a power supply terminal of the logic circuit and a power supply node;

[0334] a second transistor inserted between a ground terminal of the logic circuit and a ground node;

[0335] a first bias voltage generating circuit that generates a first bias voltage and supplies the first bias voltage to a gate of the first transistor; and

[0336] a second bias voltage generating circuit that generates a second bias voltage and supplies the second bias voltage to the gate of the second transistor, and

[0337] The control unit controls each of the first bias voltage and the second bias voltage.

[0338] (6) The electronic device according to any one of (2) to (5) above, wherein

[0339] The communication standard applied to the plurality of transmission lines includes a Mobile Industry Processor Interface (MIPI) C-PHY standard.

[0340] (7) The electronic device according to (2) above, further comprising:

[0341] a first receiving-side delay circuit that delays and outputs the first output signal as a first delayed signal;

[0342] a second receiving-side delay circuit that delays and outputs the second output signal as a second delayed signal;

[0343] a first receiver circuit receiving the first delayed signal; and

[0344] a second receiver circuit receiving a second delayed signal, wherein

[0345] The control unit further adjusts the delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit.

[0346] (8) The electronic device according to (7) above, wherein

[0347] The communication standard applied to the plurality of transmission lines includes a MIPI D-PHY standard.

[0348] (9) The electronic device according to (7) or (8) above, wherein

[0349] The control unit comprises:

[0350] a transmitting-side control unit configured to adjust respective delay times of the first transmitting-side delay circuit and the second transmitting-side delay circuit and provide a control signal related to the delay time; and

[0351] A receiving-side control unit is configured to adjust a delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit based on the control signal.

[0352] (10) The electronic device according to (9) above, wherein

[0353] The first reception-side delay circuit and the second reception-side delay circuit each include a delay-locked loop (DLL).

[0354] (11) The electronic device according to (9) or (10) above, further comprising

[0355] an edge inversion determination circuit that determines whether the sign of the phase difference between the edge of the first delayed signal and the edge of the second delayed signal is inverted and outputs a determination result, wherein

[0356] The reception-side control unit adjusts the delay time of each of the first reception-side delay circuit and the second reception-side delay circuit based on the control signal and the determination result.

[0357] (12) The electronic device according to (1) above, wherein

[0358] The communication standards applied to the plurality of transmission lines include standards applied to transmission of differential signals or single-ended signals.

[0359] (13) The electronic device according to (12) above, wherein

[0360] Communication standards applied to transmission of differential signals include Peripheral Component Interconnect Express (PCIe), and communication standards applied to transmission of single-ended signals include Double Data Rate (DDR).

[0361] (14) The electronic device according to any one of (1) to (13) above, wherein

[0362] The plurality of transmission lines include:

[0363] a predetermined number of first transmission lines for transmitting signals from the first chip to the control unit; and

[0364] A predetermined number of second transmission lines transmit signals from the second chip to the control unit.

[0365] (15) The electronic device according to (14) above, wherein

[0366] The output timing of the signals transmitted by the predetermined number of first transmission lines is the same,

[0367] The output timing of the signals transmitted by the predetermined number of second transmission lines is the same, and

[0368] The control unit adjusts a delay time of one of the first transmission line or the second transmission line relative to an output timing of the other transmission line.

[0369] (16) The electronic device according to (14) above, wherein

[0370] The control unit individually adjusts delay times of signals transmitted through each of the predetermined number of first transmission lines and the predetermined number of second transmission lines.

[0371] (17) The electronic device according to (14) above, wherein

[0372] The output timing of the signals transmitted by the predetermined number of second transmission lines is the same, and

[0373] The control unit individually controls the delay time of the output timing and the delay time of the signals transmitted by each of the predetermined number of first transmission lines.

[0374] (18) The electronic device according to any one of (14) to (17) above, wherein

[0375] The first chip sends a first authentication key,

[0376] The second chip sends a second authentication key, and

[0377] The control unit authenticates each of the first and second chips based on whether each of the first and second authentication keys matches a third authentication key, and controls directivity of electromagnetic waves radiated from a transmission line corresponding to a chip that has been successfully authenticated.

[0378] (19) The electronic device according to (18) above further includes

[0379] A rewritable third storage unit storing a third authentication key, wherein

[0380] The first chip includes a rewritable first storage unit storing a first authentication key, and

[0381] The second chip includes a rewritable second storage unit storing a second authentication key.

[0382] (20) A method for controlling an electronic device, the method comprising:

[0383] measuring a parameter indicative of reception performance of the antenna; and

[0384] Based on the parameters, the directivity of electromagnetic waves radiated from a plurality of transmission lines that transmit signals is controlled.

[0385] Reference Signs List

[0386] 100 electronic devices

[0387] 110 shell

[0388] 120 antenna

[0389] 200 camera modules

[0390] 201 module head

[0391] 202 module board

[0392] 210, 415 separation components

[0393] 211 lens

[0394] 220, 220-1, 220-2 sensor chips

[0395] 221 Data Generation Unit

[0396] 222, 430 Delay Configuration Circuit

[0397] 223, 224, 431-433, 510 Delay Circuits

[0398] 225 to 227 drive units

[0399] 230, 230-1, 230-2, 421 system control units

[0400] 231-1, 231-2, 600 Registers

[0401] 300FPC cable

[0402] 301, 302 ground wire

[0403] 310, 310-1, 310-2, 320, 320-1, 320-2, 330, 330-1, 330-2, 340, 340-1,340-2 transmission lines

[0404] 321-323, 331-333, 341-343 signal lines

[0405] 400 motherboard

[0406] 410 connector

[0407] 420SoC

[0408] 422~424 receiver circuit

[0409] 425 communication circuit

[0410] 426~428 Synchronous Circuit

[0411] 429 Data Processing Unit

[0412] 440 edge inversion determination circuit

[0413] 441, 442, 450 pulse generation circuits

[0414] 443-445 triggers

[0415] 451 Inverting Delay Line

[0416] 452, 511~524, 549 Inverters

[0417] 453 Delay Line

[0418] 454, 455 Logic AND Gates

[0419] 456 logical OR gate

[0420] 525 Selector

[0421] 531~539pMOS transistors

[0422] 540-548nMOS transistors

[0423] 550P channel bias voltage generation unit

[0424] 551N channel bias voltage generation unit

[0425] 560, 565, 566DLL

[0426] 561 Phase Comparator

[0427] 562 shift register

[0428] 563 variable delay line

[0429] 564 replica delay line

[0430] 590, 595, 596 driver circuits

[0431] 591 Serializer

[0432] 592 pre-driver

[0433] 593 Final Drive

[0434] 12000 vehicle control system

Claims

1. An electronic device comprising: antenna; multiple transmission lines for transmitting signals; and A control unit controls directivity of electromagnetic waves radiated from the plurality of transmission lines based on reception performance of the antenna.

2. The electronic device according to claim 1, further comprising: a first driving unit that outputs a first output signal; a second driving unit that outputs a second output signal; a first transmission-side delay circuit for delaying output of a first output signal; and a second transmission-side delay circuit that delays output of a second output signal, wherein The plurality of transmission lines include: a first transmission line for transmitting a first output signal; and a second transmission line transmitting a second output signal, and The control unit adjusts the delay time of the first transmission-side delay circuit and the second transmission-side delay circuit.

3. The electronic device according to claim 2, wherein The first transmission-side delay circuit and the second transmission-side delay circuit each include: a multi-stage delay element for generating a plurality of delayed signals having different delay times; and A selector that selects and outputs a clock signal or one of the plurality of delayed signals.

4. The electronic device according to claim 2, wherein The first transmission-side delay circuit and the second transmission-side delay circuit each include: a logic circuit that outputs a signal obtained by delaying a clock signal; a plurality of first transistors connected in parallel between a power supply terminal of the logic circuit and a power supply node; and a plurality of second transistors connected in parallel between a ground terminal of the logic circuit and a ground node, and The control unit controls the number of the first transistors that are in the on state and the number of the second transistors that are in the on state.

5. The electronic device according to claim 2, wherein The first transmission-side delay circuit and the second transmission-side delay circuit each include: A logic circuit that delays and outputs a clock signal; a first transistor interposed between a power supply terminal of the logic circuit and a power supply node; a second transistor inserted between a ground terminal of the logic circuit and a ground node; a first bias voltage generating circuit that generates a first bias voltage and provides the first bias voltage to the gate of the first transistor; and a second bias voltage generating circuit that generates a second bias voltage and supplies the second bias voltage to the gate of the second transistor, and The control unit controls each of the first bias voltage and the second bias voltage.

6. The electronic device according to claim 2, wherein The communication standard applied to the plurality of transmission lines includes a Mobile Industry Processor Interface (MIPI) C-PHY standard.

7. The electronic device according to claim 2, further comprising: a first receiving-side delay circuit that delays and outputs the first output signal as a first delayed signal; a second receiving-side delay circuit that delays and outputs the second output signal as a second delayed signal; a first receiver circuit receiving the first delayed signal; and a second receiver circuit receiving a second delayed signal, wherein The control unit further adjusts the delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit.

8. The electronic device according to claim 7, wherein The communication standard applied to the plurality of transmission lines includes a MIPI D-PHY standard.

9. The electronic device according to claim 7, wherein The control unit comprises: a transmitting-side control unit configured to adjust a delay time of each of the first transmitting-side delay circuit and the second transmitting-side delay circuit and provide a control signal related to the delay time; and A receiving-side control unit is configured to adjust a delay time of each of the first receiving-side delay circuit and the second receiving-side delay circuit based on the control signal.

10. The electronic device according to claim 9, wherein The first reception-side delay circuit and the second reception-side delay circuit each include a delay-locked loop (DLL).

11. The electronic device according to claim 9, further comprising: an edge inversion determination circuit that determines whether the sign of the phase difference between the edge of the first delayed signal and the edge of the second delayed signal is inverted and outputs a determination result, wherein The reception-side control unit adjusts the delay time of each of the first reception-side delay circuit and the second reception-side delay circuit based on the control signal and the determination result.

12. The electronic device according to claim 1, wherein The communication standards applied to the plurality of transmission lines include standards applied to transmission of differential signals or single-ended signals.

13. The electronic device according to claim 12, wherein Communication standards applied to transmission of differential signals include Peripheral Component Interconnect Express (PCIe), and communication standards applied to transmission of single-ended signals include Double Data Rate (DDR).

14. The electronic device according to claim 1, wherein The plurality of transmission lines include: a predetermined number of first transmission lines for transmitting signals from the first chip to the control unit; and A predetermined number of second transmission lines transmit signals from the second chip to the control unit.

15. The electronic device according to claim 14, wherein The output timing of the signals transmitted by the predetermined number of first transmission lines is the same, The output timing of the signals transmitted by the predetermined number of second transmission lines is the same, and The control unit adjusts a delay time of one of the first transmission line or the second transmission line relative to an output timing of the other transmission line.

16. The electronic device according to claim 14, wherein The control unit individually adjusts delay times of signals transmitted through each of the predetermined number of first transmission lines and the predetermined number of second transmission lines.

17. The electronic device according to claim 14, wherein The output timing of the signals transmitted by the predetermined number of second transmission lines is the same, and The control unit individually controls the delay time of the output timing and the delay time of the signals transmitted by each of the predetermined number of first transmission lines.

18. The electronic device according to claim 14, wherein The first chip sends a first authentication key, The second chip sends a second authentication key, and The control unit authenticates each of the first and second chips based on whether each of the first and second authentication keys matches a third authentication key, and controls directivity of electromagnetic waves radiated from a transmission line corresponding to a chip that has been successfully authenticated.

19. The electronic device according to claim 18, further comprising: A rewritable third storage unit storing a third authentication key, wherein The first chip includes a rewritable first storage unit storing a first authentication key, and The second chip includes a rewritable second storage unit storing a second authentication key.

20. A method for controlling an electronic device, the method comprising: measuring parameters indicative of the reception performance of an antenna; as well as Based on the parameters, the directivity of electromagnetic waves radiated from a plurality of transmission lines that transmit signals is controlled.

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