Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: a first insulating layer; a metal layer disposed on the first insulating layer; and a second insulating layer disposed on the metal layer and having a cavity, in which the metal layer includes a plurality of metal patterns spaced apart from each other in a circumferential direction of a lower end of a sidewall of the cavity.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] As the performance of electronic / electrical products advances, technologies for attaching a greater number of packages to a substrate of limited size are being proposed and studied.

[0003] A typical semiconductor package has multiple chips mounted therein. Furthermore, the size of semiconductor packages is increasing due to the higher specifications of products using these packages and the adoption of multiple chips, such as in high-bandwidth memory (HBM). Therefore, semiconductor packages now include an interposer for connecting multiple chips.

[0004] In addition, with the trend toward higher integration, semiconductor packages used in products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers require high performance and high reliability.

[0005] In addition, the semiconductor package has a vertical connection structure between a plurality of substrates, interposers, and semiconductor devices. Therefore, the thickness of the semiconductor package in the vertical direction can be increased according to the thickness and number of the substrates, interposers, and semiconductor devices.

[0006] Therefore, the semiconductor package reduces the thickness in the vertical direction by using a substrate having a cavity.

[0007] At this time, in the process of manufacturing a substrate having a cavity, a desmear process must be performed. That is, if the desmear process is not performed, the adhesion between the molding member arranged in the cavity and the substrate may be reduced, and thus the molding member may be separated from the substrate.

[0008] In addition, when the desmear process is performed, the bottom surface of the cavity can be etched together with the sidewalls of the cavity. As a result, the bottom surface of the cavity may be damaged, which may cause problems in the physical reliability of the substrate.

[0009] Furthermore, the bottom surface of the cavity may be the upper surface of the thermosetting resin containing the glass fibers. Therefore, when the desmear process is performed, the thermosetting resin is etched, and the glass fibers disposed in the thermosetting resin may be exposed through the cavity. Furthermore, the exposed glass fibers may be a factor that causes defects such as copper migration.

[0010] (Patent Document 1) KR 10-2012-0045639 A Summary of the Invention

[0011] Technical issues

[0012] The embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0013] Furthermore, the embodiment provides a circuit board including a cavity and a semiconductor package including the circuit board.

[0014] Furthermore, the embodiment provides a circuit board having improved circuit integration and a semiconductor package including the same.

[0015] Furthermore, embodiments provide a circuit board having improved electrical reliability and / or mechanical reliability and a semiconductor package including the same.

[0016] Furthermore, embodiments provide a circuit board having improved warpage characteristics and a semiconductor package including the same.

[0017] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems; rather, those skilled in the art to which the proposed embodiments pertain may clearly understand other unmentioned technical problems from the following description.

[0018] Technical Solution

[0019] According to one embodiment, a circuit board includes: a first insulating layer; a metal layer arranged on the first insulating layer; and a second insulating layer arranged on the metal layer and having a cavity, wherein the metal layer includes a plurality of metal patterns, and the plurality of metal patterns are arranged to be spaced apart from each other in a circumferential direction of a lower end of a side wall of the cavity.

[0020] In addition, the circuit board also includes a first circuit pattern layer arranged on the first insulating layer, wherein the first circuit pattern layer includes: a first solder pad, which overlaps with the cavity in the vertical direction; and a second solder pad, which does not overlap with the cavity in the vertical direction.

[0021] In addition, the first circuit pattern layer also includes a connecting pattern connected between the first pad and the second pad, wherein the connecting pattern includes: a first portion, the first portion vertically overlaps with the cavity and is not covered by the second insulating layer; and a second portion, the second portion does not vertically overlap with the cavity and is covered by the second insulating layer.

[0022] In addition, the connection pattern is disposed on the first insulating layer to cross between the plurality of metal patterns.

[0023] In addition, the connection pattern is not connected to any of the plurality of metal patterns.

[0024] In addition, the connection pattern is provided in plurality, and at least one connection pattern among the plurality of connection patterns is connected to at least one metal pattern among the plurality of metal patterns.

[0025] In addition, the plurality of metal patterns have different widths in the horizontal direction along the circumferential direction.

[0026] In addition, the plurality of metal patterns are spaced apart at intervals in a range of 2 μm to 12 μm in a circumferential direction.

[0027] In addition, each of the first pad and the second pad includes: a first layer, which is arranged on the first insulating layer; and a second layer, which is arranged on the first layer, and wherein the thickness of each metal pattern of the plurality of metal patterns corresponds to the thickness of the second layer of the first pad and the second pad.

[0028] In addition, the second insulating layer includes a first concave portion that is concavely disposed from a lower end of a sidewall of the cavity toward an outer surface of the second insulating layer in a horizontal direction.

[0029] In addition, the first recess includes a plurality of first recesses disposed between the plurality of metal patterns and a sidewall of the cavity, and a portion of a side surface of each of the plurality of metal patterns is exposed through the first recess and the cavity.

[0030] In addition, a vertical distance of each of the plurality of first recesses in the vertical direction corresponds to a thickness of each of the plurality of metal patterns.

[0031] In addition, the first insulating layer includes a second recessed portion connected to a lower end of a sidewall of the cavity and disposed recessed from an upper surface of the first insulating layer toward a lower surface of the first insulating layer in a vertical direction.

[0032] Furthermore, the second recessed portion includes a plurality of second recessed portions spaced apart from each other in the circumferential direction, and the plurality of first recessed portions and the plurality of second recessed portions are alternately arranged in the circumferential direction.

[0033] At the same time, according to one embodiment, a semiconductor package includes: a first insulating layer; a second insulating layer, the second insulating layer is arranged on the first insulating layer and includes a cavity; a first circuit pattern layer, the first circuit pattern layer includes a first pad arranged between the first insulating layer and the second insulating layer and overlapping with the cavity in a vertical direction, a second pad that does not overlap with the cavity in a vertical direction, and a connecting pattern connecting the first pad and the second pad; a joining member, the joining member is arranged on the first pad; a connecting member, the connecting member is arranged on the joining member; and a metal layer, the metal layer is arranged on the first insulating layer along the circumferential direction of the lower end of the side wall of the cavity, wherein the metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0034] Furthermore, the semiconductor package includes a molding member that is disposed within the cavity to mold the connection member and that contacts the plurality of metal patterns.

[0035] In addition, the second insulating layer includes a first recessed portion that is recessed in a horizontal direction from a lower end of the side wall of the cavity toward an outer surface of the second insulating layer, and the first recessed portion includes a plurality of first recesses that are disposed between the plurality of metal patterns and the side wall of the cavity, and the molding member is configured to fill the plurality of first recesses.

[0036] In addition, the first insulating layer includes a plurality of second recesses, which are arranged concavely from the upper surface of the first insulating layer toward the lower surface of the first insulating layer in the vertical direction, and the plurality of second recesses are alternately arranged with the plurality of first recesses along the circumferential direction, and the molding member is arranged to further fill the plurality of second recesses.

[0037] Furthermore, the connection member includes at least one of an interposer, a semiconductor device, an organic bridge, and an inorganic bridge.

[0038] Beneficial effects

[0039] This embodiment may include a first insulating layer and a second insulating layer disposed on the first insulating layer and including a cavity. A metal layer is disposed circumferentially along a lower end of a sidewall of the cavity and disposed between the first insulating layer and the second insulating layer. The metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0040] The multiple metal patterns can serve as reinforcement members to increase the rigidity of the circuit board. For example, the multiple metal patterns can disperse or reduce stress acting on the circuit board, thereby improving the circuit board's warping characteristics. Furthermore, the multiple metal patterns can reduce horizontal expansion of the circuit board caused by thermal stress in the circuit board's manufacturing or usage environment, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package incorporating the circuit board.

[0041] In addition, the embodiment further includes a connection pattern that is arranged on the first insulating layer and directly connects the first pad and the second pad. The connection pattern can be arranged to cross between the multiple metal patterns. In this case, multiple connection patterns can be provided. In this case, the multiple metal patterns are arranged to be spaced apart from each other in the circumferential direction, and therefore, the multiple connection patterns may not be electrically connected to each other on the first insulating layer. Therefore, the embodiment can use the connection pattern to directly connect the first pad and the second pad, and therefore, the first through-electrode that overlaps with the first pad in the vertical direction can be omitted. In addition, the embodiment can shorten the length of the signal line between the first pad and the second pad by using the connection pattern to directly connect the first pad and the second pad. For example, the signal line including the connection pattern can be shorter than the signal line including the first through-electrode. Therefore, the embodiment can minimize the signal transmission loss by shortening the signal transmission line between the first pad and the second pad, thereby improving the electrical characteristics. In addition, the embodiment can improve the circuit integration by arranging the connection pattern that directly connects the first pad and the second pad.

[0042] Furthermore, the second insulating layer of an embodiment may include a first recessed portion disposed between the plurality of metal patterns and the lower end of the sidewall of the cavity. The first recessed portion can disperse or reduce stress acting on the first and second insulating layers, thereby improving the warping characteristics of the circuit board. For example, the first recessed portion can reduce the area of ​​the interface between the first and second insulating layers, thereby dispersing stress acting on the second insulating layer. Thus, the first recessed portion can reduce the phenomenon of the circuit board bending in a specific direction (for example, bending upward at both ends of the circuit board, or bending downward at both ends of the circuit board).

[0043] Furthermore, the first insulating layer of an embodiment may include a second recessed portion arranged circumferentially. The second recessed portion may be arranged vertically, concavely from the upper surface toward the lower surface of the first insulating layer. In this case, the first recessed portion is a recessed portion arranged horizontally in the second insulating layer, while the second recessed portion is a recessed portion arranged vertically in the first insulating layer. Thus, the embodiment can improve the warpage characteristics of the circuit board by using the first and second recessed portions to disperse or reduce stress acting on the circuit board.

[0044] For example, the first and second recessed portions can mitigate horizontal expansion of the circuit board due to thermal stress in the circuit board's manufacturing or usage environment, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package including the circuit board. In this case, the second insulating layer can include an insulating material different from that of the first insulating layer. Therefore, the first and second insulating layers can have different coefficients of thermal expansion, potentially causing vertical warping of the circuit board. Consequently, the first and second recessed portions can prevent the circuit board from bending in a particular direction (e.g., bending upward at either end of the circuit board, or bending downward at either end of the circuit board).

[0045] Therefore, embodiments can minimize vertical warping of the circuit board and semiconductor package, or horizontal expansion or contraction, thereby improving the mechanical and / or physical reliability of the circuit board and semiconductor package. Furthermore, embodiments can enable semiconductor devices arranged on the circuit board to operate stably, thereby improving the operating characteristics of electronic products and / or servers to which the semiconductor package is applied.

[0046] Furthermore, the multiple metal patterns of the embodiments can have different horizontal widths along the circumferential direction. For example, the horizontal width of a metal pattern in an area with relatively low metal density can be greater than the horizontal width of a metal pattern in an area with relatively high metal density. Thus, embodiments can minimize circuit board warping caused by differences in metal density, thereby further improving the physical and / or electrical reliability of the circuit board and semiconductor package.

[0047] Furthermore, embodiments can perform a desmearing process on the second insulating layer after forming the cavity while the barrier layer is provided. This can prevent the glass fibers of the first insulating layer from being exposed, further resolving the resulting physical reliability and / or electrical reliability issues. Furthermore, embodiments can determine desmearing process conditions without regard to glass fiber exposure. For example, embodiments can determine desmearing process conditions to optimally improve adhesion between the second insulating layer and the second circuit pattern layer, thereby improving adhesion between the second insulating layer and the second circuit pattern layer without exposing the reinforcing member.

[0048] At the same time, the desmear process of the embodiment can be performed while a through-hole and a cavity are formed that penetrate the second insulating layer. Therefore, during the desmear process, the inner wall of the through-hole and the inner wall of the cavity can be surface treated together. This can improve the adhesion between the second through-electrode arranged in the through-hole and the second insulating layer. Furthermore, the embodiment can improve the adhesion between the molding member arranged in the cavity and the second insulating layer.

[0049] In addition, the molding member may be configured to fill at least one of the first recess and the second recess. Therefore, the embodiment can further improve the bonding strength between the molding member and the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a cross-sectional view showing a circuit board according to the first embodiment.

[0051] Figure 2 and Figure 3 Is used to illustrate Figure 1 A plan view of the process of providing a metal pattern on a circuit board.

[0052] Figure 4 is shown in the settings Figure 1 A plan view of the metal pattern on a circuit board.

[0053] Figure 5 It is along Figure 4 A cross-sectional view of the circuit board taken along the A-A' direction.

[0054] Figure 6 is a cross-sectional view showing a circuit board according to a second embodiment.

[0055] Figure 7 is a cross-sectional view showing a circuit board according to a third embodiment.

[0056] Figure 8 is a cross-sectional view showing a circuit board according to a fourth embodiment.

[0057] Figure 9 It shows Figure 8 A plan view of the circuit board.

[0058] Figure 10 is a cross-sectional view showing a circuit board according to a fifth embodiment.

[0059] Figure 11 yes Figure 10 A plan view of the circuit board.

[0060] Figure 12 It shows Figure 10 An enlarged view of a portion of a circuit board.

[0061] Figure 13 1 and 2 are diagrams illustrating the upper surface of the first region of the first insulating layer according to the embodiment and the comparative example.

[0062] Figure 14 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0063] Figures 15 to 28 The process sequence is shown in FIG. Figure 8 FIG. 1 is a diagram of a method for manufacturing a circuit board. DETAILED DESCRIPTION

[0064] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0065] However, the spirit and scope of the present invention are not limited to a part of the described embodiments, but may be implemented in various other forms, and one or more of the elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present invention.

[0066] In addition, unless otherwise explicitly defined and explained, the terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as having the same meaning as commonly understood by those skilled in the art to which the present invention belongs, and terms such as those defined in commonly used dictionaries can be interpreted as having meanings consistent with their meanings in the context of the relevant field. In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0067] In this specification, unless otherwise specified in a phrase, a singular form may also include a plural form, and when described as "at least one (or more) of A (and), B, and C", it may include at least one of all possible combinations of A, B, and C. In addition, when describing elements of the embodiments of the present invention, terms such as "first", "second", A, B, (a), and (b) may be used.

[0068] These terms are only used to distinguish these elements from other elements, and these terms are not limited by the nature, order or sequence of these elements. In addition, when an element is described as being "connected", "coupled" or "connected to" other elements, this may include not only the case where the element is directly "connected", "coupled" or "connected to" other elements, but also the case where the element is "connected", "coupled" or "connected to" through another element located between the element and the other element.

[0069] In addition, when described as being formed or arranged “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only a case where two elements are directly connected to each other, but also a case where one or more other elements are formed or arranged between the two elements. Furthermore, when expressed as being “on (above)” or “under (below)”, with reference to one element, it may include not only an upward direction but also a downward direction.

[0070] - Electronic equipment -

[0071] Before describing the embodiments, an electronic device to which the semiconductor package of the present embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the present embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0072] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into a single semiconductor device. Semiconductor devices may include logic chips, memory chips, and the like. Logic chips may include central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) chip (including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller), or may include an analog-to-digital converter, an application-specific integrated circuit (ASIC), and the like, or may include a chipset including a specific combination of the chips listed above.

[0073] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (such as DRAM), a non-volatile memory (such as ROM), or a flash memory.

[0074] On the other hand, the product group of the semiconductor package to which the present embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0075] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a display, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automobile, etc. However, the present embodiment is not limited thereto, but may also be any other electronic device that processes data in addition to these.

[0076] Hereinafter, a circuit board and a semiconductor package including the same according to embodiments will be described. The semiconductor package may have various vertical and horizontal stacking structures including the circuit board described below. For example, the semiconductor package may include a connecting member including at least one of a bridging substrate and an interposer for coupling at least one semiconductor device and / or high-density wiring to the circuit board.

[0077] Figure 1 is a sectional view showing a circuit board according to a first embodiment, Figure 2 and Figure 3 Is used to illustrate Figure 1 A plan view of the process of providing a metal pattern on a circuit board, Figure 4 is shown in the settings Figure 1 A plan view of the metal pattern on the circuit board, and Figure 5 It is along Figure 4 A cross-sectional view of the circuit board taken along the A-A' direction.

[0078] First, refer to Figure 1 , a schematic structure of a circuit board according to a first embodiment will be described.

[0079] Reference Figure 1 The circuit board of this embodiment may include multiple insulating layers. Each of the multiple insulating layers may have a single-layer structure, or alternatively, may also be composed of multiple layers.

[0080] Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112. At this time, the first insulating layer 111 may have a Figure 1 A single-layer structure is shown, but alternatively, a multi-layer structure is also possible.

[0081] The second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may have a single-layer structure, or alternatively, may have a multi-layer structure.

[0082] The second insulating layer 112 may include a cavity 150. When the second insulating layer 112 has a multi-layer structure, the cavity 150 may penetrate one layer of the multi-layer second insulating layer, or alternatively, may penetrate at least two layers simultaneously.

[0083] In one embodiment, the first insulating layer 111 and the second insulating layer 112 may include the same insulating material. In this case, the first insulating layer 111 may refer to an insulating layer without the cavity 150 , and the second insulating layer 112 may refer to an insulating layer with the cavity 150 .

[0084] In another embodiment, the first insulating layer 111 and the second insulating layer 112 may include different insulating materials.

[0085] However, for convenience of explanation, the first insulating layer 111 and the second insulating layer 112 are described as having a single-layer structure and including different insulating materials.

[0086] The first insulating layer 111 and the second insulating layer 112 may include different insulating materials. For example, the first insulating layer 111 may include a thermosetting resin, and the second insulating layer 112 may include a photocurable resin. However, this embodiment is not limited thereto. Each of the first insulating layer 111 and the second insulating layer 112 may be provided with a thermosetting resin, or each of the first insulating layer 111 and the second insulating layer 112 may be provided with a photocurable resin, or the first insulating layer 111 may be provided with a photocurable resin, while the second insulating layer 112 may be provided with a thermosetting resin.

[0087] The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the upper and lower surfaces of the second insulating layer 112. The cavity 150 may include a bottom surface and a sidewall 150S.

[0088] The bottom surface of the cavity 150 may refer to an upper surface of the first insulating layer 111 vertically overlapping the cavity 150. In addition, the sidewall 150S of the cavity 150 may refer to a sidewall of the second insulating layer 112 vertically overlapping the cavity 150.

[0089] The sidewall 150S of the cavity 150 may have an inclination. For example, the sidewall 150S of the cavity 150 may have an inclination in which the width of the cavity 150 decreases from the upper surface toward the lower surface of the second insulating layer 112. However, the present embodiment is not limited thereto. For example, the sidewall 150S may have an inclination in which the width of the cavity 150 decreases from the lower surface toward the upper surface of the second insulating layer 112. In addition, although the sidewall 150S is shown as having a single inclination in the figure, it is not limited thereto. For example, the sidewall 150S may include at least one inflection portion and may be inclined at different inclinations at the inflection point.

[0090] The upper surface of the first insulating layer 111 may be divided into a plurality of regions. For example, the first insulating layer 111 may include a first region R1 vertically overlapping the cavity 150. In this case, when the cavity 150 has different widths in the thickness direction of the second insulating layer 112, the first region R1 may refer to a region vertically overlapping the lower region of the cavity 150 corresponding to the lower end of the sidewall 150S.

[0091] In addition, the first insulating layer 111 may include a second region R2 that does not vertically overlap the cavity 150. The second region R2 may refer to a region of the upper surface of the first insulating layer 111 covered by the second insulating layer 112.

[0092] At this time, the circuit board of this embodiment may have a reinforcement portion. The reinforcement portion can disperse the stress caused by expansion and / or contraction due to thermal stress of the circuit board and prevent the circuit board from bending in the vertical and / or horizontal directions. The reinforcement portion of the first embodiment may include the first recessed portion 112R and the metal layer 121BP described below. For example, the reinforcement portion of the first embodiment may include a plurality of reinforcement patterns, and the plurality of reinforcement patterns may respectively include a plurality of first recesses of the first recessed portion 112R and a plurality of metal patterns of the metal layer 121BP.

[0093] For example, the second insulating layer 112 may have a first recessed portion 112R as a portion of the reinforcing portion.

[0094] The first recessed portion 112R may be connected to the lower end of the sidewall 150S of the second insulating layer 112. For example, the lower end of the sidewall 150S of the second insulating layer 112 may include a portion connected to the first recessed portion 112R. In this case, the lower end of the sidewall 150S of the second insulating layer 112 may be partially connected to the first recessed portion 112R. For example, the lower end of the sidewall of the second insulating layer 112 may include a connection portion connected to the first recessed portion 112R and a non-connection portion not connected to the first recessed portion 112R.

[0095] Therefore, the lower end of the sidewall 150S of the second insulating layer 112 may have a step in the circumferential direction. For example, the lower end of the sidewall 150S of the second insulating layer 112 may include a connection portion with the first recessed portion 112R and a non-connection portion, and the connection portion and the non-connection portion may have different heights. The connection portion of the lower end of the sidewall 150S of the second insulating layer 112 may be positioned higher than the non-connection portion. For example, the connection portion of the lower end of the sidewall 150S of the second insulating layer 112 may not contact the upper surface of the first insulating layer 111, while the non-connection portion may contact the upper surface of the first insulating layer 111.

[0096] At this time, the first concave portion 112R may be disposed in a horizontal direction in the second insulating layer 112. For example, the first concave portion 112R may be disposed concavely from the lower end of the sidewall 150S of the cavity 150 toward the outer surface of the second insulating layer 112.

[0097] That is, the first recessed portion 112R may be provided concavely at a lower end of the sidewall 150S of the cavity 150 of the second insulating layer 112 in a horizontal direction away from the cavity 150. The first recessed portion 112R may vertically overlap with the second region R2 of the first insulating layer 111 positioned adjacent to the first region R1 of the first insulating layer 111. The first recessed portion 112R may be a region from which a portion of the barrier layer 121BR protecting the upper surface of the first region R1 of the first insulating layer 111 is removed.

[0098] The first region R1 of the first insulating layer 111 may vertically overlap the cavity 150 and may not contact the second insulating layer 112. In addition, a portion of the second region R2 of the first insulating layer 111 may vertically overlap the first concave portion 112R and may not contact the second insulating layer 112.

[0099] In this embodiment, a first concave portion 112R concave in the horizontal direction may be provided in the second insulating layer 112 adjacent to the cavity 150. Thus, this embodiment can disperse or alleviate the stress acting on the first insulating layer 111 and the second insulating layer 112, thereby improving the warpage characteristics of the circuit board.

[0100] For example, the first recessed portion 112R can reduce the area of ​​the interface between the first insulating layer 111 and the second insulating layer 112, thereby dispersing the stress acting on the second insulating layer 112. Therefore, the first recessed portion 112R can reduce a phenomenon in which the circuit board is bent in a specific direction (for example, a phenomenon in which both ends of the circuit board are bent upward, or a phenomenon in which both ends of the circuit board are bent downward).

[0101] At this time, the first concave portion 112R is provided along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Preferably, the first concave portion 112R may include a plurality of first recesses provided along the circumferential direction of the lower end of the sidewall 150S of the cavity 150.

[0102] Furthermore, the plurality of first recesses of the first recessed portion 112R are spaced apart from one another along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Therefore, the present embodiment can efficiently disperse stress applied to the second insulating layer 112 while maintaining adhesion between the first insulating layer 111 and the second insulating layer 112.

[0103] For example, compared to the structure of the present invention, the first recessed portion 112R can be configured as a closed loop shape connected to each other along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. In this case, the adhesion between the first insulating layer 111 and the second insulating layer 112 may decrease, and the second insulating layer 112 may have a problem of peeling off from the first insulating layer 111. In addition, when the first recessed portion 112R has a closed loop shape, although the stress in the horizontal direction caused by the contraction and / or expansion of the second insulating layer 112 can be dispersed, the degree of warping in the vertical direction may increase. Therefore, this embodiment allows the first recessed portion 112R to have a plurality of first recesses spaced apart from each other along the circumferential direction, thereby achieving the effect of improving the adhesion between the first insulating layer 111 and the second insulating layer 112 and improving the warping in the vertical direction while dispersing the stress.

[0104] Furthermore, each of the plurality of first recesses of the first recessed portion 112R may have the same horizontal width along the circumferential direction of the lower end of the sidewall 150S of the cavity 150, but is not limited thereto. For example, each of the plurality of first recesses may have a different horizontal width along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Furthermore, the horizontal width of each of the plurality of first recesses may be determined according to the warping direction of the circuit board, but is not limited thereto.

[0105] Therefore, this embodiment can minimize the extent of horizontal expansion or contraction of the circuit board and semiconductor package, thereby improving the mechanical and / or physical reliability of the circuit board and semiconductor package. In addition, this embodiment can ensure stable operation of the semiconductor device arranged on the circuit board, thereby improving the operating characteristics of the electronic products and / or servers using the semiconductor package.

[0106] Furthermore, the first recess 112R can be filled with the molding member in the semiconductor package. The first recess 112R can serve as an anchor point to improve the bonding strength between the molding member and the circuit board. Therefore, this embodiment can solve the mechanical reliability problem of the molding member being peeled off from the circuit board.

[0107] At the same time, a circuit pattern layer is arranged on the first insulating layer 111 and the second insulating layer 112. In this case, a portion of the circuit pattern layer may not be used as a circuit (for example, a function of transmitting electrical signals), and this portion may be defined as a "metal layer." Therefore, the circuit pattern layer may refer to a layer used as a circuit, and the metal layer may refer to a layer not used as a circuit, but it is not limited thereto. For example, at least one of the multiple metal patterns of the metal layer may be connected to the circuit pattern layer, and the metal pattern connected to the circuit pattern layer may be used together with the circuit pattern layer to transmit electrical signals. In this case, the "metal layer" may be part of the barrier layer and may form a reinforcement portion together with the first recessed portion 112R. This will be described in detail below.

[0108] The first circuit pattern layer 121 may be disposed between an upper surface of the first insulating layer 111 and a lower surface of the second insulating layer 112 .

[0109] The second circuit pattern layer 122 may be disposed on an upper surface of the second insulating layer 112 .

[0110] The third circuit pattern layer 123 may be disposed on a lower surface of the first insulating layer 111 .

[0111] That is, the first circuit pattern layer 121 may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude on the upper surface of the first insulating layer 111.

[0112] The second circuit pattern layer 122 may protrude on the upper surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to an uppermost circuit pattern layer disposed on the uppermost side of the circuit board.

[0113] The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to a lowermost circuit pattern layer disposed at a lowermost side of the circuit board.

[0114] Each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may include pads and traces (or connection patterns) depending on their function. Pads may be mounting pads for devices or chips, or they may be terminal pads for connecting to an external substrate. Traces may be elongated signal routing lines connecting multiple pads. Traces are fine patterns with a width smaller than that of pads. For example, the spacing between the multiple traces in this embodiment may be in the range of 2μm to 15μm, and the line width of each trace may be in the range of 2μm to 15μm.

[0115] The circuit pattern layer can be formed from at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the circuit pattern layer can be formed from a paste or soldering paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 can be formed from copper (Cu), which has high conductivity and is relatively inexpensive.

[0116] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 25 μm. For example, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 23 μm. The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 20 μm.

[0117] If the thickness of each of the first, second, and third circuit pattern layers 121, 122, and 123 is less than 10 μm, the resistance of the circuit pattern may increase, thereby reducing signal transmission efficiency. For example, if the thickness of each of the first, second, and third circuit pattern layers 121, 122, and 123 is less than 10 μm, signal transmission loss may increase. For example, if the thickness of each of the first, second, and third circuit pattern layers 121, 122, and 123 exceeds 25 μm, the line width of the circuit pattern may increase, thereby increasing the overall volume of the circuit board.

[0118] The first circuit pattern layer 121 may include a plurality of pads.

[0119] The first circuit pattern layer 121 may include a first pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first pad 121-1 may vertically overlap the cavity 150. Therefore, the first pad 121-1 may not contact the second insulating layer 112.

[0120] The first circuit pattern layer 121 may include a second pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second pad 121-2 may not vertically overlap the cavity 150. Therefore, the second pad 121-2 may be covered by the second insulating layer 112.

[0121] At this time, at least a portion of the upper surface of the first region R1 of the first insulating layer 111 may vertically overlap the first pad 121 - 1 , and the remaining portion may not vertically overlap the first circuit pattern layer 121 and the second insulating layer 112 .

[0122] Therefore, when a desmear process is performed after forming the cavity 150, a portion of the first region R1 of the first insulating layer 111 where the first pad 121-1 is not disposed may also be etched together. In addition, when the first region R1 of the first insulating layer 111 is etched in the desmear process, glass fibers included in the first insulating layer 111 may be exposed through the cavity 150. The exposed glass fibers may cause reliability issues such as copper migration.

[0123] Therefore, the circuit board of this embodiment can form the cavity 150 in a state where the barrier layer 121BR is arranged on the first region R1 of the first insulating layer 111. The barrier layer 121BR can form a reinforcement portion including the first recessed portion 112R and the metal layer 121BP to improve the mechanical reliability and / or electrical reliability of the circuit board, while protecting the upper surface of the first region R1 of the first insulating layer 111 during the desmear process.

[0124] In addition, the barrier layer 121BR may be partially removed during the manufacturing process of the circuit board of the first embodiment. Therefore, the reinforcing portion of the circuit board of the first embodiment may include a metal layer 121BP corresponding to a portion of the barrier layer 121BR and connected to the first recessed portion 112R.

[0125] The metal layer 121BP may be arranged along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Preferably, the metal layer 121BP may be provided with a plurality of metal patterns, and each of the plurality of metal patterns may correspond to one of the plurality of first recesses of the first recessed portion 112R. In other words, a portion of the barrier layer 121BR may be removed to form the first recessed portion 112R of the reinforcement portion, while the remaining portion of the barrier layer 121BR may not be removed to form the metal layer 121BP of the reinforcement portion. In this case, the metal layer 121BP may be arranged on the same layer as the first circuit pattern layer 221 and may not be electrically connected to the first circuit pattern layer 221. Therefore, the metal layer 121BP may be referred to as a dummy pattern or barrier pattern that is not electrically connected to the first circuit pattern layer 221.

[0126] This embodiment may allow the first recess 112R to have a plurality of first recesses spaced apart from each other along the circumferential direction of the lower end of the sidewall 150S of the cavity 150 , and may allow the metal layer 121BP to have a plurality of metal patterns corresponding to each of the plurality of first recesses of the first recess 112R.

[0127] In summary, the second insulating layer 112 may have a first concave portion 112R disposed along the circumferential direction of the lower end of the sidewall 150S of the cavity 150, and the metal layer 121BP may be disposed along the circumferential direction of the first concave portion 112R. In addition, the first concave portion 112R and the metal layer 121BP may be connected to each other in the horizontal direction and may form a reinforcement portion.

[0128] For example, each of the metal layers 121BP has a plurality of metal patterns spaced apart from each other in the circumferential direction, and thus, a connection pattern 221-3 directly connecting a plurality of pads may be arranged, such as Figure 8 That is, the metal layer 121BP of this embodiment can arrange the connection pattern 221-3 while preventing the glass fibers disposed in the first insulating layer 111 from being exposed, thereby improving circuit integration and resolving electrical and / or mechanical reliability issues caused by the exposure of the glass fibers. This will be described in more detail below.

[0129] Furthermore, the first embodiment uses the barrier layer 121BR to provide the first concave portion 112R and the metal layer 121BP of the reinforcing portion, thereby minimizing deformation of the circuit board and the semiconductor package in the horizontal direction and in the vertical direction.

[0130] In addition, since this embodiment does not need to consider the damage of the barrier layer to the first insulating layer 111 during the desmear process, it may be advantageous in selecting the conditions for the desmear process. As a result, this embodiment can improve the adhesion between the second circuit pattern layer 122 arranged on the second insulating layer 112 and the second insulating layer 112. Specifically, in the process of forming a through hole corresponding to the second through electrode 132 in the second insulating layer 112, the cavity 150 can be formed together with the through hole. As a result, this embodiment may be advantageous in selecting the conditions for the desmear process, and therefore, the desmear process can be performed under conditions that can improve the adhesion with the second circuit pattern layer 122. As a result, this embodiment can improve the adhesion between the second insulating layer 112 and the second circuit pattern layer 122.

[0131] The circuit board of this embodiment may include through electrodes. The through electrodes may electrically connect circuit pattern layers arranged in different layers. The through electrodes may also be referred to as "vias."

[0132] The through-electrode penetrates the first insulating layer 111 and the second insulating layer 112 included in the circuit board, thereby electrically connecting circuit patterns arranged in different layers. In this case, the through-electrode can be formed by penetrating only one insulating layer, or differently, the through-electrode can be formed by penetrating at least two or more insulating layers.

[0133] For example, the circuit board includes a first through electrode 131. The first through electrode 131 can be formed by penetrating the first insulating layer 111. The first through electrode 131 can electrically connect the first circuit pattern layer 121 to the third circuit pattern layer 123. For example, the upper surface of the first through electrode 131 can be directly connected to the lower surface of the first circuit pattern layer 121. For example, the lower surface of the first through electrode 131 can be directly connected to the third circuit pattern layer 123.

[0134] Therefore, the first circuit pattern layer 121 and the third circuit pattern layer 123 may be electrically connected to each other through the first through-electrode 131 to transmit a signal.

[0135] At this time, the first through electrode 131 may include a first through portion 131 a connected to the first pad 121 - 1 and a second through portion connected to the second pad 121 - 2 .

[0136] Furthermore, the circuit board may include a second through-electrode 132. The second through-electrode 132 may be formed by penetrating the second insulating layer 112. The second through-electrode 132 may electrically connect the first circuit pattern layer 121 to the second circuit pattern layer 122. For example, the lower surface of the second through-electrode 132 may be directly connected to the first circuit pattern layer 121. For example, the upper surface of the second through-electrode 132 may be directly connected to the second circuit pattern layer 122. Thus, the first circuit pattern layer 121 and the second circuit pattern layer 122 may be directly electrically connected to each other via the second through-electrode 132 to transmit signals.

[0137] The first and second through electrodes 131 and 132 may be formed by forming through holes penetrating the first and second insulating layers 111 and 112 and filling the insides of the formed through holes with a conductive material.

[0138] Meanwhile, the circuit board of this embodiment may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be arranged at the outermost side of the circuit board.

[0139] For example, the first protection layer 141 may be disposed on the first outermost side or the lowermost side of the circuit board. For example, the first protection layer 141 may be disposed on the lower surface of the first insulating layer 111 .

[0140] For example, the second protection layer 142 may be disposed on the second outermost side or the uppermost side of the circuit board.For example, the second protection layer 142 may be disposed on the upper surface of the second insulating layer 112.

[0141] The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening that vertically overlaps at least one of the third circuit pattern layers 123. For example, the first protective layer 141 may include an opening that vertically overlaps a terminal pad (not shown) of the third circuit pattern layer 123, on which a conductive bonding portion for connection to an external substrate is arranged.

[0142] The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening that vertically overlaps at least one of the second circuit pattern layers 122. For example, the second protective layer 142 may include an opening that vertically overlaps a terminal pad (not shown) of the second circuit pattern layer 122, on which a conductive bonding portion for connection to a storage substrate or an interposer substrate is arranged. Furthermore, the second protective layer 142 may include a through hole (not shown) that vertically overlaps the cavity 121 of the second insulating layer 112.

[0143] Meanwhile, a process of providing the reinforcement portion including the first concave portion 112R and the metal layer 121BP according to the first embodiment is described as follows.

[0144] like Figure 2 , schematically depicting a first insulating layer 111, a second insulating layer 112, and a cavity 150 disposed in the second insulating layer 112. A first circuit pattern layer 121 may be disposed on the first insulating layer 111, the first circuit pattern layer 121 including a first pad 121-1 and a second pad 121-2 spaced apart from each other in a horizontal direction.

[0145] The first pad 121-1 may be provided in plurality and spaced apart from each other in the horizontal direction on the first region R1 of the first insulating layer 111. The second pad 121-2 may be physically spaced apart from the first pad 121-1 and may be provided in plurality and spaced apart from each other in the horizontal direction on the second region R2 of the first insulating layer 111.

[0146] The second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may be provided with a cavity 150 that extends through the upper surface and the lower surface of the second insulating layer 112. The planar shape of the cavity 150 may be a square shape, but is not limited thereto. For example, the planar shape of the cavity 150 may have a triangular shape, a circular shape, an elliptical shape, a polygonal shape, etc.

[0147] The sidewall 150S of the cavity 150 of the second insulating layer 112 may be divided into a plurality of parts. For example, when the planar shape of the cavity 150 is a square, the sidewall 150S may be divided into a first part 150S1, a second part 150S2, a third part 150S3, and a fourth part 150S4 corresponding to the square shape.

[0148] At this time, before forming the cavity 150, the barrier layer 121BR is disposed on the first insulating layer 111. The outer width of the barrier layer 121BR may be greater than the width of the cavity 150. Therefore, the barrier layer 121BR may include a first portion 121BR1 vertically overlapping the cavity 150 and a second portion 121BR2 vertically not overlapping the cavity 150.

[0149] In this case, the barrier layer 121BR has a concave portion 121BC. The concave portion 121BC is provided concavely inward from the outer surface of the barrier layer 121BR. Furthermore, a plurality of concave portions 121BC are provided, spaced apart from each other along the circumferential direction of the outer surface of the barrier layer 121BR. At least a portion of the concave portion 121BC may be provided in the first portion 121BR1 of the barrier layer 121BR, while the remaining portion may be provided in the second portion 121BR2 of the barrier layer 121BR.

[0150] The barrier layer 121BR may be a stopper for forming the cavity 150 in the second insulating layer 112. Alternatively, the barrier layer 121BR may be a protective portion for protecting the upper surface of the first insulating layer 111 in a process of desmearing the second insulating layer 112 after forming the cavity 150.

[0151] Therefore, the first region R1 of the first insulating layer 111 can be divided into multiple portions. For example, the first region R1 can include a first portion R1-1 that vertically overlaps with the first portion 121BR1 of the barrier layer 121BR, and a second portion R1-2 that vertically overlaps with the concave portion 121BC but does not vertically overlap with the first portion 121BR1 of the barrier layer 121BR. In this case, in one embodiment, the width of the concave portion 121BC or the desmear conditions can be adjusted so that the second portion R1-2 of the first insulating layer 111 is not desmeared during the desmear process. However, embodiments are not limited thereto. For example, the second portion R1-2 of the first insulating layer 111 can be desmeared during the desmear process, and thus, the second portion R1-2 of the first insulating layer 111 can be provided with a second concave portion (described later) that is vertically recessed.

[0152] In addition, if Figure 3 and Figure 4As shown, when the formation of the cavity 150 and the desmear process are completed while the barrier layer 121BR is disposed, a process of removing a portion of the barrier layer 121BR by etching is performed.

[0153] At this time, the first portion 121BR1 of the barrier layer 121BR vertically overlaps the cavity 150 and thus may be completely removed during the etching process.

[0154] Furthermore, due to over-etching during the process of removing first portion 121BR1, second portion 121BR2 of barrier layer 121BR may be partially removed. In this case, barrier layer 121BR may include concave portions 121BC. Therefore, due to the over-etching of second portion 121BR2 of barrier layer 121BR, second insulating layer 112 may include first recessed portions 112R. In this case, second portion 121BR2 of barrier layer 121BR may include multiple portions separated by concave portions 121BC along the circumferential direction of barrier layer 121BR. Consequently, first recessed portions 112R may include multiple first recessed portions spaced apart from each other along the circumferential direction of cavity 150.

[0155] In addition, during the etching process, a portion of the second portion 121BR2 of the barrier layer 121BR may not be removed. Therefore, a metal layer 121BP including a plurality of metal patterns may be provided, the plurality of metal patterns corresponding to the plurality of first recesses of the first recessed portion 112R along the circumferential direction of the first recessed portion 112R.

[0156] At this time, the first concave portion 112R is formed by etching the barrier layer 121BR and may have a shape corresponding to the shape of the barrier layer 121BR. For example, the vertical cross-sectional shape of the first concave portion 112R may have a square shape.

[0157] In summary, barrier layer 121BR includes first portion 121BR1 and second portion 121BR2, and second portion 121BR2 is divided into a plurality of portions spaced apart from one another along the circumferential direction of the outer surface of barrier layer 121BR by concave portion 121BC. Therefore, when second portion 121BR2 of barrier layer 121BR is etched, first concave portion 112R including a plurality of first concave portions and metal layer 121BP including a plurality of metal patterns may be provided corresponding to the plurality of portions of second portion 121BR2 of barrier layer 121BR.

[0158] In addition, reference Figure 4 and Figure 5In this embodiment, the first pads 121-1 and the second pads 121-2 of the first circuit pattern layer 121 may have the same layer structure. Although not shown in the figures, the second circuit pattern layer 122, the third circuit pattern layer 123, the first through-electrodes 131 and the second through-electrodes 132 may also have a layer structure corresponding to the first pads 121-1 and the second pads 121-2 described below.

[0159] The first circuit pattern layer 121 includes a plurality of layers.

[0160] The first circuit pattern layer 121 includes a first layer 121a disposed on the first insulating layer 111. The first layer 121a may refer to a seed layer for electroplating the second layer 121b of the first circuit pattern layer 121.

[0161] For example, the first layer 121 a may be a chemical copper plating layer. For example, the first layer 121 a may be a copper foil layer (Cu foil).

[0162] In one embodiment, the first layer 121 a may include only one of an electroless copper plating layer and a copper foil layer.

[0163] In another embodiment, the first layer 121 a may include both an electroless copper plating layer and a copper foil layer.

[0164] The thickness T1 of the first layer 121a may be within a range of 0.5 μm to 3.0 μm. Preferably, the thickness T1 of the first layer 121a may be within a range of 0.7 μm to 2.8 μm. More preferably, the thickness T1 of the first layer 121a may be within a range of 0.8 μm to 2.5 μm.

[0165] If the thickness T1 of the first layer 121a is less than 0.5 μm, the first layer 121a may not function as a seed layer. If the thickness T1 of the first layer 121a is less than 0.5 μm, it may be difficult to form the first layer 121a with a uniform thickness on the upper surface of the first insulating layer 111.

[0166] If the thickness T1 of the first layer 121a exceeds 3.0 μm, the time required to etch the first layer 121a may increase. If the thickness T1 of the first layer 121a exceeds 3.0 μm, the second layer 121b may deform during the etching of the first layer 121a. The deformation of the second layer 121b may mean that the difference between the width of the upper surface and the width of the lower surface of the second layer 121b increases because the side of the first layer 121a is also etched.

[0167] The second layer 121b may be disposed on the first layer 121a. The second layer 121b may be a plated layer obtained by electrolytic plating using the first layer 121a as a seed layer.

[0168] The thickness of the second layer 121b may correspond to a value obtained by subtracting the thickness T1 of the first layer 121a from the total thickness of the first circuit pattern layer 121. Since the total thickness of the first circuit pattern layer 121 has been described above, a detailed description thereof will be omitted.

[0169] Meanwhile, each of the first pad 121-1 and the second pad 121-2 of the first circuit pattern layer 121 may include a first layer 121a and a second layer 121b. At this time, the first pad 121-1 and the second pad 121-2 include the same first layer 121a and the same second layer 121b and can be distinguished according to arrangement position and function.

[0170] The width W1 of the first pad 121-1 in the horizontal direction may be within a range of 40 μm to 70 μm. Preferably, the width W1 of the first pad 121-1 in the horizontal direction may be within a range of 42 μm to 68 μm. More preferably, the width W1 of the first pad 121-1 in the horizontal direction may be within a range of 45 μm to 65 μm.

[0171] If the width W1 of the first pad 121-1 is less than 40 μm, a connection member (e.g., a semiconductor device) may not be stably mounted on the first pad 121-1. For example, if the width W1 of the first pad 121-1 is less than 40 μm, the amount of conductive adhesive material (e.g., solder) disposed on the first pad 121-1 may be reduced, and thus, the bonding strength between the first pad 121-1 and the connection member may be reduced.

[0172] If the width W1 of the first pad 121-1 is greater than 70 μm, the area of ​​the cavity 150 may increase corresponding to the width of the first pad 121-1, and thus, circuit integration may decrease or the area of ​​the circuit board and the semiconductor package may increase.

[0173] The first concave portion 112R may be provided concavely at a lower end of a sidewall 150S of the cavity 150 of the second insulating layer 112 in a direction toward the outer surface of the second insulating layer 112 (or in a direction away from the cavity). For example, the first concave portion 112R may be provided concavely in the second insulating layer 112 along a horizontal direction.

[0174] The vertical distance of the first concave portion 112R may correspond to the thickness T1 of the first layer 121a of the first pad 121-1. For example, in the manufacturing process of the first circuit pattern layer, the barrier layer 121BR may be a portion of the first layer 121a disposed entirely on the first insulating layer 111. Therefore, the thickness of the barrier layer 121BR may correspond to the thickness of the first layer 121a. Therefore, the vertical distance of the first concave portion 112R may correspond to the thickness T1 of the first layer 121a of the first pad 121-1.

[0175] The vertical distance of the first concave portion 112R may be within a range of 0.5 μm to 3.0 μm. Preferably, the vertical distance of the first concave portion 112R may be within a range of 0.7 μm to 2.8 μm. More preferably, the vertical distance of the first concave portion 112R may be within a range of 0.8 μm to 2.5 μm.

[0176] The horizontal width W2 of the first concave portion 112R may correspond to the vertical distance of the first concave portion 112R. That is, the first concave portion 112R may be formed by etching the portion of the second portion 121BR2 of the barrier layer 121BR covered by the second insulating layer 112 after forming the cavity 150. Therefore, the horizontal width W2 of the first concave portion 112R may correspond to the vertical distance of the first concave portion 112R. For example, the horizontal width W2 of the first concave portion 112R may be in the range of 0.5 μm to 3.0 μm. Preferably, the horizontal width W2 of the first concave portion 112R may be in the range of 0.7 μm to 2.8 μm. More preferably, the horizontal width W2 of the first concave portion 112R may be in the range of 0.8 μm to 2.5 μm.

[0177] However, considering process variations in the process of etching the entire first portion 121BR1 and a portion of the second portion 121BR2 of the barrier layer 121BR, the horizontal width W2 of the first recessed portion 112R may be smaller than the vertical distance of the first recessed portion 112R. For example, the horizontal width W2 of the first recessed portion 112R may be within a range of 50% to 95% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a. For example, the horizontal width W2 of the first recessed portion 112R may be within a range of 55% to 92% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a. For example, the horizontal width W2 of the first recessed portion 112R may be within a range of 60% to 90% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a.

[0178] For example, if the horizontal width W2 of the first concave portion 112R is less than 50% of the vertical distance of the first concave portion 112R or the thickness T1 of the first layer 121a, the first concave portion 112R may not be effective in preventing the warping of the circuit board and the semiconductor package. In addition, if the barrier layer 121BR is overetched, it may be difficult to form the horizontal width W2 of the first concave portion 112R to be greater than 95% of the vertical distance of the first concave portion 112R or the thickness T1 of the first layer 121a.

[0179] Meanwhile, the width W1 of the first pad 121-1 may be greater than the thickness T1 of the first layer 121a. In addition, the width W1 of the first pad 121-1 may be greater than the vertical distance of the first concave portion 112R. In addition, the width W1 of the first pad 121-1 may be greater than the horizontal width W2 of the first concave portion 112R.

[0180] For example, the width W1 of the first pad 121-1 may be 35 times or more, 40 times or more, or 45 times or more the thickness T1 of the first layer 121a. Furthermore, the width W1 of the first pad 121-1 may be 35 times or more, 40 times or more, or 45 times or more the vertical distance of the first recessed portion 112R. Furthermore, the width W1 of the first pad 121-1 may be 35 times or more, 40 times or more, or 45 times or more the horizontal width W2 of the first recessed portion 112R. That is, the thickness T1 of the first layer 121a, the vertical distance of the first recessed portion 112R, and the horizontal width W2 of the first recessed portion 112R may have corresponding values, thereby satisfying the relationship with the width W1 of the first pad 121-1. Thus, this embodiment can maximize the effect of the first recessed portion 112R while improving circuit integration and improving physical and electrical reliability.

[0181] Furthermore, the metal layer 121BP may be disposed along the first concave portion 112R. The metal layer 121BP may have a horizontal width W3 in the range of 1.0 μm to 7.0 μm. Preferably, the metal layer 121BP may have a horizontal width W3 in the range of 1.5 μm to 6.5 μm. More preferably, the metal layer 121BP may have a horizontal width W3 in the range of 2.0 μm to 6.0 μm.

[0182] The metal layer 121BP may be disposed adjacent to the first concave portion 112R, and thus can serve as a reinforcement member to prevent warping of the circuit board and the semiconductor package in a vertical direction while preventing thermal expansion or thermal contraction in a horizontal direction.

[0183] The horizontal width W3 of the metal layer 121BP can be greater than the horizontal width W2 of the first recessed portion 112R. In this case, when the first recessed portion 112R is provided, thermal expansion and / or thermal contraction can be reduced, but this may cause vertical warping. Therefore, the horizontal width W3 of the metal layer 121BP can be greater than the horizontal width W2 of the first recessed portion 112R. This can reduce thermal expansion and / or thermal contraction while minimizing vertical warping.

[0184] The metal layer 121BP is arranged along the periphery of the first recessed portion 112R. Therefore, at least a portion of the side surface of the metal layer 121BP may be exposed by the first recessed portion 112R. For example, the first recessed portion 112R may include a plurality of first recesses arranged along the circumferential direction of the inner surface of the plurality of metal patterns of the metal layer 121BP. For example, the side surface of the metal layer 121BP may overlap with the first recessed portion 112R in the horizontal direction, and the side surface of the metal layer 121BP may not be covered by the second insulating layer 112.

[0185] In addition, the metal layer 121BP includes a plurality of metal patterns spaced apart from each other along the circumferential direction of the lower end of the sidewall of the cavity 150. Figure 4 As shown, each of the plurality of metal patterns of the metal layer 121BP may have the same width W3 in a horizontal direction, but is not limited thereto.

[0186] For example, the plurality of metal patterns of the metal layer 121BP may have different widths in the horizontal direction. For example, the metal layer 121BP may have different widths in the horizontal direction along the circumferential direction of the first concave portion 112R, thereby more effectively preventing the circuit board from significantly bending in a specific direction.

[0187] For example, the second pads 121-2 may be arranged at different densities along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. For example, the density of the second pads adjacent to the first portion of the sidewall of the cavity 150 may be greater than the density of the second pads near the second portion opposite the first portion. In this case, the present embodiment may be configured such that: a metal pattern having a horizontal width of 3-1 width (third-first width) is arranged in the circumferential direction of the first portion of the sidewall of the cavity 150, and a metal pattern having a horizontal width of 3-2 width (third-second width) larger than the 3-1 width is arranged in the circumferential direction of the second portion of the sidewall of the cavity 150.

[0188] Thus, the present embodiment can be configured such that the metal density of each region is made uniform by using the metal layer 121BP, thereby further preventing the warping of the circuit board.

[0189] In addition, the plurality of metal patterns of the metal layer 121BP may be spaced apart from each other at a predetermined interval W4.

[0190] The spacing W4 between the plurality of metal patterns of the metal layer 121BP may be in a range of 2 μm to 12 μm. Preferably, the spacing W4 between the plurality of metal patterns of the metal layer 121BP may be in a range of 2.5 μm to 11.5 μm. More preferably, the spacing W4 between the plurality of metal patterns of the metal layer 121BP may be in a range of 3 μm to 11 μm.

[0191] If the spacing W4 between the plurality of metal patterns of the metal layer 121BP is less than 2 μm, warpage of the circuit board in the vertical direction may increase, thereby reducing the physical reliability of the circuit board. If the spacing W4 between the plurality of metal patterns of the metal layer 121BP is less than 2 μm, it may be difficult to arrange a connection pattern ( ) that directly connects the first pad to the second pad on the first insulating layer 111. Figure 8 For example, if the spacing W4 between the plurality of metal patterns of the metal layer 121BP is less than 2 μm, at least two of the plurality of metal patterns may be electrically connected to each other due to process errors in the process of forming the plurality of metal patterns, and an electrical short circuit problem may occur where the plurality of connection patterns 221-3 are electrically connected to each other due to the metal patterns.

[0192] Furthermore, if the spacing W4 between the plurality of metal patterns of the metal layer 121BP is greater than 12 μm, the adhesion between the first insulating layer 111 and the second insulating layer 112 may be reduced, thereby potentially causing a mechanical reliability issue in which the second insulating layer 112 is peeled off from the first insulating layer 111. Furthermore, if the spacing W4 between the plurality of metal patterns of the metal layer 121BP is greater than 12 μm, the effect of improving the mechanical reliability and / or electrical reliability of the metal layer 121BP may be insufficient.

[0193] Figure 6 is a cross-sectional view showing a circuit board according to a second embodiment.

[0194] Reference Figure 6 The circuit board 100A of the second embodiment includes a first insulating layer 111 , a second insulating layer 112 , a first circuit pattern layer 121 , a second circuit pattern layer 122 , a third circuit pattern layer 123 , a first through electrode 131 , a second through electrode 132 , a first protective layer 141 , and a second protective layer 142 .

[0195] Furthermore, the circuit board 100A of the second embodiment further includes a reinforcing portion.

[0196] At this time, the reinforcing portion in the circuit board of the first embodiment includes the first recessed portion 112R and the metal layer 121BP provided along the circumferential direction of the lower end of the sidewall 150S of the cavity 150 .

[0197] In contrast, the reinforcing portion of the circuit board 100A of the second embodiment may include only the first recessed portion 112R.

[0198] For example, in the first embodiment, a portion of the second portion 121BR2 of the barrier layer 121BR is removed to provide a reinforcing portion including the first recess 112R and the metal layer 121BP.

[0199] In contrast, in the second embodiment, the second portion 121BR2 of the barrier layer 121BR is entirely removed. As a result, the circuit board of the second embodiment may include only the first concave portion 112R formed by entirely removing the second portion 121BR2 of the barrier layer 121BR.

[0200] Figure 7 is a cross-sectional view showing a circuit board according to a third embodiment.

[0201] Reference Figure 7 The circuit board 100B of the third embodiment includes a first insulating layer 111 , a second insulating layer 112 , a first circuit pattern layer 121 , a second circuit pattern layer 122 , a third circuit pattern layer 123 , a first through electrode 131 , a second through electrode 132 , a first protective layer 141 , and a second protective layer 142 .

[0202] Furthermore, the circuit board 100B of the third embodiment further includes a reinforcing portion.

[0203] At this time, the reinforcing portion of the circuit board of the first embodiment includes the first recessed portion 112R and the metal layer 121BP provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150. In addition, the reinforcing portion of the circuit board of the second embodiment includes the first recessed portion 112R provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150.

[0204] In contrast, the reinforcing portion of the circuit board 100B of the third embodiment may include only the metal layer 121BP.

[0205] For example, in the first embodiment, a portion of the second portion 121BR2 of the barrier layer 121BR is removed to provide a reinforcement portion including the first concave portion 112R and the metal layer 121BP. In addition, in the second embodiment, the second portion 121BR2 of the barrier layer 121BR is entirely removed to provide a reinforcement member including only the first concave portion 112R.

[0206] In contrast, in the third embodiment, only the first portion 121BR1 of the barrier layer 121BR is selectively removed, while the second portion 121BR2 of the barrier layer 121BR is not removed. Thus, since the second portion 121BR2 of the barrier layer 121BR is not removed, the circuit board of the second embodiment can provide a reinforcement member including only the metal layer 121BP.

[0207] Therefore, the metal layer 121BP in the first embodiment is provided at a distance from the lower end of the side surface of the cavity 150 in the direction toward the outside of the second insulating layer 112 .

[0208] In contrast, the metal layer 121BP of the third embodiment may not be separated from the lower end of the side surface of the cavity 150 , and further, the side surface of the metal layer 121BP may be directly connected to the lower end of the side surface of the cavity 150 .

[0209] Figure 8 is a sectional view showing a circuit board according to a fourth embodiment, and Figure 9 It shows Figure 8 A diagram of a plan view of a circuit board.

[0210] Reference Figure 8 and Figure 9 The circuit board 200 of the fourth embodiment includes a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241 and a second protective layer 242.

[0211] Furthermore, the second insulating layer 212 may include a cavity 250 .

[0212] In addition, the first circuit pattern layer 221 may include a first pad 221 - 1 and a second pad 222 - 2 .

[0213] At this time, the circuit board of the fourth embodiment is different from the circuit board of the first embodiment in that the first circuit pattern layer 221 is further provided with a connection pattern 221 - 3 .

[0214] The connection pattern 221 - 3 may directly connect the first pad 221 - 1 and the second pad 221 - 2 of the first circuit pattern layer 221 .

[0215] One end of the connection pattern 221-3 may be connected to the first pad 221-1, and the other end of the connection pattern 221-3 may be connected to the second pad 221-2. The first pad 221-1 may be provided in plurality, and accordingly, the connection pattern 221-3 may also be provided in plurality corresponding to the number of the first pads 221-1.

[0216] The connection pattern 221-3 may include a first pattern region 221-31 vertically overlapping the cavity 250. An end portion of the first pattern region 221-31 of the connection pattern 221-3 may be connected to the first pad 221-1.

[0217] The connection pattern 221-3 may include a second pattern region 221-32 that does not vertically overlap the cavity 250. An end portion of the second pattern region 221-32 of the connection pattern 221-3 may be connected to the second pad 221-2.

[0218] The connection pattern 221-3 may not be connected to the reinforcement portion provided in the circumferential direction of the lower end of the sidewall 250S of the cavity 250. For example, the connection pattern 221-3 may not be connected to the metal layer 221BP of the reinforcement portion. That is, the metal layer 221BP may have a plurality of metal patterns, and the plurality of metal patterns may be arranged to avoid the area where the connection pattern 221-3 is arranged at the lower end of the sidewall 250S of the cavity 250. For example, the connection pattern 221-3 may be arranged to traverse the spaced areas between the plurality of metal patterns of the metal layer 221BP on the first insulating layer 211.

[0219] At this time, the metal layer 221BP in this embodiment has a plurality of metal patterns arranged along the circumferential direction of the lower end of the sidewall 250S of the cavity 250. Accordingly, the connection pattern 221-3 directly connecting the first pad 221-1 and the second pad 221-2 can be arranged on the first insulating layer 211 in this embodiment.

[0220] For example, according to conventional technology, when using a stopper, the metal layer is provided with a closed loop shape along the circumferential direction, making it impossible to arrange the connection pattern. For example, when arranging the connection pattern according to conventional technology, multiple adjacent connection patterns are electrically connected by the stopper having a closed loop shape, thereby causing an electrical short circuit problem.

[0221] In contrast, this embodiment changes the shape of the barrier layer 121BR so that the metal layer 221BP includes multiple metal patterns spaced apart from each other along the circumferential direction. Thus, even when the multiple connection patterns are arranged on the first insulating layer 211, this embodiment can solve the reliability problem of the electrical connection between the multiple connection patterns by using the spaced-apart metal patterns.

[0222] Furthermore, although the figure shows that the connection pattern 221-3 is not connected to the first concave portion 212R and the metal layer 221BP of the reinforcing portion, it is not limited thereto. For example, at least a portion of the connection pattern 221-3 may be connected to the first concave portion 112R and the metal layer 221BP. However, when multiple connection patterns are provided, each of the multiple connection patterns may be connected to a different first concave portion and metal pattern, thereby electrically isolating the multiple connection patterns from each other.

[0223] For example, the metal layer 221BP may include a first metal pattern and a second metal pattern spaced apart from each other, and the connection pattern 221-3 may include a first connection pattern and a second connection pattern spaced apart from each other. In this case, the first connection pattern may be connected to the first metal pattern, and the second connection pattern may be connected to the second metal pattern. However, the first metal pattern and the second metal pattern are electrically isolated from each other, and therefore, the first connection pattern and the second connection pattern may also be electrically isolated from each other.

[0224] Specifically, if Figure 9 As shown, one of the plurality of connection patterns 221-3 may overlap with one of the plurality of metal patterns of the metal layer 221BP in a vertical direction. For example, the first layer serving as a seed layer of at least one of the plurality of connection patterns 221-3 may include a portion whose width varies along the extending direction of the connection pattern 221-3. Furthermore, the portion whose width varies may correspond to a portion in which the metal pattern of the metal layer 221BP is arranged.

[0225] Furthermore, according to the fourth embodiment, in the first through electrode 231 penetrating the first insulating layer 211 , Figure 1 For example, if the connection pattern 221-3 is not provided, a first through electrode vertically overlapping the first pad 221-1 must be provided to electrically connect the first pad 221-1 to the second pad 221-2.

[0226] In contrast, the present embodiment can use the connection pattern 221-3 to directly connect the first pad 221-1 and the second pad 221-2, and thus the first through-electrode that overlaps with the first pad 221-1 in the vertical direction can be omitted. In addition, the present embodiment can shorten the length of the signal line between the first pad 221-1 and the second pad 221-2 by using the connection pattern 221-3 to directly connect the first pad 221-1 and the second pad 221-2. For example, the signal line including the connection pattern 221-3 can be shorter than the signal line including the first through-electrode. Therefore, the present embodiment can minimize signal transmission loss by shortening the signal transmission line between the first pad 221-1 and the second pad 221-2, thereby improving electrical characteristics.

[0227] Therefore, in this embodiment, a connection pattern 221-3 directly connecting the first pad 221-1 and the second pad 221-2 can be arranged on the first insulating layer 211, and a reinforcement portion including the first recessed portion 212R and the metal layer 221BP can be arranged at the same time. Therefore, in this embodiment, the first pad and the second pad can be directly connected using the connection pattern, thereby improving the circuit integration. Therefore, in this embodiment, the signal transmission line between the first pad 221-1 and the second pad 221-2 can be shortened to minimize signal transmission loss, thereby improving electrical characteristics.

[0228] Figure 10 is a sectional view showing a circuit board according to a fifth embodiment, Figure 11 yes Figure 10 A plan view of the circuit board, and Figure 12 yes Figure 10 An enlarged view of a portion of a circuit board.

[0229] Reference Figures 10 to 12 The circuit board 300 of the fifth embodiment includes a first insulating layer 311, a second insulating layer 312, a first circuit pattern layer 321, a second circuit pattern layer 322, a third circuit pattern layer 323, a first through electrode 331, a second through electrode 332, a first protective layer 341 and a second protective layer 342.

[0230] Furthermore, the second insulating layer 312 may include a cavity 350 .

[0231] In addition, the first circuit pattern layer 321 may include a first pad 321 - 1 , a second pad 322 - 2 , and a connection pattern 321 - 3 .

[0232] At this time, the circuit board of the fifth embodiment is different from the circuit board of the fourth embodiment in that a second recessed portion 311R is further provided on the upper surface of the first insulating layer 311 .

[0233] The second concave portion 311R may be provided on the upper surface of the first insulating layer 311 .

[0234] That is, the circuit board of the fifth embodiment may include a first concave portion 312R provided on the second insulating layer 312 and a second concave portion 311R provided on the first insulating layer 311 .

[0235] Each of the first recessed portion 312R and the second recessed portion 311R may be connected to a lower end of the sidewall 350S of the cavity 350 .

[0236] For example, a portion of the lower end of the sidewall 350S of the cavity 350 may be connected to the first recess 312R, and the remaining portion of the lower end of the sidewall 350S of the cavity 350 may be connected to the second recess 311R.

[0237] At this time, as described in the previous embodiment, the first concave portion 312R includes a plurality of first concave portions concavely provided in the second insulating layer 312 along the horizontal direction.

[0238] In addition, the second concave portion 311R includes a second concave portion concavely provided in a vertical direction on the upper surface of the first insulating layer 311 .

[0239] The second recessed portion 311R may be provided in an edge region of the first region R1 of the first insulating layer 311. For example, the second recessed portion 311R may be provided in an edge region of the bottom surface of the cavity 350. That is, the second recessed portion 311R may be provided on the upper surface of the first insulating layer 311 connected to the lower end of the sidewall 350S of the cavity 350. The second recessed portion 311R may be provided in a recessed manner from the upper surface of the first insulating layer 311 toward the lower surface of the first insulating layer 311.

[0240] The second concave portion 311R may be provided on the upper surface of the first insulating layer 311 through a desmear process performed after forming the cavity 350 in the second insulating layer 312 .

[0241] For example, the barrier layer 121BR has a concave portion 121BC, and at least a portion of the concave portion 121BC vertically overlaps the cavity 350. Therefore, when the desmear process is performed with the barrier layer 121BR disposed, a portion of the upper surface of the first insulating layer 311 may be exposed to the outside through the concave portion 121BC. In this case, the present embodiment can prevent the formation of the second concave portion 311R during the desmear process by adjusting the width of the concave portion 121BC, or can form the second concave portion 311R on the upper surface of the first insulating layer 311. The second concave portion 311R may be formed corresponding to the concave portion 121BC.

[0242] Therefore, according to the present embodiment, the second insulating layer 312 may be provided with a first concave portion 312R in a horizontal direction, and the first insulating layer 311 may be provided with a second concave portion 311R in a vertical direction.

[0243] Therefore, this embodiment can effectively disperse the stress acting on the first insulating layer 31 and the second insulating layer 32 , thereby improving the warping characteristics of the circuit board.

[0244] For example, the second recessed portion 311R may have a function of increasing the surface area of ​​the upper surface of the first insulating layer 311. Therefore, the second recessed portion 311R may reduce horizontal expansion of the circuit board due to thermal stress occurring in a manufacturing environment or a usage environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and a semiconductor package including the circuit board.

[0245] Furthermore, the first recessed portion 312R can reduce the area of ​​the interface between the first insulating layer 311 and the second insulating layer 312, thereby dispersing the stress acting on the second insulating layer 312. Therefore, the first recessed portion 312R can reduce the phenomenon of the circuit board being bent in a specific direction (for example, the phenomenon of both ends of the circuit board being bent upward or the phenomenon of both ends of the circuit board being bent downward).

[0246] At this time, the first recessed portions 312R and the second recessed portions 311R may be alternately disposed along the circumferential direction of the lower end of the sidewall 350S of the cavity 350 .

[0247] For example, the first concave portion 312R includes a plurality of first concave portions, and the second concave portion 311R includes a plurality of second concave portions. In this case, the plurality of first concave portions and the plurality of second concave portions may be alternately arranged along the circumferential direction of the lower end of the sidewall 350S of the cavity 350. This is because the second concave portion 311R corresponds to the concave portion 121BC of the barrier layer 121BR, while the first concave portion 312R corresponds to the region of the second portion 121BR2 of the barrier layer 121BR excluding the concave portion 121BC.

[0248] Furthermore, the vertical distance T2 of the second concave portion 311R may be within a range of 0.1 μm to 6.0 μm. Preferably, the vertical distance T2 of the second concave portion 311R may be within a range of 0.5 μm to 5.5 μm. More preferably, the vertical distance T2 of the second concave portion 311R may be within a range of 1.0 μm to 5 μm.

[0249] The vertical distance T2 of the second recessed portion 311R may refer to the vertical distance from the uppermost end of the upper surface of the first insulating layer 311 to the lowermost end of the bottom surface of the second recessed portion 311R. If the vertical distance T2 of the second recessed portion 311R is less than 0.1 μm, the effect of the second recessed portion 311R in reducing thermal expansion and / or thermal contraction of the circuit board may be insufficient. In addition, if the vertical distance T2 of the second recessed portion 311R is less than 0.1 μm, the adhesion between the second insulating layer 312 and the second circuit pattern layer 322 may be reduced. For example, the second recessed portion 311R can be formed during a desmear process to provide a certain degree of surface roughness to the upper surface of the second insulating layer 312, thereby increasing the adhesion between the second insulating layer 312 and the second circuit pattern layer 322. At this time, the vertical distance T2 of the second concave portion 311R being less than 0.1 μm may mean that a certain degree or more of surface roughness is not provided to the second insulating layer 312 , and thus, adhesion between the second insulating layer 312 and the second circuit pattern layer 322 may be reduced.

[0250] If the vertical distance T2 of the second recessed portion 311R exceeds 6.0 μm, the surface roughness of the second insulating layer 312 may increase accordingly, and the surface roughness of the second circuit pattern layer 322 may increase accordingly. In addition, if the surface roughness of the second circuit pattern layer 322 increases, the transmission loss of the signal transmitted through the second circuit pattern layer 322 may increase due to the skin effect. In addition, if the vertical distance T2 of the second recessed portion 311R exceeds 6.0 μm, the glass fibers 311GF disposed in the first insulating layer 311 may be exposed through the second recessed portion 311R, and the exposed glass fibers 311GF may reduce the mechanical and / or electrical reliability of the circuit board and the semiconductor package.

[0251] For example, the vertical distance T2 of the second recessed portion 311R may be determined based on the position of the glass fiber 311GF disposed in the first insulating layer 311 .

[0252] For example, the vertical distance T3 from the upper surface of the first insulating layer 311 to the uppermost end of the glass fiber 311GF may be greater than the vertical distance T2 of the second recessed portion 311R. For example, the vertical distance T3 from the upper surface of the first insulating layer 311 to the uppermost end of the glass fiber 311GF may be within a range of 3 μm to 10 μm. Preferably, the vertical distance T3 may be within a range of 3.5 μm to 9.5 μm. More preferably, the vertical distance T3 may be within a range of 4.0 μm to 9.0 μm.

[0253] If vertical distance T3 is less than 3.0 μm, glass fibers 311GF disposed in first insulating layer 311 may be exposed to the outside due to various tolerances generated during the circuit board manufacturing process, which may cause reliability issues. Furthermore, if vertical distance T3 is greater than 10 μm, the amount of glass fibers 311GF disposed in first insulating layer 311 may decrease, or the thickness of first insulating layer 311 may increase, which may degrade the warpage characteristics of the circuit board and semiconductor package, or increase the volume of the circuit board and semiconductor package.

[0254] For example, the vertical distance T2 of the second recessed portion 311R may be within a range of 4% to 70% of the vertical distance T3 of the glass fiber 311GF. Preferably, the vertical distance T2 of the second recessed portion 311R may be within a range of 8% to 65% of the vertical distance T3 of the glass fiber 311GF. More preferably, the vertical distance T2 of the second recessed portion 311R may be within a range of 10% to 60% of the vertical distance T3 of the glass fiber 311GF.

[0255] A width W5 of the second concave portion 311R in the horizontal direction may correspond to a pitch between the plurality of first concave portions of the first concave portion 312R and / or a pitch between the plurality of metal patterns of the metal layer 321BP, but is not limited thereto.

[0256] At least one of the plurality of second recesses of the second recessed portion 311R may be connected to the connection pattern 321 - 3 .

[0257] For example, the second recessed portion 311R may include a 2-1st recessed portion 311R1 disposed between the first recessed portions and not connected to the connection pattern 321-3. Furthermore, the second recessed portion 311R may include a 2-2nd recessed portion 311R2 connected to the connection pattern 321-3.

[0258] For example, the connection pattern 321-3 may include a first pattern region 321-31 vertically overlapping the cavity 350 and a second pattern region 321-32 vertically not overlapping the cavity 350. In addition, the 2-2nd recess 311R2 may be connected to at least a portion of a side surface of the second pattern region 321-32 of the connection pattern 321-3.

[0259] Thus, since the 2-2 recess 311R2 of the second recess 311R is connected to the connection pattern 321 - 3 , this embodiment can more effectively solve the electrical reliability problem of electrically connecting a plurality of connection patterns due to process errors.

[0260] Figure 131 is a diagram showing the upper surface of the first region of the first insulating layer according to the present embodiment and the comparative example.

[0261] refer to Figure 13 (a), in the comparative example, the desmear process is performed in a state where the barrier layer is not provided, and thus the glass fiber 311GF may be exposed through the upper surface of the first region R1 of the first insulating layer 311 .

[0262] In comparison, reference Figure 13 (b) In this embodiment, the desmear process is performed in a state where the barrier layer is provided, and therefore, the glass fibers 311GF are not exposed through the upper surface of the first region R1 of the first insulating layer 311. For example, only the filler provided in the first insulating layer 311 may be exposed on the upper surface of the first region R1 of the first insulating layer 311.

[0263] Figure 14 is a cross-sectional view showing the semiconductor package according to the present embodiment.

[0264] refer to Figure 14 , the semiconductor package of this embodiment may include Figure 8 However, the present embodiment is not limited thereto, and the semiconductor package may include Figures 1 to 7 as well as Figures 10 to 12 Any of the circuit boards in the.

[0265] The semiconductor package may include a bonding member 410 disposed on the first pad 221 - 1 , and a connecting member 420 disposed on the bonding member 410 .

[0266] The connection member 420 may be any one of a semiconductor device, an interposer, a package substrate, an inorganic bridge, or an organic bridge.

[0267] Meanwhile, the molding member 430 may be disposed in the cavity 250. The molding member 430 may be disposed by molding the connection member 420 within the cavity 250.

[0268] In addition, the molding member 430 may be provided to fill the first recessed portion 212R. Figure 10 In the case of a circuit board, the molding member may be configured to further fill the second recess 311R.

[0269] The first recessed portion 212R can increase the contact area between the molding member 430 and the first and second insulating layers 211 and 212. For example, the first recessed portion 212R can serve as an anchor point to improve the bonding strength between the molding member 430 and the first and second insulating layers 211 and 212. At least a portion of the molding member 430 can be connected to the metal pattern of the metal layer 221BP disposed along the first recessed portion 212R. Thus, the present embodiment can maximize the heat dissipation effect through the metal layer 221BP and the molding member 430.

[0270] Furthermore, the molding member 430 may have a low dielectric constant to improve heat dissipation. For example, the dielectric constant (Dk) of the molding member 430 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding member 430 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding member 430 may be 0.8 to 5. Therefore, in this embodiment, the molding member 430 has a low dielectric constant to improve the heat dissipation characteristics of the connecting member.

[0271] This embodiment may include a first insulating layer and a second insulating layer disposed on the first insulating layer and including a cavity. A metal layer is disposed circumferentially along a lower end of a sidewall of the cavity and disposed between the first insulating layer and the second insulating layer. The metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0272] The multiple metal patterns can serve as reinforcement members to increase the rigidity of the circuit board. For example, the multiple metal patterns can disperse or reduce stress acting on the circuit board, thereby improving the circuit board's warping characteristics. Furthermore, the multiple metal patterns can reduce horizontal expansion of the circuit board caused by thermal stress in the circuit board's manufacturing or usage environment, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package incorporating the circuit board.

[0273] In addition, this embodiment further includes a connection pattern arranged on the first insulating layer and directly connecting the first pad and the second pad. The connection pattern can be arranged to cross between the multiple metal patterns. In this case, multiple connection patterns can be provided. In this case, the multiple metal patterns are arranged spaced apart from each other in the circumferential direction, so that the multiple connection patterns are not electrically connected to each other on the first insulating layer. Therefore, this embodiment can use the connection pattern to directly connect the first pad and the second pad, thereby omitting the first through-electrode that overlaps with the first pad in the vertical direction. In addition, this embodiment can shorten the length of the signal line between the first pad and the second pad by using the connection pattern to directly connect the first pad and the second pad. For example, the signal line including the connection pattern can be shorter than the signal line including the first through-electrode. Therefore, this embodiment can minimize signal transmission loss by shortening the signal transmission line between the first pad and the second pad, thereby improving electrical characteristics. In addition, this embodiment can improve circuit integration by arranging a connection pattern that directly connects the first pad and the second pad.

[0274] At the same time, the second insulating layer of this embodiment may include a first recessed portion disposed between the plurality of metal patterns and the lower end of the sidewall of the cavity. The first recessed portion can disperse or reduce stress acting on the first and second insulating layers, thereby improving the warping characteristics of the circuit board. For example, the first recessed portion can reduce the area of ​​the interface between the first and second insulating layers, thereby dispersing the stress acting on the second insulating layer. Therefore, the first recessed portion can reduce the phenomenon of the circuit board bending in a specific direction (for example, the phenomenon of the two ends of the circuit board bending upward or the phenomenon of the two ends of the circuit board bending downward).

[0275] Furthermore, the first insulating layer of this embodiment may include a second recessed portion arranged circumferentially. The second recessed portion may be arranged vertically, concavely from the upper surface to the lower surface of the first insulating layer. In this case, the first recessed portion is a recessed portion arranged horizontally in the second insulating layer, and the second recessed portion is a recessed portion arranged vertically in the first insulating layer. Therefore, this embodiment can improve the warpage characteristics of the circuit board by using the first and second recessed portions to disperse or reduce stress acting on the circuit board.

[0276] For example, the first and second recessed portions can mitigate horizontal expansion of the circuit board due to thermal stress in the circuit board's manufacturing or usage environment, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package including the circuit board. In this case, the second insulating layer can include an insulating material different from that of the first insulating layer. Therefore, the first and second insulating layers can have different coefficients of thermal expansion, which may cause warping of the circuit board in the vertical direction. Therefore, the first and second recessed portions can prevent the circuit board from bending in a specific direction (for example, bending upward at both ends of the circuit board or bending downward at both ends of the circuit board).

[0277] Therefore, this embodiment can minimize the degree of vertical warping of the circuit board and semiconductor package, or the degree of horizontal expansion or contraction, thereby improving the mechanical and / or physical reliability of the circuit board and semiconductor package. In addition, this embodiment can enable the semiconductor device arranged on the circuit board to operate stably, thereby improving the operating characteristics of the electronic products and / or servers using the semiconductor package.

[0278] Furthermore, the multiple metal patterns in this embodiment can have different horizontal widths along the circumferential direction. For example, in an area with relatively low metal density, the horizontal width of the metal pattern can be greater than in an area with relatively high metal density. Therefore, this embodiment can minimize circuit board warpage caused by differences in metal density, thereby further improving the physical and / or electrical reliability of the circuit board and semiconductor package.

[0279] Furthermore, this embodiment can perform a desmearing process on the second insulating layer after the cavity is formed, with the barrier layer in place. This prevents exposure of the glass fibers of the first insulating layer and further addresses the physical and / or electrical reliability issues caused thereby. Furthermore, this embodiment can determine desmearing process conditions without regard to glass fiber exposure. For example, this embodiment can determine desmearing process conditions to optimally improve adhesion between the second insulating layer and the second circuit pattern layer, thereby improving adhesion between the second insulating layer and the second circuit pattern layer without exposing the reinforcing member.

[0280] At the same time, the desmear process of this embodiment can be performed while a through-hole and a cavity are formed that penetrate the second insulating layer. Therefore, during the desmear process, the inner wall of the through-hole and the inner wall of the cavity can be surface treated together. This can improve the adhesion between the second through-electrode arranged in the through-hole and the second insulating layer. In addition, this embodiment can improve the adhesion between the molding member arranged in the cavity and the second insulating layer.

[0281] Furthermore, the molding member may be configured to fill at least one of the first concave portion and the second concave portion. Therefore, this embodiment can further improve the bonding strength between the molding member and the circuit board.

[0282] Next, a method of manufacturing a circuit board according to one embodiment will be described.

[0283] Figures 15 to 28 FIG. 1 is a diagram illustrating a method for manufacturing a circuit board according to an embodiment in order of processes.

[0284] refer to Figure 15 In this embodiment, an insulating material used as a base for manufacturing a circuit board is prepared. For example, in this embodiment, an insulating member including a first insulating layer 211 and a metal member (not shown) located on the first insulating layer 211 may be prepared.

[0285] refer to Figure 16 In this embodiment, a process of forming a first through hole TH1 penetrating the first insulating layer 211 may be performed.

[0286] refer to Figure 17 In this embodiment, a process of forming a circuit pattern layer and first layers 221a and 223a of through-electrodes along the upper and lower surfaces of the first insulating layer 211 and the inner wall of the first through hole TH1 can be performed. The first layers 221a and 223a can serve as seed layers and can be formed by an electroless plating process.

[0287] refer to Figure 18 In this embodiment, a process of forming a plating layer by performing electrolytic plating on the first layers 221a and 223a as seed layers may be performed. The plating layer may include the second layer 221b of the first circuit pattern layer 221, the second metal layer 223b of the third circuit pattern layer 223, and the first through electrode 231. In addition, the first circuit pattern layer 221 may include a first pad 221-1, a second pad 221-2, and a connection pattern 221-3.

[0288] refer to Figure 19 In this embodiment, a process of removing a portion of the first layers 221a and 223a may be performed. For example, in this embodiment, the first layers 221a and 223a may be removed by etching except for the portion vertically overlapping the cavity 250 and serving as a barrier layer.

[0289] That is, in a general circuit board manufacturing process, the entire region of the first layer 221a of the first circuit pattern layer 221 that does not vertically overlap with the second layer 221b may be removed. However, in this embodiment, the portion of the first layer 221a that does not vertically overlap with the second layer 221b (e.g., the region where the cavity is to be formed) may not be removed.

[0290] For example, Figure 20 As shown, a portion of the first layer 221a of the first circuit pattern layer 221 may serve as a barrier layer 221BR. An outer surface of the barrier layer 221BR may be provided with a plurality of concave portions 221BC spaced apart from each other.

[0291] refer to Figure 21 In this embodiment, a process of stacking the second insulating layer 212 on the first insulating layer 211 may be performed.

[0292] refer to Figure 22 and Figure 23 In this embodiment, the cavity 250 and the second through hole TH2 can be formed by processing the second insulating layer 212. The second insulating layer 212 may include a photocurable resin, and thus the cavity 250 and the second through hole TH2 can be formed by a photolithography process including an exposure and development process. The barrier layer 221BR may include an overlapping portion 221BR1 that vertically overlaps with the cavity 250, and a non-overlapping portion 221BR2 that does not vertically overlap with the cavity 250 and is covered by the second insulating layer 212.

[0293] refer to Figure 24 In this embodiment, a desmear process may be performed after forming the cavity 250 and the second through hole TH2. Thus, the inner wall of the cavity 250, the inner wall of the second through hole TH2, and the upper surface of the second insulating layer 212 may be desmeared to have a certain level of surface roughness.

[0294] At this time, Figure 10 In the embodiment, at least a portion of the upper surface of the first insulating layer 211 vertically overlapping the cavity 350 (the region vertically overlapping the concave portion) is not covered by the barrier layer 221BR. Therefore, the corresponding portion can also be desmeared. Therefore, a second concave portion 311R can be additionally provided.

[0295] Next, refer to Figure 25 and Figure 26 In this embodiment, the portion of the barrier layer 221BR that does not vertically overlap with the first pad 121 - 1 and the connection pattern 121 - 3 may be removed.

[0296] At this time, the overlapping portion 221BR1 of the barrier layer 221BR can be completely removed. However, the non-overlapping portion 221BR2 of the barrier layer 221BR can be partially removed. For example, the portion of the non-overlapping portion 221BR2 of the barrier layer 221BR adjacent to the overlapping portion 221BR1 can be removed by overetching. As a result, a first recessed portion 212R can be formed in the second insulating layer 212, which is the region removed by overetching the non-overlapping portion 221BR1.

[0297] In addition, a portion of the non-overlapping portion 221BR2 of the barrier layer 221BR may not be removed. Therefore, a metal layer 221BP corresponding to the non-overlapping portion that is not removed may be formed along the first concave portion 212R between the first and second insulating layers 211 and 212 .

[0298] Next, refer to Figure 27 , this embodiment may perform a process of forming the second through electrode 232 and the second circuit pattern layer 222 .

[0299] In addition, reference Figure 28 In this embodiment, a process of forming a first protective layer 241 on the second insulating layer 212 and a process of forming a second protective layer 242 below the first insulating layer 211 may be performed.

[0300] On the other hand, when the circuit board having the above-mentioned characteristics of the present invention is used in IT equipment or household appliances such as smart phones, server computers, and televisions, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the characteristics of the present invention performs the semiconductor packaging function, the circuit board can safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical open circuit of terminals that supply power to the semiconductor chip. In addition, when responsible for the signal transmission function, the noise problem can be solved. Thus, the circuit board having the above-mentioned characteristics of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0301] When a circuit board having the aforementioned characteristics of the present invention is used in transportation equipment such as vehicles, it can resolve issues related to signal distortion transmitted to the transportation equipment. Alternatively, it can further enhance the safety of the transportation equipment by safely protecting the semiconductor chip controlling the transportation equipment from external influences and addressing issues such as leakage current, electrical shorts between terminals, or electrical opens in terminals supplying power to the semiconductor chip. Consequently, the transportation equipment and the circuit board incorporating the present invention can achieve functional integration or technical linkage.

[0302] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures, and effects shown in each of these embodiments can even be combined or modified with respect to other embodiments by a person skilled in the art to which the embodiments belong. Therefore, it should be understood that the contents related to such combinations and such modifications are included within the scope of the embodiments.

[0303] The above description focuses on the embodiments, but it is illustrative only and does not limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not shown above can be made without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, it should be understood that the differences associated with these variations and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: a first insulating layer; a second insulating layer disposed on the second insulating layer and comprising a cavity; as well as a circuit pattern layer disposed between the first insulating layer and the second insulating layer, Wherein, the circuit pattern layer includes: a first pad, wherein the first pad overlaps the cavity along a vertical direction; a second pad that overlaps the first pad in a horizontal direction and does not overlap the cavity in a vertical direction; and A connection pattern is provided, wherein the connection pattern is connected between the first pad and the second pad.

2. The circuit board according to claim 1, further comprising: a metal layer disposed between the first insulating layer and the second insulating layer, The metal layer includes a plurality of metal patterns, which are arranged along a circumferential direction of a lower end of a sidewall of the cavity and are spaced apart from each other.

3. The circuit board according to claim 1, wherein The connection pattern includes: a first portion vertically overlapping the cavity and not covered by the second insulating layer; and The second portion does not overlap with the cavity in a vertical direction and is covered by the second insulating layer.

4. The circuit board according to claim 2, wherein: The connection pattern is disposed on the first insulating layer to traverse between the plurality of metal patterns.

5. The circuit board according to claim 4, wherein The connection pattern is not connected to any of the plurality of metal patterns.

6. The circuit board according to claim 4, wherein The connection pattern is provided with a plurality of connection patterns, and At least one connection pattern among the plurality of connection patterns is connected to at least one metal pattern among the plurality of metal patterns.

7. The circuit board according to claim 2, wherein: The plurality of metal patterns have different widths in the horizontal direction along the circumferential direction.

8. The circuit board according to claim 2, wherein The plurality of metal patterns are spaced apart at intervals in a range of 2 μm to 12 μm along the circumferential direction.

9. The circuit board according to claim 2, wherein: Each of the first pad and the second pad includes: a first layer disposed on the first insulating layer; and a second layer disposed on the first layer, and The thickness of each of the plurality of metal patterns corresponds to the thickness of the second layer of the first pad and the second pad.

10. The circuit board according to any one of claims 1 to 9, wherein The second insulating layer includes a first concave portion that is concavely disposed from a lower end of a sidewall of the cavity toward an outer surface of the second insulating layer in a horizontal direction.

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