Packaging structure with airtight cavity and packaging method thereof

Abstract

The invention provides a packaging structure with airtight cavities and a packaging method thereof, and the method comprises the steps: firstly forming oxide layers of corresponding semiconductor materials on the surfaces of a first semiconductor wafer and a second semiconductor wafer in a process of forming a second cavity, and then carrying out the permanent bonding of the two oxide layers to form an oxide bonding layer, an airtight cavity bottom surface with very low roughness can be obtained; in addition, the oxide bonding layer is used as an etching barrier layer, so that the formation of the first cavity with any aperture and depth can be realized; furthermore, the oxide layer is an oxide formed based on a semiconductor material of a corresponding semiconductor wafer, lattice mismatch and thermal mismatch between the oxide layer and the semiconductor wafer are relatively low, the problems of cracking and warping are not easy to generate, and the bonding quality of the bonded oxide bonding layer is high; and finally, the packaged finished product is small in size and light in weight, the packaging period is greatly shortened, the packaging cost is greatly reduced, a wafer-level packaging part process is compatible with an existing silicon process, and the method is suitable for large-scale production and application.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging structure with an airtight cavity and a packaging method thereof. Background Art

[0002] Uncooled infrared focal plane detectors (IFPDs) operate at room temperature and offer numerous advantages, including fast startup, low power consumption, compact size, light weight, long life, and low cost. Their price-performance ratio significantly surpasses that of cooled detectors, leading to their application in numerous fields, including security, industry, medicine, power generation, construction, and automotive. Regarding RF microsystems, the development of modern military electronic equipment is driving demands for miniaturization, multi-functionality, and reconfigurability of transceiver and processing subsystems, increasing the functional complexity of micromodules. The development of modern military electronic equipment is driving demands for miniaturization, multi-functionality, and reconfigurability of transceiver and processing subsystems, increasing the functional complexity of micromodules.

[0003] Chip packaging is a very important step in the production process of integrated circuit chips. For uncooled infrared detectors, the detector chip needs to work in a high vacuum environment. Currently, metal or ceramic tube packaging is mainly used. The overall size, weight, and power consumption are relatively high, which cannot meet the market's miniaturized application needs. In addition, the packaging cost is high and the production efficiency is low, which is not suitable for large-scale, low-cost production requirements. Due to the high transmittance requirements of uncooled infrared detectors, the roughness and airtightness requirements of the light-emitting surface of the airtight cavity are extremely stringent. However, the bottom roughness of the airtight cavity prepared by the existing deep silicon etching technology is high, for example, the roughness is greater than 100nm, which does not meet the product requirements of high transmittance and high uniformity of uncooled infrared detectors, such as for the 8μm to 14μm band.

[0004] In terms of radio frequency microsystems, it is difficult to meet the circuit complexity and high integration density requirements through three-dimensional chip-to-chip stacking integration and setting an electromagnetic shielding cap outside the integrated structure. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a packaging structure with an airtight cavity and a packaging method thereof, which are used to solve the problems in the prior art of packaging structures with airtight cavities, such as uncooled infrared detectors, which have relatively high packaging size, weight and power consumption, high packaging cost and low production efficiency when packaged with metal or ceramic tube shells, and the roughness of the bottom of the airtight cavity prepared by deep silicon etching technology is high and does not meet product requirements.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a packaging method for a packaging structure having an airtight cavity, the packaging method comprising:

[0007] providing a first semiconductor wafer and a second semiconductor wafer having opposing first and second sides;

[0008] forming a first oxide layer on a first side surface of the first semiconductor wafer, and forming a second oxide layer on a first side surface of the second semiconductor wafer; wherein a material of the first oxide layer is an oxide based on the semiconductor material of the first semiconductor wafer, and a material of the second oxide layer is an oxide based on the semiconductor material of the second semiconductor wafer;

[0009] Permanently bonding the first oxide layer to the second oxide layer to achieve permanent bonding of the first semiconductor wafer to the second semiconductor wafer;

[0010] Thinning the first semiconductor wafer from its second side surface to a desired thickness;

[0011] performing dry etching downward from a predetermined area on the second side surface of the first semiconductor wafer to form a first cavity penetrating the first semiconductor wafer;

[0012] removing the first oxide layer and the second oxide layer exposed in the first cavity by wet etching to form a second cavity;

[0013] forming a bonding metal pad on the second side of the first semiconductor wafer outside the second cavity;

[0014] A device structure having a bonding metal layer formed on its surface is provided, and the bonding metal layer is bonded to the bonding metal pad, so that an airtight cavity is formed between the second cavity and the device structure.

[0015] Optionally, the first semiconductor wafer is a silicon wafer, the second semiconductor wafer is a silicon wafer, the first oxide layer is a silicon oxide layer, and the second oxide layer is a silicon oxide layer.

[0016] Furthermore, the first semiconductor wafer is etched using a Bosch process to form the first cavity; and a wet etching solution used for wet etching to form the second cavity includes hydrofluoric acid.

[0017] Optionally, the bonding metal pad is formed by an evaporation process or an electroplating process.

[0018] Optionally, the bonding metal layer and the bonding metal pad are bonded in a chip-to-chip bonding or chip-to-wafer bonding or wafer-to-wafer bonding.

[0019] Optionally, the method of forming the first cavity penetrating the first semiconductor wafer includes:

[0020] forming a hard mask layer on the second side surface of the first semiconductor wafer;

[0021] forming a photoresist layer on the surface of the hard mask layer and performing patterning;

[0022] dry-etching the hard mask layer based on the patterned photoresist layer and then removing the patterned photoresist layer to obtain the patterned hard mask layer;

[0023] The first semiconductor wafer is dry-etched based on the patterned hard mask layer, and then the patterned hard mask layer is removed to obtain the first cavity.

[0024] Optionally, after forming the second cavity and before forming the bonding metal pad, the method further includes the steps of sequentially forming an insulating dielectric layer and an electromagnetic shielding layer on the bottom wall and side walls of the second cavity and the second side surface of the first semiconductor wafer.

[0025] Furthermore, the material of the insulating dielectric layer is an oxide based on the semiconductor material of the first semiconductor wafer, and the insulating dielectric layer is formed by a CVD process; the electromagnetic shielding layer is a stack of a tantalum material layer and a copper material layer, and the electromagnetic shielding layer is formed by a PVD process.

[0026] Optionally, before permanently bonding the first oxide layer and the second oxide layer, a step of performing CMP flattening on the bonding surfaces of the first oxide layer and the second oxide layer is further included.

[0027] The present invention also provides a packaging structure with an airtight cavity, wherein the packaging structure comprises, in sequence along the thickness direction: a device structure, a first semiconductor layer, a first oxide layer, a second oxide layer, an airtight cavity, and a second semiconductor layer; wherein,

[0028] The device structure is bonded to the bonding metal pad on the first semiconductor layer via a bonding metal layer on the surface of the device structure;

[0029] The first semiconductor layer and the second semiconductor layer are permanently bonded together through the first oxide layer and the second oxide layer;

[0030] The airtight cavity penetrates the first semiconductor layer, the first oxide layer, and the second oxide layer and exposes the surface of the second semiconductor layer, and the airtight cavity is sealed between the device structure and the second semiconductor layer;

[0031] The surface roughness of the second semiconductor layer is less than 5 nm.

[0032] Optionally, the chip arranged on the device structure is an uncooled infrared detector chip.

[0033] Optionally, the chip arranged on the device structure is a radio frequency microsystem chip; the bottom wall and side walls of the airtight cavity and the surface of the first semiconductor layer are sequentially provided with an insulating dielectric layer and an electromagnetic shielding layer.

[0034] Furthermore, the insulating dielectric layer is a silicon oxide layer with a thickness of 0.3 μm to 0.9 μm; the electromagnetic shielding layer is a stack of a tantalum material layer and a copper material layer, and the thickness of the tantalum material layer is The thickness of the copper material layer is

[0035] Optionally, the first semiconductor layer is a silicon layer, the second semiconductor layer is a silicon layer, the first oxide layer is a silicon oxide layer, and the second oxide layer is a silicon oxide layer; the thickness of the first semiconductor layer is 100 μm to 500 μm, the total thickness of the first oxide layer and the second oxide layer is 0.5 μm to 3 μm, and the diameter of the airtight cavity is not greater than 20 mm.

[0036] Optionally, the material of the bonding metal pad includes at least one of tin, lead, aluminum and gold, and the thickness of the bonding metal pad is 2 μm to 6 μm.

[0037] As described above, in the packaging structure with an airtight cavity and the packaging method thereof of the present invention, in the process of forming the second cavity, first, oxide layers of corresponding semiconductor materials are formed on the surfaces of the first semiconductor wafer and the second semiconductor wafer, and then the two oxide layers are permanently bonded to form an oxide bonding layer, thereby achieving the second cavity by dry etching the first semiconductor wafer combined with wet etching of the oxide bonding layer. Since the oxide of the corresponding semiconductor material has a high etching selectivity with the corresponding semiconductor material compared to dry etching, when the oxide of the semiconductor material is wet-etched to expose the surface of the second semiconductor wafer thereunder, little damage is caused to the surface of the second semiconductor wafer, thereby obtaining an airtight cavity bottom surface with very low roughness. In addition, when dry etching the first semiconductor wafer, the oxide bonding layer serves as an etching barrier layer, thereby enabling the formation of a first cavity of arbitrary diameter and arbitrary depth, especially for the preparation of a first cavity of large diameter and large depth; furthermore, since the oxide layer formed on the semiconductor wafer is an oxide formed based on the semiconductor material of the corresponding semiconductor wafer, the lattice mismatch and thermal mismatch between the two are low, and cracking and warping problems are not easily generated, and the bonding quality of the oxide bonding layer after bonding is high; finally, the device structure is encapsulated in a single airtight cavity formed by the semiconductor material, and the finished product after encapsulation is small in size and light in weight, and the packaging cycle and cost are greatly reduced, and some processes of the wafer-level packaging are compatible with existing silicon processes, making it suitable for large-scale production applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 10 and Figures 12 to 16 Shown are cross-sectional structural schematic diagrams of various steps in a packaging method for a packaging structure with an airtight cavity according to a first embodiment of the present invention.

[0039] Figure 11 Display as Figure 12 SEM image of a certain area.

[0040] Figure 17 and Figure 18 Schematic diagrams of cross-sectional structures of two examples of packaging structures with an airtight cavity according to the second embodiment of the present invention are shown.

[0041] Component number description

[0042] 10 First Semiconductor Wafer

[0043] 100 first side of the first semiconductor wafer

[0044] 101 second side of the first semiconductor wafer

[0045] 11 First oxide layer

[0046] 12 Second oxide layer

[0047] 13 First cavity

[0048] 130 hard mask layer

[0049] 131 photoresist layer

[0050] 14 Second cavity

[0051] 15 Insulation dielectric layer / electromagnetic shielding layer

[0052] 16 bonding metal pads

[0053] 17 Device Structure

[0054] 170 bonding metal layer

[0055] 18 Airtight cavity

[0056] 19 Second semiconductor wafer

[0057] 190 first side of the second semiconductor wafer

[0058] 191 second side of the second semiconductor wafer

[0059] 20 Device Structure

[0060] 200 bonding metal layer

[0061] 21 First semiconductor layer

[0062] 210 bonding metal pad

[0063] 22 First oxide layer

[0064] 23 Second oxide layer

[0065] 24 Airtight cavity

[0066] 25 Second semiconductor layer

[0067] 26 Insulation dielectric layer / electromagnetic shielding layer DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0070] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.

[0071] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0072] See also Figures 1 to 18It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0073] Example 1

[0074] This embodiment provides a packaging method for a packaging structure with an airtight cavity. The packaging method is suitable for devices that need to operate in a vacuum-sealed environment. The packaging method includes the following steps:

[0075] S1, providing a first semiconductor wafer and a second semiconductor wafer having first and second sides opposite to each other;

[0076] S2, forming a first oxide layer on the first side surface of the first semiconductor wafer, and forming a second oxide layer on the first side surface of the second semiconductor wafer; wherein the material of the first oxide layer is an oxide based on the semiconductor material of the first semiconductor wafer, and the material of the second oxide layer is an oxide based on the semiconductor material of the second semiconductor wafer;

[0077] S3, permanently bonding the first oxide layer and the second oxide layer to achieve permanent bonding of the first semiconductor wafer and the second semiconductor wafer;

[0078] S4, thinning the first semiconductor wafer from the second side surface to a desired thickness;

[0079] S5, performing dry etching downward from a predetermined area on the second side surface of the first semiconductor wafer to form a first cavity penetrating the first semiconductor wafer;

[0080] S6, removing the first oxide layer and the second oxide layer exposed in the first cavity by wet etching to form a second cavity;

[0081] S7, forming a bonding metal pad on the second side of the first semiconductor wafer outside the second cavity;

[0082] S8, providing a device structure with a bonding metal layer formed on the surface, and bonding the bonding metal layer to the bonding metal pad to form an airtight cavity between the second cavity and the device structure.

[0083] In the packaging method of the packaging structure with an airtight cavity of this embodiment, during the process of forming the second cavity, oxide layers of corresponding semiconductor materials are first formed on the surfaces of the first semiconductor wafer and the second semiconductor wafer, and then the two oxide layers are permanently bonded to form an oxide bonding layer, thereby achieving the second cavity by dry etching the first semiconductor wafer combined with wet etching of the oxide bonding layer. Since the oxide of the corresponding semiconductor material has a high etching selectivity with the corresponding semiconductor material compared to dry etching, when the oxide of the semiconductor material is wet-etched to expose the surface of the second semiconductor wafer thereunder, minimal damage is caused to the surface of the second semiconductor wafer, thereby obtaining an airtight cavity bottom surface with very low roughness. In addition, During dry etching of the first semiconductor wafer, the oxide bonding layer serves as an etching barrier layer, thereby enabling the formation of a first cavity of arbitrary diameter and arbitrary depth, especially for the preparation of a first cavity of large diameter and large depth. Furthermore, since the oxide layer formed on the semiconductor wafer is an oxide formed based on the semiconductor material of the corresponding semiconductor wafer, the lattice mismatch and thermal mismatch between the two are low, and cracking and warping problems are not easily generated, and the bonding quality of the oxide bonding layer after bonding is high. Finally, the device structure is encapsulated in a single airtight cavity formed by the semiconductor material. The encapsulated finished product is small in size and light in weight, and the packaging cycle and cost are greatly reduced. In addition, some processes of the wafer-level packaging are compatible with existing silicon processes and are suitable for large-scale production applications.

[0084] The packaging method of the packaging structure with an airtight cavity of this embodiment is described in detail below with reference to the specific drawings.

[0085] like Figure 1 and Figure 2 As shown, step S1 is first performed to provide a first semiconductor wafer 10 and a second semiconductor wafer 19 having a first side and a second side opposite to each other; Figure 1 The first semiconductor wafer 10 has a first side 100 of the first semiconductor wafer and a second side 101 of the first semiconductor wafer opposite to each other. Figure 2 The second semiconductor wafer 19 has a first side 190 and a second side 191 opposite to each other.

[0086] The first semiconductor wafer 10 and the second semiconductor wafer 19 are made of semiconductor materials. The materials of the two can be the same or different, and preferably the same semiconductor material is selected. In addition, the first semiconductor wafer 10 and the second semiconductor wafer 19 are preferably made of the same elemental material or compound material of the fourth main group, such as a silicon wafer, a germanium wafer, or a silicon carbide wafer or a silicon germanium wafer. In this embodiment, it is preferred that the first semiconductor wafer 10 and the second semiconductor wafer 19 are both silicon wafers. On the one hand, this is easily compatible with existing silicon processes during the subsequent wafer-level packaging process. On the other hand, the silicon wafer has a high etching selectivity ratio with the silicon oxide bonding layer subsequently formed thereon, which facilitates obtaining a low-roughness second semiconductor wafer surface during the subsequent second cavity wet etching.

[0087] The thickness of the first semiconductor wafer 10 and the second semiconductor wafer 19 are generally thicker at the beginning, and whether to thin them is determined according to actual needs.

[0088] like Figure 3 and Figure 4 As shown, step S2 is then performed to form a first oxide layer 11 on the surface of the first side 100 of the first semiconductor wafer, and a second oxide layer 12 on the surface of the first side 190 of the second semiconductor wafer; wherein the material of the first oxide layer 11 is an oxide based on the semiconductor material of the first semiconductor wafer 10, for example, when the first semiconductor wafer 10 is a silicon wafer, the first oxide layer is a silicon oxide layer, and the material of the second oxide layer 12 is an oxide based on the semiconductor material of the second semiconductor wafer 19, for example, when the second semiconductor wafer 19 is a silicon wafer, the second oxide layer is a silicon oxide layer.

[0089] The first oxide layer 11 and the second oxide layer 12 may be prepared by conventional existing processes, such as thermal oxidation process, CVD process, sol-gel process, ALD process, etc., and the process is selected according to actual needs.

[0090] In this embodiment, the first oxide layer 11 and the second oxide layer 12 are preferably both silicon oxide layers. In addition, the preparation process of the first oxide layer 11 and the second oxide layer 12 is not restricted by the order, as long as they are formed on the first semiconductor wafer 10 and the second semiconductor wafer 19 respectively.

[0091] The thickness of the first oxide layer 11 and the thickness of the second oxide layer 12 may be the same or different, as long as they can meet the requirements of permanent bonding between the two. In addition, the total thickness of the first oxide layer 11 and the second oxide layer 12 is set according to actual needs. When the first oxide layer 11 and the second oxide layer 12 are selected as silicon oxide layers in this embodiment, the total thickness of the two is generally selected to be 0.5μm to 3μm. Furthermore, in order to improve the bonding quality of subsequent permanent bonding, the bonding surfaces of the first oxide layer 11 and the second oxide layer 12 can be surface CMP polished after the deposition of the first oxide layer 11 and the second oxide layer 12 and before bonding to improve the surface flatness.

[0092] like Figure 5 and Figure 6 As shown, step S3 is then performed to permanently bond the first oxide layer 11 and the second oxide layer 12 to achieve permanent bonding of the first semiconductor wafer 10 and the second semiconductor wafer 19 .

[0093] As an example, when the first oxide layer 11 and the second oxide layer 12 are selected as silicon oxide layers, during the permanent bonding process, the hydroxyl groups (-OH) and silicon-oxygen bonds (Si-O) on the silicon oxide surface interact through van der Waals forces and hydrogen bonds to form stable chemical bonds. Under appropriate temperature and pressure conditions, these chemical bonds are further strengthened, ultimately achieving permanent bonding.

[0094] like Figure 6 As shown, step S4 is then performed to thin the second side 101 of the first semiconductor wafer to a desired thickness. The thickness of the first semiconductor wafer 10 after thinning is part of the depth of the subsequently formed airtight cavity, so the thickness of the first semiconductor wafer 10 after thinning is set according to the depth requirement of the airtight cavity. The thinning process is implemented using an existing conventional thinning process, such as first using coarse grinding for thinning and then fine grinding for flattening. However, it is not limited to this, and other suitable thinning processes can be used.

[0095] As an example, the thickness H of the first semiconductor wafer 10 after thinning (eg Figure 10 shown) is 100μm to 500μm.

[0096] like Figure 10 As shown, step S5 is then performed to dry-etch downward from a predetermined area on the surface of the second side 101 of the first semiconductor wafer 10 to form a first cavity 13 that penetrates the first semiconductor wafer 10. The diameter of the first cavity 13 can be set according to actual needs. Based on the packaging method of this embodiment, the diameter D of the first cavity 13 can be up to 20 mm.

[0097] During the dry etching process of this step, since the first semiconductor wafer 10 is underneath the first oxide layer 11, the first oxide layer 11 can serve as an etching barrier layer during the dry etching process. There is no need to worry too much about the damage to the surface of the first oxide layer 11 during the dry etching process. Therefore, it is easy to obtain a first cavity 13 with a large aperture and good verticality.

[0098] As an example, when the first semiconductor wafer 10 of this embodiment is a silicon wafer, the first semiconductor wafer 10 may be etched using a Bosch process.

[0099] As a specific example, a method of forming the first cavity 13 penetrating the first semiconductor wafer 10 includes:

[0100] like Figure 7 As shown, in step S51, a hard mask layer 130, such as a silicon oxide hard mask layer, is formed on the surface of the second side 101 of the first semiconductor wafer 10;

[0101] like Figure 7 and Figure 8 As shown, in step S52, a photoresist layer 131 is formed on the surface of the hard mask layer 130, and patterned to form a patterned photoresist layer 131;

[0102] like Figure 9 As shown, in step S53, the hard mask layer 130 is dry-etched based on the patterned photoresist layer 131, and then the patterned photoresist layer 131 is removed to obtain the patterned hard mask layer 130;

[0103] like Figure 9 and Figure 10 As shown, the first semiconductor wafer 10 is dry-etched based on the patterned hard mask layer 130 and then the patterned hard mask layer 130 is removed to obtain the first cavity 13 .

[0104] like Figure 12 As shown, step S6 is then performed to remove the first oxide layer 11 and the second oxide layer 12 exposed in the first cavity 13 by wet etching to form a second cavity 14. Due to the high etching selectivity of wet etching, the surface roughness of the exposed second semiconductor wafer 19 can be effectively reduced.

[0105] like Figure 11The figure shows an SEM image of the surface of the second semiconductor wafer 19 exposed in the second cavity 14 formed when both the first semiconductor wafer 11 and the second semiconductor wafer 19 are silicon wafers. Point A in the figure shows the exposed surface of the second semiconductor wafer 19, with a surface roughness of less than 5 nm. In an even better case, the surface roughness can reach less than 1 nm, which fully meets the surface roughness requirements for the airtight cavity of an uncooled infrared detector. In addition, when the first oxide layer 11 and the second oxide layer 12 are silicon oxide layers, hydrofluoric acid is generally selected as the wet etching solution. Hydrofluoric acid has a very high etching selectivity for silicon oxide to silicon, generally within the range of 100:1 to 1000:1, so the silicon oxide layer can be removed with virtually no damage.

[0106] As another specific example, the packaging method of this embodiment can be applied to the packaging of uncooled infrared detector chips. For uncooled infrared detector chips, the roughness of the bottom of the airtight cavity is the main factor affecting the light transmittance. The packaging method of this embodiment can effectively reduce the roughness of the bottom of the airtight cavity (i.e., the second cavity 14). As mentioned above, for the silicon wafer and the silicon oxide layer, the bottom roughness of the formed second cavity 14 is less than 5nm, the depth of the first cavity 13 can reach 100μm to 500μm, and the transmittance of the infrared wavelength of 8μm to 14μm can reach more than 90%.

[0107] As another specific example, the packaging method of this embodiment can also be applied to the packaging of radio frequency microsystem chips. Radio frequency microsystem chips are generally required to have electromagnetic shielding functions. Generally, an electromagnetic shielding cap is set on the external structure of the package after the radio frequency microsystem chip is packaged, resulting in a large overall structure volume, limited selection of electromagnetic shielding materials, and disadvantageous packaging density. In this embodiment, the electromagnetic shielding function of the radio frequency microsystem chip can be achieved by means of the airtight cavity formed by the second cavity. At this time, as long as the insulating dielectric layer / electromagnetic shielding layer 15 (such as the insulating dielectric layer 15) is sequentially formed on the bottom wall and side walls of the second cavity 14 and the second side surface of the first semiconductor wafer 10, the electromagnetic shielding function of the radio frequency microsystem chip can be achieved by means of the airtight cavity formed by the second cavity 14. Figure 13As shown), since the electromagnetic shielding layer can be formed directly in the packaging process, it is equivalent to being embedded in the package body, which effectively reduces the package volume, reduces the package complexity, and is beneficial to the package density; in addition, since the electromagnetic shielding layer can be prepared by a conventional deposition process, the choice of electromagnetic shielding materials can be diversified; finally, since the bottom roughness of the second cavity 14 is low, the insulating dielectric layer / electromagnetic shielding layer 15 formed thereon has good continuity, that is, the electromagnetic shielding layer has a strong bonding force, which improves the reliability of the electromagnetic shielding layer 15. Preferably, the material of the insulating dielectric layer in the insulating dielectric layer / electromagnetic shielding layer 15 is an oxide based on the semiconductor material of the first semiconductor wafer, and the insulating dielectric layer is formed by a CVD process, and the thickness is generally selected to be 0.3μm to 0.9μm; the electromagnetic shielding layer is a stack of a tantalum material layer and a copper material layer, and the electromagnetic shielding layer is formed by a PVD process, and the thickness is generally selected to be: the thickness of the tantalum material layer is The thickness of the copper material layer is

[0108] like Figure 14 and Figure 15 As shown, Figure 14 The figure shows a situation where an insulating dielectric layer / electromagnetic shielding layer 15 is formed on the bottom wall and side wall of the second cavity 14 and the second side surface of the first semiconductor wafer 10. Figure 15 The figure shows a situation where the insulating dielectric layer / electromagnetic shielding layer 15 is not formed on the bottom wall and side wall of the second cavity 14 and the second side surface of the first semiconductor wafer 10, and then step S7 is performed to form a bonding metal pad 16 on the second side of the first semiconductor wafer 10 outside the second cavity 14.

[0109] As an example, the bonding metal pad 16 is formed by an evaporation process, but it is not limited to this. Other suitable processes, such as electroplating, can also be used. Specifically, the evaporation process includes: first forming a photoresist layer on the surface of the obtained structure; then patterning the photoresist layer to form a patterned photoresist layer; then evaporating a bonding metal pad layer on the side where the patterned photoresist layer is located; finally, removing the patterned photoresist layer and the evaporated bonding metal pad layer thereon, and the remaining bonding metal pad layer on the first semiconductor wafer 10 is formed into the bonding metal pad 16. The material of the bonding metal pad 16 can be selected from at least one of tin, lead, aluminum and gold, but it is not limited to this. Other suitable pad materials can also be used, and its thickness is selected to be 2μm to 6μm.

[0110] like Figure 16As shown, step S8 is finally performed to provide a device structure 17 having a bonding metal layer 170 formed on the surface, and bonding the bonding metal layer 170 to the bonding metal pad 16 to form an airtight cavity 18 between the second cavity 14 and the device structure 17. It should be noted that Figure 16 The bottom wall and side wall of the second cavity 14 and the second side surface of the first semiconductor wafer 10 are not formed with the insulating dielectric layer / electromagnetic shielding layer 15. In this case, if a chip is provided on the device structure 17 in the airtight cavity 18, the chip is preferably an uncooled infrared detector chip; when the chip provided on the device structure 17 is a radio frequency microsystem chip, such as Figure 14 As shown, the bottom wall and side wall of the second cavity 14 and the second side surface of the first semiconductor wafer 10 will form an insulating dielectric layer / electromagnetic shielding layer 15, which has been mentioned in the above text and will not be repeated here.

[0111] As an example, the bonding metal layer 170 and the bonding metal pad 16 in this step can be bonded in the form of chip-chip bonding, chip-wafer bonding, or wafer-wafer bonding. Specifically: when the bonding form is chip-chip bonding, the device structure 17 is provided in the form of a chip, and after step S7, the obtained structure is cut into a chip form, thereby realizing chip-chip bonding in the bonding process of this step; when the bonding form is chip-wafer bonding, the device structure 17 is provided in the form of a chip, thereby realizing chip-wafer bonding in the bonding process of this step; when the bonding form is wafer-wafer bonding, the device structure 17 is provided in the form of a wafer, thereby realizing wafer-wafer bonding in the bonding process of this step.

[0112] The material of the bonding metal layer 170 can be any material suitable for metal bonding, such as titanium, platinum, gold, etc., and is selected according to actual needs.

[0113] Example 2

[0114] This embodiment provides a packaging structure with an airtight cavity, which can be obtained by packaging using the packaging method described in the first embodiment. The beneficial effects that can be achieved can be found in the description of the first embodiment, and will not be described in detail below. Figure 17 and Figure 18 As shown, the package structure includes, in sequence along the thickness direction: a device structure 20, a first semiconductor layer 21, a first oxide layer 22, a second oxide layer 23, an airtight cavity 24 and a second semiconductor layer 25; wherein,

[0115] The device structure 20 is bonded to the bonding metal pad 210 on the first semiconductor layer 21 through the bonding metal layer 200 on the surface thereof;

[0116] The first semiconductor layer 21 and the second semiconductor layer 25 are permanently bonded together through the first oxide layer 22 and the second oxide layer 23;

[0117] The airtight cavity 24 penetrates the first semiconductor layer 21 , the first oxide layer 22 , and the second oxide layer 23 and exposes the surface of the second semiconductor layer 25 , and the airtight cavity 24 is sealed between the device structure 20 and the second semiconductor layer 25 ;

[0118] The surface roughness of the second semiconductor layer 25 is less than 5 nm, and this mainly refers to the surface facing the airtight cavity 24 .

[0119] like Figure 17 As shown, as a specific example, if a chip is provided on the device structure 17 in the airtight cavity 18 , the chip provided on the device structure 20 is an uncooled infrared detector chip.

[0120] like Figure 18 As shown, as another specific example, if a chip is provided on the device structure 17 in the airtight cavity 18, the chip provided on the device structure 20 is a radio frequency microsystem chip, and the bottom wall and side wall of the airtight cavity 24 and the surface of the first semiconductor layer 21 are sequentially provided with an insulating dielectric layer / electromagnetic shielding layer 26. Preferably, the insulating dielectric layer in the insulating dielectric layer / electromagnetic shielding layer 26 is a silicon oxide layer with a thickness of 0.3μm to 0.9μm; the electromagnetic shielding layer is a laminate of a tantalum material layer and a copper material layer, and the thickness of the tantalum material layer is The thickness of the copper material layer is

[0121] The first semiconductor layer 21 and the second semiconductor layer 25 are made of semiconductor materials. The materials of the two layers can be the same or different, but preferably the same semiconductor material is selected. In addition, the first semiconductor layer 21 and the second semiconductor layer 25 are preferably made of the same elemental material or compound material of the fourth main group, such as silicon, germanium, or silicon carbide or silicon germanium. In this embodiment, it is preferred that the first semiconductor layer 21 and the second semiconductor layer 25 are both silicon layers, the first oxide layer 22 is a silicon oxide layer, and the second oxide layer 23 is a silicon oxide layer. The thickness of the first semiconductor layer 21 is 100μm to 500μm, and the total thickness of the first oxide layer 22 and the second oxide layer 23 is 0.5μm to 3μm. The diameter of the airtight cavity 24 is no greater than 20mm.

[0122] As an example, the bonding metal pad 210 is made of at least one of tin, lead, aluminum, and gold, and has a thickness of 2 μm to 6 μm. The bonding metal layer 170 is made of at least one of titanium, platinum, and gold.

[0123] In summary, the present invention provides a packaging structure with an airtight cavity and a packaging method thereof. In the process of forming the second cavity, an oxide layer of the corresponding semiconductor material is first formed on the surface of the first semiconductor wafer and the second semiconductor wafer, and then the two oxide layers are permanently bonded to form an oxide bonding layer, so that the second cavity is obtained by dry etching the first semiconductor wafer combined with wet etching of the oxide bonding layer. Since the oxide of the corresponding semiconductor material has a high etching selectivity with the corresponding semiconductor material compared to dry etching, when the oxide of the semiconductor material is wet-etched to expose the surface of the second semiconductor wafer thereunder, the damage to the surface of the second semiconductor wafer is very small, thereby obtaining an airtight cavity bottom surface with very low roughness. In addition, when dry etching the first semiconductor wafer, the oxide bonding layer serves as an etching barrier layer, thereby enabling the formation of a first cavity of any diameter and any depth, especially for the preparation of a first cavity of large diameter and large depth. Furthermore, since the oxide layer formed on the semiconductor wafer is an oxide formed based on the semiconductor material of the corresponding semiconductor wafer, the lattice mismatch and thermal mismatch between the two are low, and cracking and warping problems are not easily generated, and the bonding quality of the oxide bonding layer after bonding is high. Finally, the device structure is encapsulated in a single airtight cavity formed by the semiconductor material. The encapsulated finished product is small in size and light in weight, and the packaging cycle and cost are greatly reduced. In addition, the wafer-level packaging process is compatible with the existing silicon process and is suitable for large-scale production applications. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A packaging method for a packaging structure having an airtight cavity, characterized in that: The packaging method comprises: providing a first semiconductor wafer and a second semiconductor wafer having opposing first and second sides; forming a first oxide layer on a first side surface of the first semiconductor wafer, and forming a second oxide layer on a first side surface of the second semiconductor wafer; wherein a material of the first oxide layer is an oxide based on the semiconductor material of the first semiconductor wafer, and a material of the second oxide layer is an oxide based on the semiconductor material of the second semiconductor wafer; Permanently bonding the first oxide layer to the second oxide layer to achieve permanent bonding of the first semiconductor wafer to the second semiconductor wafer; Thinning the first semiconductor wafer from its second side surface to a desired thickness; performing dry etching downward from a predetermined area on the second side surface of the first semiconductor wafer to form a first cavity penetrating the first semiconductor wafer; removing the first oxide layer and the second oxide layer exposed in the first cavity by wet etching to form a second cavity; forming a bonding metal pad on the second side of the first semiconductor wafer outside the second cavity; A device structure having a bonding metal layer formed on its surface is provided, and the bonding metal layer is bonded to the bonding metal pad, so that an airtight cavity is formed between the second cavity and the device structure.

2. The packaging method of the packaging structure with an airtight cavity according to claim 1, wherein: The first semiconductor wafer is a silicon wafer, the second semiconductor wafer is a silicon wafer, the first oxide layer is a silicon oxide layer, and the second oxide layer is a silicon oxide layer.

3. The packaging method of the packaging structure with an airtight cavity according to claim 2, wherein: Etching the first semiconductor wafer using a Bosch process to form the first cavity; The wet etching solution used to form the second cavity by wet etching includes hydrofluoric acid.

4. The packaging method of the packaging structure with an airtight cavity according to claim 1, wherein: The bonding metal pad is formed by an evaporation process or an electroplating process.

5. The packaging method of the packaging structure with an airtight cavity according to claim 1, wherein: The bonding metal layer and the bonding metal pad are bonded in a chip-to-chip bonding or chip-to-wafer bonding or wafer-to-wafer bonding.

6. The packaging method of the packaging structure with an airtight cavity according to claim 1, characterized in that: The method of forming the first cavity penetrating the first semiconductor wafer includes: forming a hard mask layer on the second side surface of the first semiconductor wafer; forming a photoresist layer on the surface of the hard mask layer and performing patterning; dry-etching the hard mask layer based on the patterned photoresist layer and then removing the patterned photoresist layer to obtain the patterned hard mask layer; The first semiconductor wafer is dry-etched based on the patterned hard mask layer, and then the patterned hard mask layer is removed to obtain the first cavity.

7. The packaging method of the packaging structure with an airtight cavity according to claim 1, characterized in that: After forming the second cavity and before forming the bonding metal pad, the method further includes the steps of sequentially forming an insulating dielectric layer and an electromagnetic shielding layer on the bottom wall and side walls of the second cavity and the second side surface of the first semiconductor wafer.

8. The packaging method of the packaging structure with an airtight cavity according to claim 7, wherein: The material of the insulating dielectric layer is an oxide based on the semiconductor material of the first semiconductor wafer, and the insulating dielectric layer is formed by a CVD process; the electromagnetic shielding layer is a stack of a tantalum material layer and a copper material layer, and the electromagnetic shielding layer is formed by a PVD process.

9. The packaging method of the packaging structure with an airtight cavity according to claim 1, wherein: Before permanently bonding the first oxide layer and the second oxide layer, the method further includes performing a CMP polishing step on the bonding surfaces of the first oxide layer and the second oxide layer.

10. A packaging structure with an airtight cavity, characterized in that: The packaging structure includes, in sequence along the thickness direction: a device structure, a first semiconductor layer, a first oxide layer, a second oxide layer, an airtight cavity, and a second semiconductor layer; wherein, The device structure is bonded to the bonding metal pad on the first semiconductor layer via a bonding metal layer on the surface of the device structure; The first semiconductor layer and the second semiconductor layer are permanently bonded together through the first oxide layer and the second oxide layer; The airtight cavity penetrates the first semiconductor layer, the first oxide layer, and the second oxide layer and exposes the surface of the second semiconductor layer, and the airtight cavity is sealed between the device structure and the second semiconductor layer; The surface roughness of the second semiconductor layer is less than 5 nm.

11. The packaging structure with an airtight cavity according to claim 10, characterized in that: The chip arranged on the device structure is an uncooled infrared detector chip.

12. The packaging structure with an airtight cavity according to claim 10, wherein: The chip arranged on the device structure is a radio frequency microsystem chip; the bottom wall and side walls of the airtight cavity and the surface of the first semiconductor layer are sequentially provided with an insulating dielectric layer and an electromagnetic shielding layer.

13. The packaging structure with an airtight cavity according to claim 12, wherein: The insulating dielectric layer is a silicon oxide layer with a thickness of 0.3 μm to 0.9 μm; the electromagnetic shielding layer is a stack of a tantalum material layer and a copper material layer, and the thickness of the tantalum material layer is The thickness of the copper material layer is 14. The packaging structure with an airtight cavity according to claim 10, wherein: The first semiconductor layer is a silicon layer, the second semiconductor layer is a silicon layer, the first oxide layer is a silicon oxide layer, and the second oxide layer is a silicon oxide layer; the thickness of the first semiconductor layer is 100 μm to 500 μm, the total thickness of the first oxide layer and the second oxide layer is 0.5 μm to 3 μm, and the diameter of the airtight cavity is not greater than 20 mm.

15. The packaging structure with an airtight cavity according to claim 10, wherein: The material of the bonding metal pad includes at least one of tin, lead, aluminum and gold, and the thickness of the bonding metal pad is 2 μm to 6 μm.

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