Insertion loss test system, insertion loss test method, equipment and medium

Abstract

The invention discloses an insertion loss test system, an insertion loss test method, equipment and a medium, and relates to the technical field of chip tests.An insertion loss board is arranged in the insertion loss test system, simulation of insertion losses of different sizes is achieved on the insertion loss board through different sets of test ports, meanwhile, a first change-over switch and a second change-over switch are matched, and the test efficiency is improved. According to the invention, automatic switching among multiple sections of loss can be realized, so that the to-be-tested chip is tested based on insertion loss of different sizes corresponding to different groups of test ports, and finally, the specific value of the insertion loss of the to-be-tested chip is determined according to the known insertion loss of the test ports and test results corresponding to different groups. On-line flexible configuration of different insertion loss test requirements is realized by automatically switching multi-section loss, the specific value of the insertion loss of the to-be-tested chip is finally output, accurate test of the insertion loss of the to-be-tested chip is realized, the chips with different insertion loss values can be classified and applied to products or customers with different requirements, so that the test yield of the chips is improved, and the test cost is reduced. And the cost of the chip is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to an insertion loss testing system, an insertion loss testing method, a device and a medium. Background Art

[0002] During chip production screening testing, chips supporting PCIE (Peripheral Component Interconnect Express) must undergo insertion loss screening testing. Currently, the typical testing method involves designing a fixed insertion loss trace on the printed circuit board (PCB) where the chip under test resides, based on the total insertion loss requirements for the chip's output and the actual PCB trace conditions. The chip under test transmits a test signal, which is then returned to the chip's receiver via the fixed insertion loss trace on the PCB. If the chip receives the correct data, the test passes; otherwise, it fails and is considered defective. This test system uses a fixed insertion loss, so it can only filter out good chips that are at least within a certain insertion loss requirement and defective chips that are below that requirement. This method fails to reflect the chip's more specific insertion loss conditions, resulting in a relatively low chip test yield.

[0003] It can be seen that how to achieve more accurate testing of chip insertion loss to improve chip test yield is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide an insertion loss test system, insertion loss test method, device and medium, which can solve the problem that chip insertion loss testing can only single-screen good or bad chips and cannot reflect the more specific insertion loss status of the chip.

[0005] To solve the above technical problems, an embodiment of the present invention provides an insertion loss test system, comprising:

[0006] An insertion loss board, the insertion loss board including a plurality of groups of test ports, wherein the insertion losses corresponding to the plurality of groups of test ports are different from each other; wherein a group of test ports includes a first test port and a second test port, and the insertion loss corresponding to the group of test ports is the insertion loss between the first test port and the second test port;

[0007] A first switching switch, a fixed end of which is connected to the signal sending port of the chip under test, and the first switching switch includes a plurality of switching ends connected to the plurality of first test ports in a one-to-one correspondence;

[0008] A second switching switch, a fixed end of which is connected to the signal receiving port of the chip to be tested, and the second switching switch includes a plurality of switching ends connected to the plurality of second test ports in a one-to-one correspondence;

[0009] The processor has an output end connected to the control end of the first switch and the control end of the second switch, respectively, and is used to connect the chip under test to different groups of test ports by controlling the first switch and the second switch, so as to determine the insertion loss of the chip under test based on the test results of the multiple groups of test ports and the insertion losses corresponding to the multiple groups of test ports.

[0010] In some embodiments, the insertion board is provided with a plurality of signal lines, and the lengths of the plurality of signal lines are different from each other;

[0011] The first end of the signal line is connected to the switching end corresponding to the first switch through the first test port, and the second end of the signal line is connected to the switching end corresponding to the second switch through the second test port.

[0012] To solve the above technical problems, an embodiment of the present invention further provides an insertion loss test method, which is applied to the aforementioned insertion loss test system. The insertion loss test method includes:

[0013] Controlling a group of switching terminals corresponding to a first switch and a second switch in the insertion loss test system to be connected, so as to connect the chip to be tested and the current test port group; wherein the current test port group is any group of test ports in an insertion loss board of the insertion loss test system;

[0014] Determine the test result of the current test port group based on the return result of the preset test signal sent by the chip under test;

[0015] The insertion loss of the chip to be tested is determined according to the test results of the plurality of test ports and the insertion losses corresponding to the plurality of test ports.

[0016] In some embodiments, further comprising:

[0017] Determine the insertion loss of other links of the chip under test;

[0018] The insertion loss corresponding to each group of test ports in the insertion loss board is determined according to the difference between the target insertion loss of the chip to be tested and the insertion loss of other links.

[0019] In some embodiments, further comprising:

[0020] If the test results of all groups of test ports in the insertion loss board are consistent, the insertion losses corresponding to several groups of test ports in the insertion loss board are adjusted.

[0021] In some embodiments, adjusting insertion losses corresponding to a plurality of groups of test ports in an insertion loss board includes:

[0022] If the test results of all groups of test ports in the insertion loss board are all passed, the insertion losses corresponding to the groups of test ports in the insertion loss board are increased by a first preset value;

[0023] If the test results of all groups of test ports in the insertion loss board are all test failures, the insertion losses corresponding to several groups of test ports in the insertion loss board are reduced by a second preset value.

[0024] In some embodiments, determining the test result of the current test port group based on the return result of the preset test signal sent by the chip under test includes:

[0025] When the first switch and the second switch are both connected to the switch ends corresponding to the current test port group, the chip under test is controlled to send a preset test signal to the first test port in the current test port group through the signal sending port;

[0026] If the signal receiving port of the chip under test receives a preset test signal returned from the second test port in the current test port group within a preset time period, it is determined that the test of the current test port group has passed;

[0027] If the signal receiving port of the chip under test does not receive the preset test signal returned from the second test port in the current test port group within the preset time period, it is determined that the test of the current test port group has failed.

[0028] In some embodiments, controlling a group of switching terminals corresponding to a first switch and a second switch in an insertion loss test system to be connected to connect the chip to be tested and the current test port group includes:

[0029] Sort the test ports of the insertion loss board in the insertion loss test system in ascending order of corresponding insertion loss to obtain a test sequence;

[0030] Determine the first group of test ports in the test sequence as the current test port group, and control the first switch and the second switch to connect a group of switch ports corresponding to the current test port group;

[0031] If the test result of the current test port group is that the test passes, the next group of test ports in the test sequence is determined as the current test port group, and the process jumps again to the step of controlling the first switch and the second switch to connect to a group of switch ports corresponding to the current test port group, until the test result of the current test port group is that the test fails;

[0032] Determine the insertion loss of the chip under test based on the test results of several groups of test ports and the insertion losses corresponding to the several groups of test ports, including:

[0033] The insertion loss corresponding to the current test port group that passed the last test is determined as the insertion loss of the chip to be tested.

[0034] To solve the above technical problems, an embodiment of the present invention further provides an electronic device, including:

[0035] memory for storing computer programs;

[0036] The processor is configured to execute a computer program to implement the steps of the aforementioned insertion loss testing method.

[0037] To solve the above technical problems, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above insertion loss test method are implemented.

[0038] As can be seen from the above technical solution, an insertion loss board is provided in the insertion loss test system. The insertion loss board realizes the simulation of insertion losses of different sizes through different groups of test ports. At the same time, in conjunction with the first switching switch and the second switching switch, it can realize automatic switching between multiple loss segments, thereby testing the chip to be tested based on the different insertion losses corresponding to the different groups of test ports, and finally determining the specific insertion loss value of the chip to be tested based on the known insertion losses of the test ports and the test results corresponding to the different groups. The beneficial effect of the present invention is that it realizes the online flexible configuration of different insertion loss test requirements by automatically switching multiple loss segments, and finally outputs the specific insertion loss value of the chip to be tested, realizing accurate testing of the insertion loss of the chip to be tested. Chips with different insertion loss values ​​can be classified and applied to products or customers with different requirements, thereby improving the test yield of the chip and saving the cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 A schematic structural diagram of an insertion loss test system provided by an embodiment of the present invention;

[0041] Figure 2 A schematic structural diagram of another insertion loss test system provided by an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of a configuration of an insertion loss board according to an embodiment of the present invention;

[0043] Figure 4 A schematic flow chart of an insertion loss testing method provided by an embodiment of the present invention;

[0044] Figure 5 A schematic flow chart of another insertion loss testing method provided by an embodiment of the present invention;

[0045] Figure 6A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0048] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0049] Next, an insertion loss test system provided by an embodiment of the present invention is described in detail. Figure 1 As shown, Figure 1 A schematic structural diagram of an insertion loss test system provided in an embodiment of the present invention; the insertion loss test system includes:

[0050] Insertion loss board 1, the insertion loss board 1 includes a plurality of groups of test ports, and the insertion losses corresponding to the plurality of groups of test ports are different from each other; wherein a group of test ports includes a first test port P1 and a second test port P2, and the insertion loss corresponding to a group of test ports is the insertion loss between the first test port P1 and the second test port P2;

[0051] A first switching switch K1, a fixed end of which is connected to the signal sending port of the chip under test, and the first switching switch K1 includes a plurality of switching ends connected to a plurality of first test ports P1 in a one-to-one correspondence;

[0052] A second switching switch K2, a fixed end of which is connected to the signal receiving port of the chip under test, and the second switching switch K2 includes a plurality of switching ends connected to a plurality of second test ports P2 in a one-to-one correspondence;

[0053] The processor 61 has an output end connected to the control end of the first switch K1 and the control end of the second switch K2, respectively, and is used to connect the chip under test to different groups of test ports by controlling the first switch K1 and the second switch K2, so as to determine the insertion loss of the chip under test based on the test results of the multiple groups of test ports and the insertion losses corresponding to the multiple groups of test ports.

[0054] It is easy to understand that, to achieve more accurate chip insertion loss testing, the insertion loss test system of the present application includes an insertion loss board 1. The insertion loss board 1 is provided with multiple groups of test ports, each group of which includes at least two test ports, namely, a first test port P1 and a second test port P2. Signal lines of different lengths and / or widths are provided on the insertion loss board 1 to connect the first test port P1 and the second test port P2 of a group of test ports, thereby utilizing a group of test ports to provide a single test insertion loss. Each group of test ports can provide different insertion losses, and a single insertion loss board 1 can provide different test insertion losses, thereby enabling multiple testing processes for the same chip under test. The present application does not specifically limit the specific types and implementations of the insertion loss board 1 and each test port. These can be implemented using methods such as SMA connectors (SubMiniature version A). Signal lines provided on the insertion loss board 1 are connected to corresponding switching ports via SMA connectors and cables. The specific number of test port groups can be adjusted based on actual application scenarios.

[0055] It can be understood that during each test, a group of test ports will serve as the current test port group. The signal transmission port of the chip under test is connected to the first test port P1 of the current test port group via the first switch K1. Inside the insertion board 1, the first test port P1 of the current test port group is connected to the second test port P2 of the current test port group. The second test port P2 is then connected to the signal receiving port of the chip under test via the second switch K2, so that the current test port group and the chip under test are connected to form a loop that serves as the test path for each test. When the first switch K1 and the second switch K2 are activated under the control of the processor 61, the processor 61 will notify the chip under test to start the test. At this time, the chip under test sends a preset test signal through the signal transmission port. Under normal circumstances, the preset test signal will pass through the signal transmission port, the first switch K1, the first test port P1 of the current test port group, the insertion board 1, the second test port P2 of the current test port group, and the signal receiving port in sequence and return to the chip under test. When the chip under test is able to receive the returned preset test signal, it indicates that the chip under test can support normal transmission of the preset test signal, the test passes, and the insertion loss value of the chip under test is greater than the insertion loss value corresponding to the current test port group. When the chip under test cannot receive the returned preset test signal, it indicates that the chip under test cannot support normal transmission of the preset test signal, the test fails, and the insertion loss value of the chip under test is less than the insertion loss value corresponding to the current test port group. In other words, the attenuation of the insertion loss corresponding to the current test port group is greater than the signal strength of the preset test signal, causing the preset test signal to be attenuated to a very low level (or even directly attenuated to zero), and the chip under test cannot receive the preset test signal. During multiple tests, different groups of test ports are used as the current test port group to obtain test results for multiple groups of test ports. Therefore, through multiple tests, the relationship between the insertion loss of the chip under test and the insertion loss corresponding to each group of test ports can be determined by comparing the test results. At the same time, the signal strength of the preset test signal is also known, thereby determining the specific insertion loss value of the chip under test.

[0056] It's important to note that insertion loss refers to the energy attenuation of a signal due to various factors in the transmission path, typically expressed in decibels (dB). The insertion loss of the chip under test refers to the chip's insertion loss capability, specifically the amount of insertion loss the chip supports for signal transmission over an external link. If the chip under test's insertion loss is idB, it indicates that the chip can support a link with idB of insertion loss over the corresponding transmission distance. The greater the insertion loss of the chip under test, the longer the signal transmission distance it can support. Therefore, users can use the test results to assess the chip's signal transmission capabilities and tailor their application to the specific scenario.

[0057] It should be further explained that if the insertion loss of the external link is too large, the signal at the receiving end may fall below the noise margin, resulting in an increased bit error rate and even inability to communicate normally. The insertion loss value refers to the absolute value of the insertion loss, that is, the attenuation corresponding to the insertion loss. Generally speaking, insertion loss occurs as a negative value. For ease of explanation, this application ignores the symbol and uses the insertion loss value for explanation. The insertion loss corresponding to a group of test ports refers to the energy attenuation caused by the loss of the insertion loss board 1 when the signal is transmitted from the first test port P1 to the second test port P2. In this application, the insertion loss board 1 is set to simulate the insertion loss in the link. A preset test signal is sent through the chip under test to test the transmission of the signal under different link conditions, thereby determining the insertion loss of the chip under test using the known insertion loss corresponding to a group of test ports in the insertion loss board 1. This application does not specifically limit the specific type and implementation of the processor 61. Various types of processing chips and control chips can be used, and specifically, an MCU (Microcontroller Unit) can be used for implementation. The processor 61 also needs to establish a communication connection with the chip to be tested to obtain the test results and inform the chip to be tested whether the test is turned on or not. This application does not specifically limit the specific type and implementation method of the communication connection between the processor 61 and the chip to be tested. The serial port can be used to achieve the connection, and the test instructions and test data can be communicated through the serial port.

[0058] It can be understood that in order to realize multiple test processes when the chip under test is connected to different groups of test ports, a first switching switch K1 and a second switching switch K2 are provided in the insertion loss test system to realize switching between the groups of test ports in the insertion loss board 1. The first switching switch K1 is used to realize switching of the first test port P1 connected to the signal sending port of the chip under test, and the second switching switch K2 is used to realize switching of the second test port P2 connected to the signal receiving port of the chip under test. Since the first test port P1 and the second test port P2 in the same group need to be connected to the circuit, that is, when the first test port P1 in the first group of test ports is connected to the circuit, the second test port P2 in the first group of test ports also needs to be connected to the circuit at the same time, so that the first group of test ports can normally provide the corresponding insertion loss, the processor 61 needs to control the first switching switch K1 and the second switching switch K2 to switch to the two switching ends corresponding to the same group of test ports each time. In a preferred embodiment, they are switched to the two switching ends corresponding to the same group of test ports at the same time. The switching end of the first switch K1, the first test port P1 in a group of test ports, the second test port P2 in the group of test ports, and the switching end of the second switch K2 all correspond to each other. During testing, they are connected strictly according to this correspondence. This application does not specifically limit the specific types and implementation methods of the first switch K1 and the second switch K2.

[0059] Furthermore, for the first switch K1 and the second switch K2, address identifiers can be configured for several switching terminals. For example, when there are N groups of test ports, both the first switch K1 and the second switch K2 have N switching terminals. The address identifiers of the two switching terminals corresponding to the same group of test ports can be the same. Therefore, a first address identifier can be configured for the switching terminal corresponding to the first group of test ports in the first switch K1 and the switching terminal corresponding to the first group of test ports in the second switch K2, and an Nth address identifier can be configured for the switching terminal corresponding to the Nth group of test ports in the first switch K1 and the switching terminal corresponding to the Nth group of test ports in the second switch K2, where N is a positive integer. During testing, the processor 61 sends a control instruction to control the operation of the first switch K1 and the second switch K2. The control instruction includes the address identifier, thereby instructing the fixed terminals of the first switch K1 and the second switch K2 to connect to the switching terminals corresponding to the address identifiers. The control instruction and address identifier can be implemented as a binary number consisting of multiple bits. For example, 0001 is used as the first address identifier, and the control instruction directly includes this binary number to indicate the switch end that needs to be connected. There are also multiple options for the connection between the processor 61 and the control ends of the two switches. The connection between the processor 61 and the control end of the first switch K1 can be implemented using four data lines, each of which corresponds to a binary signal, thereby implementing the transmission of the four-bit binary address identifier; or only one data line is used to connect the processor 61 to the control end of the first switch K1, and the multiple bits of the binary signal are sent to the first switch K1 in a specific order to implement the transmission of the address identifier. The control instruction can also be directly implemented using a level signal or other method, and the address identifier is transmitted by the difference between high and low levels. In order to ensure the accurate operation of the first switch K1 and the second switch K2, the processor can issue the same control instruction multiple times to ensure that the switch is switched in place. For example, after issuing two control instructions indicating the same address identifier in succession, the test is started again to ensure the accuracy and reliability of each test.

[0060] The present application provides an insertion loss test system that uses a multi-stage loss system capable of automatic switching to simulate the transmission link of the chip under test during testing, achieving online flexible configuration of different insertion loss test requirements, and more accurately determining the specific insertion loss value of the chip under test, thereby performing detailed classification of chips with different insertion loss capabilities. Chips with different insertion loss values ​​can be classified and applied to products or customers with different requirements, effectively improving the chip test yield and saving costs. If the insertion loss test requirements need to be adjusted, the insertion loss board 1 can be directly replaced or the settings of the insertion loss board 1 can be adjusted without replacing the circuit board of the chip under test, reducing testing costs and saving testing time. The entire test is supported by an automated program through the processor 61, effectively improving the efficiency of recording and analyzing test data during the test.

[0061] See also Figure 2 As shown, Figure 2 A schematic diagram of another insertion loss test system provided by an embodiment of the present invention; see Figure 3 As shown, Figure 3 A schematic diagram of a configuration of an insertion board according to an embodiment of the present invention; in some embodiments, the insertion board 1 is provided with a plurality of signal lines, and the lengths of the plurality of signal lines are different from each other;

[0062] The first end of the signal line is connected to the switching end corresponding to the first switch K1 through the first test port P1 , and the second end of the signal line is connected to the switching end corresponding to the second switch K2 through the second test port P2 .

[0063] It is understandable that the insertion loss board 1 can specifically realize the different sizes of insertion losses that can be provided by each group of test ports by setting signal lines of different lengths. Generally speaking, when other parameters are the same, the longer the length of the signal line, the greater the corresponding insertion loss. By using signal lines of different lengths to connect the first test port P1 and the second test port P2 in a group of test ports of the insertion loss board 1, the simulation of different insertion losses on the link is realized. The present application does not make any special restrictions on the method of determining the specific length of each signal line. You can first determine the insertion loss size corresponding to each group of test ports required for the test, input the insertion loss size and the material, type and other parameters of the signal line into the simulation software to calculate the signal line length corresponding to the insertion loss size, and then design the insertion loss board 1 according to the calculation result. The present application does not make any special restrictions on the specific type and implementation method of the signal line. The design of the insertion loss board 1 can also be achieved by setting different widths of the signal line, and the present application does not make any special restrictions here. The preset test signal sent by the signal sending interface of the chip under test will pass through the signal sending port, the first switching switch K1, the first test port P1 of the current test port group, the corresponding signal line on the insertion board 1, the second test port P2 of the current test port group, and the signal receiving port and return to the chip under test.

[0064] It should be noted that this application is primarily used in insertion loss testing of chips that support the PCIE Gen5 protocol. Both the signal transmission port and the signal receiving port of such chips under test are PCIE interfaces, and the PCIE Gen5 protocol is used for signal transmission. The signal transmission frequency is relatively high. For high-frequency signals, the wavelength of high-frequency signals is shorter, and the parasitic parameters of the transmission line (such as inductance and capacitance) have a more significant impact. Insertion loss can cause the signal amplitude to decay rapidly. Therefore, the insertion loss test system provided by this application is required to more accurately determine the chip's usable scenarios. Accordingly, the first switch K1 and the second switch K2 must use high-frequency microwave switches to support the effective transmission of high-frequency signals. Therefore, the first switch K1 and the second switch K2 are specifically implemented using mechanical microwave switches.

[0065] Furthermore, considering that PCIE uses serial differential signals to achieve signal transmission, each signal channel consists of a pair of differential lines. Figure 2 As shown in the figure, the insertion loss test system design uses a pair of differential lines (TX_P and TX_N) for the signal transmission port of the chip under test and a pair of differential lines (RX_P and RX_N) for the signal receiving port. A pair of test ports on insertion loss board 1 needs to be configured with a first test port P1 and a second test port P2 corresponding to the positive line (P) in the pair of differential lines, and a first test port P1 and a second test port P2 corresponding to the negative line (N) in the pair of differential lines. In other words, a pair of test ports includes two pairs of test ports (a pair of test ports is a first test port P1 and a second test port P2). The length of the signal lines between multiple pairs of test ports in the same test port group must be consistent to ensure that the group of test ports provides an effective insertion loss test. The first switching switch K1 needs to be set with a sub-switch K11 corresponding to the forward line (P) in a group of differential lines and a sub-switch K12 corresponding to the reverse line (N) in a group of differential lines. The second switching switch K2 needs to be set with a sub-switch K21 corresponding to the forward line (P) in a group of differential lines and a sub-switch K22 corresponding to the reverse line (N) in a group of differential lines. The design of the switching end corresponding to a group of differential lines and the insertion board 1 needs to be consistent to ensure the effective transmission of a group of differential signals. If the chip to be tested has M signal sending ports or multiple signal sending ports use M groups of differential lines to realize signal transmission, then a group of test ports in the insertion board 1 needs to include corresponding M pairs of test ports, and the insertion board 1 needs to be set with corresponding M signal lines of the same length. Therefore, N×M signal lines need to be set for the corresponding N groups of test ports. At the same time, in order to avoid the influence of DC bias on the signal, a coupling capacitor is also connected in series between the signal sending port and the signal receiving port. The coupling capacitor can also play a role in filtering and optimizing signal quality. For example Figure 2As shown, capacitors C1 and C2 are connected in series at the signal sending port of the signal to be measured to realize coupling capacitance.

[0066] As a specific embodiment, Figure 3 As shown in the figure, taking the insertion loss board 1 as an example, 10 groups of signal lines arranged in length order are set up, and a 10-channel insertion loss test system is realized through 10 groups of test ports, where P represents the signal line corresponding to the positive line (P) in a group of differential lines, N represents the signal line corresponding to the reverse line (N) in a group of differential lines, and L1, L2, L3, L4, L5, L6, L7, L8, L9, and L10 represent the signal lines corresponding to the first group of test ports, the second group of test ports, the third group of test ports, and the tenth group of test ports, respectively. The insertion loss of the signal line corresponding to each group of test ports is 1dB greater than that of the signal line corresponding to the previous group of test ports. On the actual insertion loss board, the signal line corresponding to the next group of test ports is slightly longer than that of the previous group of test ports. Correspondingly, as shown in the figure, Figure 2 As shown, each sub-switch is provided with corresponding 10 switching ends, which can all be implemented using an SP10T mechanical microwave switch. The insertion board 1 is provided with 10 first test ports P1 corresponding to the forward line (P), 10 first test ports P1 corresponding to the reverse line (N), 10 second test ports P2 corresponding to the forward line (P), and 10 second test ports P2 corresponding to the reverse line (N).

[0067] During testing, processor 61 controls each sub-switches to connect a single port (fixed port) on one side to one of the ten ports (switched ports) on the other side, enabling different insertion loss links on insertion loss board 1 to be connected to the test system. Processor 61 then communicates test data with the chip under test via a serial port and calculates the actual insertion loss value of the chip under test based on test parameters. An external processor 61 is used to automate the entire test system. Specifically, processor 61 controls the SP10T switch using four control signals and simultaneously connects to the chip under test via a serial port to obtain test results. Based on the test results and the switching status of the SP10T sub-switches, the insertion loss data of the chip under test can be calculated using the insertion loss information corresponding to the currently tested insertion loss board 1. This test system is not only suitable for insertion loss testing of PCIe chips, but can also be extended to implement insertion loss testing on chips using other high-speed signals, as well as for insertion loss testing and certification of PCIe boards. It can also be used for insertion loss measurement of PCIe boards, thus having a wide range of applications.

[0068] Specifically, the simulation of different insertion losses can be achieved by setting and adjusting the length of the signal line connected between the first test port P1 and the second test port P2, thereby realizing the insertion loss corresponding to a group of test ports. This method is low-cost and does not require additional components. It can be achieved by directly multiplexing the signal line connected between the first test port P1 and the second test port P2 for signal transmission. The operation is flexible, the line length can be quickly adjusted, and it can effectively adapt to different test scenarios, which is closer to the actual scenario.

[0069] See also Figure 4 As shown, Figure 4 A flow chart of an insertion loss test method provided by an embodiment of the present invention; to solve the above technical problems, an embodiment of the present invention further provides an insertion loss test method, which is applied to the aforementioned insertion loss test system; the insertion loss test method includes:

[0070] S11: Controlling a group of switching terminals corresponding to the first switch and the second switch in the insertion loss test system to be connected, so as to connect the chip under test and the current test port group; wherein the current test port group is any group of test ports in the insertion loss board of the insertion loss test system;

[0071] S12: Determine the test result of the current test port group based on the return result of the preset test signal sent by the chip under test;

[0072] S13: Determine the insertion loss of the chip to be tested according to the test results of the groups of test ports and the insertion losses corresponding to the groups of test ports.

[0073] It is not difficult to understand that the present application also provides an insertion loss test method implemented based on an insertion loss test system. The insertion loss test method is applied to the aforementioned insertion loss test system and is implemented by a processor in the insertion loss test system. The signal transmitting end of the chip under test sends a preset test signal to the insertion loss test system. The preset test signal passes through the insertion loss test system and is then output back to the signal receiving end of the chip under test. The chip under test analyzes the status of the transmitted and received signals to determine the test results. The corresponding insertion loss value of the chip under test can be effectively determined by the test results corresponding to multiple groups of test ports and the insertion loss corresponding to each group of test ports. All N groups of test ports on the insertion loss board can be traversed for N tests, or some groups of test ports can be selected for multiple tests based on the corresponding insertion loss size. Each time the first switch and the second switch are switched, a group of test ports is connected to the chip under test as the current test port group, and the chip under test will start testing and send a preset test signal to complete one test. This application does not make any special restrictions on the specific type and implementation method of the preset test signal. It can be directly implemented using a signal of a fixed size. For example, a 36dB signal is used for the entire test. The signal strength can also be adjusted according to the test results. For example, a 36dB signal is used for the test at the beginning, and then a 40dB signal is used for repeated testing to improve the test accuracy.

[0074] The present application provides a design method for a chip insertion loss test system with the ability to flexibly change insertion loss test standards in a chip production line environment, as well as a software process implementation for insertion loss testing. It also provides a design solution and implementation method for an insertion loss board. The introduction of mechanical microwave switches into the insertion loss test system expands the application field of mechanical microwave switches. For the production and testing environment of chip PCIe links, the insertion loss test standards can be changed more flexibly without having to replace the motherboard of the chip to be tested, saving the time required to replace the test system. The insertion loss value of each chip can be obtained in more detail, and detailed classification can be performed based on the chip insertion loss capability. Chips of different classifications are used in different industries and customers, saving chip costs. Through automated testing, the specific value of the chip insertion loss is output, and the final output chip insertion loss is accurate to 1dB through the setting of the insertion loss board.

[0075] See also Figure 5 As shown, Figure 5 A flow chart of another insertion loss testing method provided by an embodiment of the present invention; in some embodiments, the method further includes:

[0076] Determine the insertion loss of other links of the chip under test;

[0077] The insertion loss corresponding to each group of test ports in the insertion loss board is determined according to the difference between the target insertion loss of the chip to be tested and the insertion loss of other links.

[0078] It is understandable that the signal transmission port and signal reception port of the chip under test are both integrated within the chip under test. Therefore, in the test system, the actual signal path is, in order: the interior of the signal transmission port of the chip under test, the wiring on the PCB board where the chip under test is located, the connection line from the PCB board to the first switch, the first switch, the connection line from the first switch to the insertion board, the insertion board, the connection line from the insertion board to the second switch, the second switch, the second switch to the PCB board where the chip under test is located, the wiring on the PCB board where the chip under test is located, and the interior of the signal reception port of the chip under test. Therefore, the total link insertion loss can be simplified to (insertion loss from the internal signal transmission port of the chip under test to the input end of the insertion board) + (insertion loss on the insertion board) + (insertion loss from the output end of the insertion board to the internal signal reception port of the chip under test). Assume that the insertion loss from the chip under test's internal signal transmission port to the insertion board's input is A, the insertion loss on the insertion board is B, and the insertion loss from the insertion board's output port to the chip under test's internal signal reception port is C. Define A + C as the other link insertion loss. PCIe Gen5 protocol requirements require an end-to-end insertion loss of 36dB. Therefore, A + B + C ≥ 36dB, where A + B + C represents the insertion loss of the chip under test. The actual insertion loss of a typical chip fluctuates around 36dB. Selecting chips with an insertion loss range of 40 to 30dB is crucial based on the actual product application and system test efficiency. In practice, different hardware systems will correspond to different A + C values, which can be determined through simulation, manufacturer parameters, and other methods. Therefore, when designing the insertion board, determine the setting range for B based on the actual A + C values. To maximize compatibility with diverse hardware systems, and targeting the 40-30dB data range for chips screened for PCIe Gen5, with a target insertion loss of 40-30dB for the chips under test, the insertion loss board design is divided into the following types of boards. Table 1 shows the insertion loss design for the insertion loss board. Taking the first row as an example, if the A+C for the chip under test is 1 to 5dB, the signal lines corresponding to each group of test ports on the insertion loss board are designed within an insertion loss range of 28 to 37dB. For example, a signal line with a length of 28dB is set for the first group of test ports, a signal line with a length of 29dB for the second group of test ports, a signal line with a length of 30dB for the third group of test ports, and a signal line with a length of 37dB for the tenth group of test ports.

[0079] Table 1 Design reference table of insertion loss board corresponding to insertion loss

[0080]

[0081] As shown in Table 1, six 10-port insertion loss boards can be designed to adapt to the insertion loss values ​​of other links in the link. During testing, select the appropriate insertion loss board based on the insertion loss values ​​of other links in the actual system and connect it to the hardware test system.

[0082] Specifically, the approximate range of insertion loss that the insertion loss board needs to provide can be determined by first determining the insertion loss of other links corresponding to the chip under test in the insertion loss test system and the target insertion loss of the chip under test required by the application. Then, the insertion loss corresponding to each group of test ports in the insertion loss board can be set in a targeted manner, thereby further improving test efficiency and reducing the test costs required to design the insertion loss board.

[0083] In some embodiments, further comprising:

[0084] If the test results of all groups of test ports in the insertion loss board are consistent, the insertion losses corresponding to several groups of test ports in the insertion loss board are adjusted.

[0085] It is not difficult to understand that if the test results of all groups of test ports on the insertion loss board are consistent, that is, all pass or all fail, the specific insertion loss of the chip under test cannot be determined. In this case, the insertion loss corresponding to the test port group on the insertion loss board needs to be adjusted to effectively determine the specific insertion loss of the chip under test.

[0086] In some embodiments, adjusting insertion losses corresponding to a plurality of groups of test ports in an insertion loss board includes:

[0087] If the test results of all groups of test ports in the insertion loss board are all passed, the insertion losses corresponding to the groups of test ports in the insertion loss board are increased by a first preset value;

[0088] If the test results of all groups of test ports in the insertion loss board are all test failures, the insertion losses corresponding to several groups of test ports in the insertion loss board are reduced by a second preset value.

[0089] It is understandable that multiple insertion loss boards can be designed in advance according to the different situations of insertion loss of other links, and then the insertion loss boards can be replaced according to the actual test requirements and special circumstances of the test results. For example, refer to Table 1 to set up 6 insertion loss boards. When the test results of all groups of test ports in the insertion loss board are all passed, the insertion loss adjustment can be achieved by directly replacing the insertion loss board with a larger insertion loss value; when the test results of all groups of test ports in the insertion loss board are all failed, the insertion loss adjustment can be achieved by directly replacing the insertion loss board with a smaller insertion loss value. It is also possible to design only one insertion loss board for this chip to be tested. When the special situation occurs that the test results of all groups of test ports are consistent, the corresponding insertion loss can be adjusted directly by replacing the signal line or other methods. The signal lines corresponding to all groups of test ports can be replaced simultaneously, or the signal lines of some groups of test ports can be replaced. This application does not make any special restrictions on the specific values ​​of the first preset value and the second preset value.

[0090] Specifically, the insertion loss corresponding to the test port group in the insertion loss board can be adjusted by directly replacing the insertion loss board or adjusting the length of the signal line in the insertion loss board. If the test results cannot determine the insertion loss of the chip under test, more tests can be performed by adjusting the insertion loss corresponding to the test port group in the insertion loss board to ensure the effective implementation of the test and ensure that the test can effectively determine the insertion loss of the chip under test.

[0091] In some embodiments, determining the test result of the current test port group based on the return result of the preset test signal sent by the chip under test includes:

[0092] When the first switch and the second switch are both connected to the switch ends corresponding to the current test port group, the chip under test is controlled to send a preset test signal to the first test port in the current test port group through the signal sending port;

[0093] If the signal receiving port of the chip under test receives a preset test signal returned from the second test port in the current test port group within a preset time period, it is determined that the test of the current test port group has passed;

[0094] If the signal receiving port of the chip under test does not receive the preset test signal returned from the second test port in the current test port group within the preset time period, it is determined that the test of the current test port group has failed.

[0095] It is not difficult to understand that the test result can be directly realized by whether the chip under test receives the preset test signal sent. Therefore, a preset time period can be set to determine the signal reception status of the chip under test, thereby determining the test result. It is simple, effective and easy to implement. When the chip under test can receive the returned preset test signal, it means that the chip under test can support the normal transmission of this preset test signal under the corresponding insertion loss of the current test port group, and the test passes; when the chip under test cannot receive the returned preset test signal, it means that the chip under test cannot support the normal transmission of this preset test signal under the corresponding insertion loss of the current test port group, and the test fails. The processor communicates with the chip under test through the serial port. If the chip under test receives the preset test signal normally, a corresponding confirmation signal is sent to the processor, and the processor can determine the test result based on the confirmation signal. The specific value of the preset time period can be set according to the actual situation of the chip under test, and the communication method between the processor and the chip under test can also be adjusted according to application requirements. This application does not make any special restrictions here.

[0096] In some embodiments, controlling a group of switching terminals corresponding to a first switch and a second switch in an insertion loss test system to be connected to connect the chip to be tested and the current test port group includes:

[0097] Sort the test ports of the insertion loss board in the insertion loss test system in ascending order of corresponding insertion loss to obtain a test sequence;

[0098] Determine the first group of test ports in the test sequence as the current test port group, and control the first switch and the second switch to connect a group of switch ports corresponding to the current test port group;

[0099] If the test result of the current test port group is that the test passes, the next group of test ports in the test sequence is determined as the current test port group, and the process jumps again to the step of controlling the first switch and the second switch to connect to a group of switch ports corresponding to the current test port group, until the test result of the current test port group is that the test fails;

[0100] Determine the insertion loss of the chip under test based on the test results of several groups of test ports and the insertion losses corresponding to the several groups of test ports, including:

[0101] The insertion loss corresponding to the current test port group that passed the last test is determined as the insertion loss of the chip to be tested.

[0102] It is understandable that in order to improve the test efficiency, the tests corresponding to each group of test ports can be carried out in sequence directly according to the order of size after sorting. The test order is not limited to the implementation method in this embodiment, and can also be sorted from large to small. As long as the test order is generated by sorting in a specific way, it is feasible. This application does not make any special restrictions here. Figure 2 The insertion loss test system shown and Figure 3 The insertion loss board design shown can achieve the following Figure 5 In the insertion loss test method shown, the test system starts up, and the processor first controls the first channel connected to the insertion loss board (corresponding to the channel with the lowest insertion loss) to begin testing. If the test passes, the next channel with an insertion loss value of +1dB is connected and tested again until the test fails. The insertion loss value of the chip under test is then calculated by adding the insertion loss value B of the channel that passed the last test to the value of A+C. To ensure the reliability of the chip under test in actual application, the insertion loss value B corresponding to the channel that passed the last test can also be directly determined as the insertion loss value of the chip under test. That is, if the test result of the jth group of test ports is a pass, and the test result of the j+1th group of test ports is a fail, the insertion loss corresponding to the jth group of test ports is determined as the insertion loss of the chip under test. If the insertion loss board selected or the insertion loss corresponding to the designed test port group when setting up the test system is not appropriate, the insertion loss board can be replaced or the insertion loss provided by the insertion loss board can be adjusted before testing again.

[0103] Specifically, by using the insertion loss corresponding to the current test port group that passed the last test as the insertion loss of the chip under test, which is slightly smaller than the insertion loss capability actually supported by the chip under test, reliable signal transmission of the chip under test in actual application is ensured; at the same time, by directly testing in order from small to large, the minimum insertion loss corresponding to the test failure can be quickly and effectively determined, thereby improving test efficiency.

[0104] See also Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. To solve the above technical problems, an embodiment of the present invention further provides an electronic device, including:

[0105] Memory 60, for storing computer programs;

[0106] The processor 61 is configured to execute a computer program to implement the steps of the aforementioned insertion loss testing method.

[0107] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing content required to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor for handling computational operations related to machine learning.

[0108] Memory 60 may include one or more computer-readable storage media, which may be non-transitory. Memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory storage devices. In this embodiment, memory 60 is used to store at least the following computer program 601. After being loaded and executed by processor 61, this computer program can implement the relevant steps of the insertion loss test method disclosed in any of the aforementioned embodiments. Furthermore, resources stored in memory 60 may also include an operating system 602 and data 603, which may be stored in either a temporary or permanent manner. Operating system 602 may include Windows, Unix, Linux, etc. Data 603 may include, but is not limited to, data used in the insertion loss test method.

[0109] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0110] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation of the electronic device, and may include more or fewer components than shown in the figure.

[0111] For descriptions of features in the electronic device provided by the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the insertion loss testing method, which will not be described in detail here.

[0112] It is understood that if the insertion loss test method in the above-mentioned embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard drives, read-only memories (ROM), random access memories (RAM), electrically erasable programmable ROMs, registers, hard drives, removable disks, CD-ROMs, magnetic disks, or optical disks, and other media that can store program code.

[0113] To solve the above technical problems, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above insertion loss test method are implemented.

[0114] For descriptions of features in the computer-readable storage medium provided in the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the insertion loss testing method, which will not be described in detail here.

[0115] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the insertion loss testing method of the above embodiment when executed by a processor.

[0116] For descriptions of features in the computer program product provided by the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the insertion loss testing method, which will not be described in detail here.

[0117] The above provides a detailed introduction to the insertion loss test system, method, device, and medium provided by the embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between the various embodiments can be referenced to each other. The devices disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0118] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0119] The above describes in detail the insertion loss test system, method, device, and medium provided by the present invention. This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art will be able to make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the present invention.

Claims

1. An insertion loss test system, characterized in that: include: An insertion loss board, the insertion loss board comprising a plurality of groups of test ports, wherein the insertion losses corresponding to the plurality of groups of test ports are different from each other; wherein a group of test ports comprises a first test port and a second test port, and the insertion loss corresponding to the group of test ports is the insertion loss between the first test port and the second test port; A first switching switch, a fixed end of which is connected to the signal sending port of the chip under test, wherein the first switching switch includes a plurality of switching ends connected to the plurality of first test ports in a one-to-one correspondence; a second switching switch, a fixed end of which is connected to the signal receiving port of the chip under test, the second switching switch comprising a plurality of switching ends connected in a one-to-one correspondence with the plurality of second test ports; A processor, wherein an output end is connected to the control end of the first switch and the control end of the second switch, respectively, and is used to connect the chip under test to different groups of test ports by controlling the first switch and the second switch, so as to determine the insertion loss of the chip under test based on test results of the groups of test ports and insertion losses corresponding to the groups of test ports.

2. The insertion loss test system according to claim 1, characterized in that: The insertion board is provided with a plurality of signal lines, and the lengths of the plurality of signal lines are different from each other; The first end of the signal line is connected to the switching end corresponding to the first switch through a first test port, and the second end of the signal line is connected to the switching end corresponding to the second switch through a second test port.

3. An insertion loss test method, characterized in that: Applicable to the insertion loss test system as claimed in claim 1 or 2; The insertion loss testing method comprises: Controlling a group of switching terminals corresponding to the first switch and the second switch in the insertion loss test system to be connected, so as to connect the chip to be tested and the current test port group; wherein the current test port group is any group of test ports in the insertion loss board of the insertion loss test system; Determine the test result of the current test port group based on the return result of the preset test signal sent by the chip to be tested; The insertion loss of the chip to be tested is determined according to the test results of the groups of test ports and the insertion losses corresponding to the groups of test ports.

4. The insertion loss testing method according to claim 3, wherein: Also includes: Determine the insertion loss of other links of the chip under test; The insertion loss corresponding to each group of test ports in the insertion loss board is determined according to the difference between the target insertion loss of the chip to be tested and the insertion loss of the other links.

5. The insertion loss testing method according to claim 3, wherein: Also includes: If the test results of all groups of test ports in the insertion loss board are consistent, the insertion losses corresponding to several groups of test ports in the insertion loss board are adjusted.

6. The insertion loss testing method according to claim 5, characterized in that: Adjust the insertion loss corresponding to several groups of test ports on the insertion loss board, including: If the test results of all groups of test ports in the insertion loss board are all passed, increasing the insertion losses corresponding to several groups of test ports in the insertion loss board by a first preset value; If the test results of all groups of test ports in the insertion loss board are all test failures, the insertion losses corresponding to several groups of test ports in the insertion loss board are reduced by a second preset value.

7. The insertion loss testing method according to any one of claims 3 to 6, characterized in that: Determining the test result of the current test port group based on the return result of the preset test signal sent by the chip to be tested includes: When the first switch and the second switch are both connected to the switch ends corresponding to the current test port group, controlling the chip under test to send a preset test signal to the first test port in the current test port group through the signal sending port; If the signal receiving port of the chip under test receives a preset test signal returned from the second test port in the current test port group within a preset time period, it is determined that the test of the current test port group has passed; If the signal receiving port of the chip under test does not receive the preset test signal returned from the second test port in the current test port group within the preset time period, it is determined that the test of the current test port group has failed.

8. The insertion loss testing method according to claim 7, wherein: Controlling a group of switching terminals corresponding to the first switching switch and the second switching switch in the insertion loss test system to be connected to connect the chip to be tested and the current test port group includes: sorting the test ports of the insertion loss board in the insertion loss test system in ascending order of corresponding insertion losses to obtain a test order; Determine the first group of test ports in the test sequence as the current test port group, and control the first switch and the second switch to connect a group of switch ports corresponding to the current test port group; If the test result of the current test port group is that the test passes, the next group of test ports in the test sequence is determined as the current test port group, and the process jumps again to the step of controlling the first switch and the second switch to connect to a group of switch ends corresponding to the current test port group, until the test result of the current test port group is that the test fails; Determining the insertion loss of the chip to be tested according to the test results of the plurality of groups of test ports and the insertion losses corresponding to the plurality of groups of test ports includes: The insertion loss corresponding to the current test port group that passed the last test is determined as the insertion loss of the chip to be tested.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the insertion loss testing method according to any one of claims 3 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the insertion loss testing method according to any one of claims 3 to 8 are implemented.

Images