Wafer bonding packaging method for reducing thinning and edge collapse rate and semiconductor device

Abstract

The application provides a wafer bonding packaging method for reducing the thinning and edge collapse rate and a semiconductor device, and relates to the technical field of wafer bonding packaging. The method comprises the following steps: performing alignment exposure on a substrate wafer coated with photoresist and a packaging top cover wafer by using a special mask; developing the exposed substrate wafer and the packaging top cover wafer, so that the edge photoresist is reserved on the substrate wafer and the packaging top cover wafer as a passivation layer; etching the developed substrate wafer and the packaging top cover wafer, and evaporating a bonding layer on the passivation layer; bonding the substrate wafer and the packaging top cover wafer through the bonding layer to obtain a semi-finished product; and performing thinning treatment on the semi-finished product to obtain a finished product. The method aims to solve the problem that the traditional mask is used for wafer bonding packaging, which easily causes the finished product to have edge collapse and debris abnormalities, avoids the formation of a suspended structure, effectively reduces the edge collapse rate after bonding and thinning, and improves the overall production efficiency and product yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer bonding packaging, in particular to a wafer bonding packaging method for reducing the wafer thinning edge collapse rate and a semiconductor device. BACKGROUND

[0002] In the manufacturing process of a thin film bulk acoustic resonator, wafer level packaging (WLP) is a key step to ensure the stability of resonator performance. In this process, the packaging top cover wafer and the structure layer substrate wafer need to be permanently bonded through high-precision double alignment exposure to form a sealed and oxidation-resistant cavity structure suitable for resonator vibration.

[0003] However, referring to the prior art Figure 2 and the prior art Figure 3 In the mask used in the conventional bonding technology, the non-patterned area is a light-transmitting area, so that after exposure and development, the photoresist on the edge of the wafer corresponding to the non-patterned area is removed, resulting in the collapse of the edge of the wafer after etching, and then the whole wafer has inconsistent height when evaporating the bonding layer, which leads to the formation of a suspended structure at the edge of the wafer after bonding, and these suspended structures are prone to collapse and fragmentation due to external pressure, causing edge collapse and debris during wafer bonding and transportation, which seriously affects the yield and equipment safety.

[0004] At present, there is no effective technical solution to the above problems. SUMMARY

[0005] The present application aims to provide a wafer bonding packaging method for reducing the wafer thinning edge collapse rate and a semiconductor device, which aims to solve the problem of edge collapse and debris in the finished product caused by using the conventional mask for wafer bonding packaging, avoid the formation of suspended structures, effectively reduce the edge collapse rate after bonding and thinning, and improve the overall production efficiency and product yield.

[0006] In a first aspect, the present application provides a wafer bonding packaging method for reducing the wafer thinning edge collapse rate, comprising the following steps:

[0007] A double alignment exposure machine is used to align and expose the substrate wafer and the packaging top cover wafer coated with photoresist using a specially designed mask; the specially designed mask includes a patterned area and a non-patterned area outside the edge of the patterned area, the non-patterned area is provided with a plating layer, and the plating layer is used to block light so that the photoresist on the edge of the substrate wafer and the packaging top cover wafer corresponding to the non-patterned area is not exposed;

[0008] The exposed substrate wafer and the packaging top cover wafer are developed to retain the edge photoresist as a passivation layer on the substrate wafer and the packaging top cover wafer;

[0009] Etching the developed substrate wafer and the packaging top cover wafer, and evaporating a bonding layer on the passivation layer corresponding to the substrate wafer and the packaging top cover wafer respectively;

[0010] Bonding the substrate wafer and the packaging top cover wafer through the bonding layer to obtain a semi-finished product.

[0011] Thinning the semi-finished product to obtain a finished product.

[0012] The wafer bonding packaging method for reducing the thinning edge collapse rate provided by the application can ensure that the edge of the wafer does not collapse, thereby ensuring the uniformity of the overall height of the bonding layer evaporated subsequently, and further avoiding the formation of a suspended structure that is difficult to compress after wafer bonding, greatly reducing the wafer edge collapse risk, and realizing the improvement of overall production efficiency and product yield.

[0013] Further, the plating layer is made of chromium material.

[0014] Plating chromium ensures that the non-patterned area can reliably block light.

[0015] Further, the patterned area serves as a light transmission area and the non-patterned area serves as a light blocking area, and under the action of the plating layer, the optical density difference between the light blocking area and the light transmission area is > 2.5.

[0016] Further, the thickness of the photoresist coated on the substrate wafer and the packaging top cover wafer is > 12 μm.

[0017] Further, the double-side alignment deviation of the double-side alignment exposure machine is < 1 μm.

[0018] Further, the bonding layer is made of gold material.

[0019] Further, the step of bonding the substrate wafer and the packaging top cover wafer through the bonding layer to obtain a semi-finished product includes:

[0020] Controlling the temperature range of the bonding environment to be 300-400℃, the bonding pressure to be > 6MPa, and the annealing time to be > 30min, bonding the substrate wafer and the packaging top cover wafer through the bonding layer to obtain the semi-finished product.

[0021] A support structure is constructed at the bonding interface. The support structure resists external stress generated by the grinding wheel during the thinning process. Reduces the risk of wafer edge collapse or fragmentation.

[0022] Further, the step of thinning the semi-finished product to obtain a finished product includes:

[0023] The thickness of the substrate wafer and the package top cover wafer in the semi-finished product is thinned to within 150 μm by using a grinding wheel.

[0024] Further, the rotating speed of the grinding wheel is controlled in the range of 2000-4500 rpm and the feeding speed is < 3 μm / s.

[0025] In the second aspect, the application provides a semiconductor device made by the wafer bonding and packaging method for reducing the thinning edge collapse rate as described above.

[0026] As can be seen from the above, the wafer bonding and packaging method for reducing the thinning edge collapse rate provided by the application increases the chrome plating layer in the non-pattern area of the edge, so that the area cannot be exposed in the exposure process. This design ensures that all the photoresist in the edge removal area is retained after development, thereby preventing the downward etching of the substrate silicon in the area and maintaining the integrity of the wafer edge. Under the passivation protection of the photoresist in the edge area, high flatness of the bottom silicon of the bonding surface is achieved (to ensure the uniform height of the whole surface). Since the edge is not etched, the bonding layer after evaporation forms uniform support at the wafer edge, ensuring the horizontal consistency of the bonding interface and avoiding the formation of a suspended structure, greatly reducing the risk of edge collapse and fragmentation during thinning and transfer, effectively ensuring the yield of wafer production and the safety of the equipment, and achieving the improvement of overall production efficiency and product yield.

[0027] Other features and advantages of the application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application as described in the written description and claims. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A flow chart of the wafer bonding and packaging method for reducing the thinning edge collapse rate provided by the embodiment of the application.

[0029] Figure 2 A structural schematic diagram of a mask used by a traditional bonding technology.

[0030] Figure 3 A structural schematic diagram of a finished product formed by a traditional bonding technology.

[0031] Figure 4 A structural schematic diagram of a special mask used by the embodiment of the application.

[0032] Figure 5 A structural schematic diagram of a finished product after wafer bonding of the embodiment of the application.

[0033] Label explanation:

[0034] 100, graphic area; 200, non-graphic area; 300, package top cover wafer; 400, overhanging structure; 500, bonding layer; 600, substrate wafer. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0036] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0037] With reference to the accompanying drawings of Figure 1 , the accompanying drawings of Figure 4 , and the accompanying drawings of Figure 5 , the present application provides a wafer bonding packaging method for reducing the edge collapse rate, comprising the following steps:

[0038] A double-side alignment exposure machine is used, and a specially-made mask is used for alignment exposure of the substrate wafer coated with photoresist and the package top cover wafer. The specially-made mask includes a graphic area and a non-graphic area located outside the edge of the graphic area. The non-graphic area is provided with a plating layer made of a material with high light shielding performance, and the plating layer is used to block light so as to avoid exposure of the edge photoresist on the substrate wafer and the package top cover wafer corresponding to the non-graphic area. The graphic area and the non-graphic area of the conventional mask are both light transmission areas. In the present application, the plating layer is formed on the non-graphic area to change the non-graphic area into a light shielding area, thereby avoiding exposure of the edge photoresist, and avoiding the subsequent overhanging structure caused by etching of the edge, which further leads to collapse or fragmentation of the wafer (i.e. causing edge collapse) due to external pressure (especially the external force generated by the grinding wheel during subsequent thinning process);

[0039] The substrate wafer and the packaging top cover wafer after exposure are developed, so that the edge photoresist is retained as a passivation layer on the substrate wafer and the packaging top cover wafer; under the passivation protection of the photoresist in the edge area, high flatness of the bottom silicon of the bonding surface is realized (to ensure the uniform height of the whole surface); since the edge is not etched, the bonding layer after evaporation forms a uniform support at the edge of the wafer, ensuring the horizontal consistency of the bonding interface and avoiding the formation of a suspended structure;

[0040] The substrate wafer and the packaging top cover wafer after development are etched, and a bonding layer is evaporated on the corresponding passivation layer of the substrate wafer and the packaging top cover wafer;

[0041] The substrate wafer and the packaging top cover wafer are bonded through the bonding layer to obtain a semi-finished product;

[0042] The semi-finished product is thinned to obtain a finished product.

[0043] The method solves the problem of wafer edge collapse by changing the design of the exposure mask. First, a double-side alignment exposure machine is used to align and expose the substrate wafer 600 and the packaging top cover wafer 300 coated with photoresist. A special mask is used here. The special mask includes a pattern area 100 and a non-pattern area 200. Unlike traditional masks, the non-pattern area 200 of the special mask is provided with a plating layer. The plating layer is made of high light-blocking material. The function of the plating layer is to block light. This makes the photoresist in the edge area of the substrate wafer 600 and the packaging top cover wafer 300 corresponding to the non-pattern area 200 not be exposed. In the subsequent development step, the unexposed edge photoresist is retained to form a passivation layer. In the etching step, the retained edge photoresist passivation layer protects the edge area of the wafer to prevent the edge from being etched. This ensures the flatness of the bottom silicon of the bonding surface. Since the edge is not etched, when the bonding layer 500 is evaporated later, the bonding layer 500 forms a support structure at the edge of the wafer. This ensures the horizontal consistency of the bonding interface and avoids the suspended structure 400 caused by edge collapse in the traditional method. The substrate wafer 600 and the packaging top cover wafer 300 are bonded through the bonding layer 500 to form a semi-finished product. Finally, the semi-finished product is thinned. Since the edge structure is stable and there is no suspended structure 400, the wafer's resistance to external pressure during thinning and subsequent processing is enhanced, thereby reducing the risk of edge collapse and cracking. The plating layer on the special mask is the key to retaining the edge photoresist, the edge photoresist as a passivation layer is the key to preventing edge etching collapse, and the stability of the edge structure is the key to reducing the thinning edge collapse rate.

[0044] Specifically, in the manufacturing process of the film bulk acoustic resonator, the wafer-level vacuum bonding packaging is a key step to ensure the stability of the resonator performance. In the mask used in the traditional bonding technology, the non-patterned area 200 is a light-transmitting area, so that after the exposure and development process, the photoresist on the edge of the wafer corresponding to the non-patterned area 200 is removed, thereby causing the edge of the wafer to collapse after the etching process, and further causing the wafer to have inconsistent height when evaporating the bonding layer 500, resulting in the formation of a suspended structure 400 at the edge of the wafer after bonding. These suspended structures 400 are extremely prone to collapse and fragmentation due to external pressure, causing edge collapse and debris during wafer bonding and transportation, which seriously affects the yield of the wafer and the safety of the equipment. The method of the present application solves the above problems by using a specially designed mask. The mask has a plating layer with high light-blocking performance in the non-patterned area 200. When using the mask for double-side alignment exposure, the plating layer blocks the light, so that the photoresist on the edge of the substrate wafer 600 and the packaging top cover wafer 300 is not exposed. Subsequently, the unexposed edge photoresist is retained to form a passivation layer. In the subsequent etching step, the retained edge photoresist passivation layer protects the edge of the wafer, preventing the edge material from being etched away, thereby ensuring the flatness of the bonding surface bottom silicon. Since the edge is not etched, when the bonding layer 500 is evaporated on the surface of the wafer in the subsequent step, the bonding layer 500 forms a uniform support structure in the edge area of the wafer. This uniform support ensures the horizontal consistency of the bonding interface, avoiding the suspended structure 400 caused by edge collapse in the traditional method. Finally, the substrate wafer 600 and the packaging top cover wafer 300 are bonded through the bonding layer 500 to form a semi-finished product. When the semi-finished product is thinned, the edge structure is stable and supported by the bonding layer 500, the ability of the wafer to resist external pressure is improved, especially the external force generated by the grinding wheel during the subsequent thinning process, thereby effectively reducing the risk of wafer collapse or fragmentation, i.e. reducing the thinning edge collapse rate.

[0045] In some embodiments, the plating layer is made of chromium material. The chromium material has absorption or reflection effect on the light of the exposure wavelength. The chromium plating ensures that the non-patterned area can reliably block the light.

[0046] In some embodiments, the patterned area is a light-transmitting area and the non-patterned area is a light-blocking area, and under the action of the plating layer, the optical density difference between the light-blocking area and the light-transmitting area is > 2.5.

[0047] In some embodiments, the thickness of the photoresist coated on the substrate wafer and the packaging top cover wafer is > 12 μm.

[0048] In some embodiments, the double-side alignment deviation of the double-side alignment exposure machine is < 1 μm.

[0049] In some embodiments, the bonding layer is made of gold material.

[0050] In some embodiments, the step of bonding the substrate wafer and the package top cover wafer through the bonding layer to obtain a semi-finished product comprises:

[0051] The temperature range of the bonding environment is controlled to be 300-400℃, the bonding pressure is >6MPa, and the annealing time is >30min, and the substrate wafer and the package top cover wafer are gold-gold thermocompression bonded through the bonding layer to obtain a semi-finished product; the gold-gold thermocompression bonding forms a stable support structure, which can effectively resist external pressure even when the substrate is thinned to below 150μm, greatly reducing the risk of edge collapse and fragmentation during thinning and transportation.

[0052] The gold-gold thermocompression bonding is achieved through heat and pressure. The gold surface atoms diffuse and recrystallize to form a metal bond. The temperature is in the range of 300-400℃, which provides energy to promote atomic diffusion. The pressure is greater than 6MPa, which makes the gold layer surface contact. The annealing time is greater than 30 minutes, which provides time for atomic diffusion and bond interface formation. These conditions enable the gold-gold bond interface to form a connection and build a support structure.

[0053] Specifically, after the substrate wafer and the package top cover wafer are bonded through the bonding layer to form a semi-finished product, the structure formed by bonding has insufficient resistance to external pressure during subsequent thinning processing, resulting in edge collapse and fragmentation. Gold-gold thermocompression bonding is used, with the bonding environment temperature controlled to be 300-400℃, the bonding pressure greater than 6MPa, and the annealing time greater than 30min. Gold-gold thermocompression bonding forms a metal connection between the gold layers on the substrate wafer and the package top cover wafer. A support structure is built at the bonding interface. This support structure resists external stress generated by the grinding wheel during thinning processing. It reduces the risk of wafer edge collapse or fragmentation.

[0054] In some embodiments, the step of thinning the semi-finished product to obtain a finished product comprises:

[0055] The thickness of the substrate wafer and the package top cover wafer in the semi-finished product is thinned to within 150μm using a grinding wheel.

[0056] In some embodiments, the rotational speed of the grinding wheel is controlled to be in the range of 2000-4500rpm and the feed speed is <3μm / s.

[0057] The present application provides a semiconductor device made by the wafer bonding and packaging method for reducing thinning edge collapse rate as described in the above embodiments.

[0058] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0059] The above merely illustrates the embodiments of the present application but should not be taken as limitations to the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A wafer bonding and packaging method for reducing thinning edge breakage rate, characterized in that, Includes the following steps: A double-sided alignment exposure machine is used, and a special mask is employed to align and expose a substrate wafer coated with photoresist and a package top cover wafer. The special mask includes a patterned area and a non-patterned area located outside the edge of the patterned area. The non-patterned area is provided with a coating layer, which is used to block light so that the edge photoresist on the substrate wafer and the package top cover wafer corresponding to the non-patterned area is prevented from being exposed. The exposed substrate wafer and the package top cover wafer are developed so that the edge photoresist is retained on the substrate wafer and the package top cover wafer as a passivation layer; The developed substrate wafer and the package top cover wafer are etched, and bonding layers are deposited on the passivation layers corresponding to the substrate wafer and the package top cover wafer, respectively. The substrate wafer and the package top cover wafer are bonded together through the bonding layer to obtain a semi-finished product; The semi-finished product is thinned to obtain the finished product.

2. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The coating is made of chromium.

3. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The patterned area serves as the light-transmitting area, and the non-patterned area serves as the light-shielding area. Under the action of the coating, the optical density difference between the light-shielding area and the light-transmitting area is >2.

5.

4. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The thickness of the photoresist coated on the substrate wafer and the package top cover wafer is >12μm.

5. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The double-sided alignment deviation of the double-sided alignment exposure machine is <1μm.

6. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The bonding layer is made of gold.

7. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 6, characterized in that, The steps of bonding the substrate wafer to the package top cover wafer through the bonding layer to obtain the semi-finished product include: The bonding environment is controlled within the temperature range of 300-400℃, the bonding pressure is >6MPa, and the annealing time is >30min. Through the bonding layer, the substrate wafer and the package top cover wafer are subjected to gold-gold thermo-press bonding to obtain the semi-finished product.

8. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 1, characterized in that, The steps for thinning the semi-finished product to obtain the finished product include: The thickness of the substrate wafer and the package top cover wafer in the semi-finished product is reduced to less than 150 μm using a grinding wheel.

9. The wafer bonding and packaging method for reducing thinning edge breakage rate according to claim 8, characterized in that, The rotational speed of the grinding wheel is controlled within the range of 2000-4500 rpm and the feed rate is <3μm / s.

10. A semiconductor device, characterized in that, It is manufactured using the wafer bonding and packaging method for reducing thinning edge breakage rate as described in any one of claims 1-9.

Images