Clock frequency adjusting circuit

Abstract

A clock frequency adjusting circuit comprises a storage circuit, a frequency detection circuit and a clock management circuit. The storage circuit is used for storing data according to an input clock and outputting the data according to an output clock. The frequency detection circuit is coupled to the storage circuit and is used for detecting the change amount of the storage space of the storage circuit and generating a frequency detection result according to the change amount. The clock management unit is coupled to the frequency detection circuit and is used for adjusting the frequency of the output clock according to the frequency detection result.

Description

Technical Field

[0001] The present invention relates to a clock frequency regulating circuit, and in particular to a clock frequency regulating circuit which adaptively regulates the frequency of an output clock according to changes in storage space. Background Art

[0002] After long-distance transmission, signals degrade. A retimer is used to receive and restore the degraded signal. A retimer is a mixed-signal analog / digital device that is protocol-aware and can extract the clock to fully recover the data and transmit a fresh copy of the data using a clean clock. In short, a retimer can fully recover the data and send a fresh copy.

[0003] Generally speaking, a retimer must switch the transmit clock (or output clock) to the receive clock (or input clock) to achieve frequency homology, thereby reducing the size of the buffer required to compensate for receive / transmit clock frequency deviation and shrinking the overall circuit area.

[0004] However, if there's a significant frequency difference between the transmit and receive clocks during the clock switching process, this can cause a significant frequency change in the transmit clock at the instant of switching, potentially preventing the downstream receiving device from correctly receiving the data output by the retimer. Furthermore, using the receive clock as the transmit clock causes the retimer's output signal to carry over the frequency perturbations of the retimer's input signal, degrading the output signal's quality. Summary of the Invention

[0005] One of the objectives of the present disclosure is to provide a clock frequency adjustment circuit applicable to a retimer to avoid the problems of the prior art.

[0006] An embodiment of the clock frequency adjustment circuit disclosed herein includes a storage circuit, a frequency detection circuit, and a clock management circuit. The storage circuit is used to store data according to an input clock and output the data according to an output clock. The frequency detection circuit is coupled to the storage circuit and is used to detect the change in the storage space of the storage circuit and generate a frequency detection result accordingly. The clock management unit is coupled to the frequency detection circuit and is used to adjust the frequency of the output clock according to the frequency detection result. For example: the frequency detection circuit determines which of a plurality of change intervals the change falls within; when the change falls within a first change interval of the plurality of change intervals, the frequency detection circuit generates the frequency detection result to request the clock management unit to adjust the frequency of the output clock according to a first adjustment amount; and when the change falls within a second change interval of the plurality of change intervals, the frequency detection circuit generates the frequency detection result to request the clock management unit to adjust the frequency of the output clock according to a second adjustment amount.

[0007] The features, practical operation and effects of the present invention are described in detail below with reference to preferred embodiments thereof with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An embodiment of the clock frequency adjustment circuit disclosed herein is shown; and

[0009] Figure 2 The change of the deviation of the frequency of the input clock, the adjustment of the frequency of the output clock, and the change of the water level of the storage circuit are displayed. DETAILED DESCRIPTION

[0010] This specification discloses a clock frequency adjustment circuit that can adaptively adjust the frequency of an output clock according to changes in storage space and can be applied to a retimer.

[0011] Figure 1 An embodiment of the clock frequency adjustment circuit disclosed in the present invention is shown. Figure 1 As shown, the clock frequency adjustment circuit 100 includes a storage circuit 110 , a frequency detection circuit 120 , a water level detection circuit 130 and a clock management unit (CMU) 140 .

[0012] refer to Figure 1 The storage circuit 110 is a circuit having a memory function such as a static random access memory (SRAM), a first-in-first-out buffer (FIFO) or a counter, which is used to store data according to an input clock CLK IN Store data and output clock CLK OUTThe frequency detection circuit 120 is coupled to the storage circuit 110 and is used to detect the change in the storage space (not shown in the figure) of the storage circuit 110 (for example, the change in the used storage capacity of the storage space over a period of time) and generate a frequency detection result DET accordingly. FREQ The water level detection circuit 130 is coupled to the storage circuit 110 and the CMU 140 to detect the used storage capacity (hereinafter referred to as the water level) of the storage space of the storage circuit 110 and generate a water level detection result DET accordingly. WL The CMU 140 is coupled to the frequency detection circuit 120 and the water level detection circuit 130 to detect the water level according to the frequency detection result DET FREQ With the water level detection result DET WL Adjust the output clock CLK OUT It is worth noting that, in this specification, the water level can be interpreted as being equal to the remaining storage capacity of the storage space. It is also worth noting that, without considering performance, the water level detection circuit 130 can be selectively disabled or omitted.

[0013] Figure 2 Displays the input clock CLK IN The frequency deviation of the output clock CLK OUT The frequency of the input clock CLK is adjusted and the water level of the storage circuit 110 changes. IN The frequency deviation of the output clock CLK OUT The unit of frequency adjustment is parts per million (ppm), which can be used to express the deviation from a specific center frequency. Figure 2 As shown: The input clock CLK IN The frequency deviation of the storage circuit 110 changes periodically; before a time point T0, the water level of the storage circuit 110 is zero (or in an alternative embodiment, the water level is a non-zero fixed water level), and after the time point T0, the water level changes with the input clock CLK IN With the output clock CLK OUT After the time point T0, the output clock CLK OUT The frequency deviation of CLK changes with the water level so that the water level converges toward a predetermined level. OUT The higher the frequency of the output clock CLK, the lower the water level will be. OUT The lower the frequency, the water level will gradually rise.

[0014] refer to Figure 2 , time points T0~T 10It defines 10 time intervals: T0~T1, T1~T2, ..., T8~T9 and T9~T 10 In each time interval, the water level of the storage circuit 110 changes. More specifically, the water level at the beginning of each time interval (e.g., T0) and the water level at the end of the time interval (e.g., T1) can be used together to determine the change in the water level in the time interval, and the water level at the end of each time interval can be used to represent the water level in the time interval. However, this is not a limitation of the present invention.

[0015] Tables 1 to 3 below show how the clock frequency adjustment circuit 100 adjusts the output clock CLK according to the change in the water level of the storage circuit 110 and the water level of the storage circuit 110. OUT frequency.

[0016] Table 1

[0017]

[0018]

[0019] Table 2

[0020] water level WL1 WL2 WL3 WL4 Water level range 100％～75％ 75％～50％ 50％～25％ 25％～0％ <![CDATA[DET WL ]]> +250ppm +125ppm -125ppm -250ppm

[0021] Table 3

[0022]

[0023] Refer to Table 1 and Figure 2 When the frequency detection circuit 120 detects a change in the water level of the storage circuit 110 within a time interval (for example, the water level at the end of the time interval (hereinafter referred to as WL NOW ) minus the water level at the start of the time interval (hereinafter referred to as WL BEFORE ), or (WL NOW -WL BEFORE ) is multiplied by a weight value, wherein the weight value may be determined based on the previous frequency detection result DET FREQ When the frequency detection circuit 120 is greater than the threshold value 2000ppm / 1000ppm / 500ppm / 250ppm, the frequency detection circuit 120 generates the corresponding frequency detection result DET FREQ (ie, F1 / F2 / F3 / F4 in Table 1) to require the CMU 140 to adjust the output clock CLK OUTThe frequency deviation is +1000ppm / +500ppm / +250ppm / +125ppm, wherein the symbol “ / ” represents “or” and is used to avoid repeated and redundant descriptions; when the frequency detection circuit 120 detects the change of the water level within a time interval (for example: (WL NOW -WL BEFORE ), or (WL NOW -WL BEFORE ) is multiplied by a weight value, wherein the weight value may be determined based on the previous frequency detection result DET FREQ When the frequency detection circuit 120 is less than the threshold value 250ppm / 500ppm / 1000ppm / 2000ppm, the frequency detection circuit 120 generates the corresponding frequency detection result DET FREQ (ie, F5 / F6 / F7 / F8 in Table 1) to require the CMU 140 to adjust the output clock CLK OUT The frequency reaches -125ppm / -250ppm / -500ppm / -1000ppm.

[0024] It is worth noting that, as shown in Table 1, the threshold values ​​described above constitute multiple variation intervals: ">2000ppm", ">1000ppm", ..., "<1000ppm", and "<2000ppm". The frequency detection circuit 120 can determine the range within which the water level change falls according to the order of these multiple variation intervals (i.e., from ">2000ppm" to "<2000ppm"). It is also worth noting that, depending on implementation requirements, more refined / coarse variation intervals can be used, and the degree of frequency adjustment corresponding to each variation interval can be determined based on implementation requirements.

[0025] Refer to Table 2 and Figure 2 When the water level detection circuit 130 detects the water level of the storage circuit 110 within a time interval (eg, WL NOW ,or ) is between the water level range of 100% to 75% / 75% to 50%, the water level detection circuit 130 generates the corresponding water level detection result DET WL (ie, WL1 / WL2 in Table 2) to require CMU 140 to adjust the output clock CLK OUT The frequency reaches +250ppm / +125ppm; when the water level detection circuit 130 detects the water level within a time interval (for example: WL NOW ,or ) is between the water level range of 50% to 25% / 25% to 0%, the water level detection circuit 130 generates the corresponding water level detection result DET WL (ie, WL3 / WL4 in Table 2) to require CMU 140 to adjust the output clock CLKOUT The frequency reaches -125ppm / -250ppm.

[0026] It is worth noting that, depending on implementation requirements, a more refined or coarse plurality of water level intervals may be employed, and the degree of frequency adjustment corresponding to each water level interval may be determined based on implementation requirements. It is also worth noting that the number of intervals in the plurality of water level intervals (e.g., a total of four water level intervals in Table 2) is less than the number of intervals in the aforementioned plurality of variable intervals (e.g., a total of eight variable intervals in Table 1), but this is not a limitation of the present invention.

[0027] Referring to Table 3, CMU 140 detects the frequency DET according to Table 1. FREQ Compared with the water level detection results in Table 2 WL To adjust the output clock CLK OUT In detail:

[0028] At time point T1: the frequency detection circuit 120 can detect the water level (WL NOW ) is considered as the previous water level (WL BEFORE ), thereby not requiring CMU 140 to adjust the output clock CLK OUT The frequency detection circuit 120 may also require the CMU 140 to adjust the output clock CLK according to a preset rule (eg, the difference between the water level at the time point T1 and a preset water level). OUT In the example of Table 3, the water level detection circuit 130 detects that the water level at the time point T1 is between 50% and 25%, and generates the corresponding water level detection result DET. WL (ie, WL3 in Table 2) to require CMU 140 to adjust the output clock CLK OUT The frequency reaches -125ppm.

[0029] At time point T2: the frequency detection circuit 120 detects that the change in the water level is less than 1000ppm but greater than 500ppm, and thus generates the corresponding frequency detection result DET FREQ (ie: F3 in Table 1) to require CMU 140 to adjust the output clock CLK OUT The frequency reaches +250ppm; at this time, the water level detection circuit 130 detects that the water level at the time point T2 is between 75% and 50%, so the corresponding water level detection result DET is generated. WL (ie, WL2 in Table 2) to require CMU 140 to adjust the output clock CLK OUT The frequency reaches +125ppm. As described above, CMU 140 adjusts the output clock CLK according to the two detection results. OUTThe frequency reaches +375ppm.

[0030] The remaining time points T3~T 10 The adjustment method can be based on Table 1 to Table 3. Figure 2 And so on with the above description.

[0031] refer to Figure 1 and Figure 2 In one embodiment, the storage circuit 110 is configured to receive the input clock CLK IN After storing the data for a first period of time, the frequency detection circuit 120 begins to detect changes in the storage space of the storage circuit 110. The first period of time may be determined according to design / implementation requirements. Similarly, the storage circuit 110 generates a signal based on the input clock CLK. IN After storing the data for a second period of time, the water level detection circuit 130 starts to detect the water level of the storage space of the storage circuit 110, wherein the second period of time may be determined according to design / implementation requirements. It is worth noting that the frequency detection circuit 120 and / or the water level detection circuit 130 may also selectively detect the water level of the storage space of the storage circuit 110 according to the input clock CLK IN When the data is stored (ie at the time point T START ), that is, start their detection. It is also worth noting that when the time interval used for sampling (ie: T0~T1, T1~T2, T2~T3, etc.) is much smaller than the input clock CLK IN cycle, the output clock CLK OUT The period is approximately equal to the input clock CLK IN However, this is not a limitation of the present invention.

[0032] Please note that, provided that the implementation is feasible, persons of ordinary skill in the art may selectively implement some or all of the technical features in any of the aforementioned embodiments, or selectively implement a combination of some or all of the technical features in the aforementioned multiple embodiments, thereby increasing the flexibility of the implementation of the present invention.

[0033] In summary, the clock frequency adjustment circuit disclosed in the present invention can adaptively adjust the frequency of the output clock according to changes in storage space, and can be applied to retimers or other devices requiring clock frequency adjustment.

[0034] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

[0035]

Explanation of symbols

[0036] 100: Clock frequency adjustment circuit

[0037] 110: Storage Circuit

[0038] 120: Frequency detection circuit

[0039] 130: Water level detection circuit

[0040] 140: Clock Management Unit (CMU)

[0041] CLK IN : Input clock

[0042] CLK OUT : Output clock

[0043] DET FREQ : Frequency detection results

[0044] DET WL : Water level detection results

[0045] T START : Time point

[0046] T0~T 10 : time point.

Claims

1. A clock frequency adjustment circuit, comprising: a storage circuit for storing data according to an input clock and outputting the data according to an output clock; a frequency detection circuit coupled to the storage circuit, for detecting a change in a storage space of the storage circuit and generating a frequency detection result accordingly; and A clock management unit is coupled to the frequency detection circuit and is used for adjusting a frequency of the output clock according to the frequency detection result.

2. The clock frequency adjustment circuit according to claim 1, wherein: After the storage circuit stores the data for a period of time according to the input clock, the frequency detection circuit starts to detect the change in the storage space of the storage circuit.

3. The clock frequency adjustment circuit according to claim 1, wherein: The frequency detection circuit determines which of multiple change intervals the change amount falls within; when the change amount falls within a first change interval of the multiple change intervals, the frequency detection circuit generates the frequency detection result to request the clock management unit to adjust the frequency of the output clock according to a first adjustment amount; and when the change amount falls within a second change interval of the multiple change intervals, the frequency detection circuit generates the frequency detection result to request the clock management unit to adjust the frequency of the output clock according to a second adjustment amount.

4. The clock frequency adjustment circuit according to claim 3, further comprising: A water level detection circuit is coupled to the storage circuit and the clock management unit, and is used to detect a used storage amount of the storage space of the storage circuit and generate a water level detection result accordingly. The clock management unit is further configured to adjust the frequency of the output clock according to the water level detection result.

5. The clock frequency adjustment circuit according to claim 4, wherein: After the storage circuit stores the data for a period of time according to the input clock, the water level detection circuit begins to detect the used storage amount of the storage space of the storage circuit.

6. The clock frequency adjustment circuit according to claim 4, wherein the water level detection circuit determines which of multiple water level intervals the used storage capacity falls within; when the used storage capacity falls within a first water level interval of the multiple water level intervals, the water level detection circuit generates the water level detection result to request the clock management unit to adjust the frequency of the output clock according to a third adjustment amount; and when the used storage capacity falls within a second water level interval of the multiple water level intervals, the water level detection circuit generates the water level detection result to request the clock management unit to adjust the frequency of the output clock according to a fourth adjustment amount.

7. The clock frequency adjustment circuit according to claim 6, wherein: The number of intervals of the plurality of water level intervals is less than the number of intervals of the plurality of change intervals.

8. The clock frequency adjustment circuit according to claim 1, further comprising: A water level detection circuit is coupled to the storage circuit and the clock management unit, and is used to detect a used storage amount of the storage space of the storage circuit and generate a water level detection result accordingly. The clock management unit is further configured to adjust the frequency of the output clock according to the water level detection result.

9. The clock frequency adjustment circuit according to claim 8, wherein: After the storage circuit stores the data for a period of time according to the input clock, the water level detection circuit begins to detect the used storage amount of the storage space of the storage circuit.

10. The clock frequency adjustment circuit according to claim 8, wherein: The water level detection circuit determines which of multiple water level intervals the used storage capacity falls within; when the used storage capacity falls within a first water level interval of the multiple water level intervals, the water level detection circuit generates the water level detection result to request the clock management unit to adjust the frequency of the output clock according to a first adjustment amount; and when the used storage capacity falls within a second water level interval of the multiple water level intervals, the water level detection circuit generates the water level detection result to request the clock management unit to adjust the frequency of the output clock according to a second adjustment amount.

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