Mainboard fault detection method, device and equipment and storage medium

Abstract

The invention relates to the technical field of fault detection, and discloses a mainboard fault detection method, device and equipment and a storage medium, and the method comprises the steps: carrying out the electromagnetic field scanning of a to-be-detected mainboard, and obtaining electromagnetic field frequency spectrum original data; performing feature extraction on the electromagnetic field frequency spectrum original data to obtain a frequency spectrum fingerprint feature vector; performing multi-level nonlinear propagation modeling on a mainboard circuit system of the mainboard to be detected according to the frequency spectrum fingerprint feature vector, and generating a frequency spectrum fingerprint propagation parameter combination comprising a CPU clock harmonic interference propagation parameter, a power module switching noise propagation parameter and a DDR memory signal crosstalk propagation parameter; and performing fault source space positioning on the to-be-detected mainboard based on the frequency spectrum fingerprint propagation parameter combination to obtain a fault source space positioning result, thereby enhancing the identification capability and analysis precision of fault features, and realizing accurate traceability identification of mainboard faults.

Description

Technical Field

[0001] The present invention relates to the technical field of fault detection, and in particular to a mainboard fault detection method, device, equipment and storage medium. Background Art

[0002] Traditional motherboard fault detection methods rely primarily on electromagnetic signal scanning in a single frequency band or fixed threshold judgment mechanisms. These methods are inadequate in the complex electromagnetic environment of modern motherboards. Because modern motherboards integrate multiple high-frequency circuit modules, such as the CPU, memory, and power management, these modules experience significant electromagnetic interference and signal crosstalk. Traditional detection methods are unable to effectively distinguish between normal operating signals and fault signals, resulting in a high rate of false positives.

[0003] Existing technologies have significant defects in locating the source of faults. Most detection methods can only determine whether there is a fault on the motherboard, but cannot accurately determine the specific physical location of the fault source. Summary of the Invention

[0004] The present invention provides a mainboard fault detection method, device, equipment and storage medium, which enhance the recognition capability and analysis accuracy of fault characteristics and realize accurate tracing and identification of mainboard faults.

[0005] In a first aspect, the present invention provides a method for detecting a mainboard fault, the method comprising: Perform electromagnetic field scanning on the motherboard to be tested to obtain the original data of the electromagnetic field spectrum; Extracting features from the original electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector; Performing multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector, generating a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; The fault source spatial location is performed on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial location result.

[0006] In combination with the first aspect, in a first implementation of the first aspect of the present invention, performing electromagnetic field scanning on the motherboard to be detected to obtain raw electromagnetic field spectrum data includes: An electromagnetic sensor array is set up on the motherboard to be detected and frequency band scanning parameters are configured, and multi-band electromagnetic signals of the motherboard to be detected are synchronously collected based on the frequency band scanning parameters to obtain multi-band electromagnetic signal collection data containing electromagnetic radiation signals of multiple discrete frequencies; Performing electromagnetic radiation correction on the PCB trace geometry of the motherboard to be tested based on the multi-band electromagnetic signal acquisition data to obtain electromagnetic signal geometry correction data; The electromagnetic signal geometric correction data is reconstructed into a spectrum matrix to obtain the original electromagnetic field spectrum data.

[0007] In combination with the first aspect, in a second implementation of the first aspect of the present invention, extracting features from the original electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector includes: Inputting the electromagnetic field spectrum raw data into a wavelet packet decomposition algorithm to perform multi-level spectrum decomposition to obtain wavelet packet decomposition data containing multiple sub-bands; Performing energy distribution calculation, standard deviation calculation and mean calculation on each sub-band according to the wavelet packet decomposition data to obtain a multidimensional feature parameter set including energy distribution coefficient, standard deviation coefficient and mean coefficient; Performing principal component analysis and weight coefficient assignment on the multidimensional feature parameter set to obtain a target feature parameter combination; The target characteristic parameter combination is normalized and a characteristic vector is reconstructed to obtain a spectrum fingerprint characteristic vector.

[0008] In combination with the first aspect, in a third implementation of the first aspect of the present invention, multi-level nonlinear propagation modeling is performed on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector to generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters, including: Based on the spectrum fingerprint feature vector, a harmonic interference propagation model is performed on the CPU clock circuit of the motherboard circuit system in the motherboard to be detected, and a CPU clock harmonic interference propagation parameter including a harmonic frequency sequence and an interference intensity value is obtained; Based on the spectrum fingerprint feature vector, noise propagation modeling is performed on the power module switch circuit of the motherboard circuit system in the motherboard to be detected, and power module switch noise propagation parameters including noise intensity coefficient and spectrum attenuation index are obtained; Based on the spectrum fingerprint feature vector, a signal crosstalk propagation model is performed on the DDR memory circuit of the motherboard circuit system in the motherboard to be detected to obtain DDR memory signal crosstalk propagation parameters; The CPU clock harmonic interference propagation parameter, the power module switching noise propagation parameter and the DDR memory signal crosstalk propagation parameter are subjected to multi-level superposition operation and nonlinear coupling to obtain a spectrum fingerprint propagation parameter combination.

[0009] In combination with the first aspect, in a fourth implementation of the first aspect of the present invention, performing noise propagation modeling on the power module switch circuit of the motherboard circuit system in the motherboard to be detected based on the spectrum fingerprint feature vector to obtain power module switch noise propagation parameters including a noise intensity coefficient and a spectrum attenuation index includes: Extracting a power module frequency component based on the spectrum fingerprint feature vector, and performing switching frequency identification on a power module switch circuit of a mainboard circuit system in the mainboard to be detected based on the power module frequency component to obtain power module switching frequency feature data; Calculating the noise intensity of the power module switching circuit according to the power module switching frequency characteristic data to obtain a power supply noise intensity coefficient; Calculating a roll-off index of a spectrum attenuation characteristic of a switching circuit of the power module based on the power supply noise intensity coefficient to obtain a power supply noise spectrum attenuation index; The switching noise propagation parameters of the power module are obtained by performing a switching noise propagation analysis on the switching frequency characteristic data of the power module, the power supply noise intensity coefficient, and the power supply noise spectrum attenuation index.

[0010] In combination with the first aspect, in a fifth implementation of the first aspect of the present invention, the performing of spatial location of the fault source on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial location result includes: Establishing a three-dimensional space coordinate system and dividing the motherboard to be inspected into grid units to obtain a plurality of grid units; The local spectrum fingerprint template of each grid unit is constructed according to the spatial propagation attenuation characteristics of the spectrum fingerprint propagation parameter combination to obtain the spatial distribution model of the fault source; Performing template matching calculation on the spectrum fingerprint of the motherboard to be detected according to the fault source spatial distribution model to obtain the spectrum fingerprint matching degree; The spectrum fingerprint matching degree is input into the Bayesian probability inference algorithm to calculate the probability distribution of the fault source, and the spatial positioning result of the fault source is obtained.

[0011] In combination with the first aspect, in a sixth implementation of the first aspect of the present invention, inputting the spectrum fingerprint matching degree into a Bayesian probability inference algorithm to calculate the fault source probability distribution to obtain a fault source spatial location result includes: Establishing a priori probability distribution of the device distribution density and historical fault statistics of the motherboard to be detected based on the spectrum fingerprint matching degree to obtain prior probability distribution data of the fault source; Performing a likelihood function calculation on the spectrum fingerprint matching degree according to the prior probability distribution data of the fault source to obtain a fault source likelihood function calculation result representing the correlation between the observation value and the position; Performing Bayesian posterior probability calculation based on the fault source prior probability distribution data and the fault source likelihood function calculation result to obtain fault source posterior probability calculation data including posterior probability distribution and confidence value; The fault source posterior probability calculation data is subjected to a multi-candidate fault source competition mechanism analysis and optimal position determination to obtain a fault source spatial positioning result.

[0012] In a second aspect, the present invention provides a motherboard fault detection device, the motherboard fault detection device comprising: The electromagnetic field scanning module is used to perform electromagnetic field scanning on the motherboard to be tested and obtain the original electromagnetic field spectrum data; A feature extraction module is used to extract features from the raw electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector; a modeling module, configured to perform multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector, and generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; The fault source spatial positioning module is used to perform fault source spatial positioning on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial positioning result.

[0013] The third aspect of the present invention provides a motherboard fault detection device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the motherboard fault detection device executes the above-mentioned motherboard fault detection method.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, enable the computer to execute the above-mentioned mainboard fault detection method.

[0015] In the technical solution provided by the present invention, multiple discrete frequency points are synchronously collected through an electromagnetic sensor array, and electromagnetic radiation correction is performed in combination with the geometric shape of the PCB traces, so that more accurate and comprehensive electromagnetic field spectrum information can be obtained. A multi-level wavelet packet decomposition algorithm is used to extract multidimensional feature parameters such as energy distribution coefficient, standard deviation coefficient and mean coefficient. Compared with the traditional FFT analysis method, it can retain time domain and frequency domain feature information at the same time, significantly enhancing the recognition ability and analysis accuracy of fault features. Special propagation models are established for CPU clock harmonic interference, power module switching noise and DDR memory signal crosstalk, and nonlinear coupling is achieved through multi-level superposition operations, solving the problem of misjudgment caused by traditional methods ignoring mutual interference between circuits. An accurate mapping relationship between spectrum fingerprint features and the physical location of the fault source is established, and the spatial positioning of the fault source is achieved through a three-dimensional spatial coordinate system and grid unit division, breaking through the technical limitations of traditional detection methods that can only qualitatively judge the existence of the fault but cannot accurately locate it. Through a complete Bayesian inference process involving prior probability distribution, likelihood function, and posterior probability calculation, combined with a multi-candidate fault source competition mechanism, we achieve probabilistic and precise fault source location. This method offers greater anti-interference capabilities and positioning reliability than traditional deterministic methods. We have established a complete technical chain from electromagnetic field scanning to precise fault source location. Through in-depth mining and intelligent analysis of spectrum fingerprint features, we achieve precise tracing and identification of motherboard faults.

[0016] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of an embodiment of a method for detecting a mainboard fault according to an embodiment of the present invention; Figure 2 A schematic diagram of an embodiment of a mainboard fault detection device according to an embodiment of the present invention; Figure 3 Schematic diagram of an embodiment of a motherboard fault detection device in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] The terms "including," "having," and any variations thereof, as used in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or device.

[0021] To facilitate understanding of this embodiment, a motherboard fault detection method disclosed in an embodiment of the present invention is first described in detail. Figure 1 As shown, this method includes the following steps: 101. Perform electromagnetic field scanning on the motherboard to be tested to obtain original electromagnetic field spectrum data; It is understandable that the execution subject of the present invention may be a mainboard fault detection device, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0022] Specifically, an electromagnetic sensor array with broadband response capability is set on the surface of the motherboard. The sensor array covers the key functional areas of the motherboard, such as the CPU area, power module, memory slots and multi-layer wiring dense areas, to ensure that the collected electromagnetic information is representative and complete. After the electromagnetic sensor array is set up, a set of preset frequency band scanning parameters is configured. The parameter group includes the frequency scanning start point, end point, frequency interval, and sampling time window and sampling rate of each frequency point. The frequency range covers 1MHz to 1GHz, and the sampling time window of each discrete frequency point is set to 100 microseconds, and the sampling rate is set to 2.5GHz to ensure accurate capture of short-term electromagnetic disturbance characteristics. Based on the above-mentioned frequency band scanning parameters, the synchronous acquisition mechanism is started to capture electromagnetic signals of multiple frequency points in parallel, generating multi-band electromagnetic signal acquisition data covering 128 discrete frequency points. At the same time, the electromagnetic signal is geometrically corrected based on the geometric structural characteristics of the motherboard's PCB traces. A geometric-electromagnetic coupling factor table is constructed based on geometric parameters such as the motherboard layout file, trace length, line width, layer spacing, and metal layer structure. This coupling factor is used to correct the amplitude and phase of the electromagnetic radiation signals collected at different spatial positions and structures. By combining the collected data with the coupling factor, geometrically consistent electromagnetic signal geometric correction data is generated, effectively suppressing the amplitude distortion and signal shielding problems introduced by the complexity of the motherboard wiring. The time-frequency reconstruction algorithm is used to perform matrix reconstruction on the geometrically corrected multi-band data. The reconstructed spectrum matrix uses time as the column dimension and frequency as the row dimension to map the continuous spectrum of the electromagnetic field at each frequency point over time. The energy transfer law and phase consistency between each frequency point are automatically integrated during the matrix construction process, and the original electromagnetic field spectrum data is finally obtained.

[0023] 102. Perform feature extraction on the original electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector; Specifically, the raw electromagnetic field spectrum data is input into a wavelet packet decomposition algorithm to perform a multi-level spectrum decomposition operation. The Daubechies8 wavelet, which exhibits excellent time-frequency localization, is selected as the mother wavelet function. A seven-layer wavelet packet decomposition is performed on the electromagnetic field spectrum matrix, decomposing the original spectrum signal into 128 sub-band signals with different frequency ranges while maintaining high transient resolution in the temporal dimension. This process not only avoids the frequency leakage and transient loss problems associated with traditional Fourier transform methods, but also preserves the frequency components and their energy variations over time. Energy distribution, standard deviation, and mean calculations are performed on each of the 128 sub-band signals to construct a multi-dimensional set of characteristic parameters. The energy distribution coefficient for each sub-band describes the total energy density within that band, reflecting its relative importance within the overall spectrum. The standard deviation coefficient measures the intensity of signal fluctuations within the band and is an important indicator for identifying unstable fault radiation. The mean coefficient provides information on the average radiation intensity within the band, useful for characterizing long-term stability and the influence of the background electromagnetic environment. This stage yields a 384-dimensional feature parameter set consisting of 128 energy distribution coefficients, 128 standard deviation coefficients, and 128 mean coefficients. To reduce the computational complexity and accumulated recognition errors caused by redundant dimensions, principal component analysis (PCA) is applied to this 384-dimensional feature parameter set for dimensionality reduction. By calculating the contribution of each dimension to the overall data variance, the principal feature components with a cumulative contribution of 95% are retained. A weighting mechanism is also introduced to assign a weight coefficient to each retained principal component to reflect its importance in subsequent classification and recognition. These weights are learned through reverse evaluation of the training sample set to enhance the model's ability to detect key spectral differences, thereby forming a target feature parameter combination with strong representativeness and high discrimination. This target feature parameter combination is normalized to unify the numerical range of all feature parameters to the [0, 1] interval. This eliminates feature bias caused by different dimensions and scales and prevents a single feature from masking other important information due to its large amplitude. After normalization, the final feature vector is reconstructed by combining the principal component structure and weight coefficients to obtain the spectral fingerprint feature vector.

[0024] 103. Perform multi-level nonlinear propagation modeling on the mainboard circuit system of the mainboard to be detected based on the spectrum fingerprint feature vector, and generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; Specifically, the CPU clock circuit in the motherboard is modeled. Based on the high-frequency energy coefficients and harmonic distribution characteristics of the spectrum fingerprint feature vector, repetitive interference components related to the main frequency and its integer multiples are identified. A harmonic frequency sequence is then constructed based on this. The interference intensity of each harmonic order is calculated using the amplitude, phase perturbation, and standard deviation at the corresponding harmonic frequency points. The CPU clock harmonic interference propagation parameters, including the main harmonic components and their amplitude indicators, are obtained. This reflects the fundamental frequency amplification effect of the high-frequency clock source and reveals the long-distance interference transmission characteristics caused by its spatial structure. The low- and mid-frequency characteristics of the spectrum fingerprint feature vector are mapped to the power module switching circuit modeling process. By extracting the low-frequency energy concentration area and broadband attenuation profile, the noise distribution caused by the power inductor and MOSFET switching behavior is analyzed. The power module switching noise propagation model parameters, including the noise intensity coefficient and spectral attenuation index, are then fitted. These parameters are used to characterize the non-ideal interference caused by the high-speed switching behavior of the power devices and the noise roll-off distribution in the spectral space. Furthermore, asymmetric high-order perturbations occurring in the high-frequency band, coupled with adjacent-frequency energy coupling, are correlated with the high-speed communication mechanism of the memory bus to establish a DDR memory signal crosstalk propagation model. Based on transmission line theory, this model combines energy density and phase consistency metrics in the highly fluctuating regions of the spectrum fingerprint to infer key propagation characteristics, such as the crosstalk transmission path, frequency band, and impedance coupling. This model then develops a set of DDR memory signal crosstalk propagation parameters, including coupling distance, propagation delay, and crosstalk intensity, to quantify the interference conduction behavior of high-speed signals between closely adjacent traces. After modeling the propagation parameters of the three subsystems, the three submodels are coupled and integrated by establishing a unified nonlinear propagation superposition mechanism. Using frequency-domain synthesis, CPU clock harmonics, power module low-frequency noise, and DDR high-speed crosstalk are frequency-divided and superimposed according to their frequency response characteristics. The coupling gain is adjusted based on the device layout density, trace topology, and metal layer structure within the motherboard's spatial structure, achieving a nonlinear coupling mapping from multi-source interference to global propagation. This coupling not only takes into account the spectrum overlap and energy fusion of various interference sources, but also integrates complex mechanisms such as phase superposition, spatial reflection and attenuation distortion. The final generated spectrum fingerprint propagation parameter combination becomes an important expression structure for characterizing the current electromagnetic propagation state of the motherboard.

[0025] By extracting features from the mid- and low-frequency components in the spectrum fingerprint feature vector, the typical periodic excitation frequencies of the power module during operation are captured. In particular, in the frequency range of tens to hundreds of kilohertz, the system exhibits significant resonant energy concentration. Based on the energy peak distribution at these specific frequency points, the power module's frequency components are identified. The actual switching frequency of the power module is calculated from the energy fluctuation period between these frequency points, generating power module switching frequency characteristic data for subsequent modeling and analysis. This switching frequency characteristic data, combined with the amplitude information at the corresponding frequency points in the spectrum data, is used to calculate the electromagnetic interference intensity associated with the power switching process. Based on the energy values ​​at each frequency band in the spectrum fingerprint, the energy response peak corresponding to the switching frequency and its lower harmonics is extracted, and its relative energy contribution to the entire spectrum is calculated. The power supply noise intensity coefficient (PNIC) is derived by taking into account the reflection and coupling enhancement effects of the switching inductor and capacitor layout in the motherboard structure. This coefficient physically reflects the maximum noise amplitude level that can be excited by the switching circuit and serves as a reference for subsequent spectrum roll-off modeling. Spectral attenuation modeling is performed based on the PNIC obtained above and the decreasing energy trend at each frequency point above the switching frequency in the spectrum fingerprint. This modeling approach uses a roll-off index calculation mechanism. Taking the switching frequency as a reference point, a regression fit is performed on the energy values ​​of the frequency bands above it. Through logarithmic transformation and extraction of the fitting slope, the spectral attenuation index of the power supply noise is calculated. A larger value of this index indicates faster attenuation of high-frequency components and weaker propagation of high-frequency interference in the system. Conversely, a smaller roll-off index indicates stronger broadband propagation of the switching noise. The extracted power module switching frequency characteristic data, the power supply noise intensity coefficient, and the power supply noise spectral attenuation index are integrated and analyzed to construct the power module switching noise propagation parameters.

[0026] 104. Perform spatial location of the fault source on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a spatial location result of the fault source.

[0027] Specifically, a three-dimensional rectangular coordinate system is established with the lower left corner of the motherboard as the origin, in which the X-axis extends along the long side of the motherboard, the Y-axis extends along the short side, and the Z-axis extends upward perpendicular to the motherboard surface, forming a three-dimensional spatial reference system with a directional and structural correspondence. Based on this three-dimensional coordinate system, the entire motherboard area is divided into multiple grid cells with fixed scales. Each grid cell is set to a two-dimensional plane range of 10mm×10mm, and the motherboard thickness is assumed to be unchanged on the Z axis, thereby dividing the original physical motherboard space into regular, quantifiable positioning primitives. These grid cells will serve as the minimum analytical unit in the subsequent spatial positioning process, used to load and compare spectral response characteristics. After the motherboard is gridded, a local spectral response template is constructed for each grid cell in combination with the spatial propagation attenuation model in the spectrum fingerprint propagation parameter combination. This process, based on a combination of simulation and field measurements, uses a propagation attenuation function to model spectral energy at different spatial locations. Factors such as distance attenuation, elevation directional attenuation, and an azimuth correction function are considered. The process also incorporates the combined effects of propagation characteristics from multiple interference sources, such as the CPU, DDR, and power modules. A local spectral fingerprint template is generated for each grid cell. This template characterizes the expected spectral response distribution pattern at that location under ideal or normal operating conditions. Together, these templates form a spatial distribution model of fault sources covering the entire spatial extent of the motherboard, providing the underlying framework for mapping spectral data to physical coordinates. Based on this, the spectral fingerprint feature vectors measured on the motherboard under test are matched against the pre-set spectral templates in each grid cell. A matching function is calculated to assess the similarity between the measured spectrum and the templates. This matching function is implemented using normalized Euclidean distance, cosine similarity, or the L1 norm. A weighted approach is used to assign higher sensitivity to key frequency bands, ensuring that the template matching reflects both global similarity and local anomalies. A set of spectral fingerprint matching values ​​is generated for each grid cell. The above spectrum fingerprint matching data is input into the Bayesian probability inference algorithm to derive the probability distribution of the fault source. The system first constructs a priori probability distribution of the fault source, combining the historical fault frequency and device layout density of each functional area in the motherboard. For example, the prior probability of the CPU area is set to 0.25, and the power area is set to 0.18. The matching degree is used as the likelihood function input, and the Bayesian theorem is used to calculate the posterior probability of each grid cell, that is, the probability value of the grid cell being the fault source under the current spectrum observation conditions. By sorting and aggregating the posterior probability results of all grid cells, the grid cell coordinates with the maximum posterior probability are selected as the spatial location output of the fault source. At the same time, the confidence index is calculated by combining the maximum value of the Bayesian probability distribution and the sum of the normalized probabilities. If the confidence is greater than 0.85, the positioning result is considered to have high reliability.

[0028] By deeply integrating spectral fingerprint matching with motherboard component density and historical fault data, a physically interpretable prior probability distribution is established for the entire motherboard space. The system divides the motherboard space into multiple grid cells and assigns each cell a component density score related to its functional area. This score is then combined with historical fault records accumulated during long-term maintenance. For example, the CPU area, due to its high-frequency and high-speed operating characteristics, is assigned a prior probability of 0.25; the memory area is assigned a prior probability of 0.20; and the power management module is assigned a prior probability of 0.18. Other areas are assigned proportional values ​​based on the actual number of components deployed and their functional complexity. This results in a set of prior probability distributions for fault sources covering the entire motherboard area. This distribution provides a basic assessment of the likelihood of a fault occurring in each area, assuming no external observational data. Based on this, the spectral fingerprint matching is combined with the prior probability to calculate the likelihood function. The matching value reflects the degree of similarity between the measured spectrum and a preset normal template; the lower the value, the more likely the area is to contain an anomaly. Therefore, the spectral fingerprint matching value is used as input and converted into the relative probability of the current spectral feature occurring in each grid location, thereby establishing a correlation between the observed value and the location. This process not only considers the degree of energy deviation between features but also combines standard deviation and mean difference to produce results reflecting the degree of spectral anomaly and the strength of spatial coupling. It also quantifies the relative likelihood of each location on the motherboard being the fault source under the current spectrum observation conditions. The prior probability distribution data and the likelihood calculation results are input into the Bayesian inference framework to perform the posterior probability evaluation process. This method generates a posterior probability value for each spatial grid cell—the comprehensive estimated probability of that grid cell being the fault source under the current spectrum observation data. The relative ratios between the posterior probabilities of each grid cell are then combined to calculate a value representing the overall identification confidence. For example, when the posterior probability of a location accounts for a high proportion of the overall probability distribution, its corresponding confidence level increases significantly. If the confidence level exceeds 0.85, the location is considered reliable. To ensure the uniqueness and operational decision-making of the final location, a multi-candidate fault source competition mechanism is introduced. All grid cells with posterior probability values ​​greater than a set threshold (e.g., 0.10) are identified as candidate regions, and the probability ratios between these candidate regions are analyzed. When the probability ratio of a particular location to all other candidate regions is greater than 2.5, it is determined to be the primary fault source for the current motherboard. If the posterior probability values ​​of multiple regions are close, a convergence mechanism is introduced. For example, particle filtering technology is used to resample the probability density of the candidate regions and iterate multiple rounds of updates, so that the fault probability distribution gradually converges to a prominent location coordinate point in space. Ultimately, the optimal location coordinates are used as the spatial localization result of the fault source, and the final confidence index for this location is output.

[0029] In an embodiment of the present invention, an electromagnetic sensor array is used to synchronously collect multiple discrete frequency points, and electromagnetic radiation correction is performed in combination with the geometry of the PCB traces. This allows for more accurate and comprehensive electromagnetic field spectrum information to be obtained. A multi-level wavelet packet decomposition algorithm is used to extract multidimensional feature parameters such as energy distribution coefficient, standard deviation coefficient, and mean coefficient. Compared to traditional FFT analysis methods, this method can simultaneously retain both time-domain and frequency-domain feature information, significantly enhancing the ability to identify fault features and the accuracy of analysis. Dedicated propagation models are established for CPU clock harmonic interference, power module switching noise, and DDR memory signal crosstalk, respectively. Nonlinear coupling is achieved through multi-level superposition operations, addressing the problem of misjudgment caused by traditional methods that ignore mutual interference between circuits. A precise mapping relationship between spectral fingerprint features and the physical location of the fault source is established, and spatial localization of the fault source is achieved through a three-dimensional spatial coordinate system and grid unit division. This overcomes the technical limitation of traditional detection methods, which can only qualitatively determine the existence of a fault but cannot accurately locate it. Through a complete Bayesian inference process involving prior probability distribution, likelihood function, and posterior probability calculation, combined with a multi-candidate fault source competition mechanism, we achieve probabilistic and precise fault source location. This method offers greater anti-interference capabilities and positioning reliability than traditional deterministic methods. We have established a complete technical chain from electromagnetic field scanning to precise fault source location. Through in-depth mining and intelligent analysis of spectrum fingerprint features, we achieve precise tracing and identification of motherboard faults.

[0030] In a specific embodiment, the process of executing step 101 may specifically include the following steps: An electromagnetic sensor array is set up on the motherboard to be detected and frequency band scanning parameters are configured, and multi-band electromagnetic signals of the motherboard to be detected are synchronously collected based on the frequency band scanning parameters to obtain multi-band electromagnetic signal collection data containing electromagnetic radiation signals of multiple discrete frequencies; Performing electromagnetic radiation correction on the PCB trace geometry of the motherboard to be tested based on the multi-band electromagnetic signal acquisition data to obtain electromagnetic signal geometry correction data; The electromagnetic signal geometric correction data is reconstructed into a spectrum matrix to obtain the original electromagnetic field spectrum data.

[0031] Specifically, at the physical level, an electromagnetic sensor array with wide frequency band, high sampling accuracy, and multi-channel parallel capability is set up. This array is installed above the motherboard and can cover key functional areas on the motherboard surface, such as the central processing unit, power module, memory slots, high-speed I / O channels, etc., to ensure comprehensive coverage of the entire electromagnetic environment of the motherboard. In terms of sensor type selection, near-field electromagnetic sensors with a response bandwidth between 1MHz and 1GHz and a sensitivity greater than -80dBm are selected. They are combined with a high-frequency analog front end and a multi-channel analog-to-digital conversion module to achieve original signal acquisition. To ensure that the signal does not alias during the sampling process and to meet the requirements of the Nyquist theorem, the sampling frequency is set to 2.5GHz, thereby obtaining high-frequency electromagnetic interference events and the harmonic signal distribution generated by the high-frequency subsystems within the motherboard with fine resolution. To improve the structural and distribution integrity of the electromagnetic field data, the electromagnetic signals of the motherboard are synchronously collected in a divided frequency manner according to the preset frequency band scanning parameters. This process uses a spectrum controller to uniformly configure core parameters such as the sampling range, frequency interval, and acquisition time window. The acquisition frequency range starts at 1 MHz and increases in equal intervals until it reaches 1 GHz, divided into 128 discrete frequency points. The acquisition time window for each frequency point is set to 100 microseconds. A high-speed channel synchronization control module enables parallel sampling and buffering of signals across the entire frequency band, preventing feature distortion caused by time domain misalignment during frequency hopping acquisition. This mechanism generates an initial electromagnetic signal dataset with time as the horizontal axis and frequency as the vertical axis, representing the multi-band electromagnetic signal acquisition data. Each frequency point in this dataset corresponds to a time series signal, reflecting the fluctuations in electromagnetic radiation intensity of the motherboard at a specific frequency within a specific time window. Due to the inherent structural complexity of the motherboard and the non-uniform geometry of the PCB traces, electromagnetic radiation intensity can be significantly affected. Direct spectrum analysis using the raw acquired data can be affected by the non-uniform coupling and shielding effects of the trace structure, leading to overestimation or underestimation of the electromagnetic signal in certain areas, thus affecting the accuracy of fault signature identification. Therefore, during the data preprocessing stage, structural compensation and geometric correction are performed on the raw electromagnetic data. Based on the motherboard's PCB design file or 3D scan model, geometric parameters such as trace length, line width, number of layers, interlayer spacing, reference ground distance, and the dielectric constant of the cladding material are extracted for each signal channel's corresponding area. A geometric-electromagnetic coupling model is then constructed and applied to the amplitude channel of the acquired data. The data amplitude and phase information of each sensor channel at each frequency point are corrected using a scaling factor and a directional correction function, generating geometrically corrected electromagnetic signal data with structural perception capabilities. The spectral matrix of the geometrically corrected electromagnetic signal data is then reconstructed, combining the raw acquired data with the structural correction results into a unified, standardized matrix structure suitable for time-frequency analysis and feature extraction.The reconstruction method utilizes a dual-processing mechanism of frequency-domain interpolation and time alignment. During the frequency-domain interpolation process, the amplitude and phase trends between adjacent frequency points are smoothly compensated to prevent data jumps in the spectral transition region. Simultaneously, the sampling time of all channel signals is synchronized and corrected on the time axis to ensure comparability and synthesis capability of all frequency points within the same time slice. The corrected signal for each frequency point within a given time window is constructed as a column vector and arranged in ascending frequency order to form a complete spectrum matrix, forming a two-dimensional time × frequency tensor data structure.

[0032] In a specific embodiment, the process of executing step 102 may specifically include the following steps: Inputting the electromagnetic field spectrum raw data into a wavelet packet decomposition algorithm to perform multi-level spectrum decomposition to obtain wavelet packet decomposition data containing multiple sub-bands; Performing energy distribution calculation, standard deviation calculation and mean calculation on each sub-band according to the wavelet packet decomposition data to obtain a multidimensional feature parameter set including energy distribution coefficient, standard deviation coefficient and mean coefficient; Performing principal component analysis and weight coefficient assignment on the multidimensional feature parameter set to obtain a target feature parameter combination; The target characteristic parameter combination is normalized and a characteristic vector is reconstructed to obtain a spectrum fingerprint characteristic vector.

[0033] Specifically, the raw electromagnetic field spectrum data is input into the wavelet packet decomposition module in a two-dimensional matrix format of time × frequency. The Daubechies8 wavelet, which has excellent boundary resolution and energy concentration, is selected as the mother wavelet function, and the raw spectrum signal is subjected to a seven-level wavelet packet decomposition. The decomposition process is similar to recursive filtering and subband reconstruction of the spectrum signal, resulting in the raw data being divided into 128 wavelet subbands with different center frequencies and bandwidths. Each subband contains its amplitude response values ​​at different time segments, forming a compact and hierarchical wavelet packet decomposition data. Multi-angle statistical feature extraction operations are performed on each subband, specifically including three types of features: energy distribution, standard deviation, and mean. Energy distribution is calculated by summing the squares of the signal amplitudes within each sub-band to obtain the total energy contained in that frequency band, thereby assessing its contribution and dominance in the overall electromagnetic field energy structure. The standard deviation of the signal fluctuation amplitude within each sub-band is calculated to characterize the signal stability and degree of interference perturbation within that frequency band. High standard deviation frequency bands suggest the presence of significant periodic shocks or external crosstalk interference. Simultaneously, a mean is calculated for each frequency band to measure its overall amplitude level, which is used to distinguish normal background radiation from persistent offset interference. After extracting the above three features one by one, the three indicators obtained for each sub-band are combined to construct a three-dimensional multidimensional feature parameter set consisting of 128 energy distribution coefficients, 128 standard deviation coefficients, and 128 mean coefficients. This total of 384 independent feature dimensions covers the three structural statistical properties of the spectrum space: energy, stability, and intensity. Principal component analysis is performed on this multidimensional feature parameter set. The covariance matrix of the feature set is calculated and eigenvalue decomposition is performed on it to identify the most representative set of feature axes that dominate the direction of data variation. By evaluating the cumulative contribution rate, several principal components with a total information retention rate of 95% are selected. The original 384-dimensional features are then mapped into this principal component subspace, forming a compressed low-dimensional feature combination. Furthermore, a weight coefficient is assigned to each principal component based on its contribution to the overall variance explained. The higher the weight, the more significant its contribution to fault identification. Ultimately, these principal components and their weights are combined to form the target feature parameter combination, forming the optimal low-dimensional representation of the original spectral data. To improve the comparability and model adaptability of the target feature combination, this combination is normalized. During normalization, a linear scaling method is used to map all principal component eigenvalues ​​to a standard interval between 0 and 1. This ensures that features of different scales and amplitudes participate in subsequent modeling calculations in a unified dimension, preventing the excessive amplitude of individual features from obscuring other valid information. After normalization is completed, all feature vectors that have been screened by principal components, weighted and standardized are reconstructed and combined into a unified data structure output, namely the spectrum fingerprint feature vector.

[0034] In a specific embodiment, the process of executing step 103 may specifically include the following steps: Based on the spectrum fingerprint feature vector, a harmonic interference propagation model is performed on the CPU clock circuit of the motherboard circuit system in the motherboard to be detected, and a CPU clock harmonic interference propagation parameter including a harmonic frequency sequence and an interference intensity value is obtained; Based on the spectrum fingerprint feature vector, noise propagation modeling is performed on the power module switch circuit of the motherboard circuit system in the motherboard to be detected, and power module switch noise propagation parameters including noise intensity coefficient and spectrum attenuation index are obtained; Based on the spectrum fingerprint feature vector, a signal crosstalk propagation model is performed on the DDR memory circuit of the motherboard circuit system in the motherboard to be detected to obtain DDR memory signal crosstalk propagation parameters; The CPU clock harmonic interference propagation parameter, the power module switching noise propagation parameter and the DDR memory signal crosstalk propagation parameter are subjected to multi-level superposition operation and nonlinear coupling to obtain a spectrum fingerprint propagation parameter combination.

[0035] Specifically, based on the high-resolution, multi-band, and structured statistical properties extracted from the spectrum fingerprint feature vector, such as energy, standard deviation, and mean, targeted interference modeling is performed for the CPU clock circuit, power module switching circuit, and DDR memory high-speed signal channel. In the first stage of modeling, the high-frequency region of the spectrum fingerprint feature vector, which exhibits periodic peaks in the frequency dimension, is analyzed. This region, located above hundreds of megahertz, appears as evenly spaced integer multiples, exhibiting a typical harmonic structure. This characteristic is caused by harmonic radiation generated in the frequency domain by signal conversion and sharp edges during stable operation of the motherboard CPU clock source. After identifying these frequency locations, the system automatically extracts the corresponding frequency values ​​as harmonic frequency sequences. Combining the energy coefficient and amplitude trends at these frequency points, the system calculates the interference strength of each harmonic component. These interference strengths reflect the potential for coupling interference caused by the harmonics within the motherboard space; higher values ​​indicate a greater impact on surrounding circuits. By extracting and quantifying all valid harmonic frequency bands, a CPU clock harmonic interference propagation parameter is generated, consisting of multiple frequency points and their corresponding interference intensities. This parameter characterizes the radiation pattern of the CPU operating clock in the spatial spectrum. The low- and mid-frequency regions of the spectrum fingerprint feature vector are analyzed to identify the broadband, low-frequency noise characteristics caused by the switching process of the power module. This noise primarily originates from the periodic conduction and shutdown behavior of switching devices such as the motherboard power converter, DC-DC module, and inductors and MOSFETs. Its spectrum exhibits a characteristic curve centered between tens and hundreds of kHz, with the spectrum edge gradually rolling off toward higher frequencies. The system extracts the continuous energy distribution coefficient within this frequency band and combines it with the matching periodic variation interval to identify the switching frequency of the power module. The power supply noise intensity factor is then calculated based on the amplitude levels of the frequency bands below it, reflecting the interference amplitude generated by the overall switching behavior. The degree of spectral attenuation is extracted by trend fitting the rate of energy decrease in frequency bands above the switching frequency. This index is expressed as a spectral attenuation index. A smaller index indicates a wider spectral spread and greater long-range interference potential for the power supply noise. The above two key parameters are integrated into the power module switching noise propagation parameters to describe the energy output capacity and frequency domain propagation trend of low-frequency interference. After completing the modeling of the above two low-frequency and high-frequency interference sources, crosstalk propagation modeling and analysis are performed on the high-speed signals involved in the DDR memory circuit. DDR signals are characterized by high frequency, high speed, and low amplitude when transmitted on the motherboard. They are easily affected by capacitive coupling, inductive coupling, or ground reflection interference between traces, forming cross-interference signals, which are particularly obvious in dense wiring areas. The frequency bands in the spectrum fingerprint feature vector that are above several hundred megahertz and have high-speed oscillation and energy fluctuation characteristics are identified as DDR crosstalk candidate areas. The frequency bands with high standard deviation coefficients, significant mean offsets, and continuous energy transitions in this area are further extracted as crosstalk propagation characteristic bandwidths.Based on this, an equivalent propagation model is constructed, combining input conditions such as motherboard wiring topology parameters, trace length, and load characteristics. By calculating the signal superposition strength and phase consistency between adjacent wires along the signal transmission path, the crosstalk interference intensity is extracted and output as the crosstalk propagation parameter for DDR memory signals, describing the motherboard's signal coupling and interference migration capabilities in the high-speed signal area. The propagation parameters of CPU clock harmonic interference, power module switching noise, and DDR memory signal crosstalk are superimposed in a unified spectral space at multiple levels. Each interference source is assigned a frequency band weight, energy impact range, and propagation priority. Nonlinear coupling modeling is performed based on the degree of frequency overlap, energy superposition, and spatial impact area between different signal sources. This process simulates the propagation effects of multiple signal sources acting together in the motherboard's complex electromagnetic field environment, such as the interference of harmonics and crosstalk at a specific frequency point and the effect of low-frequency power supply noise on the noise floor of high-frequency signals. All relevant spectral impact mechanisms are mapped into a unified propagation parameter matrix, ultimately forming a spectrum fingerprint propagation parameter combination.

[0036] In this embodiment, the harmonic interference propagation modeling of the CPU clock circuit of the motherboard circuit system in the motherboard to be detected is performed based on the spectrum fingerprint feature vector to obtain the CPU clock harmonic interference propagation parameters including the harmonic frequency sequence and the interference intensity value, including: extracting features and performing frequency identification calculation on the CPU clock frequency component based on the spectrum fingerprint feature vector, and performing numerical determination processing on the clock signal fundamental frequency according to the peak frequency distribution in the spectrum fingerprint feature vector to obtain the CPU clock fundamental frequency identification parameter including the CPU fundamental frequency value and frequency stability; performing mathematical calculation and frequency generation processing on the CPU clock harmonic sequence according to the CPU clock fundamental frequency identification parameter, and performing frequency identification processing on the CPU clock harmonic sequence based on the fundamental frequency integer. The method adopts a multiple relationship to calculate and analyze each harmonic frequency step by step to obtain CPU clock harmonic frequency sequence data including first harmonic to multiple harmonic frequencies; based on the CPU clock harmonic frequency sequence data, intensity calculation and interference quantification processing are performed on the amplitude of each harmonic, and the harmonic interference intensity is numerically extracted and calculated according to the amplitude value of the corresponding frequency point in the spectrum fingerprint feature vector to obtain CPU clock harmonic interference intensity data including the amplitude value of each harmonic and the relative intensity ratio; the CPU clock fundamental frequency identification parameter, the CPU clock harmonic frequency sequence data and the CPU clock harmonic interference intensity data are parameter integrated and a propagation model is constructed to obtain CPU clock harmonic interference propagation parameters.

[0037] In a specific embodiment, the step of performing noise propagation modeling on the power module switch circuit of the motherboard circuit system in the motherboard to be detected based on the spectrum fingerprint feature vector to obtain power module switch noise propagation parameters including a noise intensity coefficient and a spectrum attenuation index may specifically include the following steps: Extracting a power module frequency component based on the spectrum fingerprint feature vector, and performing switching frequency identification on a power module switch circuit of a mainboard circuit system in the mainboard to be detected based on the power module frequency component to obtain power module switching frequency feature data; Calculating the noise intensity of the power module switching circuit according to the power module switching frequency characteristic data to obtain a power supply noise intensity coefficient; Calculating a roll-off index of a spectrum attenuation characteristic of a switching circuit of the power module based on the power supply noise intensity coefficient to obtain a power supply noise spectrum attenuation index; The switching noise propagation parameters of the power module are obtained by performing a switching noise propagation analysis on the switching frequency characteristic data of the power module, the power supply noise intensity coefficient, and the power supply noise spectrum attenuation index.

[0038] Specifically, the system extracts frequency component features related to the power module's switching activity from the spectral fingerprint feature vector. This spectral fingerprint feature vector is a high-dimensional structured data set generated through wavelet packet decomposition and feature reconstruction. The low- to mid-frequency region contains a broadband energy response caused by the power module's periodic switching during on- and off-state cycles. In the frequency domain, this response manifests as a high-amplitude peak at the bottom of the spectrum and a gradually decreasing roll-off characteristic toward higher frequencies. The system scans the energy distribution coefficient within this frequency band, identifying regions where the energy density continuously increases and peaks at specific frequencies. By combining the local trends of the standard deviation and mean coefficients, the system identifies key frequency points in the signal that match the power module's operating frequency, thereby constructing a frequency component set for the power module. During this process, the system verifies and compares the extracted frequency components against the nominal switching frequency range of the power module from historical calibration data or design documents to ensure the electrical plausibility of the extracted frequency components. Based on the identified frequency components, these frequency points are categorized and aggregated, and their frequency spacing, amplitude fluctuations, and occurrence patterns are calculated to determine the primary switching frequency characteristics of the power module. This identification process not only considers the main frequency with the highest amplitude in the spectrum data but also analyzes the frequency stability of the sub-highest frequency and its harmonic energy symmetry above and below it. This yields a set of power module switching frequency signature data that not only characterizes the actual switching action but also corresponds to the physical drive cycle. This data reflects the conduction frequency of the power chip or DC-DC converter in its current operating state. After identifying the power module switching frequency signature, the system focuses on the energy distribution in the frequency band centered on that frequency and quantifies the switching noise intensity based on the energy coefficient of that frequency band in the spectrum fingerprint. During the calculation, the system aggregates energy within that frequency point and several adjacent frequency points above and below it, measuring the total amplitude response. The transient intensity of the noise signal in that frequency band is estimated based on the energy gradient trend between the frequency points, thereby obtaining the power supply noise intensity coefficient. This coefficient physically represents the intensity of the periodic high-amplitude electromagnetic radiation generated by the internal MOSFET, inductor, transformer, and filter network during the power module's conduction process. A larger value indicates more dramatic transient switching current changes or significant load fluctuations, potentially causing significant interference to surrounding wiring, signal channels, or sensitive modules. After noise intensity estimation, trend modeling is performed on the frequency band extending from the switching frequency toward higher frequencies to characterize the spectral attenuation characteristics of the power supply switching noise. This frequency band exhibits a characteristic curve on the frequency response graph, where energy gradually decreases as frequency increases. Therefore, the system extracts a series of energy distribution coefficients within this range and, based on their distribution position on the frequency axis, performs curve fitting or downward trend regression analysis to calculate the roll-off exponent of the power supply noise spectrum.A larger roll-off index indicates a more rapid energy drop-off, limiting the propagation range of the power supply noise signal at high frequencies. Conversely, a smaller roll-off index indicates a stronger high-frequency extension capability, potentially impacting other high-speed circuits or RF modules on the motherboard. The power module's switching frequency characteristic data, the power supply noise intensity coefficient, and the power supply noise spectrum attenuation index are integrated and input into the switching noise propagation analysis module to describe and model the propagation mechanism of the periodic interference generated by the power module within the motherboard's spatial domain. This analysis model treats the power module as an interference source, defines its geometric position and radius of effect within the motherboard's structural coordinate system, and derives its impact on adjacent circuit areas using propagation parameters. In the propagation model, the switching frequency characteristics determine the main frequency distribution of the interference, the noise intensity coefficient determines the starting point of the main frequency interference's radiated power, and the roll-off index determines the diffusion capacity of the interference energy in the spatial frequency domain. Based on these parameters, the system constructs a propagation attenuation function. Incorporating factors such as the motherboard's layout, trace density, metal layer arrangement, and grounding scheme, the system then spatially models the superposition, coupling, and diffusion of the power module noise within the motherboard's electromagnetic environment, ultimately generating the power module switching noise propagation parameters as output.

[0039] In this embodiment, the signal crosstalk propagation modeling of the DDR memory circuit of the motherboard circuit system in the motherboard to be detected is performed based on the spectrum fingerprint feature vector to obtain the DDR memory signal crosstalk propagation parameters, including: extracting and identifying the DDR memory signal frequency component based on the spectrum fingerprint feature vector, and performing frequency domain analysis and calculation on the DDR data transmission signal according to the memory signal characteristic frequency to obtain the DDR memory signal frequency domain characteristic parameters including the memory signal frequency characteristics and signal amplitude distribution; performing transmission line modeling and calculation on the DDR memory routing according to the DDR memory signal frequency domain characteristic parameters, and based on the routing geometry and medium The method numerically solves the characteristic impedance and propagation constant of the transmission line according to the characteristics to obtain DDR transmission line model parameters including the characteristic impedance value and the propagation constant; calculates the crosstalk transfer function of the DDR memory circuit based on the DDR transmission line model parameters, and performs mathematical operation on the crosstalk coupling coefficient according to the transmission line length and the load impedance to obtain DDR crosstalk transfer function parameters including the crosstalk transfer function and the coupling strength coefficient; performs frequency domain response analysis and pole-zero configuration calculation on the DDR crosstalk transfer function parameters, and quantitatively evaluates the crosstalk propagation characteristics based on the fault type spectrum response characteristics to obtain DDR memory signal crosstalk propagation parameters.

[0040] In this embodiment, the CPU clock harmonic interference propagation parameters, the power module switching noise propagation parameters and the DDR memory signal crosstalk propagation parameters are subjected to multi-level superposition operation and nonlinear coupling to obtain spectrum fingerprint propagation parameters, including: parameter standardization and compatibility processing of the CPU clock harmonic interference propagation parameters, the power module switching noise propagation parameters and the DDR memory signal crosstalk propagation parameters, and numerical preprocessing of the three types of propagation parameters based on frequency domain alignment and amplitude normalization to obtain a standardized propagation parameter combination; multi-level weight allocation and superposition operation processing are performed based on the standardized propagation parameter combination, and the spectrum fingerprint propagation parameters are obtained according to the propagation parameters of each level. The superposition weight coefficient is mathematically calculated based on the spectrum contribution of the propagation parameters to obtain a multi-level superposition operation result including the hierarchical weight and the spectrum superposition value; a nonlinear coupling analysis and calculation is performed on the mutual influence between the propagation parameters according to the multi-level superposition operation result, and the nonlinear coupling coefficient is quantitatively solved based on the spectrum cross term and coupling strength between the parameters to obtain a nonlinear coupling calculation result including the coupling coefficient and the cross-influence factor; the multi-level superposition operation result and the nonlinear coupling calculation result are subjected to comprehensive propagation function construction and parameter fusion processing, and the final propagation characteristics are mathematically modeled based on the pole-zero point configuration of the propagation function to obtain the spectrum fingerprint propagation parameters.

[0041] In a specific embodiment, the process of executing step 104 may specifically include the following steps: Establishing a three-dimensional space coordinate system and dividing the motherboard to be inspected into grid units to obtain a plurality of grid units; The local spectrum fingerprint template of each grid unit is constructed according to the spatial propagation attenuation characteristics of the spectrum fingerprint propagation parameter combination to obtain the spatial distribution model of the fault source; Performing template matching calculation on the spectrum fingerprint of the motherboard to be detected according to the fault source spatial distribution model to obtain the spectrum fingerprint matching degree; The spectrum fingerprint matching degree is input into the Bayesian probability inference algorithm to calculate the probability distribution of the fault source, and the spatial positioning result of the fault source is obtained.

[0042] Specifically, a three-dimensional spatial coordinate system corresponding to the motherboard's geometry is established, and a gridding operation is performed within this coordinate system, transforming the entire motherboard's physical area into quantifiable spatial units. In this implementation, with the motherboard's lower left corner as the origin, the X-axis is set to extend along the motherboard's long side, the Y-axis along its short side, and the Z-axis perpendicular to the motherboard's surface, forming a three-dimensional rectangular coordinate system with directionality, calibration, and resolution. Within this coordinate system, the motherboard surface is divided into a number of two-dimensional grid cells, each with a planar dimension of 10 mm x 10 mm, forming a spatially resolved structure with physically constrained boundaries. Based on the spectrum fingerprint propagation parameter combination, a local spectrum fingerprint template is constructed for each grid cell, based on the attenuation characteristics of CPU clock harmonics, power module noise, and DDR crosstalk in the frequency domain and space. This construction process is based on the premise that spectrum signals attenuate with distance as they propagate in space and are modulated by multiple factors, including angular direction, material damping, and layout impedance. Therefore, the system incorporates a spatial propagation attenuation model when constructing templates. Combined with parameter combinations such as interference source strength, frequency distribution, and roll-off exponent, the system calculates the theoretical spectral response pattern that each grid cell should exhibit under the influence of a specific interference source. Grids near the CPU area exhibit prominent high-frequency harmonics in the template; grids near the power supply area exhibit a stronger low-frequency, broadband response; and grids adjacent to DDR traces exhibit high-frequency irregularities and in-band noise coupling. These differentiated response characteristics are used to generate a set of local spectral templates covering the entire board surface, which are then unified into a fault source spatial distribution model. This model constructs a baseline of normal electromagnetic behavior for different regions of the motherboard in three dimensions: frequency, energy, and space, providing an ideal reference for fault location. After constructing the spatial templates, the system uses the spectral fingerprint feature vectors generated by geometrically correcting and spectrally reconstructing the electromagnetic signals collected by the sensor array during actual operation of the motherboard to calculate the point-by-point match between the local templates corresponding to each grid cell in the fault source spatial distribution model. During the matching calculation process, a distance measurement method is used to compare the similarity between the measured spectrum characteristics and the template characteristics. The smaller the calculated result, the more consistent the actual response is with the theoretical template. The matching difference is then reversely processed to obtain the spectrum fingerprint matching value. In order to improve the discrimination sensitivity of the matching, a weighted multi-scale indicator comparison mechanism is introduced, that is, different proportions are set for the three dimensions of energy distribution characteristics, standard deviation change, and mean shift. This makes abnormal signals such as sudden changes in spectrum structure and energy concentration jumps more significant in terms of matching. The matching data of all grids are recorded as a set of spatially distributed matching strength value matrices. The spectrum fingerprint matching matrix is ​​input into the Bayesian probability inference algorithm to perform the derivation and analysis of the fault source probability distribution.In the priori stage, a spatial prior probability distribution of fault occurrence is established based on the component density and historical failure statistical probabilities of each functional area of ​​the motherboard. For example, the CPU area is assigned a probability of 0.25, the memory area is assigned a probability of 0.20, and the power module area is assigned a probability of 0.18. The remaining probabilities are then weighted based on component density and historical failure rates for the remaining areas. Next, in the likelihood inference stage, the system uses the matching degree of each grid as a conditional observation input to determine the likelihood that each location is the fault source given the current spectral fingerprint. By combining the matching degree with the prior probability, the posterior probability of each grid location is derived, indicating the degree of confidence that the current observations support that location as the fault source. All posterior probability results are normalized to form a probability distribution map. The system then selects the area with the highest probability and, combined with the confidence value, outputs the location location. When the posterior probability of a grid location is significantly higher than that of other locations and its corresponding confidence value is higher than 0.85, the system marks it as the optimal fault source location, further supporting spatial tracing and fault explanation.

[0043] In a specific embodiment, the execution step of inputting the spectrum fingerprint matching degree into the Bayesian probability inference algorithm to calculate the fault source probability distribution and obtain the fault source spatial location result may specifically include the following steps: Establishing a priori probability distribution of the device distribution density and historical fault statistics of the motherboard to be detected based on the spectrum fingerprint matching degree to obtain prior probability distribution data of the fault source; Performing a likelihood function calculation on the spectrum fingerprint matching degree according to the prior probability distribution data of the fault source to obtain a fault source likelihood function calculation result representing the correlation between the observation value and the position; Performing Bayesian posterior probability calculation based on the fault source prior probability distribution data and the fault source likelihood function calculation result to obtain fault source posterior probability calculation data including posterior probability distribution and confidence value; The fault source posterior probability calculation data is subjected to a multi-candidate fault source competition mechanism analysis and optimal position determination to obtain a fault source spatial positioning result.

[0044] Specifically, by parsing motherboard schematics or structural design documents, the physical distribution information of each functional module on the motherboard surface and within the multi-layer layout is obtained, including the location and density of key components such as the CPU, memory, power modules, northbridge chips, and I / O interface areas. For each divided grid cell, a structural density score is calculated based on the number of devices covered, their type, and their electrical activity (e.g., whether they are high-frequency or high-power devices). Combined with a long-term, accumulated historical fault database, the probability statistics of various fault types occurring in different areas are extracted. For example, the CPU area has a high historical fault concentration due to its high frequency, high current, and significant electromagnetic disturbances, so the prior probability for this area is set to 0.25. The memory area is set to 0.20 due to its frequent high-speed read and write operations. The power module, as an interference source and load interface, has a prior probability of 0.18. The remaining probabilities are evenly distributed among the remaining areas based on their device complexity and historical failure rates, forming a prior probability distribution map covering all grid cells. Based on the established prior probability and the previously calculated spectrum fingerprint matching value, a quantitative model is constructed to determine the strength of correspondence between the current state of each grid cell on the motherboard and the spectrum observation. This process is known as constructing the likelihood function. The matching value itself reflects the degree of similarity between the measured spectrum and the local template. A higher value indicates that the spectral characteristics at that location are more consistent with a known interference model. The system uses this matching value as the basis for measuring the conditional probability that a particular area is a potential fault source under the current observation. In the specific operation, the spectrum fingerprint matching value of each grid cell is compared with its expected characteristic value under the standard template. The deviation range and response consistency are calculated, and this value is converted into a numerical output representing the reasonableness of the location response, which is used to represent the strength of the correlation between the current observation and the grid location. This correlation strength value is the actual input to the likelihood function, reflecting the likelihood of a specific spectrum observation occurring in a specific spatial region. Based on the prior probability distribution data of the fault source and the calculated fault source likelihood function, a Bayesian posterior probability calculation is performed to obtain the posterior probability output for each grid cell. The posterior probability represents the overall probability assessment that each location is the true fault source under the current spectrum observation results. It is the output after normalization based on the product relationship between the prior probability and the observed data, and has the consistency of probabilistic semantics and the traceability of physical interpretation. Each grid cell forms the final posterior evaluation result through a weighted combination of the prior value and the likelihood value. The system forms a spatial distribution map of the posterior values ​​of all grids and extracts the grid location with the largest posterior probability value as the potential fault point. Based on this, the corresponding confidence value is calculated. This value is the ratio of the current maximum posterior probability to the sum of the posterior probabilities of all grids, which is used to assess the credibility of the positioning result. If the confidence value exceeds the preset threshold, such as 0.85, the positioning result is considered reliable and can be used for subsequent maintenance or diagnostic decisions.To improve fault-tolerant judgment under multi-region interference coupling, a multi-candidate fault source competition mechanism is introduced to perform relative comparisons between multiple grid locations with high posterior probabilities. During execution, all grid cells with posterior probability values ​​exceeding a certain threshold (e.g., 0.10) are identified as candidate fault regions. Posterior probabilities are then ratio-analyzed between these candidate regions, calculating the difference in probability ratios between each pair of regions and identifying grid points with significant relative advantages. For example, if the posterior probability ratio of a candidate location relative to any other candidate location is greater than 2.5, the system selects it as the optimal location. If multiple locations have similar probability distributions and no clear advantage, the system further introduces a resampling mechanism. Using a particle filter, the system performs sparse particle sampling and density approximation on the current posterior probability space. The system tracks the posterior probability trend during continuous iterations and determines the final location coordinates after the particles converge and stabilize. This mechanism effectively avoids misjudgments caused by local optima, improving judgment accuracy and positioning robustness in complex coupled interference scenarios. The final output of the fault source spatial positioning result includes the coordinate position of the optimal grid, as well as the corresponding posterior probability value and confidence index.

[0045] The above describes the motherboard fault detection method in the embodiment of the present invention. The following describes the motherboard fault detection device in the embodiment of the present invention. Figure 2 In one embodiment of the present invention, a motherboard fault detection device includes: The electromagnetic field scanning module 201 is used to perform electromagnetic field scanning on the motherboard to be detected to obtain the original electromagnetic field spectrum data; A feature extraction module 202 is used to extract features from the electromagnetic field spectrum raw data to obtain a spectrum fingerprint feature vector; A modeling module 203 is configured to perform multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector, and generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; The fault source spatial location module 204 is configured to perform fault source spatial location on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial location result.

[0046] Through the collaborative efforts of these components, the electromagnetic sensor array simultaneously acquires multiple discrete frequency points, and electromagnetic radiation correction is performed based on the geometry of the PCB traces. This enables more accurate and comprehensive electromagnetic field spectrum information to be obtained. A multi-level wavelet packet decomposition algorithm is used to extract multidimensional characteristic parameters such as energy distribution coefficient, standard deviation coefficient, and mean coefficient. Compared to traditional FFT analysis methods, this method can simultaneously preserve both time-domain and frequency-domain characteristic information, significantly enhancing the ability to identify fault signatures and the accuracy of analysis. Dedicated propagation models are established for CPU clock harmonic interference, power module switching noise, and DDR memory signal crosstalk, respectively. Nonlinear coupling is achieved through multi-level superposition operations, addressing the problem of misjudgment caused by traditional methods that ignore mutual interference between circuits. A precise mapping relationship between spectral fingerprint characteristics and the physical location of the fault source is established, and the fault source is spatially located using a three-dimensional spatial coordinate system and grid cell division. This overcomes the technical limitation of traditional detection methods, which can only qualitatively determine the presence of a fault but cannot accurately locate it. Through a complete Bayesian inference process involving prior probability distribution, likelihood function, and posterior probability calculation, combined with a multi-candidate fault source competition mechanism, we achieve probabilistic and precise fault source location. This method offers greater anti-interference capabilities and positioning reliability than traditional deterministic methods. We have established a complete technical chain from electromagnetic field scanning to precise fault source location. Through in-depth mining and intelligent analysis of spectrum fingerprint features, we achieve precise tracing and identification of motherboard faults.

[0047] above Figure 2 The mainboard fault detection device in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The mainboard fault detection device in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0048] Figure 3 The figure is a schematic diagram of the structure of a motherboard fault detection device provided by an embodiment of the present invention. The motherboard fault detection device 300 may vary significantly depending on its configuration or performance. It may include one or more central processing units (CPUs) 310 (e.g., one or more processors), a memory 320, and one or more storage media 330 (e.g., one or more mass storage devices) storing application programs 333 or data 332. The memory 320 and storage medium 330 may be either transient or persistent storage. The program stored in the storage medium 330 may include one or more modules (not shown), each of which may include a series of instructions operating on the motherboard fault detection device 300. Furthermore, the processor 310 may be configured to communicate with the storage medium 330, executing the series of instructions stored in the storage medium 330 on the motherboard fault detection device 300 to implement the steps of the above-described motherboard fault detection method.

[0049] The motherboard fault detection device 300 may further include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and / or one or more operating systems 331, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. It will be understood by those skilled in the art that Figure 3 The illustrated structure of the motherboard fault detection device does not constitute a limitation on the motherboard fault detection device provided by the present invention, and may include more or fewer components than illustrated, or a combination of certain components, or a different arrangement of components.

[0050] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions, and when the instructions are run on a computer, the computer executes the steps of the motherboard fault detection method.

[0051] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0052] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0053] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting a mainboard fault, characterized in that: include: Perform electromagnetic field scanning on the motherboard to be tested to obtain the original data of the electromagnetic field spectrum; Extracting features from the original electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector; Performing multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector, generating a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; The fault source spatial location is performed on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial location result.

2. The method for detecting a mainboard fault according to claim 1, wherein: The electromagnetic field scanning is performed on the motherboard to be detected to obtain the original electromagnetic field spectrum data, including: An electromagnetic sensor array is set up on the motherboard to be detected and frequency band scanning parameters are configured, and multi-band electromagnetic signals of the motherboard to be detected are synchronously collected based on the frequency band scanning parameters to obtain multi-band electromagnetic signal collection data containing electromagnetic radiation signals of multiple discrete frequencies; Performing electromagnetic radiation correction on the PCB trace geometry of the motherboard to be tested based on the multi-band electromagnetic signal acquisition data to obtain electromagnetic signal geometry correction data; The electromagnetic signal geometric correction data is reconstructed into a spectrum matrix to obtain the original electromagnetic field spectrum data.

3. The mainboard fault detection method according to claim 1, wherein: The feature extraction of the electromagnetic field spectrum raw data to obtain a spectrum fingerprint feature vector includes: Inputting the electromagnetic field spectrum raw data into a wavelet packet decomposition algorithm to perform multi-level spectrum decomposition to obtain wavelet packet decomposition data containing multiple sub-bands; Performing energy distribution calculation, standard deviation calculation and mean calculation on each sub-band according to the wavelet packet decomposition data to obtain a multidimensional feature parameter set including energy distribution coefficient, standard deviation coefficient and mean coefficient; Performing principal component analysis and weight coefficient assignment on the multidimensional feature parameter set to obtain a target feature parameter combination; The target characteristic parameter combination is normalized and a characteristic vector is reconstructed to obtain a spectrum fingerprint characteristic vector.

4. The method for detecting a mainboard fault according to claim 1, wherein: The method performs multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector to generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters, including: Based on the spectrum fingerprint feature vector, a harmonic interference propagation model is performed on the CPU clock circuit of the motherboard circuit system in the motherboard to be detected, and a CPU clock harmonic interference propagation parameter including a harmonic frequency sequence and an interference intensity value is obtained; Based on the spectrum fingerprint feature vector, noise propagation modeling is performed on the power module switch circuit of the motherboard circuit system in the motherboard to be detected, and power module switch noise propagation parameters including noise intensity coefficient and spectrum attenuation index are obtained; Based on the spectrum fingerprint feature vector, a signal crosstalk propagation model is performed on the DDR memory circuit of the motherboard circuit system in the motherboard to be detected to obtain DDR memory signal crosstalk propagation parameters; The CPU clock harmonic interference propagation parameter, the power module switching noise propagation parameter and the DDR memory signal crosstalk propagation parameter are subjected to multi-level superposition operation and nonlinear coupling to obtain a spectrum fingerprint propagation parameter combination.

5. The mainboard fault detection method according to claim 4, characterized in that: The noise propagation modeling of the power module switch circuit of the motherboard circuit system in the motherboard to be detected is performed based on the spectrum fingerprint feature vector to obtain the power module switch noise propagation parameters including the noise intensity coefficient and the spectrum attenuation index, including: Extracting a power module frequency component based on the spectrum fingerprint feature vector, and performing switching frequency identification on a power module switch circuit of a mainboard circuit system in the mainboard to be detected based on the power module frequency component to obtain power module switching frequency feature data; Calculating the noise intensity of the power module switching circuit according to the power module switching frequency characteristic data to obtain a power supply noise intensity coefficient; Calculating a roll-off index of a spectrum attenuation characteristic of a switching circuit of the power module based on the power supply noise intensity coefficient to obtain a power supply noise spectrum attenuation index; The switching noise propagation parameters of the power module are obtained by performing a switching noise propagation analysis on the switching frequency characteristic data of the power module, the power supply noise intensity coefficient, and the power supply noise spectrum attenuation index.

6. The method for detecting a mainboard fault according to claim 1, wherein: The performing spatial location of the fault source on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial location result includes: Establishing a three-dimensional space coordinate system and dividing the motherboard to be inspected into grid units to obtain a plurality of grid units; The local spectrum fingerprint template of each grid unit is constructed according to the spatial propagation attenuation characteristics of the spectrum fingerprint propagation parameter combination to obtain the spatial distribution model of the fault source; Performing template matching calculation on the spectrum fingerprint of the motherboard to be detected according to the fault source spatial distribution model to obtain the spectrum fingerprint matching degree; The spectrum fingerprint matching degree is input into the Bayesian probability inference algorithm to calculate the probability distribution of the fault source, and the spatial positioning result of the fault source is obtained.

7. The mainboard fault detection method according to claim 6, characterized in that: The inputting the spectrum fingerprint matching degree into the Bayesian probability inference algorithm to calculate the fault source probability distribution and obtain the fault source spatial location result includes: Establishing a priori probability distribution of the device distribution density and historical fault statistics of the motherboard to be detected based on the spectrum fingerprint matching degree to obtain prior probability distribution data of the fault source; Performing a likelihood function calculation on the spectrum fingerprint matching degree according to the prior probability distribution data of the fault source to obtain a fault source likelihood function calculation result representing the correlation between the observation value and the position; Performing Bayesian posterior probability calculation based on the fault source prior probability distribution data and the fault source likelihood function calculation result to obtain fault source posterior probability calculation data including posterior probability distribution and confidence value; The fault source posterior probability calculation data is subjected to a multi-candidate fault source competition mechanism analysis and optimal position determination to obtain a fault source spatial positioning result.

8. A motherboard fault detection device, characterized in that: Used to perform the mainboard fault detection method according to any one of claims 1 to 7, the mainboard fault detection device comprising: The electromagnetic field scanning module is used to perform electromagnetic field scanning on the motherboard to be tested and obtain the original electromagnetic field spectrum data; A feature extraction module is used to extract features from the raw electromagnetic field spectrum data to obtain a spectrum fingerprint feature vector; a modeling module, configured to perform multi-level nonlinear propagation modeling on the motherboard circuit system of the motherboard to be detected based on the spectrum fingerprint feature vector, and generate a spectrum fingerprint propagation parameter combination including CPU clock harmonic interference propagation parameters, power module switching noise propagation parameters, and DDR memory signal crosstalk propagation parameters; The fault source spatial positioning module is used to perform fault source spatial positioning on the mainboard to be detected based on the spectrum fingerprint propagation parameter combination to obtain a fault source spatial positioning result.

9. A motherboard fault detection device, characterized in that: The mainboard fault detection device includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor calls the instructions in the memory to enable the mainboard fault detection device to execute the mainboard fault detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the mainboard fault detection method according to any one of claims 1 to 7 is implemented.

Images