Fault data storage method and device, controller and medium

Abstract

The invention discloses a fault data storage method and device, a controller and a medium. The invention relates to the technical field of controllers, and the method comprises the steps that a programmable logic device is controlled to write running data into an FIFO cache region according to read flag bits, and the flag bits comprise the read flag bits; if it is detected that the alarm number is generated, controlling the programmable logic device to write the alarm number into an FIFO cache region after a preset delay interruption time; and if the reading flag bit is the preset reading flag value, controlling the programmable logic device to stop writing the running data into the FIFO cache region, and controlling the processor to write the running data read from the FIFO cache region and an alarm number into a fault file and store the fault file into a storage space. According to the invention, the FIFO cache region is arranged in the controller, and the operation data and the alarm number when the fault occurs are written into the fault file to be stored in the storage space, so that the storage reliability of the fault data is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of controller technology, and in particular to a method, device, controller, and medium for storing fault data. Background Art

[0002] In the field of industrial robots, controllers, as core control units, undertake crucial responsibilities such as robot motion control, task scheduling, data processing, and fault diagnosis. With the rapid development of industrial automation and intelligent systems, the application of industrial robots in the manufacturing industry is becoming increasingly widespread, and their operating environment is becoming increasingly complex. In actual production, robot controllers may experience system anomalies or downtime due to hardware failures, software logic errors, external interference, and other factors, impacting production efficiency and product quality. However, professional personnel are often unable to conduct on-site troubleshooting. Remote problem analysis requires factory personnel to communicate with the technical support team multiple times, detailing the fault symptoms and operational procedures. This not only increases communication costs but can also lead to inaccurate or missed information, hindering problem resolution efficiency. Furthermore, it is difficult to obtain specific trigger conditions and operating data, significantly increasing the difficulty of reproducing faults. Therefore, recording and storing fault data is a key step in fault diagnosis and problem reproduction, and is crucial for improving the reliability and maintenance efficiency of industrial robot systems.

[0003] Related technologies disclose a method and device for retrieving fault data from a drive motor controller. This method continuously and continuously records fault data for M points before a fault occurs, and cumulatively records fault data for N points after the fault occurs, before storing all the data in the controller. However, this method does not address the transmission path and clock domain issues involved in the transmission process. Furthermore, controllers typically need to process high-frequency, real-time control signals and sensor data, and any storage operations must be completed in a very short time. Therefore, storing all the fault data together can increase the transmission pressure on the controller and reduce storage reliability. Summary of the Invention

[0004] Embodiments of the present invention provide a method, device, controller, and medium for storing fault data, aiming to solve the problem of low reliability of existing fault data storage.

[0005] In a first aspect, an embodiment of the present invention provides a method for storing fault data, including:

[0006] Controlling the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit;

[0007] If it is detected that an alarm number is generated, then after a preset delay interrupt time, controlling the programmable logic device to write the alarm number into the FIFO buffer area;

[0008] If the read flag is a preset read flag value, the programmable logic device is controlled to stop writing the operating data to the FIFO buffer area, and the processor is controlled to compile the operating data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

[0009] In a second aspect, an embodiment of the present invention further provides a fault data storage device, comprising:

[0010] A first control unit is configured to control the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit;

[0011] a detection control unit, configured to control the programmable logic device to write the alarm number into the FIFO buffer area after a preset delay interrupt time if it is detected that an alarm number has been generated;

[0012] The control saving unit is used to control the programmable logic device to stop writing the operating data to the FIFO buffer area if the read flag is a preset read flag value, and control the processor to compile the operating data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

[0013] In a third aspect, an embodiment of the present invention further provides a controller, which includes a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above method when executing the computer program.

[0014] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program can implement the above method when executed by a processor.

[0015] The embodiment of the present invention provides a fault data storage method, device, controller and medium. The method includes: controlling a programmable logic device to write operating data to a FIFO buffer according to a read flag, wherein the flag includes a read flag; if it is detected that an alarm number is generated, then after a preset delay interrupt time, controlling the programmable logic device to write the alarm number to the FIFO buffer; if the read flag is a preset read flag value, controlling the programmable logic device to stop writing the operating data to the FIFO buffer, and controlling the processor to write the operating data and the alarm number read from the FIFO buffer into a fault file and save it to a storage space. The technical solution of the embodiment of the present invention, by setting a FIFO buffer in the controller, not only simplifies the fault data transmission path, reduces the fault data transmission time, ensures the consistency of data during the transmission process, but also avoids the potential problems caused by clock domain conversion, thereby improving the reliability of fault data storage; and only writes the operating data and the alarm number when a fault occurs into a fault file and saves it to the storage space, thereby reducing storage pressure, saving storage space, and thus improving the reliability of fault data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic flow chart of a method for storing fault data provided by one embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a sub-process of a fault data storage method provided by an embodiment of the present invention;

[0019] Figure 3 A schematic flow chart of a fault data storage method provided in another embodiment of the present invention;

[0020] Figure 4 A schematic flow chart of a fault data storage method provided in yet another embodiment of the present invention;

[0021] Figure 5 A schematic flow chart of a fault data storage method provided in yet another embodiment of the present invention;

[0022] Figure 6 A schematic flow chart of a fault data storage method provided by yet another embodiment of the present invention;

[0023] Figure 7 A simplified flowchart of a fault data storage method provided by an embodiment of the present invention;

[0024] Figure 8 for Figure 7 A simplified flow chart of the FPGA read-write judgment module;

[0025] Figure 9 A schematic block diagram of a fault data storage device provided by an embodiment of the present invention;

[0026] Figure 10 A schematic block diagram of a controller provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0029] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0031] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0032] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for storing fault data provided by an embodiment of the present invention. The method for storing fault data is described in detail below. Figure 1 As shown, the method includes the following steps S110-S130.

[0033] S110 . Control the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit.

[0034] In the embodiment of the present invention, the programmable logic device is an FPGA. FPGA (Field-Programmable Gate Array) is a highly flexible and programmable hardware device. FIFO is a first-in-first-out queue structure transmission method. The operating data is the data when the controlled object is running, specifically including the speed setting, speed feedback, torque setting and torque feedback data when the controlled object is running. It can be understood that when the controller is a robot controller, the controlled object is a robot. The flag bit also includes a read empty flag bit and a read flag bit, such as Figure 2 As shown, step S110 may specifically include steps S111-S112: S111, reading the read empty flag and the read flag; S112, if the read empty flag is a preset read empty flag value and the read flag is not the preset read flag value, controlling the programmable logic device to write the operating data into the FIFO buffer. It should be noted that in this embodiment, the flag also includes a write full flag, and the read empty flag is a Fifo read empty flag, and the write full flag is a Fifo write full flag. The Fifo read empty flag and the Fifo write full flag are both flags set in the FIFO buffer. The Fifo read empty flag indicates that there is no data in the FIFO buffer, and the Fifo write full flag indicates that the FIFO buffer is full of data. The read flag indicates that the FPGA notifies the processor to read the data in the FIFO buffer, wherein the processor is an ARM Cortex-A53 processor. It is understandable that in other embodiments, the processor may also be other types of processors. It should also be noted that, in this embodiment, the preset read empty flag value is 1, the preset read flag value is 1, and if the read flag is not 1, it is a preset non-read flag value, and the preset non-read flag value is 0. It can be understood that when the read empty flag is 1 and the read flag is 0, the programmable logic device is controlled to write the operating data to the FIFO buffer area.

[0035] S120: If it is detected that an alarm number is generated, the programmable logic device is controlled to write the alarm number into the FIFO buffer after a preset delay interruption time.

[0036] In an embodiment of the present invention, after the programmable logic device is controlled to write the operating data into the FIFO buffer area according to the read empty flag and the read flag, the controlled object is controlled to enter the enabled state and start running. If it is detected that an alarm number is generated, indicating that a fault has occurred in the controlled object, then after a preset delay interruption time, the programmable logic device is controlled to write the alarm number instead of the operating data into the FIFO buffer area. It should be noted that, in this embodiment, the preset delay interruption time is the time for a preset number of interruptions, wherein the preset number is 8191. It should also be noted that, in this embodiment, after the programmable logic device is controlled to write the alarm number into the FIFO buffer area, the read flag will also be set to a preset read flag value, that is, the read flag will be set to 1. The alarm number is the controller fault number.

[0037] S130. If the read flag is a preset read flag value, the programmable logic device is controlled to stop writing the operating data to the FIFO buffer area, and the processor is controlled to compile the operating data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

[0038] In an embodiment of the present invention, if the read flag is 1, the programmable logic device is controlled to stop writing the operating data to the FIFO buffer area, and the processor is controlled to read the operating data and the alarm number from the FIFO buffer area, and the operating data and the alarm number are written into a fault file in a preset format and saved to the storage space, wherein the preset format is the file format allowed by the controller storage security file.

[0039] Figure 3 A flowchart of a fault data storage method provided by another embodiment of the present invention is shown in FIG. Figure 3 As shown, in this embodiment, the method includes steps S100 to S130. That is, in this embodiment, the method further includes step S100 before step S110 of the above embodiment.

[0040] S100 , in response to a startup instruction, controlling the programmable logic device to generate the operating data of the controlled object.

[0041] In an embodiment of the present invention, when the controller is started, it controls the programmable logic device to generate the operating data of the controlled object, so that the controller controls the programmable logic device to write the operating data into the FIFO buffer area according to the read flag bit.

[0042] Figure 4 A flowchart of a method for storing fault data is provided in accordance with another embodiment of the present invention. Figure 4 As shown, in this embodiment, the method includes steps S100 to S140. That is, in this embodiment, the method further includes step S140 after step S130 of the above embodiment.

[0043] S140 , if the processor reads the read empty flag, then the read flag is set to a preset non-read flag value, and the process returns to step 100 .

[0044] In the embodiment of the present invention, if the processor reads the read empty flag, indicating that the reading of data in the FIFO buffer area is completed, the processor sets the read flag to 0 and returns to step S100.

[0045] Figure 5 A flowchart of a method for storing fault data provided by another embodiment of the present invention is shown in FIG. Figure 5 As shown, in this embodiment, the method includes steps S100 to S150. That is, in this embodiment, the method further includes step S150 after step S110 of the above embodiment.

[0046] S150: If the alarm signal is not detected and the read flag is not the preset read flag value, control the programmable logic device to read and write the FIFO buffer area according to the full flag.

[0047] In an embodiment of the present invention, if the alarm signal is not detected and the read flag is 0, the programmable logic device is controlled to read and write the FIFO buffer area according to the full flag. Specifically, it is determined whether the preset full flag value is the preset full flag value, wherein the preset full flag value is 1. If the full flag is not the preset full flag value, that is, the full flag is 0, the process returns to executing the step of controlling the programmable logic device to write operation data to the FIFO buffer area according to the read flag, that is, returns to executing step S110; if the full flag is the preset full flag value, that is, if the full flag is 1, the programmable logic device is controlled to read the operation data stored in the FIFO buffer area, and write the new operation data to the FIFO buffer area, that is, the programmable logic device is enabled to read and write data to the FIFO buffer area at the same time.

[0048] Figure 6 A flowchart of a method for storing fault data is provided in yet another embodiment of the present invention, as shown in FIG. Figure 6As shown, in this embodiment, the method includes steps S100 to S160. That is, in this embodiment, the method further includes step S160 after step S150 of the above embodiment.

[0049] S160 , determining whether the read flag is the preset non-read flag value; if the read flag is not the preset non-read flag value, returning to step 120 ; otherwise, returning to step S150 .

[0050] In the embodiment of the present invention, if the read flag is 1, indicating that the controlled object has a fault, the process returns to step 120; if the read flag is 0, indicating that the controlled object is operating normally and no fault has occurred, the process returns to step S150.

[0051] See also Figure 7 and Figure 8 , Figure 7 A simplified flowchart of a fault data storage method provided by an embodiment of the present invention is shown below. Figure 8 for Figure 7 The flow chart of FPGA read and write judgment module is as follows: Figure 7 and Figure 8 In the example, FPGA represents a programmable logic device, FIFO represents a FIFO buffer, the Fifo read empty flag is the read empty flag, the Fifo write full flag is the write full flag, and the A53 read flag is the read flag. Figure 7 and Figure 8 As shown, the fault data storage in this embodiment specifically includes the following steps: Step 1, when the controller is started, the FPGA generates the operating data of the controlled object; Step 2, obtain the Fifo read empty flag and A53 read the Fifo flag; Step 3, if the Fifo read empty flag is 1 and the A53 read flag is 0, the FPGA can write the speed setting, speed feedback, torque setting, torque feedback and other operating data of the controlled object to the Fifo; Step 4, the controlled object enters the enabled state and starts running, and continues to execute if there is no fault; Step 5, if a fault is detected, the FPGA will report after a delay of 8191 interrupts. The alarm signal is written into the FIFO instead of the operating data, and the A53 read flag is set to 1. Step 6: If the A53 read flag is 1, the FPGA stops writing data to the FIFO. A53 reads the operating data in the FIFO and, after reading the alarm signal, compiles the operating data and the alarm signal into a fault file and stores it in the storage space. Step 7: When A53 reads the FIFO read empty flag, the A53 read flag is set to 0, and the process returns to Step 1. Step 8: If there is no fault, and the A53 flag is 0, the FPGA determines that the flag is full. Step 9: If the FIFO full flag is 0, the process returns to Step 3.

[0052] Step 10: If the FIFO full flag is 1, the FPGA enters the simultaneous read and write FIFO mode. Step 11: The FPGA first reads the operating data that entered the FIFO earlier, then writes the newly acquired operating data into the FIFO. Step 12: Determine whether the A53 read flag is 0. If it is 1, it indicates that the controlled object has failed, and repeat steps 5, 6, and 7. After completing step 7, return to step 1. Step 13: If the A53 read flag is 0, return to step 11, and normal operation will occur without any failure.

[0053] To sum up, in this embodiment, by setting a FIFO buffer area in the controller, not only the fault data transmission path is simplified, the fault data transmission time is reduced, and the consistency of data during the transmission process is ensured, but also the potential problems caused by clock domain conversion are avoided, and the reliability of fault data storage is improved; and only the operating data and alarm number when the fault occurs are written into a fault file and saved to the storage space, which reduces storage pressure, saves storage space, and thus improves the reliability of fault data storage.

[0054] Figure 9 FIG. 2 is a schematic block diagram of a fault data storage device 200 provided by an embodiment of the present invention. Figure 9 As shown, corresponding to the above fault data storage method, the present invention also provides a fault data storage device 200. The fault data storage device 200 includes a unit for executing the above fault data storage method, and the device can be configured in a controller. Figure 9 The fault data storage device 200 includes a first control unit 201 , a detection control unit 202 and a control storage unit 203 .

[0055] Among them, the first control unit 201 is used to control the programmable logic device to write operation data to the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit; the detection control unit 202 is used to control the programmable logic device to write the alarm number into the FIFO buffer area after a preset delay interrupt time if it is detected that an alarm number is generated; the control and storage unit 203 is used to control the programmable logic device to stop writing the operation data to the FIFO buffer area if the read flag bit is a preset read flag value, and control the processor to compile the operation data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

[0056] In some embodiments, such as this embodiment, the first control unit 201 includes a reading unit and a first control subunit.

[0057] Among them, the reading unit is used to read the read empty flag and the read flag; the first control subunit is used to control the programmable logic device to write the operating data to the FIFO buffer area if the read empty flag is a preset read empty flag value and the read flag is not the preset read flag value.

[0058] In some embodiments, such as the present embodiment, the fault data storage device 200 further includes a second control unit, a setting unit, a third control unit, a judgment unit, a first return execution unit, and a second return execution unit.

[0059] The second control unit is configured to control the programmable logic device to generate the operating data of the controlled object in response to a startup instruction; the setting unit is configured to set the read flag to a preset non-read flag value if the processor reads the read empty flag, and return to executing the step of controlling the programmable logic device to generate the operating data of the controlled object in response to the startup instruction; the third control unit is configured to control the programmable logic device to read and write the FIFO buffer area according to the write full flag if the alarm signal is not detected and the read flag is not the preset read flag value; the judgment unit is configured to judge whether the read flag is the preset non-read flag value; the first return execution unit is configured to return to executing the step of controlling the programmable logic device to write the alarm signal to the FIFO buffer area after a preset delay interruption time if the read flag is not the preset non-read flag value; and the second return execution unit is configured to return to executing the step of controlling the programmable logic device to read and write the FIFO buffer area according to the write full flag if the read flag is the preset non-read flag value.

[0060] In some embodiments, such as this embodiment, the third control unit includes a third return execution unit and a second control subunit.

[0061] Among them, the third return execution unit is used to return to execute the step of controlling the programmable logic device to write operating data to the FIFO buffer area according to the read flag if the full flag is not the preset full flag value; the second control subunit is used to control the programmable logic device to read the operating data stored in the FIFO buffer area and write the new operating data into the FIFO buffer area if the full flag is the preset full flag value.

[0062] The above-mentioned fault data storage device can be implemented in the form of a computer program. The computer program can be used in Figure 10 Runs on the controller shown.

[0063] See also Figure 10 , Figure 10 FIG3 is a schematic block diagram of a controller provided by an embodiment of the present invention. The controller 300 is a device with a fault data storage function.

[0064] See Figure 10 The controller 300 includes a processor 302 , a memory, and a network interface 305 connected via a system bus 301 , wherein the memory may include a non-volatile storage medium 303 and an internal memory 304 .

[0065] The non-volatile storage medium 303 may store an operating system 3031 and a computer program 3032. When the computer program 3032 is executed, the processor 302 may execute a fault data storage method.

[0066] The processor 302 is used to provide computing and control capabilities to support the operation of the entire controller 300 .

[0067] The internal memory 304 provides an environment for the operation of the computer program 3032 in the non-volatile storage medium 303. When the computer program 3032 is executed by the processor 302, the processor 302 can execute a fault data storage method.

[0068] The network interface 305 is used to communicate with other devices through the network. Figure 10 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the controller 300 to which the solution of the present invention is applied. The specific controller 300 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0069] The processor 302 is configured to run a computer program 3032 stored in a memory to implement any embodiment of the above-mentioned fault data storage method.

[0070] It should be understood that in the embodiment of the present invention, the processor 302 may be a central processing unit (CPU), and the processor 302 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0071] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0072] Therefore, the present invention further provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to execute any embodiment of the above-mentioned fault data storage method.

[0073] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0074] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0075] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0076] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0077] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for causing a controller to execute all or part of the steps of the method described in various embodiments of the present invention.

[0078] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0079] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, to the extent such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to encompass such changes and modifications.

[0080] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for storing fault data, characterized in that: include: Controlling the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit; If it is detected that an alarm number is generated, then after a preset delay interrupt time, controlling the programmable logic device to write the alarm number into the FIFO buffer area; If the read flag is a preset read flag value, the programmable logic device is controlled to stop writing the operating data to the FIFO buffer area, and the processor is controlled to compile the operating data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

2. The method according to claim 1, characterized in that The flag bit also includes a read empty flag bit, and the step of controlling the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit includes: Reading the read empty flag and the read flag; If the read empty flag is a preset read empty flag value and the read flag is not the preset read flag value, the programmable logic device is controlled to write the operating data into the FIFO buffer area.

3. The method according to claim 2, characterized in that Before the step of controlling the programmable logic device to write the operation data into the FIFO buffer area according to the read flag bit, the method further includes: In response to a start-up instruction, the programmable logic device is controlled to generate the operating data of the controlled object.

4. The method according to claim 3, characterized in that After the control processor compiles the operating data and the alarm number read from the FIFO buffer into a fault file and saves it into a storage space, the method further includes: If the processor reads the read empty flag, it sets the read flag to a preset non-read flag value and returns to execute the step of controlling the programmable logic device to generate the operating data of the controlled object in response to the start instruction.

5. The method according to any one of claims 1 to 4, characterized in that The flag bit also includes a full flag bit, and the method further includes: If the alarm signal is not detected and the read flag is not the preset read flag value, the programmable logic device is controlled to read and write the FIFO buffer area according to the full flag.

6. The method according to claim 5, characterized in that The step of controlling the programmable logic device to read and write the FIFO buffer area according to the full flag bit includes: If the full flag bit is not the preset full flag value, returning to the step of controlling the programmable logic device to write the operation data into the FIFO buffer area according to the read flag bit; If the full flag is the preset full flag value, the programmable logic device is controlled to read the operating data stored in the FIFO buffer area and write the new operating data into the FIFO buffer area.

7. The method according to claim 5, characterized in that After the step of controlling the programmable logic device to read and write the FIFO buffer area according to the full flag bit, the method further includes: Determining whether the read flag bit is the preset non-read flag value; If the read flag bit is not the preset non-read flag value, returning to the step of controlling the programmable logic device to write the alarm number into the FIFO buffer area after the preset delay interrupt time; If the read flag is the preset non-read flag value, the process returns to executing the step of controlling the programmable logic device to read and write the FIFO buffer area according to the full flag.

8. A fault data storage device, characterized in that: include: A first control unit is configured to control the programmable logic device to write operation data into the FIFO buffer area according to the read flag bit, wherein the flag bit includes a read flag bit; a detection control unit, configured to control the programmable logic device to write the alarm number into the FIFO buffer area after a preset delay interrupt time if it is detected that an alarm number has been generated; The control saving unit is used to control the programmable logic device to stop writing the operating data to the FIFO buffer area if the read flag is a preset read flag value, and control the processor to compile the operating data and the alarm number read from the FIFO buffer area into a fault file and save it to the storage space.

9. A controller, characterized in that: The controller includes a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the computer program can implement the method according to any one of claims 1 to 7.

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