Sequential margin detection device and method and integrated circuit

Abstract

The embodiment of the invention discloses a timing margin detection device and method and an integrated circuit. The time sequence margin detection device comprises a time sequence path and a time sequence margin circuit which are independent of a detected circuit, wherein the time sequence path is configured to receive the same clock signal as the detected circuit; and the time sequence margin circuit obtains the time sequence margin of the detected circuit by detecting the time sequence path. According to the detection device for the time sequence margin, the measurement of the time sequence margin and the decoupling of the detected circuit do not depend on the selection of a key time sequence path any more, and the complexity caused by searching the key time sequence path in the chip design process is reduced. In the detection of the time sequence margin, independent operation can be realized, and observation signals are not led out from the detected circuit any more, so that the influence on the detected circuit is reduced, and iteration repetition is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a timing margin detection device, method, and integrated circuit. Background Art

[0002] During the integrated circuit design process, timing closure is crucial to ensuring that the designed circuit meets timing requirements and operates according to the pre-set logic. Timing closure is affected by various factors, such as temperature, voltage noise, on-chip variation (OCV), process variation, and aging. Therefore, during the timing closure phase, a large amount of timing margin is reserved for the circuit to address the worst-case scenario, resulting in wasted timing margin. Summary of the Invention

[0003] The present application provides a timing margin detection device, method, and integrated circuit to reduce the waste of timing margin in the timing closure stage.

[0004] In a first aspect, a timing margin detection device is provided, comprising a timing path independent of a circuit under test and a timing margin circuit, wherein the timing path is configured to receive the same clock signal as the circuit under test, and the timing margin circuit obtains the timing margin of the circuit under test by detecting the timing path.

[0005] The above detection device can decouple the measurement of the timing margin from the circuit under test, so that the measurement of the timing margin no longer depends on the selection of the critical timing path, reducing the complexity brought about by finding the critical timing path during the chip design process.

[0006] In one implementation, the timing margin circuit includes a calibration module and a detection module, wherein the calibration module is used to calibrate the timing path in a first operating mode so that the timing delay of the timing path is aligned with the timing delay of the circuit under test; the detection module is used to detect the timing margin of the timing path in a second operating mode, and the timing margin is used to characterize the timing margin of the circuit under test.

[0007] The above detection device can operate independently during timing margin detection and no longer draws observation signals from the circuit under test, thereby reducing the impact on the circuit under test and the occurrence of repeated iterations. Before monitoring the timing margin of the circuit under test, the timing margin of the timing path can be calibrated to align the timing margin of the timing path with the timing margin of the circuit under test. This makes the timing margin detection solution flexible and applicable to different chips, realizing chip-specific timing margin measurement, and at the same time obtaining more accurate detection results that better reflect the actual timing margin situation of the chip.

[0008] In one implementation, the first operating mode corresponds to the lowest voltage or the highest frequency of the circuit under test; the second operating mode corresponds to the operating voltage or the operating frequency of the circuit under test.

[0009] In one implementation, the detection device further includes a gating circuit, which is configured to gating the timing path as a part of the sensing circuit in the third operating mode, and utilizing the output of the sensing circuit to determine the lowest voltage or the highest frequency.

[0010] Compared with the conventional minimum voltage test and maximum frequency test process, which requires step-by-step adjustment of the voltage test gear and the frequency test gear to obtain the lowest voltage or the highest frequency, the above detection device improves the efficiency of the calibration module in obtaining the lowest voltage or the highest frequency in the first working mode, accelerates the alignment speed of the timing delay results of the calibration module, and saves on-chip space by switching the working mode of the selection circuit to reuse part of the timing path to form the sensing circuit.

[0011] In one implementation, the sensing circuit includes an oscillating ring. A statistical correlation between the oscillating ring frequency and the minimum voltage or maximum frequency is utilized to predict the numerical range of the minimum voltage or maximum frequency using an algorithm such as linear regression of an empirical formula representing the relationship between the oscillating ring frequency and the minimum voltage or maximum frequency, thereby reducing calibration time of the calibration module in the first operating mode.

[0012] In one implementation, the detection module is further configured to generate a first signal when detecting that the timing margin is less than or equal to a first threshold, the first signal being configured to indicate a first timing margin state. Alternatively, the detection module is further configured to generate a first signal when detecting that the timing margin is less than or equal to the first threshold a first preset number of times, the first signal being configured to indicate a first timing margin state.

[0013] When the detection module determines that the detected timing margin is less than or equal to the pre-calibrated threshold range and a timing margin too low exception occurs, a first signal is generated to represent the current abnormal state to prompt the functional module under test circuit that cooperates with the detection module to have an abnormality in the current timing margin, so as to reduce the risk of timing violation; or, when the abnormality reaches a certain number of times, a first signal is generated to prevent the voltage fluctuation from causing the detection module to falsely report an abnormality and affect the accuracy of the detection result of the detection module.

[0014] In one implementation, the detection module is further configured to generate a second signal when detecting that the timing margin is greater than or equal to a second threshold, the second signal being configured to indicate a second timing margin state. Alternatively, the detection module is further configured to generate a second signal when detecting that the timing margin is greater than or equal to the second threshold a second preset number of times, the second signal being configured to indicate a second timing margin state.

[0015] When the detection module determines that the detected timing margin is greater than or equal to a pre-calibrated threshold range and a timing margin is too high abnormality occurs, a second signal is generated to represent the current abnormal state to prompt the functional module under test circuit that cooperates with the detection module to have an abnormality in the current timing margin, so as to reduce the waste of timing margin and optimize power consumption; or, when the abnormality reaches a certain number of times, a second signal is generated to prevent voltage fluctuations from causing the detection module to falsely report an abnormality and affect the accuracy of the detection result of the detection module.

[0016] In one implementation, the detection module is used to detect the timing margin of the timing path within the sampling delay window, and sample the timing margin in a windowed manner to further prevent local voltage fluctuations from causing frequent abnormalities in the timing margin detection results, thereby improving the stability of the timing margin sampling results.

[0017] In one implementation, the detection device also includes a signal generating circuit and a signal receiving circuit, wherein the signal generating circuit generates a transmission signal under the drive of a clock signal, the transmission signal reaches the signal receiving circuit through a timing path, and the signal receiving circuit obtains a reception signal; the calibration module calibrates the timing path in the first working mode, and calibrating the timing path includes adjusting the timing delay of the timing path by comparing the transmission signal and the reception signal to calibrate the timing path.

[0018] In one implementation, the timing path includes an adjustable delay circuit and a sampling delay circuit.

[0019] In one implementation, the adjustable delay circuit includes a first selection end and a second selection end, wherein the first selection end is used to conduct a first path among multiple first delay paths; the second selection end is used to conduct a second path among multiple second delay paths; the delay of the first delay path is greater than the delay of the second delay path; and a calibration module is connected to the first selection end and the second selection end, respectively, to control the first selection end and the second selection end to select the path to be conducted.

[0020] The above detection device divides two groups of adjustment paths in the adjustable delay circuit to jointly adjust the timing delay of the adjustable delay circuit. By setting two groups of adjustment paths with different delays and their coordinated selection ends, each selection end has a different adjustment accuracy when selecting the corresponding adjustment path, thereby realizing a multi-precision coordinated adjustable delay circuit and improving the adjustment accuracy of the adjustable delay circuit during the calibration process.

[0021] In one implementation, the delay of the first delay path is less than or equal to the total delay of the plurality of second delay paths.

[0022] In one implementation, the adjustable delay circuit includes a first multiplexer and a second multiplexer, wherein the first multiplexer includes multiple first input terminals, a first selection terminal and a first output terminal, and the multiple first input terminals are respectively connected to multiple first delay paths; the second multiplexer includes multiple second input terminals, a second selection terminal and a second output terminal, and the multiple second input terminals are respectively connected to multiple second delay paths, and the multiple second delay paths include a third path connected to the first output terminal, the third path is the same as or different from the second path, and the second output terminal is connected to the sampling delay circuit.

[0023] In one implementation, the sampling delay circuit includes multiple delay terminals; the detection device also includes multiple latches, the data terminals of the multiple latches are respectively connected to the multiple delay terminals, the enable terminals are coupled to the clock signal, and the output terminals are connected to the detection module.

[0024] In one implementation, the signal generating circuit is coupled to a clock signal, and outputs an inverted signal as a transmitting signal when a clock trigger edge arrives.

[0025] In one implementation, the signal generating circuit includes a register and an inverter, wherein a clock signal terminal of the register is coupled to a clock signal; and the inverter is connected between an input terminal and an output terminal of the register.

[0026] In one implementation, the timing path represents the timing margin of the circuit under test in units of buffers.

[0027] In a second aspect, an integrated circuit is provided, comprising a circuit under test and any one of the detection devices provided in the first aspect above, wherein the circuit under test operates under the drive of a clock signal, and the detection device is used to detect the timing margin of the circuit under test.

[0028] In one implementation, the integrated circuit further includes a clock circuit for outputting a clock signal.

[0029] According to a third aspect, a timing margin detection method is provided for detecting the timing margin of an integrated circuit, wherein the integrated circuit includes a circuit under test and a timing margin detection device, the detection device including a timing path independent of the circuit under test; the detection method includes: setting the operating parameters of the integrated circuit to a working state; in the working state, obtaining the timing margin of the timing path of the detection device, the timing margin of the timing path being used to characterize the timing margin of the circuit under test.

[0030] In one implementation, the above detection method further includes: setting the operating parameters of the integrated circuit to a critical state of the timing margin; and adjusting the timing delay of the timing path so that the timing delay of the timing path is aligned with the timing delay of the circuit under test. Setting the operating parameters of the integrated circuit to the operating state includes: setting the operating parameters of the integrated circuit to the operating state after the timing delay of the timing path is aligned with the timing delay of the circuit under test.

[0031] In one implementation, it also includes: generating a first signal or a second signal based on the timing margin of the timing path, wherein the first signal is generated when the timing margin is less than or equal to a first threshold or when the timing margin is less than or equal to the first threshold and reaches a first preset number of times, and is used to indicate a first timing margin state; the second signal is generated when the timing margin is greater than or equal to a second threshold or when the timing margin is greater than or equal to the second threshold and reaches a second preset number of times, and is used to indicate a second timing margin state.

[0032] In one implementation, the operating parameter includes voltage or frequency, and setting the operating parameter of the integrated circuit to a critical state of the timing margin includes: setting the voltage of the integrated circuit to a minimum voltage, the minimum voltage corresponding to the critical state of the timing margin; or setting the frequency of the integrated circuit to a maximum frequency, the maximum frequency corresponding to the critical state of the timing margin.

[0033] In a fourth aspect, a controller is also provided, comprising the integrated circuit implemented in the second aspect above.

[0034] In the fifth aspect, a vehicle is also provided, comprising the controller provided in the fourth aspect.

[0035] In a sixth aspect, a computer-readable storage medium is further provided, comprising instructions stored thereon, wherein when the instructions are executed by a processor, the control method implemented in either the first aspect or the first aspect is executed.

[0036] In a seventh aspect, a computer program product is also provided, comprising instructions, wherein when the instructions are executed by a processor, the control method implemented in any one of the first aspect or the second aspect is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the following is a brief introduction to the drawings used in the description of the embodiments. The drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0038] Figure 1 An exemplary structural block diagram of an integrated circuit provided in an embodiment of the present application;

[0039] Figure 2 is an exemplary schematic diagram of a non-independent timing margin detection;

[0040] Figure 3 An exemplary structural block diagram of a timing margin detection device provided in an embodiment of the present application;

[0041] Figure 4An exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application;

[0042] Figure 5 An exemplary flow chart of a minimum voltage search process provided in an embodiment of the present application;

[0043] Figure 6 An exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application;

[0044] Figure 7 An exemplary schematic diagram of a timing margin state provided in an embodiment of the present application;

[0045] Figure 8 An exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application;

[0046] Figure 9 An exemplary flow chart of a method for calibrating a timing path provided in an embodiment of the present application;

[0047] Figure 10 An exemplary flow chart of another method for calibrating a timing path provided in an embodiment of the present application;

[0048] Figure 11 An exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application;

[0049] Figure 12 An exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application;

[0050] Figure 13 This is an exemplary schematic diagram of calibration of a data path signal of a circuit under test and a timing path signal of a detection device provided in an embodiment of the present application;

[0051] Figure 14 This is an exemplary schematic diagram of a data path signal of a circuit under test and a timing path signal of a detection device in a working state provided by an embodiment of the present application;

[0052] Figure 15 An exemplary flow chart of a timing margin detection method is provided for an embodiment of the present application;

[0053] Figure 16 An exemplary flowchart of another timing margin detection method is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The embodiments described below are only some embodiments of the present application. For those of ordinary skill in the art, other embodiments can be obtained based on these embodiments without inventive work. Any adjustments and improvements made without departing from the concept of the present application are within the scope of protection of the present application.

[0055] To simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure. They do not represent the actual structure of the product. In addition, to simplify the drawings and facilitate understanding, in some figures, only a portion of the components with the same structure or function are schematically depicted. In reality, more or fewer components with the same structure or function may exist.

[0056] In the embodiments of the present application, unless otherwise clearly specified and limited, ordinal numbers such as "first", "second", etc. are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects; in addition, it does not represent the number of related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which represents the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects, for example, "a and / or b" includes: "a alone", "b alone", or "a and b".

[0057] In the embodiments of the present application, "connection" includes direct connection or indirect connection, which can be directly connected through a medium (for example, a wire, a trace, etc.), or can be indirectly connected through other elements, or can be internally connected.

[0058] During the design of integrated circuits (such as chips), timing closure ensures that the designed circuits meet timing requirements and operate properly according to the pre-set logic. Timing closure is a crucial step in IC design. Taking chips as an example, timing closure is crucial to the mass production yield of chips after they are returned for production, and even to the proper implementation of the chip's designed functionality. Timing closure is affected by various factors, such as temperature, voltage noise, on-chip variation (OCV), process variations, and aging effects. Therefore, during the timing closure phase, a significant amount of timing margin is reserved for the chip to account for possible worst-case scenarios. However, the probability of encountering the worst-case scenario is extremely low during chip manufacturing and application, and most chips have a significant amount of wasted timing margin. For a given operating frequency, chip timing margin is positively correlated with chip power consumption. For power-sensitive applications, it is desirable to reduce excess timing margin to a reasonable range to reduce the chip's operating power consumption.

[0059] Based on this, the embodiment of the present application embeds a timing margin detection device on the chip, which can realize individualized timing margin measurement of the chip and reduce the waste of timing margin; thus, the operating voltage of the chip can be dynamically set according to the actual manufacturing and working conditions of the chip to achieve power consumption optimization.

[0060] The following is a description with reference to the accompanying drawings:

[0061] Please refer to Figure 1 , which is an exemplary structural block diagram of an integrated circuit provided in an embodiment of the present application. Figure 1 As shown, the integrated circuit 100 includes a circuit under test 110 and a timing margin detection device 120; the detection device 120 is used to detect the timing margin of the circuit under test. In an embodiment of the present application, the detection device 120 includes a timing path independent of the circuit under test, and the timing margin of the circuit under test is obtained by detecting the timing path; the timing path is coupled to the same clock signal as the circuit under test.

[0062] The timing path of the detection device 120 is independent of the circuit under test. This means that the timing elements of the timing path of the detection device 120 transmit signals at their input and output ends independently of the circuit under test, with only the clock signals used for driving them being the same. In other words, the timing path of the detection device 120 contains no data signals from the circuit under test.

[0063] In one implementation, the timing path and the circuit under test are coupled to two identical clock signals; in another implementation, the timing path and the circuit under test are coupled to the same clock signal. Coupling the same clock signal can simplify the calibration requirements between the two clock signals and simplify the circuit implementation. Please continue to refer to Figure 1 The clock signal may be provided by a clock circuit 130, such as a phase-locked loop (PLL) clock circuit. Alternatively, the clock circuit 130 may be integrated into the integrated circuit 100 to form an on-chip clock source, or the clock circuit 130 may be located outside the integrated circuit 100 to form an off-chip clock source.

[0064] The circuit under test in the embodiments of the present application can be any type of circuit, without any restrictions on its function, composition, structure, parameters, etc. For example, it can be a circuit module that has been designed and verified for reuse, or it can be an application-specific integrated circuit (ASIC) designed to implement a specific function; or it can be a circuit implemented by a programmable logic device (PLD), such as a field programmable gate array (FPGA), etc.

[0065] The above embodiments not only enable individualized timing margin measurement for chips, thus reducing timing margin waste, but also dynamically set the operating voltage for the chip based on its actual manufacturing and operating conditions, thereby optimizing power consumption. They also reduce chip design complexity, bringing significant advantages to chip design.

[0066] For example, the above timing margin detection device uses a timing path independent of the circuit under test to detect the timing margin of the circuit under test. Compared with the scheme of extracting the data signal from the circuit under test as the observation signal to measure the timing margin, it has many advantages. The following is a description with reference to the accompanying drawings:

[0067] Please refer to Figure 2 , which is an exemplary schematic diagram of a non-independent timing margin detection. Figure 2 As shown in the figure, D represents the input end of the register, Q represents the output end of the register, and clk represents the clock signal end of the register. A timing circuit is connected between timing devices (such as registers), and the timing circuit is, for example, a combination logic of a logic element. The timing margin detection device pulls the data signal from the D end of the register as an observation signal to observe the time when the signal arrives at the D end of the register after passing through the combination logic compared to the advance of the next clock edge, thereby sensing the timing margin of the circuit under test. Using this timing margin detection scheme, there are at least the following problems:

[0068] First, there are a large number (e.g., hundreds of millions) of timing paths in actual logic circuits, but only the timing margin of the critical timing path (the path with the smallest timing margin) is the determining factor. The critical timing path can only be determined when timing closure is nearing completion. Therefore, an additional engineering change order (ECO) process can only be added near the end of the chip physical implementation to connect the finalized critical signals (i.e., the observation signals from the critical timing path) to the timing margin detection device. This increases the complexity of the back-end implementation process. At the same time, this operation itself may affect the timing margin of the detected signal, resulting in new timing violation risks; this leads to frequent iterations during the implementation process, and even forced abandonment of detection of some critical signals.

[0069] Second, with advanced semiconductor processes, on-chip variations are becoming increasingly significant. Consequently, the critical timing paths identified during timing closure may not necessarily be the critical timing paths on the actual chip. If timing margin testing is performed on all critical timing paths during chip design implementation, this will increase complexity. Furthermore, even if timing margin testing is performed on all critical timing paths during chip design implementation, there is no guarantee that the actual timing margin will be accurately observed on the actual chip.

[0070] Compared to Figure 2 The timing margin detection scheme shown in the embodiment of the present application Figure 1 The proposed solution decouples timing margin measurement from the circuit under test, making it independent of the selection of critical timing paths and reducing the complexity of finding critical timing paths during chip design. Timing margin detection can be performed independently, without drawing observation signals from the circuit under test. This reduces the impact on the circuit under test and reduces the need for repeated iterations.

[0071] The following describes a device for detecting a timing margin with reference to the accompanying drawings.

[0072] Please refer to Figure 3 , which is an exemplary structural block diagram of a timing margin detection device provided by an embodiment of the present application. Figure 3 As shown, the detection apparatus 300 includes a timing path 310 independent of the circuit under test and a timing margin circuit 320. The timing path 310 is configured to receive the same clock signal as the circuit under test; the timing margin circuit 320 obtains the timing margin of the circuit under test by detecting the timing path 310.

[0073] This detection device decouples timing margin measurement from the circuit under test, making it independent of the selection of critical timing paths and reducing the complexity of finding critical timing paths during chip design. Timing margin detection can be performed independently, without drawing observation signals from the circuit under test. This reduces the impact on the circuit under test and reduces the need for repeated iterations.

[0074] The timing margin detection device 120 or 300 may include a first operating mode and a second operating mode. The first operating mode, also known as a calibration mode, is used to calibrate the timing path of the detection device so that the timing delay of the timing path is aligned with the timing delay of the circuit under test. The second operating mode, also known as a task mode, is used to monitor the timing margin of the circuit under test in a working environment; the timing margin of the calibrated timing path can represent the timing margin of the circuit under test. Therefore, the detection device monitors the timing margin of the circuit under test by detecting the timing margin of the timing path.

[0075] The timing margin circuit 320 can adjust and detect the timing margin of the timing path 310, such as Figure 4 As shown, the system includes a calibration module (or calibration circuit) 321 and a detection module (or detection circuit) 322. The calibration module 321 is used to calibrate the timing path 310 in the first operating mode so that the timing delay of the timing path 310 is aligned with the timing delay of the circuit under test; the detection module 322 is used to detect the timing margin of the timing path 310 in the second operating mode, and the timing margin is used to characterize the timing margin of the circuit under test.

[0076] The timing path of the detection device and the circuit under test are constructed using the same standard cell library and back-end implementation methodology. The timing margin of the timing path and the timing margin of the circuit under test have a very strong statistical correlation. The timing margin of the actual circuit (i.e., the circuit under test) is characterized by the timing margin of the timing path, so that the detection results can better reflect the actual timing margin of the actual circuit. In addition, before monitoring the timing margin of the circuit under test, the timing margin of the timing path can be calibrated to align the timing margin of the timing path with the timing margin of the circuit under test, making the timing margin detection solution flexible and applicable to different chips, realizing individualized timing margin measurement of the chip, and at the same time obtaining more accurate detection results that better reflect the actual timing margin of the chip.

[0077] In some embodiments of the present application, the calibration of the timing path can be achieved by aligning the minimum voltage (VMIN). In this method, the timing margin boundary of the circuit under test is explored by the minimum voltage search (Vmin search), that is, the operating voltage corresponding to the timing margin being substantially 0 is searched; thereby obtaining a critical state in which the timing margin of the integrated circuit is substantially 0. After the minimum voltage search is completed, the minimum voltage is maintained, and the timing margin detection device 300 enters the calibration mode. In the calibration mode, the calibration module 321 automatically adjusts the timing delay of the timing path 310 so that it is substantially equal to the clock period. After the calibration is completed, the timing margin of the timing path 310 is aligned with the timing margin of the circuit under test. For example, the timing margin of the timing path 310 and the timing margin of the circuit under test are substantially 0.

[0078] After completing the calibration process, the integrated circuit can be placed under a normal operating voltage (i.e., the operating voltage of the circuit under test). The normal operating voltage usually adds a certain margin on the basis of the minimum operating voltage to cope with the timing jitter that may occur under various working conditions. Therefore, the normal operating voltage will be higher than the minimum operating voltage, but it will usually be lower than the nominal voltage set during the chip design phase. When the voltage rises, the circuit under test will obtain a certain timing margin, and the timing path of the detection device will also obtain a certain timing margin, and the timing margin of the timing path can be used to characterize the timing margin of the actual circuit (i.e., the circuit under test). At this time, the timing margin detection device 300 enters the task mode, and the detection module 320 obtains the timing margin of the circuit under test by detecting the timing margin of the timing path 310.

[0079] Minimum voltage search can also be applied to mass production testing, allowing the relevant processes to be reused in mass production testing. Therefore, using minimum voltage search to explore the timing margin boundaries of the circuit under test can reduce the complexity of the chip design process.

[0080] Please refer to Figure 5 , which is an exemplary flow chart of a minimum voltage search process provided by an embodiment of the present application. Figure 5 As shown, the lowest voltage search process includes, for example:

[0081] S510: Setting initial operating parameters for the circuit under test, where the initial operating parameters include an initial operating voltage.

[0082] S520: Perform a test; if the test passes, execute step S530; otherwise, the test ends.

[0083] S530: Record the current operating voltage.

[0084] S540: Reduce the operating voltage of the circuit under test by one level.

[0085] Steps S520 to S540 are repeated until the lowest voltage is found. The lowest voltage is the last working voltage that passes the test and is recorded at the end of the test.

[0086] When setting the initial operating parameters, other parameters other than the operating voltage can also be set, such as the initial operating frequency. In the process of searching for the lowest voltage, other parameters such as the operating frequency remain unchanged, that is, the lowest voltage search process of S520-S540 mentioned above is performed when the operating frequency remains unchanged. During the test process, it can be achieved by running a test vector (pattern), and the test pattern is used to send a series of timing signals to the input end of the circuit under test, and compare the output timing at the output end of the circuit under test, so as to test whether the chip meets its function. The process of reducing the operating voltage can adopt a step-by-step reduction method, and the step size of the reduction can be the same or different; for example, the operating voltage changes by the same magnitude each time a gear is reduced, or the operating voltage changes by different magnitudes each time a gear is reduced. When the step size of the reduction is different, the step size of the reduction can be adjusted linearly or nonlinearly.

[0087] In some other embodiments of the present application, the timing path can be calibrated by aligning the maximum frequency (FMAX). The implementation method is similar to the minimum voltage alignment method; the timing margin boundary of the circuit under test is explored by the maximum frequency search (Fmax search), that is, the operating frequency corresponding to the timing margin being substantially 0 is searched; thereby obtaining the critical state where the timing margin of the integrated circuit is substantially 0. Similarly, during the search for the maximum frequency, other parameters such as the operating voltage remain unchanged. After the maximum frequency search is completed, the maximum frequency is maintained, and the timing margin detection device 300 enters the calibration mode; the calibration module 321 automatically adjusts the timing delay of the timing path 310 to align the timing margin of the timing path 310 with the timing margin of the circuit under test. After completing the calibration process, the integrated circuit can be placed at the normal operating frequency (that is, the operating frequency of the circuit under test), and the timing margin detection device 300 enters the task mode; the detection module 320 obtains the timing margin of the circuit under test by detecting the timing margin of the timing path 310.

[0088] In some other embodiments of the present application, a prediction method can be used to replace or optimize the minimum voltage search or the maximum frequency search. For example, a predicted voltage or predicted frequency is obtained by predicting the minimum voltage or maximum frequency prediction model, and the predicted voltage or predicted frequency is used in the calibration process of the timing margin detection device. For another example, the predicted voltage or predicted frequency is used in the minimum voltage search or the maximum frequency search process to reduce the search range. This implementation method can improve the efficiency of chip mass production testing. The prediction model can be constructed through an algorithm or obtained through big data training.

[0089] For example, there is a statistical correlation between the output of the sensing circuit and the minimum voltage (or maximum frequency). The empirical formula between the output of the sensing circuit and the minimum voltage (or maximum frequency) can be obtained through algorithms such as linear regression to predict the range of the minimum voltage (or maximum frequency), thereby reducing the time for searching the minimum voltage (or maximum frequency) in the mass production test. Assuming the nominal voltage is 0.75v, in the process of searching for the minimum voltage, the operating voltage is adjusted downward in steps of 10mv until the test fails. If the minimum voltage of the integrated circuit under test is relatively low, many rounds of testing will be required. By predicting the voltage, the output of the sensing circuit 640 can be used to predict the upper limit of the minimum voltage, assuming it is 0.70v. In this way, the search process from 0.75v to 0.70v can be skipped, thereby saving search time and improving the efficiency of chip mass production testing.

[0090] In the process of obtaining the predicted voltage or predicted frequency, the timing path 310 of the detection device 300 can be reused, the timing path 310 can be equivalent to a sensing circuit, and the output of the sensing circuit can be provided to the prediction model to obtain the predicted voltage or predicted frequency. The sensing circuit includes, for example, an oscillation ring, and the oscillation frequency of the oscillation ring is used as the output of the sensing circuit. The sensing circuit is similar to a process sensor to sense the process corner of the integrated circuit, for example, the oscillation frequency of the oscillation ring. In one implementation, during the training of the prediction model, data transmitted by a third-party process sensor can also be received to obtain more training data to train the prediction model, so that the data source is richer and the fitting effect of the prediction model is better.

[0091] Please refer to Figure 6 , which is an exemplary structural block diagram of another timing margin detection device provided in an embodiment of the present application. Different from the above detection devices, the detection device 600 also has a third working mode. In addition to the timing path 610 and the timing margin circuit 620, the detection device 600 also includes a gating module (or gating circuit) 630. The gating circuit 630 is used to select the timing path 610 as part of the sensing circuit 640 in the third working mode, and the output of the sensing circuit 640 is used to determine the lowest voltage or the highest frequency. For example, the output of the sensing circuit 640 is used to determine a predicted voltage or a predicted frequency, and the predicted voltage is used to determine the initial operating voltage in the lowest voltage search process, or the predicted frequency is used to determine the initial operating frequency in the highest frequency search process. The output of the sensing circuit 640 can be recorded by the calibration module 621, or recorded by the detection module 622, or recorded by an independent circuit, and this application does not impose any restrictions.

[0092] In an embodiment of the present application, the first operating mode (i.e., calibration mode) corresponds to the minimum voltage or maximum frequency of the circuit under test; the minimum voltage is the lowest voltage at a given frequency, and the maximum frequency is the highest frequency at a given voltage. The second operating mode (i.e., task mode) corresponds to the operating voltage or operating frequency of the circuit under test. In this way, in the first operating mode, the minimum voltage and the maximum frequency can be used to explore the timing margin boundary of the circuit under test, and the timing margin boundary state can be used to calibrate the timing path so that the timing delay of the timing path is aligned with the timing delay of the circuit under test. In the second operating mode, the operating voltage or operating frequency will have a certain margin to cope with the timing jitter that may occur under various working conditions. At this time, the timing margins of the circuit under test and the timing path will produce similar changes. At this time, the timing margin of the circuit under test can be obtained by observing the timing margin of the timing path.

[0093] The timing margin obtained by the detection device can be used for timing margin indication setting, so that the chip system can be notified of the status of the timing margin in a timely manner, so that the chip system can take timely measures to reduce timing risks or save power consumption.

[0094] For example, Figure 7 As shown, the detection module 322 is configured to generate a first signal when the detected timing margin is less than or equal to a first threshold; or generate a first signal when the detected timing margin is less than or equal to the first threshold a first preset number of times. This first signal, also known as an alarm signal, is configured to indicate a first timing margin state; the first timing margin state is a state where the timing margin is too small, indicating a possible timing violation risk. In this case, operating parameters can be dynamically changed to reduce the timing violation risk, such as dynamically increasing the operating voltage to reduce the timing violation risk.

[0095] For another example, the detection module 322 is configured to generate a second signal when the detected timing margin is greater than or equal to a second threshold value, or generate a second signal when the detected timing margin is greater than or equal to the second threshold value for a second preset number of times. This second signal can also be referred to as a prompt optimization signal, and is configured to indicate a second timing margin state. The second timing margin state is a state in which the timing margin is too high, resulting in wasted power consumption. Operating parameters can be dynamically changed to reduce timing margin waste and optimize power consumption, such as dynamically reducing the operating voltage to optimize power consumption.

[0096] Both the first and second thresholds can be used to determine the timing margin status and subsequently set a timing margin indication; or only one of them can be used to set an alarm or prompt an optimization setting. The first threshold is lower than the second threshold, and the first and second preset times can be the same or different.

[0097] The detection module can periodically collect statistics and detect timing margins to reduce power consumption. During a detection cycle, the detection module compares the obtained timing margin with a threshold (a first threshold and / or a second threshold) and, based on the comparison result, uses any of the above signal trigger mechanisms to indicate the timing margin status. After the detection cycle ends, the detection module can reset the detection status to zero to prepare for the next detection cycle.

[0098] In some embodiments of the present application, a sampling delay window can be set, and the sampling delay window can be a time range (or time period). The detection module 322 detects the timing margin of the timing path within the sampling delay window; compared with continuous detection, a relatively stable time range with less noise can be selected to detect the timing margin, thereby reducing the impact of random noise on margin detection. Furthermore, a smoothing (or moving average) method can be used to filter out misjudgments caused by occasional noise. For example, the sampling delay window is a sliding average window of N cycles, and the window slides forward one cycle in turn. Multiple detections are completed within the sliding average window of N cycles. When the detected timing margin is less than or equal to the first threshold for a first preset number of times, a first signal is generated; when the detected timing margin is greater than or equal to the second threshold for a second preset number of times, a second signal is generated. The present application is not limited to the number of cycles in the sliding average window. For example, N can be 4-8 (including boundary values).

[0099] In one implementation, detection module 322 includes a control circuit and a storage circuit. The storage circuit is configured to store the first threshold and / or the second threshold (collectively referred to as the timing margin warning threshold), or to store the first threshold and the first preset number of times, and / or the second threshold and the second preset number of times (collectively referred to as the timing margin violation detection threshold). The control circuit obtains the timing margin from the timing path and compares it with the first threshold. When the timing margin is less than or equal to the first threshold, a first signal is generated to issue an alarm. Alternatively, when the timing margin is less than or equal to the first threshold, a record may be made, and when the number of recorded times reaches the first preset number, a first signal is generated to issue an alarm. The control circuit obtains the timing margin from the timing path and compares it with the second threshold. When the timing margin is greater than or equal to the second threshold, a second signal is generated to indicate power consumption optimization. Alternatively, when the timing margin is greater than or equal to the second threshold, a record may be made, and when the number of recorded times reaches the second preset number, a second signal is generated to indicate power consumption optimization. The storage circuit may include, for example, one or more registers. The control circuit may include, for example, a comparator or other combinational logic to implement the above comparison function. The control circuit may also include a counter that increments when the timing margin is less than or equal to a first threshold or greater than or equal to a second threshold; and generates a first signal or a second signal when the counter counts to a first preset number of times or a second preset number of times. The detection results of timing margin being too large (greater than or equal to the second threshold) or too small (less than or equal to the first threshold) may share a single counter or use different counters.

[0100] In some embodiments of the present application, Figure 8 As shown, the detection device 800 further includes a signal generating circuit 851 and a signal receiving circuit 852. Driven by a clock signal, the signal generating circuit 851 generates a transmit signal s1. The transmit signal s1 reaches the signal receiving circuit 852 via the timing path 810, and the signal receiving circuit 852 obtains a receive signal s2. In a first operating mode (i.e., calibration mode), the calibration module 821 adjusts the timing delay of the timing path 810 by comparing the transmit signal s1 with the receive signal s2, thereby calibrating the timing path 810.

[0101] In some embodiments of the present application, Figure 8As shown, timing path 810 includes an adjustable delay circuit 811 and a sampling delay circuit 812. A timing margin circuit 820 includes a calibration module 821 and a detection module 822. Adjustable delay circuit 811 and calibration module 821 cooperate to calibrate the timing delay. Sampling delay circuit 812 is used to quantify the timing margin; detection module 822 is used to obtain the quantized value of the timing margin of sampling delay circuit 812, compare it with a predetermined first threshold and / or second threshold, and, based on the comparison result, use a trigger mechanism using any of the above signals to indicate the timing margin status.

[0102] In some embodiments of the present application, calibration module 821 determines the relationship between the delay time of timing path 810 and the clock cycle by comparing transmitted signal s1 and received signal s2, and uses the comparison result to calibrate timing path 810. For example, when the delay time is less than one clock cycle, transmitted signal s1 and received signal s2 are in opposite directions; when the delay time is greater than one clock cycle, transmitted signal s1 and received signal s2 are in the same direction. By detecting changes in the states of transmitted signal s1 and received signal s2, adjustable delay circuit 811 is adjusted to achieve timing path calibration.

[0103] In some embodiments of the present application, the calibration module 821 can adjust the adjustable delay circuit 811 through a state machine. The calibration module 821 may include a state register and a control circuit (for example, it can be implemented in the form of a combinational logic circuit), and the control circuit can perform state transition according to the state configured in the state register according to the control signal to achieve calibration of the timing path. Or the calibration module 821 can achieve calibration of the timing path through a processing circuit, for example, the calibration module 821 includes at least one processor, which implements calibration of the timing path by executing instructions. The control signal, for example, includes a transmitted signal s1 and a received signal s2; or, includes a signal obtained by performing a logical operation on the transmitted signal s1 and the received signal s2.

[0104] In one implementation, the adjustable delay circuit 811 includes a coarse adjustment part and a fine adjustment part. During the calibration process, the coarse adjustment part can be adjusted first, and then the fine adjustment part can be adjusted. For example, please refer to Figure 9 , which is an exemplary flow chart of a method for calibrating a timing path provided by an embodiment of the present application. Figure 9 As shown, the calibration process includes at least the following steps:

[0105] S910: Setting the delay of the fine adjustment part to 0;

[0106] S920: calibrating the coarse adjustment part;

[0107] S930: Perform calibration on the fine adjustment part.

[0108] During the calibration process, after the delay of the fine adjustment part is set to 0, the calibration of the coarse adjustment part is performed. When the calibration of the coarse adjustment part reaches the calibration target, the fine adjustment part is calibrated until the calibration target is reached. The calibration target can be obtained by detecting the changes in the states of the transmitted signal s1 and the received signal s2.

[0109] The above calibration process can be implemented using a binary method. For example, please refer to Figure 10 , which is an exemplary flow chart of another method for calibrating the timing path provided by an embodiment of the present application. First, set the initial value of the loop variable i, for example, i=0; and initialize the delay of the adjustable delay circuit, for example, set the initialization delay to half of the total delay of the adjustable delay circuit. The above initial value and initial delay values ​​are only examples, and can also be set to other values, such as i=1, for example, the initialization delay is 1 / 3 of the total delay of the adjustable delay circuit, or other proportions of the total delay of the adjustable delay circuit, or 0, or the total delay of the adjustable delay circuit. Set the adjustable delay circuit, at this time, set the delay of the adjustable delay circuit to the initialization delay. Test the delay of the adjustable delay circuit to determine whether the adjustable delay circuit has reached the maximum adjustment accuracy. When the maximum adjustment accuracy has not been reached, continue to adjust. At this time, the loop variable can be increased, for example, i=i+1. Before continuing to adjust, it can be determined whether the delay of the adjustable delay circuit is greater than one clock cycle; when it is not greater than one clock cycle, set a first incremental adjustment factor. The first incremental adjustment factor is, for example, When the value is greater than one clock cycle, a second incremental adjustment factor is set. For example, the second incremental adjustment factor is Then, the adjustable delay circuit is set according to the first incremental adjustment factor or the second incremental adjustment factor. Corresponding to the size of the first incremental adjustment factor or the second incremental adjustment factor, the coarse adjustment part or the fine adjustment part can be selected to set the adjustable delay circuit. Test the delay of the adjustable delay circuit to determine whether the adjustable delay circuit has reached the maximum adjustment accuracy. When the maximum adjustment accuracy has not been reached, the adjustment can be continued. At this time, the loop variable can be continued to increase. The above adjustment process is repeated until the maximum adjustment accuracy is reached. When the maximum adjustment accuracy is reached, it is determined whether the delay of the current adjustable delay circuit is greater than one clock cycle. When the delay is greater than one clock cycle, the last (i.e., the last) incremental adjustment factor Δi is discarded. The incremental adjustment factor Δi can be the first incremental adjustment factor or the second incremental adjustment factor. At this time, the result of the last adjustment is taken as the calibration result, and the calibration process is ended. When the delay time is not greater than one clock cycle, the result of the current adjustment is taken as the calibration result, and the calibration process is ended. This calibration process is only an example. In other implementations, other calibration methods may be selected. For example, the incremental adjustment factor may be set in other ways, such as linear or nonlinear change, or set to a fixed value.

[0110] In some embodiments of the present application, the adjustable delay circuit 811 includes an adjustable delay line. The adjustable delay line may include one or more logic devices such as a buffer, a flip-flop, or a register. Implementing the adjustable delay line through a buffer has the advantages of a simple circuit structure and being unaffected by clock signals. In one implementation, the adjustable delay line includes a coarse adjustment portion and a fine adjustment portion. The coarse adjustment portion has a delay adjustment level with a larger granularity, and the calibration module 821 can improve calibration efficiency by adjusting the coarse adjustment portion; the fine adjustment portion has a delay adjustment level with a smaller granularity, and the calibration module 821 can improve calibration accuracy by adjusting the fine adjustment portion. Through this setting, the calibration module 821 can achieve a balance between calibration efficiency and accuracy, and implement calibration faster and more accurately. In other implementations, more or fewer (for example, only one adjustment level) adjustment levels may be set.

[0111] When the adjustable delay line includes a coarse adjustment portion and a fine adjustment portion, the adjustable delay circuit 811 includes a first selector terminal and a second selector terminal. The first selector terminal is used to conduct a first path among a plurality of first delay paths; the second selector terminal is used to conduct a second path among a plurality of second delay paths. The delays of the plurality of first delay paths are greater than the delays of the plurality of second delay paths. The calibration module 821 is connected to the first selector terminal and the second selector terminal, respectively, to control the first selector terminal and the second selector terminal to select the path to be conducted.

[0112] The following is a description with reference to the accompanying drawings:

[0113] like Figure 11As shown, the adjustable delay circuit 811 includes a first multiplexer M1 and a second multiplexer M2. The first selection terminal and the second selection terminal are the selection terminal E1 of the first multiplexer M1 and the selection terminal E2 of the second multiplexer M2, respectively. The first multiplexer M1 includes multiple input terminals (to distinguish it from the input terminals of the second multiplexer, it can be called the first input terminal), a selection terminal E1 (to distinguish it from the selection terminal of the second multiplexer, it can be called the first selection terminal), and an output terminal O1 (to distinguish it from the output terminal of the second multiplexer, it can be called the first output terminal); each first input terminal is connected to a first delay path P1. The second multiplexer M2 includes multiple input terminals (to distinguish it from the input terminals of the first multiplexer, it can be called the second input terminal), a selection terminal E2 (to distinguish it from the selection terminal of the first multiplexer, it can be called the second selection terminal), and an output terminal O2 (to distinguish it from the output terminal of the first multiplexer, it can be called the second output terminal); each second input terminal is connected to a second delay path P2. The plurality of second delay paths P2 include a third path connected between the output terminal O1 of the first multiplexer M1 and the input terminal of the second multiplexer M2. The second multiplexer M2 can select to conduct the third path or other paths. The output terminal O2 of the second multiplexer M2 is connected to the sampling delay circuit 812.

[0114] In the above embodiments, the number of first delay paths and the number of buffers on the paths are for illustrative purposes only and are not intended to limit the present application. Similarly, the number of second delay paths and the number of buffers on the paths are for illustrative purposes only and are not intended to limit the present application. In addition, the number of first delay paths and the number of second delay paths may be the same or different, for example, the number of first delay paths may be equal to, greater than, or less than the number of second delay paths. In multiple first delay paths, the delay of each path may be the same or different, for example, the number of buffers in each first delay path may be the same or different; similarly, in multiple second delay paths, the delay of each path may be the same or different, for example, the number of buffers in each second delay path may be the same or different.

[0115] In some embodiments of the present application, the adjustment unit of the coarse adjustment part (i.e., the delay size of one adjustment) is set to be less than or equal to the total delay of the fine adjustment part, so that the minimum unit of the delay line adjustment remains as consistent as possible, reducing the problem of delay duration jumps that may occur during the adjustment process. The adjustment unit (or unit delay) of the coarse adjustment part can be achieved by setting the delay size of the first delay path, and the adjustment unit (or unit delay) of the fine adjustment part can be achieved by setting the delay size of the second delay path. The unit delay duration of the coarse adjustment part is set to be less than or equal to the maximum delay duration of the fine adjustment part, that is, the delay of the first delay path P1 is less than or equal to the total delay of the multiple second delay paths P2, so that in the process of continuously increasing or decreasing the delay length of the delay line, the problem of delay duration jumps can be prevented. When the delay sizes of the multiple first delay paths P1 are different, the delay of the first delay path P1 with the smallest delay is less than or equal to the total delay of the multiple second delay paths P2.

[0116] In one implementation, considering the balance between chip area and functionality, the delays of the first delay path and the second delay path can be set to a certain ratio, exemplarily 4:1, 8:1, or 16:1. This balances the chip area occupied by the delay circuit and its functionality, and thus the chip area occupied by the detection device and its functionality.

[0117] In some embodiments of the present application, the detection device 800 includes a sampling circuit, and the sampling circuit includes a sampling delay circuit 812 and a plurality of latches. The sampling delay circuit 812 includes a plurality of delay terminals connected to a plurality of registers to quantify the timing margin of the timing path 810. Figure 11 As shown, the sampling delay circuit 812 includes multiple delay terminals T1-Tn; the detection device 800 includes multiple latches L1-Ln, the data terminal D of the latch is connected to the corresponding delay terminal, the enable terminal E is coupled to the clock signal, and the output terminal Q is connected to the detection module 822. n is a positive integer greater than or equal to 2. The sampling delay circuit 812 is, for example, a delay line. Each delay unit in the delay line has a tap connected to the latch, and the latch is responsible for sampling. The number of latches can be determined according to the specific process of the chip, and the settings vary from chip to chip, and are not limited in the embodiments of the present application. The sampling window width is, for example, greater than or equal to 50ps.

[0118] In some embodiments of the present application, the signal generating circuit 851 is, for example, an inverting signal generating circuit that is coupled to a clock signal and outputs an inverted signal as the transmission signal s1 upon the clock trigger edge (rising edge or falling edge). This simplifies the implementation of the signal generating circuit, simplifies the circuit structure, and reduces design difficulty.

[0119] For example, Figure 11As shown, the signal generating circuit 851 includes a register 1 and an inverter F1. The clock signal terminal clk of the register 1 is coupled to the clock signal; the inverter F1 is connected between the input terminal D and the output terminal Q of the register. Accordingly, the signal receiving circuit 852 can be implemented using the register 2.

[0120] Similar to the description of the above embodiment, the timing path 810 can be reused as part of the sensing circuit to provide a sensing output for predicting the minimum voltage or maximum frequency (or the initial minimum voltage or maximum frequency). Figure 12 , which Figure 11 As an example of the detection device shown in FIG. 1 , in this implementation, Figure 11 The detection device shown in FIG. 1 further includes an inverter F2, a third multiplexer M3, and a fourth multiplexer M4. By configuring the paths in which the third multiplexer M3 and the fourth multiplexer M4 are conductive, the delay lines of the adjustable delay circuit 811 and the sampling delay circuit 812 form an oscillation loop. In this case, the gating module 630 includes the third multiplexer M3 and the fourth multiplexer M4. The sensing circuit 640 includes the inverter F2 and the timing path 810.

[0121] Optionally, the oscillation frequency of the oscillation ring within a given voltage and a given time window is recorded in the calibration module 821, and the recorded oscillation frequency is sent to an external prediction model to obtain a predicted voltage or frequency; the predicted voltage or frequency is used to determine the minimum voltage or maximum frequency; the determination method is similar to the above embodiment.

[0122] Described below Figure 8 The working process of the detection device shown:

[0123] First, take the lowest voltage alignment as an example, set the operating frequency and voltage of the integrated circuit (or chip) where the detection device and the circuit under test are located to the nominal value, for example 0.75V, 1.0GHz. Then follow Figure 5 The process shown in the figure performs the lowest voltage search. After the search is completed, the timing margin of the circuit under test is aligned to a state of almost 0. Figure 13 As shown in Figure 1, after searching for the lowest voltage, the timing margin of the worst timing path in the data path signal of the circuit under test has approached the minimum allowable value of the setup time. At this point, it can be considered that the timing margin is basically (or almost) zero.

[0124] Next, a zero-point calibration process is performed on the timing margin detection device. Specifically, calibration module 821 calibrates timing path 810 in a first operating mode (calibration mode). Calibration module 821 receives transmit signal s1 from register 1 and receive signal s2 from register 2. Calibration module 821 calibrates timing path 810 by adjusting an adjustable delay line.

[0125] The calibration module 821 determines whether the delay time of the adjustable delay line exceeds one clock cycle based on the transmission signal s1 of register 1 and the reception signal s2 of register 2. If the delay time is less than one clock cycle, the inverted signal transmitted by register 1 at the current clock rising edge can be correctly received by register 2 at the next clock rising edge. Therefore, the output (Q-end) signals of register 1 and register 2 should be reversed, that is, the transmission signal XOR the reception signal = 1, where XOR represents the "exclusive OR" operation. If the delay time of the delay line exceeds one clock cycle, the inverted signal transmitted by register 1 at the current clock rising edge cannot be received by register 2 at the next clock rising edge. Therefore, the Q-end signals of register 1 and register 2 will become the same direction, that is, the transmission signal XOR the reception signal = 0.

[0126] The calibration module 821 can determine whether the length of the adjustable delay line exceeds one clock cycle based on the above principle, and then control the adjustable delay line. Similar to the above description, in one implementation, a binary method can be used to control the adjustable delay line. First, the coarse adjustment part is calibrated. After the coarse adjustment calibration is completed, the fine adjustment part is calibrated to calibrate the delay length of the adjustable delay line to be basically consistent with the clock cycle, but less than the clock cycle, such as Figure 13 The “calibrated delay line signal” shown in .

[0127] After calibration, the timing margin of the timing path of the detection device and the timing margin of the circuit under test are aligned to a state of almost zero.

[0128] After the detection module 822 completes the calibration, it puts the detection device and the integrated circuit (or chip) where the circuit under test is located back to the operating voltage (i.e., the voltage when the chip is working normally). The operating voltage is higher than the minimum voltage. Therefore, the delays of the data path of the circuit under test and the timing path of the detection device will expand and contract due to the voltage increase. Since both have been aligned to a timing margin of basically 0 before expansion and contraction, the timing margin of the timing path of the detection device can reflect the timing margin of the circuit under test after expansion and contraction. Since the lowest voltage search process of the circuit under test actually reflects the worst path among the tens of millions of timing paths in the entire circuit under test, the adjustable delay line after calibration is equivalent to being aligned with the worst path in the circuit module under test. Therefore, it can reflect the timing margin of the worst timing path in the circuit under test, such as Figure 14 shown.

[0129] Furthermore, the absolute value of the timing margin of the stretched timing path does not need to be completely consistent with the absolute value of the timing margin of the circuit under test. This is because the timing margin is converted into a digital value by the sampling circuit, and this digital value is measured in units of buffer delays. Therefore, as long as the relative timing margin information in units of buffers is obtained, it is sufficient to achieve the functional requirements of timing margin detection and timing margin status indication.

[0130] The timing margin detection device provided in the above embodiments of the present application can achieve decoupling of timing margin measurement from the circuit under test, so that the timing margin measurement no longer depends on the selection of key timing paths, reducing the complexity of finding key timing paths during chip design. In the detection of timing margin, it can operate independently and no longer draws observation signals from the circuit under test, thereby reducing the impact on the circuit under test and the occurrence of repeated iterations.

[0131] An integrated circuit with this detection device can realize individualized timing margin measurement of the chip and reduce the waste of timing margin; thereby, the operating voltage of the chip can be dynamically set according to the actual manufacturing and working conditions of the chip to achieve power consumption optimization.

[0132] Accordingly, the embodiment of the present application also provides a timing margin detection method for detecting the timing margin of an integrated circuit. The integrated circuit includes a circuit under test and a timing margin detection device, and the detection device includes a timing path independent of the circuit under test. Please refer to Figure 15 , the detection method at least includes:

[0133] S151: Setting the operating parameters of the integrated circuit to the operating state;

[0134] S152: Monitor the timing margin of the timing path of the detection device in the working state, where the timing margin of the timing path is used to characterize the timing margin of the circuit under test.

[0135] This method decouples timing margin measurement from the circuit under test, making it independent of the selection of critical timing paths and reducing the complexity of finding critical timing paths during chip design. Timing margin testing can be performed independently, eliminating the need to draw observation signals from the circuit under test. This reduces the impact on the circuit under test and reduces the need for repeated iterations.

[0136] Please continue to refer to Figure 16 In some embodiments of the present application, the above detection method further includes a timing path calibration process, which includes the following steps:

[0137] S161: Setting the operating parameters of the integrated circuit to a critical state of the timing margin;

[0138] S162: Adjusting the timing delay of the timing path so that the timing delay of the timing path is aligned with the timing delay of the circuit under test;

[0139] The above step S151 includes: after the timing delay of the timing path is aligned with the timing delay of the circuit under test, setting the operating parameters of the integrated circuit to an operating state.

[0140] In this way, before monitoring the timing margin of the circuit under test, the timing margin of the timing path can be calibrated to align the timing margin of the timing path with the timing margin of the circuit under test, so that the timing margin detection scheme can be flexibly applied to different chips, realizing individualized timing margin measurement of the chip, and obtaining more accurate detection results that better reflect the actual timing margin situation of the chip.

[0141] Please continue to refer to Figure 15 In some embodiments of the present application, a timing margin status indication may also be set, and the detected timing margin may be used to indicate the timing margin status, thereby promptly notifying the chip system of the timing margin status, so that the chip system can take timely measures to reduce timing risks or save power consumption. In this case, the above detection method may also include:

[0142] S153: Generate a first signal or a second signal according to the timing margin of the timing path.

[0143] The first signal is generated and used to indicate a first timing margin state when the timing margin is less than or equal to a first threshold, or when the timing margin is less than or equal to the first threshold for a first preset number of times; the second signal is generated and used to indicate a second timing margin state when the timing margin is greater than or equal to a second threshold, or when the timing margin is greater than or equal to the second threshold for a second preset number of times.

[0144] The operating parameters of the integrated circuit include, for example, voltage or frequency. The critical state of the timing margin corresponds to the substantially zero state of the timing margin described in the above embodiments. Setting the operating parameters of the integrated circuit to the critical state of the timing margin includes: setting the voltage of the integrated circuit to a minimum voltage, which corresponds to the critical state of the timing margin; or setting the frequency of the integrated circuit to a maximum frequency, which corresponds to the critical state of the timing margin.

[0145] The acquisition of the minimum voltage and maximum frequency is the same as the above minimum voltage and maximum frequency search process, which will not be repeated here. The process of adopting and acquiring the timing margin and adjusting the timing delay of the timing path in the embodiment of the present application is the same as the above embodiment, which will not be repeated here.

[0146] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A timing margin detection device, characterized in that: Includes timing paths and timing margin circuitry independent of the circuit under test, where: The timing path is configured to receive the same clock signal as the circuit under test; The timing margin circuit obtains the timing margin of the circuit under test by detecting the timing path.

2. The detection device according to claim 1, characterized in that The timing margin circuit includes: a calibration module, configured to calibrate the timing path in a first operating mode so that a timing delay of the timing path is aligned with a timing delay of the circuit under test; The detection module is used to detect the timing margin of the timing path in the second working mode, where the timing margin is used to characterize the timing margin of the circuit under test.

3. The detection device according to claim 2, characterized in that The first operating mode corresponds to the lowest voltage or the highest frequency of the circuit under test; The second operating mode corresponds to the operating voltage or operating frequency of the circuit under test.

4. The detection device according to claim 3, characterized in that Also includes: The gating circuit is used to select the timing path as a part of the sensing circuit in a third working mode, and the output of the sensing circuit is used to determine the lowest voltage or the highest frequency.

5. The detection device according to claim 4, characterized in that The sensing circuit includes an oscillating ring.

6. The detection device according to any one of claims 2 to 5, characterized in that: The detection module is also used for: When detecting that the timing margin is less than or equal to a first threshold, generating a first signal, wherein the first signal is used to indicate a first timing margin state; or When it is detected that the timing margin is less than or equal to the first threshold value for a first preset number of times, a first signal is generated, where the first signal is used to indicate a first timing margin state.

7. The detection device according to any one of claims 2 to 6, characterized in that: The detection module is also used for: When detecting that the timing margin is greater than or equal to a second threshold, generating a second signal, wherein the second signal is used to indicate a second timing margin state; or When it is detected that the timing margin is greater than or equal to the second threshold value for a second preset number of times, a second signal is generated, where the second signal is used to indicate a second timing margin state.

8. The detection device according to any one of claims 2 to 7, characterized in that: The detection module is used to detect the timing margin of the timing path within a sampling delay window.

9. The detection device according to any one of claims 2 to 8, characterized in that: The detection device further includes a signal generating circuit and a signal receiving circuit, wherein the signal generating circuit generates a transmission signal under the drive of the clock signal, the transmission signal reaches the signal receiving circuit via the timing path, and the signal receiving circuit obtains a reception signal; The calibration module calibrates the timing path in the first operating mode, wherein the calibrating the timing path includes adjusting a timing delay of the timing path by comparing the transmit signal and the receive signal.

10. The detection device according to claim 9, characterized in that: The timing path includes an adjustable delay circuit and a sampling delay circuit.

11. The detection device according to claim 10, characterized in that: The adjustable delay circuit comprises: A first selection terminal, configured to conduct a first path among a plurality of first delay paths; A second selection terminal, used for conducting a second path among the plurality of second delay paths; The delay of the first delay path is greater than the delay of the second delay path; The calibration module is connected to the first selection end and the second selection end respectively, and controls the first selection end and the second selection end to select a conductive path.

12. The detection device according to claim 11, characterized in that: The delay of the first delay path is less than or equal to the total delay of the plurality of second delay paths.

13. The detection device according to any one of claims 1 to 12, characterized in that: The timing path represents the timing margin of the circuit under test using buffers as units.

14. An integrated circuit, characterized in that: include: The circuit under test works under the drive of the clock signal; The detection device according to any one of claims 1 to 13, configured to detect a timing margin of the circuit under test.

15. A method for detecting a timing margin, characterized in that: A method for detecting a timing margin of an integrated circuit, wherein the integrated circuit includes a circuit under test and a timing margin detection device, wherein the detection device includes a timing path independent of the circuit under test, and wherein the detection method includes: Setting the operating parameters of the integrated circuit to an operating state; In the working state, a timing margin of a timing path of the detection device is obtained, and the timing margin of the timing path is used to characterize the timing margin of the circuit under test.

16. The detection method according to claim 15, characterized in that: Also includes: Setting the operating parameters of the integrated circuit to a critical state of the timing margin; Adjusting the timing delay of the timing path so that the timing delay of the timing path is aligned with the timing delay of the circuit under test; Setting the operating parameters of the integrated circuit to an operating state includes: After the timing delay of the timing path is aligned with the timing delay of the circuit under test, the operating parameters of the integrated circuit are set to an operating state.

17. The detection method according to claim 15 or 16, characterized in that: Also includes: A first signal or a second signal is generated according to the timing margin of the timing path, wherein: The first signal is generated when the timing margin is less than or equal to a first threshold or when the timing margin is less than or equal to the first threshold for a first preset number of times, and is used to indicate a first timing margin state; The second signal is generated when the timing margin is greater than or equal to a second threshold or when the timing margin is greater than or equal to the second threshold for a second preset number of times, and is used to indicate a second timing margin state.

18. The detection method according to any one of claims 15 to 17, characterized in that: The operating parameter includes voltage or frequency, and setting the operating parameter of the integrated circuit to a critical state of the timing margin includes: Setting the voltage of the integrated circuit to a minimum voltage, the minimum voltage corresponding to a critical state of the timing margin; or, The frequency of the integrated circuit is set to a maximum frequency, where the maximum frequency corresponds to a critical state of the timing margin.

19. A controller, characterized in that: comprising the integrated circuit of claim 14.

20. A vehicle, characterized in that: Comprising a controller as claimed in claim 19.

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