Methods, systems, and devices to improve simulation of gate-level netlists

Abstract

The disclosure relates to methods, systems, and devices to improve simulation of gate-level netlists. An example apparatus includes interface circuitry (202) to obtain a register transfer level code (114) indicating operation of an integrated circuit; a machine readable instruction; and programmable circuitry to at least one of instantiate machine-readable instructions or execute machine-readable instructions to obtain a gate-level netlist (101) corresponding to the integrated circuit, the gate-level netlist (101) containing modules (302, 304, 306, 308, 310, 312) in the integrated circuit and connections between the modules (302, 304, 306, 308, 310, 312); obtaining a first probe (314a, 318a), the first probe (314a, 318a) representing a first position within the gate-level netlist (101) to monitor the behavior; identifying a root module (306), the root module comprising an output configured to determine the signal at the first location; and generating a second probe (314b, 318b) to replace the first probe (314a, 318a), the second probe representing a second position within the gate-level netlist (101) closer to the output of the root module (306) than the first probe (314a, 318a).

Description

Technical Field

[0001] The present disclosure relates generally to design and verification of integrated circuits, and more particularly to methods, systems, and apparatus to improve simulation of gate-level netlists of integrated circuit devices. Background Art

[0002] An integrated circuit is an assembly of circuits on a typically small block of semiconductor material. Integrated circuits are important because they facilitate the miniaturization of electronic devices such as computers, tablet computers, and cell phones. For example, integrated circuits allow thousands to billions of electronic components to be integrated on a single small chip, making electronic devices portable and convenient. Consumers have become dependent on the performance, efficiency, and convenience of electronic devices. Consequently, the demand for smaller, faster, and better integrated circuits has increased. Therefore, designing and building efficient and reliable integrated circuits has become crucial. Summary of the Invention

[0003] In one aspect, the present disclosure provides an apparatus comprising: an interface circuit system configured to obtain register-transfer level code indicative of operation of an integrated circuit; machine-readable instructions; and programmable circuit system configured to at least one of instantiate the machine-readable instructions or execute the machine-readable instructions to perform the following operations: obtain a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules and connections between modules in the integrated circuit; obtain a first probe, the first probe representing a first location within the gate-level netlist for monitoring behavior; identify a root module, the root module including an output configured to determine a signal at the first location; and generate a second probe to replace the first probe, the second probe representing a second location within the gate-level netlist that is closer to the output of the root module than the first probe.

[0004] In another aspect, the present disclosure provides a method comprising: obtaining register transfer level code indicative of operation of an integrated circuit; obtaining a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules and connections between modules in the integrated circuit; obtaining a first probe, the first probe representing a first location within the gate-level netlist for monitoring behavior; identifying a root module, the root module including an output configured to determine a signal at the first location; and generating a second probe to replace the first probe, the second probe representing a second location within the gate-level netlist that is closer to the output of the root module than the first probe.

[0005] In another aspect, the present disclosure provides a non-transitory machine-readable storage medium including instructions for causing a programmable circuit system to perform at least the following operations: obtain register-transfer level code indicating operation of an integrated circuit; obtain a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules in the integrated circuit and connections between the modules; obtain a first probe, the first probe representing a first location within the gate-level netlist for monitoring behavior; identify a root module, the root module including an output configured to determine a signal at the first location; and generate a second probe to replace the first probe, the second probe representing a second location within the gate-level netlist that is closer to the output of the root module than the first probe. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an example simulation environment in which an example synthesis circuit system operates to simulate and verify a gate-level netlist.

[0007] Figure 2 for Figure 1 A block diagram of an example implementation of a probe selection controller is shown.

[0008] Figure 3 An example simulated gate-level netlist that is part of a system on a chip (SoC).

[0009] Figures 4 to 5 To represent that can be implemented, instantiated and / or executed by an example programmable circuit system to implement Figure 2 Example machine-readable instructions and / or a flow chart of example operations of the probe selection controller 126 are provided.

[0010] Figure 6 is a block diagram of an example processing platform including a processor structured to implement, instantiate, and / or execute example machine-readable instructions and / or execute Figures 4 to 5 Instance operations to implement Figure 2 The programmable circuitry of the probe selection controller 126.

[0011] Figure 7 for Figure 6 A block diagram of an example implementation of a programmable circuit system.

[0012] Figure 8 for Figure 6 A block diagram of another example implementation of a programmable circuit system.

[0013] Generally, the same reference numbers will be used throughout the drawings and accompanying written description to refer to the same or like parts.The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0014] Designing integrated circuits (ICs) is a meticulous process. Synthesis tools provide design engineers with a way to simplify IC design. Synthesis is the process of converting register transfer level (RTL) code into a gate-level netlist (GLN). RTL code is code that captures the desired behavior of the circuit design. RTL code is written in a hardware description language (e.g., Verilog, VHDL, etc.) and serves as one of the inputs to the synthesis tool. The second input to the synthesis tool is the technology library. The technology library is a collection of standard cells, gates, and other components specific to the target technology (e.g., the target circuit system to be implemented in the IC). The third input to the synthesis tool is the constraint file. The constraint file guides the synthesis tool, providing additional information and specifications for optimizing the generation of the GLN. In some instances, the constraint file contains the timing constraints, power targets, and area requirements of the IC.

[0015] A gate-level netlist (GLN) is the output of a synthesis tool. It is a netlist view of an IC, containing a complete list of gate connections with complete functionality and timing behavior. A gate-level netlist is a list of the electronic components (e.g., modules) in a circuit and the nodes connected to those components. In some instances, a netlist is a textual catalog of electronic components and their connections.

[0016] During synthesis, the synthesis tool performs an elaboration process after obtaining the input. The elaboration process reads the RTL code and converts the RTL code into modules based on the logical hierarchy of the module. A module represents a design unit that implements certain behavioral characteristics of the IC design. For example, any parameters, logical conditions, etc. contained in the RTL are inferred when the module is created. In some instances, a module represents a circuit component (e.g., a logic gate, a comparator, etc.), an entire circuit (e.g., an analog-to-digital converter, a transmitter, a receiver, etc.), and / or an entire IC. For example, a top-level module describes the entire IC, a sub-module describes the circuit included in the IC design, and a bottom-level module describes the circuit components within the circuit on the IC. Each module is described in a hardware description language (HDL). The naming convention of the module makes it identifiable in a large RTL file. For example, a hierarchical naming convention can be used, where a portion of the HDL (e.g., register W) belongs to a subset of the HDL (called, for example, C) that is part of a higher-level function (e.g., B), which in turn belongs to a larger context portion of the HDL that executes the higher-level function A, which in turn belongs to an even larger context portion of an even higher-level function (e.g., bus controller BC). Thus, the identifier for register W might be "BC.ABCRegisterW." Other naming conventions can also be used, but the hierarchical approach provides clarity and simplicity.

[0017] After the RTL is converted into modules, the synthesis tool maps the modules and corresponding logic to cells in the technology library. For example, it maps gates to actual technology-related logic gates accessible in the technology library.

[0018] After refinement, the synthesis tool optimizes the RTL logic and design based on the constraints specified in the constraint file. For example, during synthesis, the synthesis tool may optimize the IC design based on the constraints. In some instances, this includes reducing the number of logic gates, reducing the target IC area, optimizing power, and so on. While these optimizations are beneficial, they can also cause changes in the synthesis output (e.g., changes from RTL code to GLN). For example, wire logic may change, signals may have reversed polarity, signals may be merged, or signals may be disconnected. These optimization changes are reflected in the GLN.

[0019] The GLN undergoes simulation in the development environment. For example, the development environment simulates the GLN (and RTL) to determine and analyze the behavior of the target IC. As used herein, gate-level simulation (GLS) is the simulation of the gate-level netlist (GLN). When running gate-level simulation (GLS) in the development (DV) environment, changes in the logic and design of the RTL code 114, as well as changes that occur each time synthesis is rerun due to optimizations during the synthesis process, can cause changes to the GLN under test. In some instances, these changes can cause problems when testing and analyzing the GLN. For example, a DV environment may lack integrity (e.g., uniformity, cohesion, etc.) over time due to wire connections (e.g., interconnects, nets, wires) being disconnected during optimization, wires being merged, wires having different polarity, etc. Consequently, a subsequent DV environment may not be able to accurately sample (e.g., probe, test, analyze, etc.) the same wires as a previous iteration of the DV environment because those wire names may represent different functionality.

[0020] In some instances, the DV environment generates initial probe points during RTL code simulation to monitor and / or analyze the actual (e.g., logical) behavior of the RTL code at specified locations (e.g., the behavior of a module's output or input). Probes are logical markers placed in the hardware description language (HDL) indicating where something of interest is occurring and a value is to be measured at a specific time. For example, the DV environment creates HDL statements (e.g., logic markers, probes) and / or GLN probe points and uses them when simulating the RTL code and / or GLN. In some instances, probes have a hierarchical naming convention to facilitate identification of probes in the HDL and / or to distinguish probes from modules. The actual behavior observed at the probe points can be compared to the expected behavior of the IC, as dictated by the RTL. Initial probe points are also used to monitor and / or analyze the actual (e.g., physical) behavior of the GLN. This monitoring enables engineers to determine whether the GLS is operating as expected. Traditionally, engineers must manually debug GLS failures by manually identifying inverted and / or disconnected signals (and / or associated wires) and then changing the corresponding probe point (e.g., test point) locations and / or expected behavior in the code. Manually searching for signals and changing probe points can take considerable time. Additionally, manually searching for signals and changing probe points may cause engineers to spend time analyzing real problems in a DV environment.

[0021] Therefore, many examples disclosed herein reduce or eliminate the manual debugging process of probe points by automatically identifying alternative locations for probe points in a GLS and converting the expected results at the original probe point to the expected results at the alternative location. For example, examples disclosed herein use RTL code and GLN to modify probe points in a DV environment. In the examples disclosed herein, probe points are changed to locations that are less likely to be affected by optimization changes and are more consistent across design iterations. As a result, the examples disclosed herein significantly reduce the amount of time spent debugging a GLS and producing a target IC.

[0022] Figure 1 is a block diagram of an example development environment 100, in which example synthesis circuitry 102 operates to simulate and verify a gate-level netlist (GLN) 101, example GLN simulation circuitry 110 operates to simulate GLN 101, and example debug circuitry 112 operates to generate a final layout 104. Example development environment 100 includes example RTL simulation circuitry 106, example synthesis circuitry 102, example probe data storage 108, example GLN simulation circuitry 110, example debug circuitry 112, and example probe selection controller 126.

[0023] exist Figure 11 , example RTL simulation circuitry 106 obtains input for simulating and verifying RTL code 114. For example, RTL simulation circuitry 106 obtains RTL code 114, one or more constraints 116, and one or more libraries 118. Example RTL simulation circuitry 106 is executed in example development environment 100. Example RTL simulation circuitry 106 simulates RTL code 114 to check and verify the logical operations of the circuit design.

[0024] For example, RTL code 114 is code that captures the desired or expected behavior (e.g., operation) of a circuit design, is written in a hardware description language, and is synthesizable into a technology-specific gate-level netlist (e.g., GLN 101). As used herein, the expected behavior and / or expected operation of an IC is the operation of the IC created from the RTL code 114 and the final layout 104. The example RTL simulation circuitry 106 executes and / or runs the RTL code 114 in the development environment 100 to enable modification and / or verification of the logic parameters of the RTL code 114. In some examples, the development environment 100 enables such modification and / or verification by generating and inserting initial probes in the RTL code 114. The initial probes provide the development engineer with a deep understanding of how the logic parameters of the RTL code 114 are working. Figure 1 In the example development environment 100 , the initial probe is stored in the example probe data storage area 108 .

[0025] One or more instance constraints 116 are one or more requirements that the development environment 100 must ensure the final layout 104 meets and / or represents, including timing constraints, power constraints, area constraints, configuration constraints, etc. One or more instance libraries 118 are one or more technology libraries that contain standard cells, gates, and other components specific to the target technology. One or more instance libraries 118 are used to synthesize RTL code 114 and generate GLN 101 by mapping the abstract and / or conceptual design of the IC to the actual technology (e.g., circuit components) in which such conceptual design will be implemented.

[0026] like Figure 1 As described in , RTL simulation circuitry 106 modifies RTL code 114 until RTL code 114 operates as expected and is therefore verified. In some examples, RTL simulation circuitry 106 obtains input (e.g., RTL code 114, one or more constraints 116, and one or more libraries 118) from a development engineer, such as an integrated circuit (IC) design engineer who develops and designs the IC. In some examples, the engineer imports and / or uploads the input to development environment 100.

[0027] exist Figure 1In the example embodiment, example synthesis circuitry 102 is a synthesis tool used to synthesize RTL code 114 and generate GLN 101. Example synthesis circuitry 102 includes an example conversion controller 120, an example mapping controller 122, and an example optimization controller 124. Example synthesis circuitry 102 can be instantiated (e.g., an instance is created, exists for any length of time, is realized, implemented, etc.) by programmable circuitry, such as a central processing unit (CPU), that executes a first instruction.

[0028] exist Figure 1 In the example, the conversion controller 120 obtains RTL code 114 verified by the example RTL simulation circuitry 106 and converts the RTL code 114 into modules according to the module's logic hierarchy. For example, the conversion controller 120 converts code and arithmetic operators (e.g., addition, subtraction, division, multiplication, etc.) into modules corresponding to basic logic gates, flip-flops, counters, switches, etc. In some examples, the conversion controller 120 converts the RTL file into modules by analyzing the design hierarchy and then executing initial commands in the RTL 114. The example conversion controller 120 detects asynchronous resets (e.g., signals used to initialize an IC and force it into a known state for simulation). The example conversion controller 120 converts one or more decision trees into one or more multiplexer modules. The example conversion controller 120 converts synchronous code into level-triggered device modules, flip-flop modules, etc. The example conversion controller 120 detects finite state machine (FSM) logic, extracts multiple input / output bits and status bits, and then converts the FSM logic into basic logic (e.g., Boolean logic). The example conversion controller 120 generates memory cells and maps the memory cells to basic logic (e.g., Boolean logic). In some examples, the conversion controller 120 adds additional components and / or features to the module using one or more constraints 116. For example, the conversion controller 120 adds power domains, level shifters, power switches, retention flip-flops, and / or any other components / features that a design engineer requires for a target (e.g., hypothetical) IC.

[0029] When the RTL code 114 and the one or more constraints 116 have been converted, the instance conversion controller 120 notifies the instance mapping controller 122. For example, the conversion controller 120 triggers the mapping controller 122 to map the modules and corresponding logic to the one or more technology libraries 118.

[0030] exist Figure 1, the instance mapping controller 122 maps the module to the one or more technology libraries 118. For example, when the RTL code 114 and the one or more constraints 116 have been converted into a module (e.g., a logical Boolean representation), the mapping controller 122 maps the module and the corresponding logic to technology-related cells from the one or more libraries 118. In some examples, the cell mapping depends on the one or more constraints 116. Therefore, when mapping the module to the one or more libraries 118, the instance mapping controller 122 considers the one or more constraints 116.

[0031] exist Figure 1 In some examples, the optimization controller 124 optimizes the logic and design of the converted RTL code 114. In some examples, optimizing the logic of the converted RTL code 114 includes, but is not limited to, detecting and removing identical cells, performing constant folding (e.g., removing expressions that compute values ​​that may be determined before the code is executed), merging multiplexers, reducing inputs, removing flip-flops with constant values, reducing the word length of cells, and removing unused cells and wires. In some examples, optimizing the design of the converted RTL code 114 includes, but is not limited to, optimizing power, optimizing area, and reducing the amount of worst negative slack (e.g., reducing the amount of timing missed by a critical path throughout the IC design) and total negative slack (e.g., the sum of the number of paths that miss timing across all paths throughout the IC design).

[0032] In some examples, optimization controller 124 outputs GLN 101 after optimization is complete. For example, optimization controller 124 may perform optimization of converted RTL code 114, compile optimized RTL code 114, and generate GLN 101. GLN 101 specifies a set of gates and / or other circuit devices found in library 118 and a set of interconnects (nets) between the circuit devices in order to implement the behavior defined in RTL 114 and satisfy constraints 116. GLN 101 may also specify properties of the gates and circuit devices, such as device sizing, type, placement, etc. As used herein, gates and circuit devices are referred to as modules.

[0033] exist Figure 1In the example GLN simulation circuitry 110, the example GLN simulation circuitry 110 uses RTL code 114, one or more constraints 116, one or more libraries 118, and a set of probe points to simulate the GLN 101 to create the GLS. The example GLN simulation circuitry 110 operates within the development environment 100 to simulate the GLN 101. Simulating the GLN 101 refers to modeling a physical IC on a computer to study how the physical IC will operate under real-world scenarios. To analyze and / or study how the physical IC will operate, the example GLN simulation circuitry 110 monitors the probe points in the GLS by reporting their behavior under various operating conditions. The probe points provide a way for development or test engineers to see how the GLS actually operates. For example, the GLN simulation circuitry 110 can record and monitor the values ​​of signals (e.g., logic 1s, logic 0s, voltage, current, resistance, power, temperature, etc.) at the inputs and outputs of gates or other circuit devices in the GLN 101 and display these values ​​on a user interface. In some examples, GLN simulation circuitry 110 compares simulated operation of GLN 101 (eg, as indicated by a probe) to expected operation of the IC (eg, as indicated by RTL code 114 , user-provided specifications, or other golden models).

[0034] GLN simulation circuitry 110 monitors probe points in GLN 101. For example, GLN simulation circuitry 110 may use and / or select initial probes stored in probe data storage 108. However, in some instances, the initial placement of the initial probes may be incorrect and / or suboptimal due to optimization variations. For example, while the initial probes are stable for monitoring RTL code 114, they may be unstable for monitoring GLN 101 due to optimization variations in wire connections between modules. For example, changes in device placement between synthesis iterations may result in different buffering along long wires. As another example, changes in logic gates in a synthesized block between synthesis iterations may result in different values ​​or polarities being driven along a particular wire. Therefore, the instance probe selection controller 126 may modify the placement of the initial or automatic probes to alternative locations. The probe selection controller 126 may also convert the expected operation at the initial placement to the expected operation at the alternative location. For example, if the initial probe point is at the output of an inverter that may or may not be present in a given iteration of the GLN 101 depending on downstream logic, the probe selection controller 126 may select an alternate location for the probe point before the inverter and, therefore, invert the intended operation for determining whether the signal at the alternate location meets the intended operation.

[0035] Thanks to the probe selection controller 126, development engineers or test engineers do not need to identify the optimal probe point in the GLS. Instead, the GLN simulation circuitry 110 can position the probe point at the location selected by the probe selection controller 126, and the engineer can monitor the probe. Thus, engineers can use their time to debug the GLS instead of selecting better or new probe points.

[0036] exist Figure 1 In the example, probe selection controller 126 determines alternative locations for probe points in GLN 101. Probes are assigned to the outputs and / or inputs of the simulated GLN (GLS) to test and monitor whether the GLS is operating as expected. For example, if RTL code 114 specifies that a particular output should be equal to 1 when A=B, then the probe should read as equal to 1 when A=B, and as 0 when A≠B. Due to variations in GLN 101 during optimization, signals A and B, and even outputs, may be inverted or may not exist in a given version of GLN 101. Therefore, the example probe selection controller 126 can identify and select initial probe points that may not exist and modify their locations to locations or points that are more likely to exist and locations with a lower probability of inverted polarity or floating positions (floating paths). A probe is placed on a wire connection (e.g., a net, interconnect, wire, conductor, signal path, input, output, etc.), and thus, the instance probe selection controller 126 identifies a location or point on the wire connection where there is a low probability that the location or point will float or have reversed polarity.

[0037] In some examples, the probe selection controller 126 modifies the location of the probe based on parsing and analyzing the RTL 114 code to find the root of each wire connection. The root can be a module with a root output, where the root output is driven internally from fixed (e.g., hard-coded) logic or registers. For example, the root output provides the first output in a series of two or more outputs. In some examples, the root module is a splitter, and the non-root module is an inverter located outside the output of the splitter. Therefore, the splitter provides a root output of a wire connection, and the wire connection includes the output of the splitter and the output of the inverter. Figure 2 The example probe selection controller 126 is described in further detail.

[0038] exist Figure 1In the example probe data storage 108, the example probe data storage 108 stores initial probes from the development environment 100 and alternative probe points from the probe selection controller 126. The example probe data storage 108 can be accessed by the example GLN simulation circuitry 110 to obtain alternative probe points. The example probe data storage 108 can be implemented by volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), etc.) and / or non-volatile memory (e.g., flash memory). The example probe data storage 108 can also or alternatively be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDDR), etc. The example probe data storage 108 can also or alternatively be implemented by one or more mass storage devices, such as one or more hard disk drives, one or more compact disk (CD) drives, one or more digital versatile disk (DVD) drives, one or more solid-state disk drives, etc. Although in the illustrated example, the probe data store 108 is illustrated as a single data store, the probe data store 108 may be implemented by any number and / or type of data stores. Furthermore, the data stored in the example probe data store 108 may be in any data format, such as, for example, binary data, comma-delimited data, tab-delimited data, Structured Query Language (SQL) structures, etc.

[0039] exist Figure 1 In some examples, the debug circuit system 112 compares the behavior measured at the probe points in the GLN 101 with the expected behavior based on the RTL 114 to debug the GLS and make any necessary corrections to the GLN 101. For example, the debug circuit system 112 scans the GLS to assist engineers in identifying problems in the design and the device. In some examples, the debug circuit system 112 scans the GLS to find timing delays, faulty devices, etc. In some examples, the debug circuit system 112 generates a report of the identified problems. In some examples, the debug circuit system 112 notifies the engineer of the identified problems via a user interface. In some examples, the debug circuit system 112 performs the scan after being triggered (e.g., in response to receiving a command). In other examples, the debug circuit system 112 automatically performs the scan when the GLS is generated. Figure 1 As described in , when debug circuitry 112 identifies a problem and an engineer corrects the problem, GLN simulation circuitry 110 simulates GLN 101 again. This process is repeated until GLN 101 is fully debugged and verified. Thus, example GLN simulation circuitry 110 and example debug circuitry 112 operate to check the physical parameters of GLN 101.

[0040] When the engineer determines that there are no issues in the GLS (e.g., debug was successful), the GLN simulation circuit system 110 generates a final layout 104. In some examples, the final layout 104 is used by the engineer to generate a "master blueprint" for the target IC. The debugged GLS allows the test engineer to complete the gate-level netlist 101. The final version of the gate-level netlist 101 can be used to generate a detailed layout of the target IC, including placed and routed transistors, circuits, and other components, referred to as the final layout 104.

[0041] Figure 2 for Figure 1 1 is a block diagram of an example implementation of a probe selection controller 126 for selecting a probing point. Figure 2 The probe selection controller 126 may be instantiated (e.g., created as an instance, exists for any length of time, implemented, carried out, etc.) by programmable circuitry, such as a central processing unit (CPU), executing a first instruction. Additionally or alternatively, Figure 2 The probe selection controller 126 may be instantiated (e.g., created as an instance, exists for any length of time, is implemented, is implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. Therefore, it should be understood that Figure 2 Some or all of the circuitry may be instantiated at the same or different times. Figure 2 Some or all of the circuitry of may be instantiated, for example, in one or more threads that are executed concurrently in hardware and / or serially in hardware. Figure 2 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0042] The example probe selection controller 126 includes an example interface circuitry 202, an example resolution circuitry 204, an example tracking circuitry 206, and an example allocation circuitry 208. In some examples, the interface circuitry 202 is configured to execute interface instructions and / or to perform operations such as by Figures 4 to 5 In some examples, parsing circuitry 204 is implemented by executing parsing instructions and / or configured to perform operations (such as by Figures 4 to 5 In some examples, the trace circuitry 206 is implemented by executing trace instructions and / or configured to perform operations such as those described in the flowchart of FIG. Figures 4 to 5In some examples, the allocation circuitry 208 is implemented by executing allocation instructions and / or configured to perform operations (such as by Figures 4 to 5 The programmable circuit system instantiates the operation of the flowchart represented by the flowchart.

[0043] Figure 1 and 2 The example probe selection controller 126 includes an interface circuit system 202 to obtain inputs for selecting a probe point. The inputs for selecting a probe point include the RTL code 114, the GLN 101, and the initial probe. The example interface circuit system 202 receives the GLN 101 as a trigger to start modifying and / or selecting an alternative probe. In some examples, the interface circuit system 202 communicates the inputs with the parsing circuit system 204, the tracing circuit system 206, the allocation circuit system 208, and / or the probe data storage area 108 ( Figure 1 ) connected.

[0044] Figure 1 and 2 The example probe selection controller 126 includes an example parsing circuitry 204 to extract information representing parameters and statements from the input. For example, the parsing circuitry 204 parses and / or extracts the RTL code 114. When the parsing circuitry 204 parses the RTL code 114, it obtains statements and parameters corresponding to modules (e.g., gates and other circuit devices). In some examples, the tracing circuitry 206 uses the statements and parameters to identify the root module of the initial probe. In some examples, the parameters and statements of the RTL code 114 and the initial probe of the development environment 100 provide a lower-level view of the GLN 101. The example parsing circuitry 204 can implement any type of parsing algorithm.

[0045] Figure 1 and 2The example probe selection controller 126 includes an example tracing circuitry 206 for tracing (e.g., iterating) the RTL code 114 using parsed input to identify a root module that generates an initial data output for a wire connection (e.g., a connector, a signal path, a wire, a conductor, etc.). The example tracing circuitry 206 identifies the wire connection (e.g., a connector, a signal path, a wire, a conductor, etc.) and determines whether the wire connection is an output of a root module or an output of a non-root module. As described above and reiterated here for convenience, a root module may be a gate or circuit device with root outputs, where the root outputs are internally driven from fixed (e.g., hard-coded) logic or registers. As used herein, a non-root module may be a gate or circuit device that receives input from a root module and provides output to another non-root module. The example tracing circuitry 206 selects a wire connection to be traced based on an initial probe. For example, the GLN 101 includes an initial probe or an automatically placed probe, and the probe selection controller 126 automatically modifies the placement of the initial probe to an alternate location. The instance tracing circuit system 206 selects an initial probe and uses the RTL code 114 to identify a module with a corresponding input or output. For example, the instance tracing circuit system 206 identifies a statement in the RTL code 114 that matches the name of the initial probe. The initial probe has a name, where the name defines the wire connection (input, location, signal, wire, etc.) of the initial probe. For example, the probe name "module1_inputbus" indicates that the initial probe is probing the input bus of module 1. Thus, the instance tracing circuit system 206 identifies the input or output of the tested (e.g., probed) module. In some instances, the tracing circuit system 206 then iterates through the parsed RTL code 114 to identify the root (root module) of the input or output. In some instances, the tracing circuit system 206 traces the wire connection in GLN 101 back to the root of the input or output. Figure 3 The operation of the example tracking circuitry 206 is described.

[0046] Figure 3An example simulated gate-level netlist (GLS) 300 for a portion of a system-on-chip (SoC) is shown. GLS 300 is a schematic illustration of an SoC created from RTL code and final layout. Example GLS 300 for the SoC includes an example interconnect block 302 and an example secure digital input / output (SDIO) controller 304. Example interconnect block 302 is a component used to manage communication and data exchange between various subsystems, modules, and components within the SoC. Example interconnect block 302 can be a synthesizable logic set and includes an example splitter 306, which can itself be a hard-coded or synthesizable logic set. Interconnect block 302 also includes an example first logic gate 308, which is a synthesis product of the RTL code defining interconnect block 302. Example SDIO controller 304 is an interface for an input or output device. For example, SDIO controller 304 interfaces a device (e.g., a modem) to a host (e.g., a processor). The example SDIO controller 304 can be a synthesizable set of logic and includes an example bus unit 310, which can itself be a hard-coded or synthesizable set of logic. The SDIO controller 304 also includes an example second logic gate 312, which is a product of the RTL code that defines the SDIO controller 304. The example interconnect block 302 and the example SDIO controller 304 can include multiple devices for managing communications and data exchange and for interfacing with input or output devices. However, for the purposes of this description, Figure 2 For purposes of example tracking circuitry 206 , an example splitter 306 , an example first logic gate 308 , an example bus unit 310 , and an example second logic gate 312 are illustrated.

[0047] exist Figure 3 In the example, splitter 306 routes data in parallel between multiple endpoints. For example, splitter 306 divides, copies, and / or directs data streams to one or more destinations. In this example, splitter 306 transmits at least one or more data streams to bus unit 310 of SDIO controller 304. For example, splitter 306 provides a command (CMD) and a corresponding memory address bus 316 to bus unit 310. In this example, the memory address bus 316 output by splitter 306 is 4 bits (address [3:0]). In some examples, the splitter 306 configures the least significant bit (LSB) of the memory address bus 316 to be zero because the memory address bus 316 only needs to be indexed by multiples of four, such as 4, 8, and 12 (e.g., binary value "0000" equals decimal value "0", binary value "0100" equals decimal value "4", binary value "1000" equals decimal value "8", and binary value "1100" equals decimal value "12"). Therefore, the destination of the memory address bus 316 does not check the LSB of the 4-bit memory address bus 316. During synthesis, the example synthesized circuit system (e.g., Figure 1The integrated circuit system 102) makes the LSB floating because the probe will not check the LSB.

[0048] exist Figure 3 In the example, the example bus unit 310 transmits commands and / or data from the example splitter 306 to a device interfaced with the example SDIO controller 304. For example, the bus unit 310 directs commands and / or data from the splitter 306 to the device intended to receive such commands and / or data. In the example, the RTL of the interconnect block 302 and the SDIO controller 304 are merely wrappers around the command and data lines and do not specify any intervening logic between the splitter 306 and the bus unit 310.

[0049] However, in Figure 3 In the associated GLN shown in FIG, the example interconnect block 302 includes a first logic gate 308 coupled to the output of the splitter to facilitate driving the signal along the physical wire, and similarly, the example SDIO controller 304 includes a second logic gate 312 coupled to the output of the first logic gate 308 and the input of the bus unit 310. The first logic gate 308 and the second logic gate 312 are inverters. In some examples, in the RTL code 114 ( Figure 1 During optimization of the GLN, first logic gate 308 and second logic gate 312 are added. First logic gate 308 inverts the output of splitter 306, and second logic gate 312 inverts the output of first logic gate 308 back to the original output of splitter 306. For example, in some iterations of synthesis, inverting logic gates 308 and 312 are replaced by a pair of inverters (e.g., buffers). This has the effect of changing the logic value of some intermediate wires, but for a given value at the output of splitter 306, the value at the input of bus unit 310 remains the same. In this way, bus unit 310 will obtain an output from splitter 306 regardless of the number of inverters coupled in the wire path. For example, splitter 306 includes a conditional statement indicating that if (a=b), then the value on the command line is "1." In this example, when the condition is met (e.g., when a=b), splitter 306 will output 1 and bus unit 310 will receive 1.

[0050] Although the command (e.g., data) passed to the bus unit 310 is the same command output by the separator 306, the probes on the command line may read different outputs depending on where the probes are placed and the number of reversals that occur along the wire path. For example, before implementing the probe selection controller 126, the development environment 100 ( Figure 1) places a first initial probe 314a at the input of the second logic gate 312 (e.g., at the boundary of the SDIO controller 304). If a condition is met (e.g., when a=b), then this first initial probe 314a places a read of "0" instead of "1." The value read and returned by the first initial probe 314a is not the value output by the demultiplexer 306 and, furthermore, is not the value actually received by the bus unit 310 during the desired behavior of the SoC.

[0051] Therefore, the example tracing circuitry 206 modifies and / or changes the placement of the initial probe 314a to a location that is less likely to return undesired results. For example, the example tracing circuitry 206 employs the first initial probe 314a, identifies an equivalent wire connection (e.g., a CMD line) in the RTL code 114 where the first initial probe 314a is placed, and analyzes the equivalent wire connection in the RTL code 114. The example tracing circuitry 206 traces the equivalent wire connection (e.g., a net, interconnect, wire, conductor, signal path, input, output, etc.) from the end point to the start point. For example, the tracing circuitry 206 uses the RTL code 114 to trace a wire connection (e.g., a CMD line) from the current module (SDIO 304) to the source module (interconnect block 302).

[0052] When identifying a source module, example tracing circuitry 206 determines whether the wire connection is connected to the output of another module (e.g., a gate or other circuit device). For example, tracing circuitry 206 determines that the CMD line is connected to the output of splitter 306 at the boundary of interconnect block 302. In this example, tracing circuitry 206 has determined that the wire connection is connected to the output of another module. In some examples, tracing circuitry 206 determines that there is no other module, and therefore, the source module of the CMD line (e.g., interconnect block 302) is a root module (e.g., a module with root outputs, where the root outputs are internally driven from fixed (e.g., hard-coded) logic or registers) that drives the output on the CMD line. Tracing circuitry 206 identifies the output of the root module as an alternative probe location because the output is more predictable.

[0053] exist Figure 3, when tracing a wire connection (e.g., a CMD line) from the boundary of the interconnect block 302 to the output of the next module, the instance tracing circuit system 206 identifies the first module output at the output of the first logic gate 308. The instance tracing circuit system 206 repeats the steps of determining whether the wire connection is connected to the output of another module and tracing the wire connection from the source module (e.g., the most current module being analyzed by the tracing circuit system 206, which in this instance is now the first logic gate 308) to the output of the next module (e.g., the output of the splitter 306). In some instances, the tracing circuit system 206 stops repeating these steps when the wire connection is not connected to another module output at a particular module output. For example, in Figure 3 , tracing circuitry 206 stops tracing the interconnect at the output of splitter 306. Tracing circuitry 206 stops at the output of splitter 306 because splitter 306 does not receive input from another module. Alternatively, the example splitter 306 is internally driven from fixed (e.g., hard-coded) logic, or a register provides the initial output of the CMD line.

[0054] In this example, the tracing circuitry 206 determines that the separator 306 is the root module of the wire connection (e.g., CMD line). When the root module is identified, the instance tracing circuitry 206 triggers the instance allocation circuitry 208 ( Figure 2 ) to allocate an alternative probe location based on the identified root module. For example, the tracking circuitry 206 triggers the allocation circuitry 208 to modify the placement of the first initial probe 314a to the alternative probe location 314b (eg, the output of the splitter 306).

[0055] In another example, the trace circuitry 206 finds an alternate probe location 318b for the memory address bus 316 verification bus probe 318a (second initial probe 318a). The example development environment 100 generates a checksum in the RTL code (e.g., Figure 1 The second initial probe 318a is generated for the memory address bus 316 during the simulation and verification of the RTL code 114 of the integrated circuit system. The second initial probe 318a may have correctly probed the memory address bus 316 during the RTL code simulation, but due to the optimization changes, the second initial probe 318a may not correctly probe the memory address bus 316 during the GLN simulation. Figure 1The integrated circuit system 102 of the example tracing circuitry 206 floats the LSB in the 4-bit memory address bus 316, causing the LSB value on the destination module to be "HighZ." In some examples, the "HighZ" value causes the second initial probe 318a to incorrectly display and / or read the memory address bus 316. For example, "HighZ" can cause an error or fault when the second initial probe 318a attempts to read the value of the memory address bus 316. Therefore, the example tracing circuitry 206 identifies an alternate probe location 318b for the second initial probe 318a.

[0056] The example tracing circuitry 206 selects the second initial probe 318a, identifies the equivalent wire connection (e.g., CMD line) in the RTL code 114 where the second initial probe 318a is placed, and analyzes the equivalent wire connection in the RTL code 114. The example tracing circuitry 206 traces the equivalent wire connection (e.g., net, wire connection, wire, conductor, signal path, input, output, etc.) from the end point to the start point. For example, the tracing circuitry 206 uses the RTL code 114 to trace the wire connection (e.g., memory address bus 316) from the current module (SDIO 304) to the source module (interconnect block 302). Upon identifying the source module, the example tracing circuitry 206 determines whether the wire connection is connected to the output of another module (e.g., a gate or other circuit device). For example, the tracing circuitry 206 determines that the memory address bus 316 is connected to the output of the separator 306 at the boundary of the interconnect block 302. In this example, the tracing circuitry 206 has determined that the wire connection is connected to the output of the other module. Instance tracking circuitry 206 determines that another module does not exist and, therefore, the source module (e.g., interconnect block 302) of memory address bus 316 is a root module (e.g., a module having root outputs, where the root outputs are driven internally from fixed (e.g., hard-coded) logic or registers) that drives outputs on memory address bus 316. Upon identifying the root module, instance tracking circuitry 206 triggers instance allocation circuitry 208 ( Figure 2 ) to allocate an alternative probe location 318b based on the identified root module. For example, the tracking circuitry 206 triggers the allocation circuitry 208 to modify the placement of the second initial probe 318a to the alternative probe location 318b (e.g., the output of the splitter 306).

[0057] Return to Figure 2 , Figure 1 and 2 The example probe selection controller 126 includes an example allocation circuit system 208 to allocate the output of the root module as a probe point. For example, the allocation circuit system 208 determines Figure 3The example assignment circuitry 208 assigns the output of the example splitter 306 as the first alternative probe location 314b. The example assignment circuitry 208 stores the probe point assignments in the example probe data storage area 108. For example, the assignment circuitry 208 stores information indicating a root module and its corresponding alternative probe point. The example assignment circuitry 208 stores alternative probe points for the initial probe, where the initial probe is placed at a location with a high probability of encountering the optimization problem. In some examples, the assignment circuitry 208 generates a report of the GLN 101, including the root module and the corresponding alternative probe points. In this example, the assignment circuitry 208 stores the report in the probe data storage area 108. This report can be used by the example GLN simulation circuitry 110 and / or the example debug circuitry 112 to change the probes on the wire connections in the simulated GLN. In some examples, the GLN simulation circuitry 110 automatically uses alternative probes before simulation and debugging, thereby automatically replacing the initial probes. In this example, the probe selection controller 126 reduces the amount of time spent debugging the GLS because the test engineer does not need to spend time replacing / moving the probe point to a better location on a given wire connection.

[0058] Although Figure 2 Implementation Figure 1 The probe selection controller 126 is an example of a method, but Figure 2 One or more of the elements, processes, and / or devices described in the examples may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. In addition, the interface circuitry 202, the instance resolution circuitry 204, the instance tracking circuitry 206, the instance allocation circuitry 208, and / or more generally Figure 2 The instance probe selection controller 126 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the interface circuitry 202, the instance resolution circuitry 204, the instance tracking circuitry 206, the instance allocation circuitry 208, and / or more generally the instance probe selection controller 126 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more ASICs, one or more programmable logic devices (PLDs), and / or one or more programmable logic devices (FPLDs), such as FPGAs. Further, in addition to or in lieu of Figure 2 The elements, processes and / or devices described in Figure 2The example probe selection controller 126 may also include one or more elements, processes, and / or devices, and / or may include more than one of any or all of the illustrated elements, processes, and devices.

[0059] Figures 4 to 5 The diagrams shown in FIG. 1 may be implemented and / or instantiated by a programmable circuit system. Figure 2 Example machine-readable instructions and / or representations of the probe selection controller 126 may be executed by programmable circuitry to implement and / or instantiate Figure 2 The machine readable instructions may be a flow chart of an example operation of the probe selection controller 126. Figure 6 One or more executable programs or one or more portions of one or more executable programs implemented by the programmable circuit system 612 shown in the example processor platform 600 described herein, and / or may be described below in conjunction with Figure 7 In some examples, the machine-readable instructions cause an operation, task, or the like to be performed and / or executed automatically in the real world. As used herein, "automatic" means without human intervention.

[0060] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray Discs, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuitry located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated by one or more hardware devices other than programmable circuitry and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between the server and the endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, while reference is made to Figures 4 to 5 The flowcharts illustrated in the description describe example procedures, but many other methods of implementing the example probe selection controller 126 may be used instead. For example, the order of execution of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed across different network locations and / or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., in the same integrated circuit (IC) package, or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any one or more combinations thereof.

[0061] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., one or more portions of instructions, code, a representation of code, etc.) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations on a network or collection of networks (e.g., in the cloud, on an edge device, etc.). The machine-readable instructions may need to be one or more of installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., in order to make the machine-readable instructions directly readable, interpretable, and / or executable by a computing device and / or another machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of machine-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form a program, such as those described herein.

[0062] In another example, the machine-readable instructions may be stored in a state in which they can be read by a programmable circuit system, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or one or more corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be fully or partially executed. Therefore, as used herein, machine-readable, computer-readable, and / or machine-readable media may contain instructions and / or one or more programs, regardless of the specific format or state of the machine-readable instructions and / or one or more programs.

[0063] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0064] As mentioned above, Figures 4 to 5 The example operations of can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media. Examples of such non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, temporarily buffered, and / or cached information). As used herein, the terms "non-transitory computer-readable storage" and "non-transitory machine-readable storage" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but exclude propagating signals and transmission media. Examples of non-transitory computer-readable storage and / or non-transitory machine-readable storage include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, that may or may not be configured with computer-readable instructions, machine-readable instructions, etc., and / or manufactured to carry out computer-readable instructions, machine-readable instructions, etc.

[0065] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, the phrase "at least" when used as a transition term, such as in the preamble of a technical solution, is open-ended in the same manner as the terms "include" and "comprising." The term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and A and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to refer to an embodiment that includes any of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B.

[0066] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude the plural. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0067] Figure 4 is a flow diagram representative of example machine-readable instructions and / or example operations 400 that may be executed, instantiated, and / or performed by programmable circuitry to generate a replacement probe for a GLN. Figure 4 The example machine readable instructions and / or example operations 400 begin at block 402 where the probe selection controller 126 ( Figure 1 ) determines whether a probe modification request has been initiated. For example, the interface circuit system 202 ( Figure 2 ) Waiting for the controller 126 to be selected from the development environment 100 and / or probe ( Figure 1 ) obtains a request to modify the probe. In some examples, the probe selection controller 126 triggers the probe modification when the probe selection controller 126 obtains the GLN 101. For example, the probe selection controller 126 may intercept the GLN 101 before emulating the GLN 101.

[0068] At block 404, the example probe selection controller 126 obtains RTL code. For example, the interface circuitry 202 obtains the RTL code 114. In some examples, the probe selection controller 126 uses the RTL code 114 to find and trace wire connections with initial probes that need to be modified. In some examples, the probe selection controller 126 uses the RTL code 114 to identify modules (e.g., gates and other circuit devices) connected to the wire connections. For example, the trace circuitry 206 uses the RTL code 114 to trace the wire connections and identify root modules connected to the wire connections.

[0069] At block 406, the instance probe selection controller 126 parses the RTL code 114 to identify parameters and statements. For example, the parsing circuitry 204 extracts information representing the expected and / or actual connections of modules in the GLN 101. In some examples, the parsing circuitry 204 extracts the naming conventions of the modules, such as a hierarchical naming convention representing the logical hierarchy of the modules.

[0070] At block 408, the instance probe selection controller 126 selects the instance probe data store 108 ( Figure 1 ) obtains the initial probe. For example, interface circuitry 202 requests the initial probe generated during simulation of RTL code 114 because GLN simulation circuitry 110 also uses the initial probe when simulating GLN 101. Due to optimization changes in RTL code 114 during synthesis, the initial probe fails during simulation of GLN 101.

[0071] At block 410, the instance probe selection controller 126 modifies the initial probe based on the parsed RTL code 114. Figure 5The operations of block 410 are described in further detail.

[0072] At block 412, the example probe selection controller 126 notifies an engineer (e.g., a software engineer, a development engineer, a design engineer, or any person or entity designing a target IC) that an alternative probe is available. For example, the interface circuitry 202 may generate instructions that cause the development environment 100 to notify the engineer that an alternative probe has been selected and stored for subsequent use.

[0073] At block 414 , the example probe selection controller 126 determines whether the engineer has elected to use an alternative probe. For example, the interface circuitry 202 may obtain a request to use an alternative probe in response to sending a notification that an alternative probe is available.

[0074] At block 416, when the example probe selection controller 126 determines that the engineer has selected to use an alternative probe (block 414 returns a "yes" value), the example probe selection controller 126 instructs the example GLN simulation circuitry 110 to use the alternative probe. In some examples, the instruction to use the alternative probe causes the GLN simulation circuitry 110 to load the alternative probe into the DV environment 100 before simulating the GLN 101.

[0075] At block 418, when the example probe selection controller 126 determines that the engineer has not selected to use an alternative probe (block 414 returns a "no" value), the example probe selection controller 126 instructs the example GLN simulation circuitry 110 to use the initial probe. In some examples, the instruction to use the initial probe causes the GLN simulation circuitry 110 to simulate the GLN 101 normally.

[0076] The example operations 400 end when the example probe selection controller 126 instructs the example GLN simulation circuitry 110 to use or not use the replacement probe. The example operations 400 may be repeated when the example probe selection controller 126 obtains a new GLN.

[0077] Figure 5 is a flow diagram representative of example machine-readable instructions and / or example operations 410 that may be carried out, instantiated, and / or executed by programmable circuitry to modify an initial probe based on parsed RTL code 114 . Figure 5 The example machine readable instructions and / or example operations 410 begin at block 502 where the probe selection controller 126 ( Figure 1 ) selects the initial probe to be analyzed. For example, the tracking circuit system 206 ( Figure 2) traverses the list of initial probes to analyze and modify them as needed. In some instances, the initial probes are located at locations where there is a low probability of optimization problems existing and therefore do not need to be modified. In some instances, the trace circuitry 206 still traces the wire paths of the probes (described in further detail below) to ensure that such initial probes are located at locations that are more predictable than initial probes placed at locations that have been optimized during synthesis.

[0078] At block 504, the instance probe selection controller 126 identifies a wire connection in the RTL code 114 that is equivalent to the wire connection being probed by the initial probe. For example, the trace circuitry 206 identifies which wire connection the selected initial probe is located on, and then finds the equivalent wire connection in the RTL code 114. In some examples, the trace circuitry 206 uses the RTL code 114 and the initial probe to identify the wire connection because the initial probe is a logical identifier with a hierarchical naming convention that enables identification of the probe in the RTL code 114 and / or differentiation between the probe and the module. For example, the trace circuitry 206 uses the name of the initial probe to determine the portion of the GLN 101 being probed (e.g., the output of a module).

[0079] At block 506, the example probe selection controller 126 determines whether the wire connection is input to a module. For example, the tracing circuitry 206 determines the direction of the wire connection and whether one end of the wire connection is connected to a module. In some examples, the tracing circuitry 206 determines whether the wire connection is connected between two modules to identify whether the wire path is input to a module (e.g., a gate or other circuit device).

[0080] If the instance probe selection controller 126 and / or the instance trace circuitry 206 determines that the wire connection is input to a module (block 506 returns a "yes" value), then the instance probe selection controller 126 traces the wire connection from the current module to the source module (block 508). For example, the trace circuitry 206 identifies the module (e.g., the current module) that is receiving the input from the wire connection. The trace circuitry 206 then uses the RTL code 114 ( Figure 1 ) Find the module (e.g., source module) that sends output to the current module via a wire connection. The RTL code 114 includes information that represents how the modules interact with each other, and therefore, the tracing circuitry 206 can use this information to identify the source module that is connected to the current module via a wire connection.

[0081] If the instance probe selection controller 126 and / or the instance trace circuitry 206 determine that the wire connection is not an input to a module (block 506 returns a "no" value), the instance probe selection controller 126 determines a root module in which the wire connection is found (block 514). For example, the trace circuitry 206 determines that the initial probe is located at the output of the root module, where the output of the root module is internally driven from fixed (e.g., hard-coded) logic or registers and is more predictable than outputs that have been optimized during synthesis.

[0082] At block 510, the example probe selection controller 126 determines whether a wire connection at a source module is connected to an output of another module. For example, the trace circuit system 206 determines whether the wire connection is an output of a bottom-level module in the current source module. In some examples, a source module is a submodule that includes bottom-level modules that describe circuit components (such as logic gates and other circuit devices) within the submodule. The wire connection can be connected to an output of one of those bottom-level components. For example, the CMD line ( Figure 3 ) is traced from the output of interconnect block 302 (which is a submodule) to the output of first logic gate 308 (which is a bottom-level module). Next, the CMD line is traced from the input of first logic gate 308 to the output of splitter 306, which is also a bottom-level module of interconnect block 302. Trace circuitry 206 uses RTL code 114 to determine whether the source module contains any bottom-level modules. RTL code 114 provides the module's hardware description language (HDL), which describes how the module is connected to another module.

[0083] If the instance probe selection controller 126 determines that the wire connection at the source module is connected to the output of another module (block 510 returns a "yes" value), the instance probe selection controller 126 traces the wire connection from the current source module to the output of the other module (block 512). For example, the tracing circuitry 206 uses the RTL code 114 to identify the previous module (e.g., the first logic gate 308) on the wire connection (e.g., the CMD line), where the previous module is a module that outputs to the boundary of the current source module (e.g., the interconnect block 302). When the instance tracing circuitry 206 traces the wire connection from the source module to the output of the other module, control returns to block 510 and steps 510 and 512 are repeated.

[0084] If the instance probe selection controller 126 determines that the wire connection is not connected to the output of another module (block 510 returns a "no" value), the instance probe selection controller 126 determines the root module where the wire connection is found (block 512). For example, the trace circuit system 206 determines that the current source module is the root module. Figure 3, tracing circuitry 206 determines that splitter 306 is the root module because splitter 306 is internally driven from fixed (eg, hard-coded) logic or registers.

[0085] At block 516, the instance probe selection controller 126 assigns the output of the root module as a replacement probe. For example, the assignment circuitry 208 ( Figure 2 ) The module is marked and / or labeled as a root module. Next, the instance allocation circuitry 208 generates a replacement logic flag that detects the output of the root module.

[0086] At block 518, the example probe selection controller 126 stores the replacement probe in the database. For example, the allocation circuitry 208 stores the replacement probe in the probe data storage area 108 ( Figure 1 ) and map (e.g., associate) the replacement probe to the root module.

[0087] At block 520 , the instance probe selection controller 126 determines whether there is another initial probe. For example, the tracking circuitry 206 determines whether there are any additional probes that should be modified.

[0088] If the instance probe selection controller 126 determines that there is another initial probe (block 520 returns a value of "yes"), then control returns to block 502. If the instance probe selection controller 126 determines that there is no other initial probe to modify (block 520 returns a value of "no"), then operation 410 ends and control returns to Figure 4 Block 412 (eg, the probe selection controller 126 notifies the engineer ( Figure 1 ) an alternative probe is available). When the probe selection controller 126 is triggered to modify the probe before simulating the GLN 101, the example operation 410 may be repeated.

[0089] Figure 6 is a block diagram of an example programmable circuitry platform 600 that is structured to implement and / or instantiate Figures 4 to 5 Example machine readable instructions and / or example operations to implement Figure 2 The probe selection controller 126. The programmable circuit system platform 600 can be, for example, a server, a personal computer, a workstation, a self-learning machine (eg, a neural network or any other type of computing and / or electronic device).

[0090] The programmable circuitry platform 600 of the illustrated example includes programmable circuitry 612. The programmable circuitry 612 of the illustrated example is hardware. For example, the programmable circuitry 612 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuitry 612 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this embodiment, the programmable circuitry 612 implements the probe selection controller 126, the resolution circuitry 204, the tracking circuitry 206, and the distribution circuitry 208.

[0091] The programmable circuit system 612 of the illustrated example includes a local memory 613 (e.g., cache, registers, etc.). The programmable circuit system 612 of the illustrated example communicates with main memory 614, 616 via a bus 618, the main memory including volatile memory 614 and non-volatile memory 616. The volatile memory 614 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory The nonvolatile memory 616 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 614, 616 of the illustrated example is controlled by a memory controller 617. In some examples, the memory controller 617 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 614, 616.

[0092] The programmable circuitry platform 600 of the illustrated example also includes an interface circuitry 620. The interface circuitry 620 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, In this example, interface circuitry 620 implements interface circuitry 202 .

[0093] In the illustrated example, one or more input devices 622 are connected to the interface circuitry 620. The one or more input devices 622 allow a user (e.g., a human user, a machine user, etc.) to enter data and / or commands into the programmable circuitry 612. The one or more input devices 622 may be implemented by, for example, a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, and / or an isopoint device, and / or a voice recognition system.

[0094] One or more output devices 624 are also connected to the interface circuitry 620 of the illustrated example. The one or more output devices 624 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switch (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 620 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0095] The interface circuitry 620 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) over a network 626. Communication may occur through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, and the like.

[0096] The programmable circuitry platform 600 of the illustrated example also includes one or more mass storage disks or devices 628 to store firmware, software, and / or data. Examples of such mass storage disks or devices 628 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs. In this example, the mass storage disks or devices 628 implement the probe data storage area 108.

[0097] can be Figures 4 to 5 The machine-readable instructions 632 implemented by the machine-readable instructions may be stored in the mass storage device 628, in the volatile memory 614, in the non-volatile memory 616, and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD that may be removable.

[0098] Figure 7 for Figure 6 612. In this example, Figure 6 The programmable circuit system 612 is implemented by the microprocessor 700. For example, the microprocessor 700 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). Figures 4 to 5 Some or all of the machine-readable instructions of the flowchart to effectively Figure 2 In some such instances, the circuitry is instantiated as logic circuits to perform operations corresponding to those machine-readable instructions. Figure 2 The circuit system is instantiated by the hardware circuits of the microprocessor 700 in combination with machine-readable instructions. For example, the microprocessor 700 may be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although the microprocessor may include any number of instance cores 702 (for example, 1 core), the microprocessor 700 of this example is a multi-core semiconductor device including N cores. The cores 702 of the microprocessor 700 may operate independently or may cooperate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 702, or may be executed by multiple of the cores 702 at the same or different times. In some instances, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores 702. The software program may correspond to a thread executed by Figures 4 to 5 A flowchart represents a portion or all of machine-readable instructions and / or operations.

[0099] The cores 702 can communicate via a first example bus 704. In some examples, the first bus 704 can be implemented as a communication bus to facilitate communications associated with one or more of the cores 702. For example, the first bus 704 can be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 704 can be implemented by any other type of computing or electrical bus. The cores 702 can obtain data, instructions, and / or signals from one or more external devices via example interface circuitry 706. The cores 702 can output data, instructions, and / or signals to the one or more external devices via interface circuitry 706. While the cores 702 of this example include example local memory 720 (e.g., a level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 700 also includes example shared memory 710 (e.g., a level 2 (L2) cache) that may be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 710. The local memory 720 and shared memory 710 of each of the cores 702 may be a plurality of levels of cache memory and main memory (e.g., Figure 6 Cache memory is part of a storage hierarchy (e.g., main memory 614, 616). Typically, higher-level memory in the hierarchy exhibits shorter access times and has smaller storage capacity than lower-level memory. Changes to various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0100] Each core 702 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuitry. Each core 702 includes control unit circuitry 714, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 716, a plurality of registers 718, local memory 720, and a second instance bus 722. Other configurations are possible. For example, each core 702 may include vector unit circuitry, single instruction, multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / jump unit circuitry, floating point unit (FPU) circuitry, and the like. Control unit circuitry 714 includes semiconductor-based circuitry structured to control (e.g., coordinate) data movement within the corresponding core 702. AL circuitry 716 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on data within the corresponding core 702. Some examples of AL circuitry 716 perform integer-based operations. In other examples, AL circuitry 716 also performs floating-point operations. In still other examples, AL circuitry 716 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 716 may be referred to as an arithmetic logic unit (ALU).

[0101] Registers 718 are semiconductor-based structures used to store data and / or instructions, such as the results of one or more operations performed by the AL circuitry 716 of the corresponding core 702. For example, registers 718 may include one or more vector registers, one or more SIMD registers, one or more general registers, one or more flag registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. Registers 718 may be, for example, vector registers, one or more SIMD registers, one or more general registers, one or more flag registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. Figure 7 Alternatively, registers 718 may be organized in any other arrangement, format, or structure, such as by being distributed among core 702 to reduce access time. Second bus 722 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0102] Each core 702 and / or the microprocessor 700 more generally may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stoppers (CMSs), one or more shifters (e.g., one or more barrel shifters), and / or other circuitry. The microprocessor 700 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) included in one or more packages.

[0103] The microprocessor 700 may include and / or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, an accelerator is implemented by logic circuitry to perform certain tasks more quickly and / or efficiently than can be performed by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be onboard the microprocessor 700, in the same chip package as the microprocessor 700, and / or in one or more separate packages from the microprocessor 700.

[0104] Figure 8 for Figure 6 FIG. 8 is a block diagram of another example embodiment of a programmable circuit system 612. In this example, the programmable circuit system 612 is implemented by an FPGA circuit system 800. For example, the FPGA circuit system 800 can be implemented by an FPGA. The FPGA circuit system 800 can be used, for example, to execute a programmable circuit system 612. Figure 7 However, once configured, FPGA circuitry 800 instantiates operations and / or functions corresponding to machine-readable instructions in hardware and, therefore, can typically perform operations / functions faster than they could be performed by a general-purpose microprocessor executing corresponding software.

[0105] More specifically, as described above Figure 7 The microprocessor 700 (which is programmable to perform Figures 4 to 5 Compared to a general device that represents some or all of the machine-readable instructions in a flowchart, but whose interconnections and logic circuitry are fixed once manufactured, Figure 8 The interconnects and logic circuitry included in the FPGA circuitry 800 of the example can be configured, structured, programmed, and / or interconnected in different ways after fabrication to instantiate, for example, a device corresponding to a device represented by Figures 4 to 5800. Specifically, FPGA circuitry 800 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected via the interconnects, effectively forming one or more dedicated logic circuitry systems (unless and until FPGA circuitry 800 is reprogrammed). The logic circuitry is configured so that the logic gates can cooperate in different ways to perform different operations on data received by the input circuitry. Those operations may correspond to the operations performed by Figures 4 to 5 Thus, FPGA circuitry 800 may be configured and / or structured to effectively process the instructions (e.g., software and / or firmware) corresponding to the flowchart of FIG. Figures 4 to 5 Some or all of the operations / functions of the machine-readable instructions of the flowchart are instantiated as dedicated logic circuits to perform the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit system 800 can be used with a general-purpose microprocessor to perform the operations / functions corresponding to the software instructions. Figures 4 to 5 The operations / functions of some or all of the machine-readable instructions are performed faster than those of the machine-readable instructions.

[0106] exist Figure 8 In an example, the FPGA circuit system 800 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in the HDL; the code / program may be converted to a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Figure 8 The FPGA circuit system 800 can access and / or load binary files to enable Figure 8 The FPGA circuit system 800 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Figure 8 The FPGA circuit system 800 can access a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to cause Figure 8 Configuration and / or structuring of the FPGA circuit system 800 or one or more portions thereof.

[0107] In some examples, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform may convert first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 8 The FPGA circuit system 800 can access and / or load binary files to enable Figure 8 The FPGA circuit system 800 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Figure 8 The FPGA circuit system 800 can access a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to cause Figure 8 Configuration and / or structuring of the FPGA circuit system 800 or one or more portions thereof.

[0108] Figure 8 The FPGA circuit system 800 includes an example input / output (I / O) circuit system 802 to obtain data from and / or output data to an example configuration circuit system 804 and / or external hardware 806. For example, the configuration circuit system 804 may be implemented by an interface circuit system that can obtain a binary file, which may be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuit system 800 or one or more portions thereof. In some such examples, the configuration circuit system 804 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any one or more combinations thereof. In some examples, the external hardware 806 may be implemented by an external hardware circuit system. For example, the external hardware 806 may be implemented by Figure 7 The microprocessor 700 is implemented.

[0109] FPGA circuitry 800 also includes an array of instance logic gate circuitry 808, a plurality of instance configurable interconnects 810, and instance storage circuitry 812. Logic gate circuitry 808 and configurable interconnects 810 may be configured to instantiate a logic gate circuitry corresponding to a logic gate. Figures 4 to 5 One or more operations / functions of at least some of the machine-readable instructions, and / or other desired operations. Figure 8Logic gate circuitry 808 is fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controlled switches (e.g., transistors) are present within each of logic gate circuitry 808 to enable configuration of the electrical structures and / or logic gates to form circuits that perform desired operations / functions. Logic gate circuitry 808 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0110] The configurable interconnect 810 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controlled switches (e.g., transistors) whose states can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 808 to program a desired logic circuit.

[0111] The storage circuitry 812 of the illustrated example is structured to store one or more results of one or more operations performed by corresponding logic gates. The storage circuitry 812 may be implemented by registers, etc. In the illustrated example, the storage circuitry 812 is distributed among the logic gate circuitry 808 to facilitate access and increase execution speed.

[0112] Figure 8 The example FPGA circuit system 800 also includes an example dedicated operation circuit system 814. In this example, the dedicated operation circuit system 814 includes dedicated circuit systems 816, which can be called to implement common functions, thereby eliminating the need to program those functions in the field. Examples of such dedicated circuit systems 816 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may exist. In some examples, the FPGA circuit system 800 may also include an example general-purpose programmable circuit system 818, such as an example CPU 820 and / or an example DSP 822. In addition or alternatively, there may be other general-purpose programmable circuit systems 818 that can be programmed to perform other operations, such as a GPU, XPU, etc.

[0113] Although Figure 7 and 8 illustrate Figure 6 These are two example implementations of programmable circuitry 612, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as Figure 7 One or more of the instance CPUs 820. Therefore, Figure 6 The programmable circuit system 612 may additionally be configured by combining at least Figure 7 The example microprocessor 700 and Figure 8 In some such hybrid embodiments, Figure 7 The one or more cores 702 may execute Figures 4 to 5 The flowchart represents a first portion of machine-readable instructions to perform one or more first operations / functions, Figure 8 The FPGA circuitry 800 may be configured and / or structured to perform operations corresponding to those performed by Figures 4 to 5 One or more second operations / functions of a second portion of the machine-readable instructions represented by a flowchart, and / or the ASIC may be configured and / or structured to perform the operations corresponding to the operations / functions of the second portion of the machine-readable instructions represented by Figures 4 to 5 The flowchart represents one or more third operations / functions of a third portion of the machine-readable instructions.

[0114] Therefore, it should be understood that Figure 2 Some or all of the circuitry of may be instantiated at the same or different times. For example, Figure 7 One or more of the same and / or different portions of the microprocessor 700 may be programmed to execute one or more portions of the machine-readable instructions at the same and / or different times. In some examples, Figure 8 One or more same and / or different portions of FPGA circuitry 800 may be configured and / or structured to perform operations / functions corresponding to one or more portions of machine-readable instructions at the same and / or different times.

[0115] In some instances, Figure 2 Some or all of the circuitry of may be instantiated, for example, in one or more threads that are executed in parallel and / or serially. Figure 7 The microprocessor 700 can execute machine-readable instructions in one or more threads executed in parallel and / or serially. In some examples, Figure 8 The FPGA circuit system 800 can be configured and / or structured to perform operations / functions in parallel and / or serially. In addition, in some examples, Figure 2 Some or all of the circuitry in the Figure 7 The system is implemented in one or more virtual machines and / or containers executed on the microprocessor 700.

[0116] In some instances, Figure 6 The programmable circuit system 612 can be in one or more packages. For example, Figure 7 The microprocessor 700 and / or Figure 8 The FPGA circuit system 800 can be in one or more packages. In some examples, the XPU can be composed of Figure 6The XPU may be implemented by a programmable circuit system 612, which may be in one or more packages. For example, the XPU may be included in a CPU in one package (e.g., Figure 7 Microprocessor 700, Figure 8 CPU 820, etc.), a DSP in another package (e.g., Figure 8 DSP 822), a GPU in yet another package, and an FPGA in yet another package (e.g., Figure 8 FPGA circuit system 800).

[0117] As used herein, unless otherwise specified, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and / or relative movement between those elements. Thus, connection references do not necessarily imply that two elements are directly connected and / or are in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0118] Unless specifically stated otherwise, descriptors such as "first," "second," "third," and the like are used herein without importing or otherwise indicating a meaning of priority, physical order, arrangement in a list, and / or ordering in any manner, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to in the claims by a different descriptor, such as "second" or "third." In such cases, it should be understood that such descriptors are only used to clearly identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0119] As used herein, "substantially" and "approximately" modify the subject matter / values ​​thereof to recognize the potential for variations that occur in real-world applications. For example, as one of ordinary skill in the art will understand, "substantially" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections.

[0120] As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be delays in real-world computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + 1 second.

[0121] As used herein, the phrase "communication" includes variations thereof encompassing direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but instead includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-time events.

[0122] As used herein, "programmable circuitry" is defined to include: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are structured to perform one or more specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions and / or one or more operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include a programmable microprocessor, such as a central processing unit (CPU), which can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction so as to configure and / or structure the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any one or more combinations thereof) and orchestration technology (e.g., one or more application programming interfaces (APIs)) that can distribute one or more computing tasks to one or more types of programmable circuit systems among the multiple types of programmable circuit systems that are suitable and available to perform the one or more computing tasks.

[0123] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0124] From the foregoing, it should be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed for improving the simulation of gate-level netlists by generating probes to monitor outputs with a low probability of optimization problems. The disclosed methods and apparatus improve the efficiency of using a computing device by reducing the amount of time the computing device spends performing simulations of gate-level netlists. Thus, the disclosed apparatus and methods relate to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

[0125] The appended claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: interface circuitry for obtaining register transfer level code indicative of operation of the integrated circuit; machine-readable instructions; and A programmable circuit system configured to instantiate the machine-readable instructions or execute at least one of the machine-readable instructions to perform the following operations: Obtaining a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules in the integrated circuit and connections between the modules; Obtaining a first probe, the first probe representing a first location in the gate-level netlist for monitoring behavior; identifying a root module, the root module comprising an output configured to determine a signal at the first location; and A second probe is generated to replace the first probe, the second probe indicating a second location within the gate-level netlist that is closer to the output of the root module than the first probe.

2. The apparatus of claim 1 , wherein the programmable circuitry is to identify the root module by: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to determine the signal at the first location; and The source module is determined to be the root module of the first connection.

3. The apparatus of claim 2, wherein the programmable circuitry is to replace the first probe with the second probe, the second probe representing the second location closer to the output of the root module.

4. The apparatus of claim 1 , wherein the programmable circuitry is to identify the root module by: selecting a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying the source module of the first module based on tracing the first connection from the first module to a source module, the source module including a first output configured to provide the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; and When the first connection does not trace back to an additional module, the second module is assigned as the root module of the first connection.

5. The apparatus of claim 1, wherein the integrated circuit is an integrated circuit created from the register transfer level code and the gate level netlist.

6. The apparatus of claim 1 , wherein the programmable circuitry is to identify the root module by: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to provide the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; determining, based on tracing the first connection from the input of the second module to the output of the third module, that the first connection at the second module connects the input of the second module to the output of the third module; and When the first connection is not traced back to an additional module, the third module is assigned as the root module of the first connection.

7. The apparatus of claim 1, wherein the programmable circuitry is to obtain the first probe from the interface circuitry, wherein the first probe is generated during simulation of register transfer level code to monitor behavior of a logic parameter of the register transfer level code.

8. A method comprising: obtaining register transfer level code indicative of operation of the integrated circuit; Obtaining a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules in the integrated circuit and connections between the modules; Obtaining a first probe, the first probe representing a first location in the gate-level netlist for monitoring behavior; identifying a root module, the root module comprising an output configured to determine a signal at the first location; and A second probe is generated to replace the first probe, the second probe indicating a second location within the gate-level netlist that is closer to the output of the root module than the first probe.

9. The method of claim 8, wherein identifying the root module comprises: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to determine the signal at the first location; and The source module is determined to be the root module of the first connection.

10. The method of claim 9, further comprising replacing the first probe with the second probe, the second probe representing the second location closer to the output of the root module.

11. The method of claim 8, wherein identifying the root module comprises: selecting a first one of the connections to be tracked based on the first position of the first probe; tracing the first connection to determine the first connection as an input to a first module; identifying the source module of the first module based on tracing the first connection from the first module to a source module, the source module including a first output configured to provide the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; and When the first connection does not trace back to an additional module, the second module is assigned as the root module of the first connection.

12. The method of claim 8, wherein the integrated circuit is an integrated circuit created from the register transfer level code and the gate level netlist.

13. The method of claim 8, wherein identifying the root module comprises: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to provide the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; determining, based on tracing the first connection from the input of the second module to the output of the third module, that the first connection at the second module connects the input of the second module to the output of the third module; and When the first connection is not traced back to an additional module, the third module is assigned as the root module of the first connection.

14. The method of claim 8, further comprising obtaining the first probe from interface circuitry, wherein the first probe is generated during simulation of register transfer level code to monitor behavior of a logic parameter of the register transfer level code.

15. A non-transitory machine-readable storage medium comprising instructions for causing a programmable circuit system to perform at least the following operations: obtaining register transfer level code indicative of operation of the integrated circuit; Obtaining a gate-level netlist corresponding to the integrated circuit, the gate-level netlist including modules in the integrated circuit and connections between the modules; Obtaining a first probe, the first probe representing a first location in the gate-level netlist for monitoring behavior; identifying a root module, the root module comprising an output configured to determine a signal at the first location; and A second probe is generated to replace the first probe, the second probe indicating a second location within the gate-level netlist that is closer to the output of the root module than the first probe.

16. The non-transitory machine-readable storage medium of claim 15, wherein the instructions will cause the programmable circuitry to identify the root module by: selecting a first one of the connections to be tracked based on the first position of the first probe; tracking the first connection to determine the first connection as an input to a first module; identifying the source module of the first module based on tracing the first connection from the first module to a source module, the source module including a first output configured to determine the signal at the first location; and The source module is determined to be the root module of the first connection.

17. The non-transitory machine-readable storage medium of claim 16, wherein the instructions are to cause the programmable circuitry to replace the first probe with the second probe, the second probe representing the second location closer to the output of the root module.

18. The non-transitory machine-readable storage medium of claim 15, wherein the instructions will cause the programmable circuitry to identify the root module by: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracing the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to determine the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; and When the first connection does not trace back to an additional module, the second module is assigned as the root module of the first connection.

19. The non-transitory machine-readable storage medium of claim 15, wherein the instructions will cause the programmable circuitry to identify the root module by: selecting the first probe; identifying a first one of the connections to be tracked based on the first position of the first probe; tracing the first connection to determine the first connection as an input to a first module; identifying a source module of the first module, the source module comprising a first output configured to provide the signal at the first location; determining, based on tracing the first connection from the input of the source module to the output of the second module, that the first connection at the source module connects the input of the source module to the output of the second module; determining, based on tracing the first connection from the input of the second module to the output of the third module, that the first connection at the second module connects the input of the second module to the output of the third module; and When the first connection is not traced back to an additional module, the third module is assigned as the root module of the first connection.

20. The non-transitory machine-readable storage medium of claim 15, wherein the instructions are to cause the programmable circuitry to obtain the first probe from interface circuitry, wherein the first probe is generated during simulation of register-transfer level code to monitor behavior of a logic parameter of the register-transfer level code.

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