Method for learning-based automatic component placement of analog circuits

Abstract

A method for learning-based automatic component placement of analog circuits is presented. The method comprises the following steps: acquiring a netlist file of an analog circuit comprising a plurality of components; according to the netlist file, obtaining the total number of a plurality of wells of the analog circuit and the number of components sharing the first well, the number of the components sharing the first well among the wells being the largest; according to the total number of the traps, determining the number of a plurality of bounded-slice grid (BSG, BSG) units, and according to the total number of the traps, determining the number of the plurality of bounded-slice grid (BSG, BSG) units; determining the size of each bounded slice line grid unit according to the number of the components sharing the first trap; and performing a training process to determine an optimal component placement scheme by using a reinforcement learning model including an actor model and a reviewer model.

Description

Technical Field

[0001] The present application relates to a technique for learning-based automatic component placement for analog circuits. Background Art

[0002] Analog component placement is a prominent topic in analog circuit layout synthesis, used to achieve final analog circuit layout quality and circuit performance. It determines the physical location of analog building blocks in an analog integrated circuit (IC) composed of one or more components before interconnection. In order to effectively measure the analog circuit layout quality in the physical domain during analog component placement, which is correlated to circuit performance in the electronic domain, it is crucial to minimize the total chip area and estimated interconnect length while considering the most critical analog circuit component placement factors. Summary of the Invention

[0003] Therefore, a learning-based automatic component placement method for analog circuits is proposed.

[0004] According to an exemplary embodiment, a method includes: obtaining a network connection list (also known as a netlist) file of an analog circuit including multiple components; obtaining, based on the netlist file, a total number of wells of the analog circuit and a number of components sharing a first well, wherein the number of components sharing the first well is the largest among the wells; determining a number of bounded-sliceline grid (BSG) cells based on the total number of wells; determining a size of each BSG cell based on the number of components sharing the first well; and performing a training process to determine an optimal component placement solution using a reinforcement learning model including an actor model and a critic model. The netlist file defines basic information describing each component and includes a connection line name and a component size, wherein the reinforcement learning model includes the actor model and the critic model. The training process includes: placing a first component block from a plurality of component blocks in a first grid structure to form a first placement scheme by using a reinforcement learning model, wherein the first grid structure is composed of a plurality of BSG units merged in a first arrangement form; and placing components of the analog circuit in another grid structure formed by merging the plurality of BSG units in an arrangement form different from the first arrangement, wherein each component block from the plurality of component blocks is a component or a combination of at least two components.

[0005] However, it should be understood that this summary may not include all aspects and embodiments of the present application, and therefore is not intended to be limiting or restrictive in any way. In addition, the present application will include improvements and modifications that are obvious to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present application and together with the description serve to explain the principles of the present application.

[0007] Figure 1 A schematic diagram illustrating an electronic device according to an exemplary embodiment of the present application.

[0008] Figure 2 A flow chart illustrating a method for learning-based automatic component placement for analog circuits according to an exemplary embodiment of the present application is shown.

[0009] Figure 3 A schematic diagram and implementation of a method for learning-based automatic component placement for analog circuits according to an exemplary embodiment of the present application are shown.

[0010] Figure 4A A schematic diagram illustrating component placement subject to proximity constraints according to an exemplary embodiment of the present application.

[0011] Figure 4B A schematic diagram illustrating component placement subject to symmetry-island constraints according to an exemplary embodiment of the present application.

[0012] Figure 5 A flow chart illustrating a training process for automatic component placement of analog circuits according to an exemplary embodiment of the present application is shown.

[0013] Figures 6A to 6C A schematic diagram illustrating a symmetry-island refinement algorithm according to an exemplary embodiment of the present application is shown.

[0014] In order to better understand the above features and advantages of the present application, several embodiments are described in detail below with accompanying drawings.

[0015] Explanation of Figure Numbers

[0016] 70: Model training;

[0017] 100: electronic equipment;

[0018] 110: memory;

[0019] 120: processor;

[0020] 310: Netlist file;

[0021] 320: BSG unit;

[0022] 330: Grid structure;

[0023] 360: first node embedding information;

[0024] 370: Actor Model;

[0025] 375: Component placement requirements;

[0026] 380: Critic Model;

[0027] 430A: Grid structure;

[0028] 430B: Grid structure;

[0029] 610, 620: BSG unit;

[0030] S202, S204, S206, S208, S210, S212: steps;

[0031] AX: axis of symmetry;

[0032] BSG' num : the number of BSG units;

[0033] BSG' size : The size of the BSG unit;

[0034] D1-D6, D1'-D4', Dx, Dx': components;

[0035] (Dx, Dx'): component pair;

[0036] G: symmetric component group;

[0037] g r 、g c :category;

[0038] s0: initial state;

[0039] S1: status;

[0040] S2: status;

[0041] s t : current status;

[0042] s t+1 : new state;

[0043] TD error : time difference error;

[0044] W total : the total number of wells;

[0045] WD max : the number of components sharing the first well;

[0046] D a :area;

[0047] N HPWL :HPWL;

[0048] P w : Width of the layout area;

[0049] P l : length of the layout area;

[0050] N n : the number of nets;

[0051] (x, y): grid position;

[0052] p θ (a t |s t ): probability;

[0053] a t :action;

[0054] Time difference error;

[0055] r t : current reward;

[0056] q t : The expected value of the current state;

[0057] q t+1 : The expected value of the new state;

[0058] α: convergence constant;

[0059] γ: decay constant;

[0060] q θ (a t ,s t ): first expected value;

[0061] q θ′ (a t , s t ): The second expected value. DETAILED DESCRIPTION

[0062] Some embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the present application. Indeed, the various embodiments of the present application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0063] Figure 1 A schematic diagram of an electronic device according to an exemplary embodiment of the present application is shown. All components and configurations of the electronic device are first Figure 1 The functions of these components are combined Figure 2 More details disclosed.

[0064] Please refer to Figure 1 , the electronic device 100 includes at least a memory 110 and a processor 120. The electronic device 100 can be an electronic system or a computer system. The memory 110 can be various forms of non-volatile storage devices, such as flash memory, non-volatile random access memory (NVRAM), hard disk drive (HDD) and solid-state drive (SSD). The processor 120 can be one or more of a north bridge, a south bridge, a field programmable array (FPGA), a programmable logic device (PLD), an application specific integrated circuit (ASIC), other similar devices or a combination thereof. The processor 120 can also be a central processing unit (CPU), a programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a graphics processing unit (GPU), other similar devices or a combination thereof.

[0065] Figure 2 A flow chart showing a method for learning-based automatic component placement for analog circuits according to an exemplary embodiment of the present application is shown, wherein Figure 2 The steps can be Figure 1 The electronic device 100 is shown as an implementation.

[0066] Please also refer to Figure 2 and Figure 1 , the processor 120 will obtain a network connection list (also known as a netlist) file of the analog circuit containing the components (step S202). In this article, the netlist file will define basic information describing each component. Such basic information may include: (1) the name of the connection line (net name) connected to the component, and the connection name is represented by numbers, letters, and alphanumeric characters; (2) the name of the power net connected to the well where the component is located, such as n-well or p-well; (3) the size of the component (e.g., length and width), etc.

[0067] Next, the processor 120 obtains the total number of wells of the analog circuit and the number of components sharing the first well according to the netlist file, wherein the number of components sharing the first well is the largest among the wells (step S204 ).

[0068] In detail, the processor 120 determines the number of bounded-sliceline grid (BSG) cells based on the total number of wells (step S206), and determines the size of each BSG cell based on the number of components sharing the first well (step S208). In this article, the number of BSG cells may not be less than the total number of wells. In an exemplary embodiment, the length (expressed as the number of BSG cells in the horizontal direction) and width (expressed as the number of BSG cells in the vertical direction) of each BSG cell can be determined based on the square root of the maximum number of components plus a constant to avoid wasting too much unnecessary memory space, but the present application is not limited in this regard. Different grid structures can be formed by merging BSG cells in different arrangements (in terms of the relative positions of the BSG cells). Therefore, the training process for determining the optimal component placement scheme can be based on the grid structure by using a reinforcement learning model including an actor model and a critic model. The training process includes: placing each component block of multiple components of the analog circuit in one grid structure among multiple grid structures; after all multiple components are placed in the used grid structure, changing the used grid structure to an unused grid structure; and repeatedly performing the following steps: placing each component block of the multiple component blocks in another grid structure formed by merging the multiple BSG units in a different arrangement from the first.

[0069] For a simple and clear introduction, the following steps S210 and S212 are described as steps in the training process. The processor 120 can place a first component block among the multiple component blocks in a first grid structure to form a first placement scheme by using a reinforcement learning model, and the first grid structure is composed of multiple BSG units merged in a first arrangement (step S210), and the processor 120 can place multiple components of the analog circuit in another grid structure, and the other grid structure is composed of multiple BSG units merged in other arrangement forms different from the first arrangement form (step S212). In detail, the actor-critic model is a reinforcement learning model that combines a policy-based algorithm and a value-based algorithm. Under such a hybrid framework, the processor 120 can use the actor model to learn a strategy for making decisions, and use the critic model to evaluate the actions taken by the actor model, thereby effectively searching for component placement positions of the analog circuit.

[0070] For better understanding, Figure 3A schematic diagram and an embodiment of a method for learning-based automatic component placement for analog circuits according to an exemplary embodiment of the present application are shown, and Figure 3 The method can also be Figure 1 The electronic device 100 is shown as an implementation.

[0071] Please also refer to Figure 3 and Figure 1 , similar to Figure 2 In step S202 to step S210, the processor 120 obtains the netlist file 310 of the analog circuit containing the components, thereby obtaining the total number of wells W of the analog circuit accordingly. total and the number of components sharing the first well WD max The processor will be based on the total number of wells W total Determine the number of BSG units BSG' num , and according to the number of components sharing the first well WD max Determine the size of each BSG unit BSG' size , and further creating a grid structure 330 by merging the BSG cells 320 .

[0072] Next, the processor 120 generates node embedding information corresponding to the component blocks based on the netlist file 310, where each component block is a component of the analog circuit or a combination of at least two components. The processor 120 generates multiple node embedding information by using an inductive representation learning model, such as a Graph Sampling and Aggregation (Graph SAGE) model. The processor 120 inputs the node embedding information into the actor model 370 and the critic model 380 respectively. The combination of the actor model 370 and the critic model 380 can be a reinforcement learning model with two hidden layers. Assume that the dimension of the node embedding information of each component is set to 128. The number of hidden layers of the actor model 370 and the critic model 380 can be (128, 128) and (128, 64), respectively.

[0073] Processor 120 generates a plurality of actions as outputs of actor model 370 in response to first node embedding information 360 in the node embedding information, wherein first node embedding information 360 corresponds to a first component block among a plurality of component blocks of the analog circuit and is an input to actor model 370. Processor 120 selects a first action from the generated actions based on component placement requirements 375 for placing the first component block in the grid structure, wherein the first action indicates a grid position of grid structure 320 (e.g., in this case, the first action is 7). Next, processor 120 may generate a reward corresponding to a first placement plan, the first placement plan being formed in response to placing the first component block according to the first action, wherein the reward is a function of the entire placement area of ​​the analog circuit and the half-perimeter wirelength (HPWL) of the entire placement area of ​​the analog circuit. The reward is updated each time a component is placed.

[0074] In an exemplary embodiment, the reward rt for the current state can be expressed as follows:

[0075]

[0076] Among them D a Indicates the layout area, N HPWL Indicates HPWL, P w Indicates the width of the layout area, P l Indicates the length of the layout area, N n represents the number of connecting lines, and (x, y) is the grid position indicated by the first action in the coordinate system.

[0077] On the other hand, the processor 120 will generate a first expected value as an output of the critic model 380, wherein the first expected value is about a current state, which represents the current placement plan before the first component block is placed in the first grid structure according to the first action. It should be noted that in the training process using the actor model 370 and the critic model 380, the term "state" is used to represent the placement environment, which is also regarded as a placement plan. The initial state s0 when starting to place components is a random distribution of components in the preconfigured grid structure. In addition, the processor 120 will generate a second expected value as another output of the critic model 380, wherein the second expected value is about a new state adjacent to the current state, and the new state represents the first placement plan formed in response to the first component block having been placed in the first grid structure according to the first action. The processor 120 will calculate the temporal difference error TD based on the reward, the first expected value and the second expected value. error .

[0078] Next, the processor 120 will calculate the time difference error TD error The proximal policy optimization algorithm is used to update the parameters of the actor model 370. In an exemplary embodiment, the actor model 370 can calculate the loss function as follows:

[0079]

[0080] Here, p θ (a t |s t ) indicates relative to the current state s t Select action a t The probability of is the time difference error TD error Next, the processor 120 sets the current state s t Change to new state t+1 Time difference error TD error It can be expressed as follows:

[0081] TD error =α*(r t +γq t+1 -q t )

[0082] Here, r t represents the current reward, q t Indicates the current state s t The expected value, q t+1 Represents the new state s t+1 α is the convergence constant, and γ is the decay constant between 0 and 1.

[0083] Next, the processor 120 updates the parameters of the critic model 380 according to the time difference error, the first expected value, and the second expected value. In an exemplary embodiment, the critic model 380 may calculate a loss function as follows:

[0084] Critic loss =(TD error +q θ (s t , a t )-q θ′ (s t ,a t )) 2

[0085] Here, q θ (a t , s t ) represents the first expected value, and q θ′(a t , s t ) represents the second expected value.

[0086] It should be noted that the processor 120 will use the expected value q t and reward r t Calculate the loss function of the actor model 370 and slowly and incrementally update the parameters in the actor model 370 and the critic model 380 to minimize the temporal difference error TD error .

[0087] Processor 120 processes the remaining node embedding information in a manner similar to the first node embedding information. Here, processor 120 sequentially inputs the node embedding information into actor model 370 and critic model 380 based on placement priority, which is determined based on the importance of the analog circuit's component blocks. For example, the placement priority, from highest to lowest, could be: differential pair, op amp current mirror, bias current mirror, capacitor, and other components. Furthermore, among components or component blocks with the same placement priority, the component or component block with the largest area is placed first.

[0088] Additionally, the aforementioned component placement requirement 375 may be a well island requirement, a proximity requirement, and a symmetrical island requirement.

[0089] The well island requirement allows components of the same MOS type to be assigned to the same BSG cell, so each BSG cell is considered independent and processed sequentially.

[0090] The proximity factor allows components in a close component group to be assigned to be placed close to each other. Figure 4A ), the processor 120 can select component D1 from the close component group and place it in the grid structure 430A, use the Breath-First Search algorithm to search the surrounding positions around component D1, remove non-empty positions and decide the remaining components D2, component D3, component D4... that need to be placed, and repeat the above steps until all components in the close component group are placed.

[0091] The symmetrical island requirement allows components in a symmetrical component group to be placed close to each other and symmetrically. Figure 4B), the processor 120 may determine the axis of symmetry AX and its direction (vertical or horizontal) so that the components in the symmetry group have a common axis of symmetry. For all component pairs (Dx, Dx') of (D1, D1'), (D2, D2'), (D3, D3'), (D4, D4'), ..., the processor 120 first places the component Dx in the grid structure 430B in the same manner as the technique proposed in the proximity requirement. The processor 120 then places the component Dx' at a position symmetrical to the component Dx about the axis of symmetry.

[0092] Figure 5 A flow chart illustrating a training process for automatic component placement of analog circuits according to an exemplary embodiment of the present application is shown, wherein Figure 5 The steps can be Figure 1 The electronic device 100 is shown as an implementation. Figure 5 Shows the inclusion Figure 2 and Figure 3 The training process of the process.

[0093] Please also refer to Figure 5 and Figure 1 , the processor 120 will randomly generate an initial state S0 when the components begin to be placed, which is a random assignment of the positions of the components in the preconfigured grid structure. Figure 5 Components (or component blocks) of the same MOS type among components (or component blocks) D1 to D6, components D1', and components D2' are shown to be assigned to the same BSG cell to ensure well island formation. For example, components D1 and D1' having the same MOS type, as well as components D2 and D2' having the same MOS type, are assigned to BSG cell 610, and components D5 and D6 having the same MOS type are assigned to BSG cell 620.

[0094] Next, the processor begins the training process using a reinforcement learning model comprising an actor model and a critic model by selecting components to be placed from component D1, component D1', component D2, and component D2' based on the placement priority. For example, the processor first selects component D1, and the node embedding information of component D1 is input into the reinforcement model to determine a selected action, which results in a new position for component D1 in the placement plan for the initial state S0. In response to component D1 being placed, another placement plan is formed for state S1 that is different from the placement plan for the initial state. Next, the processor 120 selects component D1' to be placed based on the placement priority, and the node embedding information of component D1' is input into the reinforcement model to determine a selected action, which results in a new position for component D1' in the placement plan for state S1, and the state transitions to state S2. When components D1, D2, D1', and D2' are all placed, the processor 120 places components in another identical well until components D1 through D6, D1', and D2' are all placed. The details of the reinforcement learning model and placement priority have been provided in the previous exemplary embodiments and, therefore, are omitted here for simplicity.

[0095] After components D1 through D6, D1', and D2' are all placed in the preconfigured grid structure consisting of BSG cells 610 through 640 merged in the first arrangement, processor 120 counts how many times full placements have been performed (i.e., all components have been placed), denoted as k, and determines whether k is less than a predetermined number, denoted as N (e.g., 15,000). If the number of full placements has not reached the predetermined number (N), processor 120 may generate another initial state representing another random allocation of component positions in the same preconfigured grid structure, return to the new initial state, and perform full placements in a similar manner until the number of full placements reaches the predetermined number (N). After reaching the predetermined number (N), processor 120 changes to an unused grid structure consisting of BSG cells 610 through 640 merged in a second arrangement different from the first arrangement, and processor 120 performs the training process in a similar manner until all optional arrangements of the grid structure have been used in the training process. Alternatively, processor 120 can record the maximum reward in real time. For example, processor 120 can compare each current reward with the maximum reward stored in a register and rewrite the register only when the current reward is greater than the reward stored in the register. Processor 120 also records the placement solution that achieved the maximum reward. In this way, after the training process is fully completed, the optimal component placement solution is determined.

[0096] It should be noted that due to the characteristics of the BSG structure, even if the placement on the BSG structure is symmetrical, it may not be satisfied after compression. Therefore, according to the exemplary embodiment of the present application, Figures 6A to 6C The schematic diagram shows a symmetric island refinement algorithm. The symmetric island refinement algorithm is used to adjust the optimal component placement solution determined through the training process. In an exemplary embodiment, the symmetric island refinement algorithm includes a symmetric island compression algorithm and a symmetry axis alignment algorithm.

[0097] exist Figure 6A In , for each symmetric component group G, the processor 120 will find the symmetry axis of each symmetric pair (Dx, Dx'), where the direction can be vertical or horizontal. Figure 6B In the example, the processor 120 divides each symmetric component group G into two categories g r and g c . This article, g r Indicates that the components are in the same row, g c Indicates that components are in the same column.

[0098] Next, in the symmetric island compression step, for each g r , the processor 120 will select the intermediate component as the target component. Figure 6C In the step, if the component is on the left side of the target component, the processor 120 will move the component to the right, and vice versa. In this step, the processor 120 will ensure that there is no overlap between the components.

[0099] Next, in the symmetry axis alignment step, since all components in the symmetric component group G are close to each other after compression, the processor 120 will calculate the r , select the largest symmetry axis as the common symmetry axis of g, and align the remaining symmetry axes with the common symmetry axis.

[0100] It should also be noted that in one exemplary embodiment, the processor 120 may be Figure 2 or Figure 3 Prior to the process in step 1, a user-specified requirement regarding the length of the analog circuit layout area and / or a requirement regarding the width of the analog circuit layout area is received.

[0101] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present application. In view of the foregoing, it is intended that the present application encompasses modifications and variations of the present application that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for learning-based automatic component placement for analog circuits, comprising: Acquire a netlist file of an analog circuit including a plurality of components, wherein the netlist file defines basic information describing each of the plurality of components and includes a name and size of a connection net of the component; Obtaining, according to the netlist file, a total number of multiple wells of the analog circuit and a number of components sharing a first well, wherein the number of components sharing the first well is the largest among the multiple wells; determining a number of a plurality of bounded slice grid (BSG) cells based on the total number of the plurality of wells; determining a size of each bounded slice line grid cell in the plurality of bounded slice line grid cells based on the number of components sharing the first well; as well as A training process is performed to determine an optimal component placement solution using a reinforcement learning model comprising an actor model and a critic model, wherein the training process comprises: placing first component blocks of the plurality of components in a first grid structure to form a first placement scheme by using the reinforcement learning model, the first grid structure being composed of the plurality of bounded slice line grid cells merged in a first arrangement, wherein each component block of the plurality of components is one component or a combination of at least two components; as well as The plurality of components of the analog circuit are placed in another grid structure composed of the plurality of bounded slice line grid cells merged in an arrangement different from the first arrangement. 2 . The method for learning-based automatic component placement for analog circuits according to claim 1 , wherein the number of the plurality of bounded slice line grid cells is not less than the total number of the plurality of wells.

3. The method for learning-based automatic component placement for analog circuits according to claim 1 , further comprising: A plurality of node embedding information respectively corresponding to a plurality of component blocks of the analog circuit is generated according to the netlist file, wherein each of the plurality of component blocks is a component or a combination of at least two components of the analog circuit. 4 . The method for learning-based automatic component placement for analog circuits according to claim 3 , wherein the plurality of node embedding information is generated by using an inductive representation learning model.

5. The method for learning-based automatic component placement for analog circuits according to claim 1 , wherein the step of placing the first component blocks of the plurality of components in the first grid structure by using the reinforcement learning model comprises: generating a plurality of actions as outputs of the actor model in response to first node embedding information among a plurality of node embedding information as inputs of the actor model, wherein the first node embedding information corresponds to the first component block; selecting a first action from the plurality of actions based on at least one placement requirement for placing the first component block in the first grid structure, wherein the first action indicates a grid position of the first grid structure; and A reward corresponding to the first placement scheme formed in response to placing the first component piece according to the first action is generated. 6 . The method for learning-based automatic component placement for analog circuits according to claim 5 , wherein the reward is a function of a placement area of ​​the analog circuit and a half-circumference length of the placement area.

7. The method for learning-based automatic component placement for analog circuits according to claim 5, wherein the step of placing the first component blocks of the plurality of components in the first grid structure by using the reinforcement learning model comprises: generating a first expected value as an output of the critic model, wherein the first expected value is about a current state representing a current placement solution before placing the first component block in the first grid structure according to the first action; as well as A second expected value is generated as another output of the critic model, wherein the second expected value is about a new state immediately adjacent to the current state, and the new state represents the first placement solution formed in response to the first component block having been placed in the first grid structure according to the first action.

8. The method for learning-based automatic component placement for analog circuits according to claim 7 , wherein the step of placing the first component blocks of the plurality of components in the first grid structure by using the reinforcement learning model further comprises: A time difference error is calculated based on the reward, the first expected value, and the second expected value.

9. The method for learning-based automatic component placement for analog circuits according to claim 8, wherein the step of placing the first component blocks of the plurality of components in the first grid structure by using the reinforcement learning model further comprises: updating the parameters of the actor model using a proximal strategy optimization algorithm according to the time difference error; as well as The parameters of the critic model are updated according to the time difference error, the first expected value and the second expected value.

10. The method for learning-based automatic component placement for analog circuits according to claim 1 , wherein the step of placing the first component blocks of the plurality of components in the first grid structure by using the reinforcement learning model comprises: First node embedding information is input into the actor model and the critic model according to a placement priority, wherein the placement priority is determined according to the importance of multiple component blocks of the analog circuit, wherein each of the multiple component blocks is a component or a combination of at least two components of the analog circuit, and the first node embedding information corresponds to the first component block.

11. A method for learning-based automatic component placement for analog circuits according to claim 10, wherein the placement priority among the component blocks of the analog circuit is differential pairs higher than operational amplifier current mirrors, higher than bias current mirrors, higher than capacitors, higher than other components, and wherein the component or component block with the largest area among components or component blocks with the same placement priority is placed first.

12. The method for learning-based automatic component placement for analog circuits according to claim 5, wherein the at least one component placement requirement comprises a well island requirement that allows components of the same MOS type to be assigned to the same bounded slice line grid cell.

13. The method for learning-based automatic component placement for analog circuits according to claim 5, wherein the at least one component placement requirement includes a proximity requirement that allows components in a group of proximate components to be assigned to be placed proximate to each other.

14. The method for learning-based automatic component placement for analog circuits according to claim 5, wherein the at least one component placement requirement comprises a symmetric island constraint that allows components in a symmetric component group to be placed close to each other and symmetrically.

15. The method for learning-based automatic component placement for analog circuits according to claim 1, further comprising: The optimal component placement scheme is adjusted based on a symmetric island refinement algorithm including a symmetric island compression algorithm and a symmetric axis alignment algorithm.

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