Digital circuit wiring method and related equipment

Abstract

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit wiring method and related equipment. The method comprises the steps that wiring grid parameters of all wiring layers in a digital circuit to be wired are acquired, and grid lines of a wiring grid are used for restraining a wiring track; on the basis of the wiring grid parameters, the digital circuit is divided into a plurality of wiring subareas, and the area size of each wiring layer in each wiring subarea is different; traversing each signal path, and determining an access point for performing wiring indexing on each signal path; based on the access points of the signal paths in the wiring partitions, wiring the signal paths in the wiring partitions in parallel through wiring threads respectively configured for the wiring partitions; and combining the wirings of the signal paths in the wiring partitions to obtain a complete wiring of the digital circuit. According to the technical scheme provided by the invention, the wiring efficiency of the digital circuit can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor design automation technology, and in particular relates to a digital circuit wiring method and related equipment. Background Art

[0002] With the rapid development of semiconductor technology, the scale and complexity of digital circuits (such as digital integrated circuits) are constantly increasing, which makes wiring a crucial link in the field of semiconductor design automation (Electronic Design Automation, EDA).

[0003] FinFET processes, due to multiple masks, diverse metal line widths, highly irregular logic cell pin shapes, and the presence of FinTracks (transistor fin-shaped channel tracks), significantly complicate routing design rules (such as Metal Spacing, MinStep, and End of Line). On the same routing layer, it's difficult to standardize grid parameters, line widths, and trace density across different regions, increasing the pressure on routing DRC (Design Rule Check) convergence and leading to low routing efficiency for digital circuits. Therefore, improving routing efficiency for digital circuits has become a pressing technical challenge. Summary of the Invention

[0004] The embodiments of the present application provide a digital circuit wiring method, apparatus, computer program product, computer-readable storage medium, and electronic device, which can improve the wiring efficiency of digital circuits to a certain extent.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0006] According to a first aspect of an embodiment of the present application, a digital circuit routing method is provided, the method comprising: obtaining routing grid parameters of each routing layer in a digital circuit to be routed, wherein the grid lines of the routing grid are used to constrain routing tracks; based on the routing grid parameters of each routing layer, dividing the digital circuit into multiple routing partitions, wherein the area sizes of each routing layer in each routing partition are different; traversing each signal path to determine an access point of each signal path, wherein the access point is used to perform routing indexing on each signal path; based on the access point of the signal path in each routing partition, routing the signal paths in each routing partition in parallel by using routing threads respectively configured for each routing partition; merging the routing of the signal paths in each routing partition to obtain a complete routing of the digital circuit.

[0007] In some embodiments of the present application, based on the aforementioned scheme, the wiring grid parameters include a grid spacing, and the wiring grid parameters based on each wiring layer are used to divide the digital circuit into multiple wiring partitions, including: traversing each wiring layer, dividing each wiring layer into multiple wiring layer areas, the length and width of each wiring layer area are integer multiples of the grid spacing of each wiring layer, and the number of wiring layer areas of each wiring layer is the same as the number of wiring partitions; defining a set of wiring layer areas of each wiring layer that are opposite to each other in the vertical direction as a wiring partition, and obtaining the multiple wiring partitions.

[0008] In some embodiments of the present application, based on the aforementioned scheme, the access points include original access points and temporary access points, and determining the access points of each signal path includes: obtaining a pre-set original access point on each signal path; and setting a temporary access point on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition.

[0009] In some embodiments of the present application, based on the aforementioned solution, each signal path includes a metal pin, which is used to send and / or receive signals; and setting a temporary access point on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition includes: if any metal pin on each signal path spans multiple wiring partitions, and any metal pin does not have an original access point set in any of the multiple wiring partitions spanned by it, then setting a first temporary access point on the any metal pin, where the first temporary access point falls within the any wiring partition.

[0010] In some embodiments of the present application, based on the aforementioned scheme, after setting the first temporary access point on any one of the metal pins, the method further includes: generating a virtual through hole for the any one of the metal pins at the first temporary access point based on the through hole design rules defined in the basic process database; calling a violation detection engine to detect whether the virtual through hole generates a violation; if the virtual through hole does not generate a violation, determining an evaluation prediction value of the first temporary access point, the evaluation prediction value being used to characterize the probability that the first temporary access point will not be selected in the future actual wiring process.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the method further includes: if the virtual through hole generates a violation, based on the through hole design rule, generating a virtual metal line for the virtual through hole in the target wiring layer, the target wiring layer being the next wiring layer of the wiring layer where the virtual through hole is located, and the projection of the virtual metal line in the vertical direction is surrounded by the projection of any one of the metal pins in the vertical direction.

[0012] In some embodiments of the present application, based on the aforementioned scheme, a temporary access point is set on each signal path according to the distribution characteristics of the original access points of each signal path in each wiring partition, including: if any two adjacent original access points on each signal path fall into two wiring partitions respectively, then determine the boundary line of the wiring layer where the any two original access points are located between the two wiring partitions; set a second temporary access point at the intersection of the guide line connecting the any two original access points and the boundary line, the second temporary access point being used to eliminate violations generated when wiring each signal path separately in the two wiring partitions.

[0013] In some embodiments of the present application, based on the aforementioned scheme, after setting a second temporary access point at the intersection position of the guide line connecting any two original access points and the dividing line, the method further includes: generating a virtual metal line at the second temporary access point based on the metal line design rules defined in the basic process database; calling a violation detection engine to detect whether the virtual metal line generates a violation; if the virtual metal line generates a violation, generating a new second temporary access point at a position on the dividing line that is separated from the intersection position by the grid spacing, and returning to execute the step of generating a virtual metal line at the second temporary access point until the virtual metal line generates no violation.

[0014] In some embodiments of the present application, based on the aforementioned scheme, the signal paths in each wiring partition are routed in parallel based on the access points of the signal paths in each wiring partition through the wiring threads respectively configured for each wiring partition, including: configuring a wiring thread for each wiring partition; based on the original access points and temporary access points of each signal path in each wiring partition, calling the wiring engine through the wiring thread to route the signal paths falling into each wiring partition, and calling the violation detection engine to detect whether the routing of the signal paths in each wiring partition generates violations; if the routing of the signal paths in each wiring partition generates violations, the routing that generates violations is removed and re-routed; when all signal paths falling into each wiring partition are routed and no violations are generated, the routing of the signal paths in each wiring partition is terminated.

[0015] In some embodiments of the present application, based on the aforementioned scheme, the merging of the wiring of the signal paths in each wiring partition includes: traversing each signal path in the digital circuit, deleting the invalid wiring generated by the temporary access point in each signal path, and merging the wiring of each signal path in different wiring partitions; calling the violation detection engine to detect whether the wiring of each signal path generates a violation; if the wiring of each signal path generates a violation, removing the wiring of each signal path and rewiring until the wiring of each signal path generates no violation.

[0016] According to a second aspect of an embodiment of the present application, a digital circuit routing device is provided, the device comprising: an acquisition unit for acquiring routing grid parameters of each routing layer in a digital circuit to be routed, wherein the grid lines of the routing grid are used to constrain routing tracks; a segmentation unit for segmenting the digital circuit into a plurality of routing partitions based on the routing grid parameters of each routing layer, wherein the area sizes of each routing layer in each routing partition are different; a determination unit for traversing each signal path and determining an access point of each signal path, wherein the access point is used to perform routing indexing on each signal path; a routing unit for routing the signal paths in each routing partition in parallel based on the access points of the signal paths in each routing partition through routing threads respectively configured for each routing partition; and a merging unit for merging the routing of the signal paths in each routing partition to obtain a complete routing of the digital circuit.

[0017] According to a third aspect of an embodiment of the present application, a computer program product is provided, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device having the processor executes to implement the operations performed by the method described in the first aspect above.

[0018] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one computer program instruction is stored. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the method described in the first aspect above.

[0019] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising one or more processors and one or more memories, wherein at least one computer program instruction is stored in the one or more memories, and the at least one computer program instruction is loaded and executed by the one or more processors to implement the operations performed by the method described in the first aspect above.

[0020] Based on the technical solution proposed in this application, by introducing the concept of parallel routing within routing partitions, the overall efficiency of digital circuit routing can be significantly improved. First, the grid parameters of each routing layer are used to divide the circuit to be routed into several routing partitions that adapt to physical characteristics and have adjustable area sizes, thereby achieving regional resource management. This partitioning method fully considers the size differences between different routing layers in different areas, making the partitions more suitable for actual design needs and optimizing the routing difficulty distribution from the source. Secondly, within each routing partition, by traversing all signal paths and accurately defining access points as indexes for routing tasks, the routing engine can greatly improve its focus on signal paths, which is beneficial for ensuring the performance and reliability of critical signal paths. Furthermore, by assigning independent routing threads to each routing partition, parallel routing within multiple routing partitions is supported on multi-core or multi-processor platforms. This can greatly improve resource utilization and routing speed, effectively reducing the overall design cycle. In addition, based on partition-level routing, by efficiently merging and resolving conflicts between routing results of cross-region signal paths, seamless integration of global routing is achieved, avoiding process and rule violations that may be caused by partition boundaries. The combination of this series of measures enables this method to not only improve the concurrency and automation of digital circuit routing, but also enhance the convergence efficiency and design quality of the final physical implementation, greatly meeting the actual needs of large-scale complex circuits in terms of design cycle, reliability and performance, and has outstanding technical application value.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings: Figure 1 A flow chart of a digital circuit wiring method according to an embodiment of the present application is shown; Figure 2 A schematic diagram of wiring partitioning of each wiring layer in a digital circuit according to an embodiment of the present application is shown; Figure 3 shows a partial perspective view of a digital circuit according to an embodiment of the present application; Figure 4 shows a partial top view of each wiring layer in a digital circuit according to an embodiment of the present application; Figure 5 shows a partial cross-sectional view of a digital circuit according to an embodiment of the present application; Figure 6 A block diagram of a digital circuit wiring device in an embodiment of the present application is shown; Figure 7 A schematic structural diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0025] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should also be noted that in the accompanying drawings, certain components that do not affect the explanation of the technical solutions of this application have been omitted for clarity.

[0026] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0027] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] In order to enable those skilled in the art to better understand this application, the technical concepts and application background involved in this application are first briefly explained.

[0029] Digital Circuit (DC): A digital circuit is an electronic circuit that uses digital signals (i.e., signals that take on a finite number of discrete values, typically "0" and "1") as information carriers, processing, transmitting, and storing information through electronic devices such as logic gates. Based on Boolean algebra, digital circuits can perform various logical and arithmetic operations, data storage, and control functions, and are a core component of modern computer, communications, and automatic control systems.

[0030] Digital Circuit Routing (DCR): Digital circuit routing usually refers to the process of connecting various functional units, logic gates, and circuit blocks inside a chip (such as FPGA, CPU, GPU, etc.) through metal wires according to design requirements.

[0031] Signal paths include timing paths and logic paths. A signal path refers to the path a signal takes through a series of logic gates and connections from its starting point (usually the output of a timing trigger, such as a register, flip-flop, or latch) to its destination (usually the input or output of the next register, flip-flop, or latch). A logic path follows the logic structure within a digital circuit, starting from a signal source (such as an input pin, the output of a previous logic gate, or a register output), passing through several logic gates (such as AND gates, OR gates, and NOT gates) and their connections, and ultimately reaching the destination node (such as a logic gate input, output pin, or register input). The logic path focuses on the implementation of circuit functionality, ensuring that signals are correctly transmitted and processed according to design intent. Unlike a timing path, a logic path does not necessarily include clock constraints, but it reflects the logical connections between various units within the circuit and is a crucial foundation for implementing and verifying the functional integrity of the circuit.

[0032] Metal Pin: Metal pin refers to the metal contact area exposed at the layout level of functional blocks such as standard cells, macro cells, IP cores in digital circuits, which is used to achieve electrical connection with external metal interconnections.

[0033] With the rapid development of semiconductor technology, the scale and complexity of digital circuits are constantly increasing, making routing a crucial step in semiconductor design automation. In FinFET processes, routing design rules (such as Metal Spacing, MinStep, and End of Line) are significantly complex due to multiple masks, varying metal line widths, highly irregular logic cell pin shapes, and the presence of FinTracks (transistor fin-shaped channel tracks).

[0034] In the process of implementing digital circuit routing, most existing mainstream EDA tools use a grid-based routing method to discretize the routing space into controllable grid tracks. However, the complexity of the routing space and the diversity of routing requirements, especially in a multi-layer routing structure, often result in different grid parameters and constraint rules for different routing layers, making routing space subdivision and resource scheduling difficult. What's more serious is that these violations caused by inaccurate virtual access points are often formed in the early stages of merging partition routing and full-chip, but are not discovered until the later unified DRC check, at which time large-scale rewiring and repair are required, resulting in low routing efficiency of digital circuits. In this case, the present application proposes a digital circuit routing solution to improve the routing efficiency of digital circuits.

[0035] The following describes the implementation details of the technical solution of the embodiment of the present application: Reference Figure 1 , shows a flow chart of a digital circuit wiring method in an embodiment of the present application, which can be executed by a device with a computing and processing function. Figure 1 As shown, the digital circuit wiring method includes at least steps 110 to 170, which are described in detail as follows: Reference Figure 1 In step 110, the routing grid parameters of each routing layer in the digital circuit to be routed are obtained, wherein the grid lines of the routing grid are used to constrain the routing track.

[0036] In modern FinFET and high-end processes, due to the complexity of the manufacturing process, the wiring grid parameters of different metal layers in the chip are often different. Therefore, it is necessary to obtain grid parameters for each wiring layer separately to avoid wiring violations and mismatches caused by a one-size-fits-all approach.

[0037] In the present application, the wiring grid parameters may include a grid spacing, ie, the physical distance between two adjacent grid lines, which is a key parameter that determines wiring density and reliability.

[0038] In the present application, the wiring grid parameters may further include the physical coordinates of the grid lines. The physical coordinates of the grid lines may be used to locate the specific position of each wiring track on the X-axis and Y-axis, as well as the number of wiring layers on which the wiring track is located. The wiring grid parameters may further include the grid coordinates of the grid lines. The grid coordinates may be used to locate the grid order of each wiring track on the X-axis and Y-axis, as well as the number of wiring layers on which the wiring track is located.

[0039] In the present application, the routing grid parameters may further include grid starting coordinates, allowed routing directions, and the number / distribution of grid lines.

[0040] In this application, the grid lines of the routing grid can be used to constrain the routing track, that is, all automatic routing engines and manual planning must refer to the grid line position and cannot deviate from the track for routing. This can effectively avoid process problems such as metal short circuits and distance violations caused by "drift". In addition, in the subsequent process of splitting the routing partitions, the routing layer area of ​​each routing layer in the routing partition can be physically divided based on the grid, so that the subsequent partition routing is consistent with the actual process data.

[0041] Continue to refer to Figure 1 In step 120, the digital circuit is divided into a plurality of wiring partitions based on the wiring grid parameters of each wiring layer, wherein the area size of each wiring layer in each wiring partition is different.

[0042] In order to make those skilled in the art better understand the multiple wiring partitions of the digital circuit in this application, the following will be combined with Figure 2 A specific embodiment is used for description.

[0043] See also Figure 2 , shows a schematic diagram of wiring partitioning of each wiring layer in a digital circuit according to an embodiment of the present application.

[0044] like Figure 2 As shown, the digital circuit 100 includes multiple wiring layers from bottom to top, such as a polysilicon layer ploy, a via layer V1, a metal layer M1, a via layer V2, and a metal layer M2.

[0045] It should be noted that, in this application, the polycrystalline silicon layer (poly layer) is a thin film material composed of many tiny silicon grains and is a common structural layer in integrated circuit manufacturing. Polycrystalline silicon layers are primarily used as gate materials for MOS transistors, but can also serve as doped diffusion layers for source and drain electrodes, and even for local wiring. In the manufacturing process, polycrystalline silicon is first deposited on a silicon oxide substrate, and then the desired pattern is formed through photolithography and etching techniques. Its conductivity is between that of single-crystalline silicon and amorphous silicon, making it easy to control doping in subsequent processes.

[0046] In integrated circuit manufacturing, metal layers are conductive layers used for large-scale horizontal routing, enabling signal and power transmission between circuit elements. Primarily made of aluminum (Al) or copper (Cu), metal layers typically serve as the primary wiring medium for circuits, carrying electrical signals, distributing power and ground lines, and so on. In modern IC designs (particularly those in CMOS and FinFET processes), metal layers can comprise dozens of layers, creating complex and dense signal and power networks. Generally, the first metal layer is called "Metal 1" (M1), the second "Metal 2" (M2), and so on (M3, M4, etc.).

[0047] A via layer is a layer used to connect different metal layers in the integrated circuit manufacturing process. It typically consists of small holes (vias) opened in an insulator (such as SiO2) and then filled with metal material to achieve electrical connection. Modern ICs often have multiple layers of metal wiring, with each metal layer separated by an insulating layer. The via layer allows signals to penetrate the insulator from one metal layer and connect vertically to the upper or lower metal layer, achieving vertical conduction (electrical connection) across the chip. For example, "V1" represents a via between metal 1 and metal 2, "V2" represents a via between metal 2 and metal 3, and so on.

[0048] In general, the polysilicon layer is used for device structure, the metal layer is responsible for horizontal wiring, and the via layer realizes vertical connectivity between the metal layers.

[0049] Further, such as Figure 2 As shown, each wiring layer is divided into 9 areas by wiring partitions K1 to K9, and the area size of each wiring layer in each wiring partition is different.

[0050] Specifically, in the present application, the digital circuit is divided into a plurality of wiring partitions based on the wiring grid parameters of each wiring layer, and can be performed according to the following steps 121 to 122: Step 121, traverse each wiring layer and divide each wiring layer into multiple wiring layer areas, the length and width of each wiring layer area are integer multiples of the grid spacing of each wiring layer, and the number of wiring layer areas of each wiring layer is the same as the number of wiring partitions.

[0051] Step 122 : defining a set of wiring layer regions that are opposite to each other in the vertical direction of each wiring layer as a wiring partition, thereby obtaining the plurality of wiring partitions.

[0052] In this application, it is important to note that for non-FinFET processes, since the wiring grid parameters (such as grid spacing and starting point coordinates) of the wiring layers are unified in the design rules, the grid spacing and coordinates of the first wiring layer can be directly used as the basis for the wiring partitions of all wiring layers. This way, the wiring partition sizes, boundaries, and division methods remain consistent across all wiring layers, greatly simplifying subsequent wiring processing.

[0053] However, under advanced processes such as FinFET, different wiring layers have their own independent wiring grid spacing, grid starting coordinates, and even special process restrictions. Therefore, for each wiring layer, each wiring layer can be divided into multiple wiring layer areas according to an integer multiple of its grid spacing. Specifically, each wiring layer can be traversed, and the starting grid of the wiring layer can be used as a reference point. A wiring layer area can be divided in the wiring layer every m grid spacings in the X-axis direction and every n grid spacings in the Y-axis direction (m and n are partition granularity parameters set by the user or algorithm, m and n can be different, such as m=4, n=6, or the same, such as m=n=5). Among them, the area range of each wiring layer area can be limited by the physical coordinates or grid coordinates of two relative corner points on the wiring layer area (such as the lower left corner and upper right corner of the wiring layer area, or the lower right corner and upper left corner of the wiring layer area).

[0054] In a preferred embodiment, the area of ​​each wiring layer region can be defined by the grid coordinates of two opposing corner points on the wiring layer region. This advantage lies in the simplicity and efficiency of grid coordinate representation and calculation, requiring far less data processing than directly using physical coordinates. In actual chip design and EDA implementation, the use of grid coordinates can significantly reduce memory usage and data transmission overhead, accelerate region location and determination, improve algorithm efficiency and scalability, and facilitate unified management and alignment of cross-layer regions, making it suitable for large-scale parallel processing of wiring partitions.

[0055] In this application, it is understood that the length and width of each wiring layer region can be an integer multiple of the grid pitch of each wiring layer. For example, if the grid pitch of the M1 metal layer is 0.1 μm (i.e., 100 nm), and if m=n=10000, then the size of a wiring layer region of the M1 metal layer is 1000 μm × 1000 μm.

[0056] In the present application, it is also necessary to explain that, for a same wiring layer, the area sizes of the multiple wiring layer areas divided therefrom may be the same or different.

[0057] In the present application, it should also be noted that the number of wiring layer regions of each wiring layer is the same as the number of the wiring partitions, so that each wiring layer can be divided into the same number of wiring layer regions.

[0058] Furthermore, after all wiring layers have completed their respective wiring layer area divisions, the wiring layer areas can be overlapped and combined along the vertical direction of the digital circuit (i.e., the Z axis) to obtain corresponding wiring partitions. Figure 2 As shown, for example, the set of K1 wiring layer areas of each wiring layer is a wiring partition, and the set of K2 wiring layer areas of each wiring layer is a wiring partition. Each wiring partition has corresponding wiring layer areas in all wiring layers.

[0059] Based on the technical solutions in steps 121 to 122 above, through the adaptive routing grid track division design, it is possible to achieve accurate segmentation of multi-level routing layer areas, which can effectively adapt to the complex situations such as multiple masks, FinTracks, and different routing layers in the FinFET process, thereby significantly reducing the probability of problems such as a surge in DRC violations and inaccurate routing path guidance caused by routing partitioning. First, in terms of refined physical alignment, the area division of each metal layer is based on its own routing grid parameters, ensuring the physical accuracy of the routing partition and improving the consistency of the routing layer area with the actual process layout, thereby avoiding violations and repair problems caused by cross-layer inconsistencies. Secondly, it can flexibly adapt to advanced processes with complex process parameters and strict rules such as FinFET, realize automatic adaptation of the entire process, and effectively reduce the probability of manual adjustment and rule conflicts. In addition, each routing partition after routing becomes the smallest unit of routing optimization and parallel processing, improving the parallelism and data isolation of tasks, thereby significantly accelerating the overall routing speed and improving resource utilization. Finally, through parameter setting, the division granularity of the wiring layer area can be flexibly adjusted, which facilitates the customization of the wiring partitioning strategy according to the chip scale and wiring complexity, and achieves more efficient and accurate wiring optimization.

[0060] Continue to refer to Figure 1In step 130, each signal path is traversed to determine an access point of each signal path, and the access point is used to perform routing indexing on each signal path.

[0061] In this application, an access point refers to a key node or port in a signal path. These typically correspond to registers, latches, input / output ports, or key nodes in the path. These points are typically the physical locations where signals enter or exit a logic unit. For example, an access point can be the starting point or end point of a signal path, as well as the data paths and control signal interfaces involved in the path.

[0062] In this application, the access point may include an original access point and a temporary access point. Specifically, the access point of each signal path may be determined by performing the following steps 131 to 132: Step 131: Acquire a preset original access point on each signal path.

[0063] Step 132 : Setting a temporary access point on each signal path according to the distribution characteristics of the original access points of each signal path in each wiring partition.

[0064] In this application, the so-called original access points refer to the key nodes on each signal path that are pre-defined in the process database or the early stage of chip design according to process rules and design specifications. These original access points usually include register input / output, module interfaces, input / output ports, etc. They are clearly defined at the layout and process level and have stable physical coordinates. The acquisition of original access points depends on the completeness and accuracy of the process database and is the basis for the physical marking of signal paths. By extracting the original access points associated with each signal path, a standard reference can be provided for subsequent wiring allocation.

[0065] In this application, since a signal path may span multiple wiring partitions during the actual wiring process, relying solely on the original access point will result in some unnecessary violations during the wiring process within a single wiring partition. Therefore, it is necessary to combine the spatial distribution characteristics of the original access points in each wiring partition to intelligently add temporary access points to the signal path. These temporary access points are not fixed, but are dynamically set based on the wiring layer area division, path length, congestion or physical distance. In this application, temporary access points can be set at the wiring partition boundary or wiring turning point to achieve efficient path connection and transition between multiple wiring partitions.

[0066] By combining original access points with temporary access points, complex global signal paths can be broken down into complete small paths within routing partitions, and indexed and optimized separately, effectively improving routing resource utilization, meeting the constraints of key signal paths, and significantly enhancing the adaptability of routing tools to large-scale, complex chip structures.

[0067] In the present application, each signal path includes a metal pin, which is used to send and / or receive signals. Specifically, each signal path includes a metal pin. These metal pins serve as the sending and / or receiving points of timing signals and are key nodes for signal transmission in the physical chip structure. In a complex chip layout, a metal pin (such as a long-distance bus or a cross-region network connection) may span multiple wiring partitions, and the original access point is generally only set in some partitions. In this case, relying solely on the original access point can easily lead to a lack of effective wiring anchor points in certain partitions, thereby affecting subsequent wiring partition optimization and timing convergence.

[0068] To solve this problem, this application proposes an intelligent dynamic generation mechanism for temporary access points. The specific implementation steps are as follows: In the present application, setting a temporary access point on each signal path according to the distribution characteristics of the original access point of each signal path in each wiring partition may be performed according to the following step 1321: Step 1321: If any metal pin on each signal path spans multiple routing partitions, and any metal pin does not have an original access point set in any of the multiple routing partitions it spans, a first temporary access point is set on the any metal pin, and the first temporary access point falls into the any routing partition.

[0069] Specifically, first, all metal pins on each signal path are detected to determine whether a metal pin spans multiple routing partitions. For metal pins detected to span multiple partitions, each routing partition covered by it is checked in turn to see if an original access point has been set. If it is found that the metal pin does not have an original access point in a routing partition it spans, it means that the partition lacks a positioning anchor point during subsequent routing processing, which may affect signal integrity and path optimization. In this case, a first temporary access point can be automatically set in the layout partition corresponding to the metal pin. The coordinates of this first temporary access point can be located at the intersection of the metal pin and the routing partition boundary or at a key layout point of the metal pin in the routing partition.

[0070] In order to make those skilled in the art better understand this application, Figures 3 to 5, explains how to set up temporary access points on the signal path from different perspectives. Figure 3 shows a partial perspective view of a digital circuit according to an embodiment of the present application; Figure 4 shows a partial top view of each wiring layer in a digital circuit according to an embodiment of the present application; Figure 5 A partial cross-sectional view of a digital circuit according to an embodiment of the present application is shown.

[0071] Reference Figures 3 to 5 The wiring partition boundary 101 divides the digital circuit 100 into wiring partition 1 and wiring partition 2. In the M1 metal layer (i.e., a wiring layer), a metal pin 104 spans wiring partition 1 and wiring partition 2. Metal pin 104 has an original access point T1 in wiring partition 1 but no original access point in wiring partition 2. Therefore, a first temporary access point F1 can be set on the metal pin 104 that falls into wiring partition 1.

[0072] In this application, by intelligently adding a first temporary access point to the metal pins that span multiple wiring partitions but lack access points, the spatial blind spots that the original access points on the metal pins cannot cover can be effectively filled, and reasonable anchor points can be assigned to the wiring layer areas of each wiring partition. This dynamic setting of temporary access points can ensure that each wiring partition has a clear goal when performing independent wiring optimization, timing analysis, and parallel processing, thereby improving the controllability and efficiency of physical implementation. For large-scale SoCs, complex heterogeneous integration, or long-distance cross-region signal transmission, this mechanism can greatly reduce the difficulty of cross-region wiring and the risk of timing violations, and also facilitate the wiring engine to reasonably split the global signal path according to the access point information, achieving a balance between local optimization and global coordination, and further improving the overall performance and yield of the chip.

[0073] Furthermore, in the present application, after the first temporary access point is set on any one of the metal pins, the following steps 1322 to 1325 may be performed: Step 1322 , generating a virtual through hole for the arbitrary metal pin at the first temporary access point based on the through hole design rule defined in the basic process database; Step 1323, calling a violation detection engine to detect whether the virtual via generates a violation; Step 1324: If the virtual via does not generate a violation, determine an evaluation prediction value of the first temporary access point, where the evaluation prediction value is used to represent the probability that the first temporary access point will not be selected in a future actual routing process.

[0074] Step 1325: If the virtual through hole generates a violation, a virtual metal line is generated for the virtual through hole in a target wiring layer based on the through hole design rule, and the target wiring layer is the next wiring layer of the wiring layer where the virtual through hole is located, and the projection of the virtual metal line in the vertical direction is surrounded by the projection of any one of the metal pins in the vertical direction.

[0075] In the routing process of the present application, after the first temporary access point is set on the metal pin, the feasibility of the temporary access point and the efficiency of routing implementation can be ensured by further virtual via generation and evaluation mechanisms based on process databases (such as TechDatabase) and via design rules (such as LEF58ENCLOSURE, etc.).

[0076] Specifically, after setting the first temporary access point on a metal pin, the corresponding virtual via can be generated based on the via generation rules in the process database, according to the specific location of the temporary access point, the actual geometric information of the metal pin, and the process constraints (including the layout of each metal layer, via size and metal enclosure requirements, etc.), such as Figures 3 to 5 The virtual via 105 is shown. This virtual via is only used for feasibility assessment, and represents the via structure that may be laid in the future actual wiring at this temporary access point.

[0077] Subsequently, the violation detection engine (i.e., the Design Rule Check (DRC) module) can be invoked to perform DRC validation (i.e., violation detection) on the virtual via's relationship to the existing wiring geometry in the layout, including but not limited to via spacing, distance to surrounding metal lines / pins, and coverage. This step can early identify whether the temporary access point, given the existing design resource distribution, poses a manufacturing conflict risk.

[0078] If the DRC check result is "No Violation" (i.e., the virtual via generates no violations), the temporary access point is usable, subject to process and layout rule constraints. At this point, an evaluation prediction value (DRC EVA) can be calculated for the temporary access point, taking into account factors such as local routing density and surrounding resource constraints. This value represents the probability of the temporary access point being selected by the routing engine during future physical routing. To control the probability of selection of the temporary access point, the evaluation prediction value can be set higher than that of other real physical access points. This ensures that the routing engine prioritizes the original access point and only considers the temporary access point when absolutely necessary, thereby enhancing routing robustness and global convergence.

[0079] If the DRC check result is "violation", it means that the temporary access point cannot be implemented in compliance with the wiring layer. In this case, the algorithm will not simply abandon the temporary access point, but will further generate a virtual metal line in the next wiring layer of the wiring layer where the through hole is located based on the through hole generation rules of the process database, such as Figures 3 to 5 The virtual metal line 106 is shown. The generation process ensures that the virtual metal line is completely vertically enclosed by the vertical projection of the original metal pin. This ensures both physical space for electrical connectivity and improved DRC compliance. For example, in advanced processes such as FinFET, unique enclosing rules such as LEF58ENCLOSURE must be followed to ensure that each endpoint meets coverage requirements, thereby avoiding gaps or violations caused by process specificities.

[0080] This application generates virtual vias on temporary access points and performs violation detection, combining evaluation prediction values ​​with a virtual metal line replacement mechanism to achieve dynamic prediction and optimization of the feasibility of physical routing anchor points, deeply integrating process manufacturability (DFM) with forward-looking verification of digital routing physical design, and effectively avoiding the risk of global signal path reconstruction due to anchor point failure in the later stage. By automatically optimizing violating access points, manual intervention can be reduced, and the efficiency and compliance of automated routing can be improved. Intelligent routing scheduling is achieved by using evaluation prediction values, so that temporary access points are only used as supplements when the original access points are unavailable, which can reduce the probability of iteration failure and rework. In addition, by synchronously updating the three-dimensional database, it can also ensure that all virtual structures can accurately participate in subsequent global routing and 3D integration, which helps to improve product yield and convergence speed, especially for multi-layer routing, complex SoC and highly integrated chip scenarios. Overall, this application deeply integrates the virtual through-hole legality evaluation, wiring priority adjustment, and cross-layer virtual metal generation mechanism under violations, realizing an efficient closed loop from metal pin shape, process rules to wiring point optimization, which can significantly improve the controllability, fault tolerance and global optimality of the wiring engine, thereby optimizing the reliability of chip design and production.

[0081] Furthermore, in the present application, the setting of temporary access points on each signal path according to the distribution characteristics of the original access points of each signal path in each wiring partition may also be performed according to the following steps 1326 to 1327: Step 1326: If any two adjacent original access points on each signal path fall into two wiring partitions respectively, determine the boundary line of the wiring layer where the two original access points are located between the two wiring partitions.

[0082] Step 1327 : Setting a second temporary access point at the intersection of the guide line connecting the two original access points and the boundary line, wherein the second temporary access point is used to eliminate violations generated when routing each signal path in the two routing partitions.

[0083] In this application, for the same signal path, if two adjacent original access points (i.e., critical routing anchor points) belong to different routing partitions, the boundary between the two routing partitions corresponding to the routing layers where these two original access points reside must be determined. This boundary serves as the physical and design rule interface for subsequent cross-partition physical connections.

[0084] A second temporary access point is dynamically generated at the intersection of the guide line connecting the two original access points and the dividing line. The main function of this temporary access point is to serve as an auxiliary anchor point when splicing routing partitions, and to eliminate DRC violations that may occur in cross-partition signal paths during the independent routing of each routing partition. In other words, because each routing partition in the distributed algorithm performs routing independently, cross-partition paths are prone to connectivity interruptions, non-compliance with physical rules, or other conflicts at the interface. The second temporary access point, by pre-determining its position and participating in routing, can effectively guide the subsequent routing algorithm, automatically open up connectivity at the routing partition boundary and avoid violations, thereby ensuring the correct splicing and global physical compliance of distributed parallel routing.

[0085] Please continue to refer to Figures 3 to 5 For example, for the original access point T2 and the original access point T3, which fall into the wiring partition 1 and the wiring partition 2 respectively, the wiring layer M2 where the original access point T2 and the original access point T3 are located can be determined to be at the boundary line 101 between the wiring partition 1 and the wiring partition 2, and then the second temporary access point F2 is set at the intersection of the guide line connecting the original access point T2 and the original access point T3 and the boundary line.

[0086] It should be noted here that if two adjacent original access points fall into two wiring partitions and are located in two different metal wiring layers. Figures 3 to 5 For the original access points T1 and T3 shown in the figure, the via 103 connected to the original access point T1 can be determined first (the via is connected to the metal wiring layer M2 where the original access point T3 is located). In this case, the second temporary access point F2 can be set at the intersection of the guide line connecting the via 103 and the original access point T3 and the boundary line.

[0087] In this application, it should also be noted that the generation of temporary access points is mainly used to assist distributed parallel routing, and they need to be merged and eliminated later. However, in the parallel routing process, in order not to change the logic of the original routing algorithm, these auxiliary temporary access points need to have corresponding through-hole shapes to match them, but this will bring about a large number of new DRC violations. Therefore, during the generation process, these temporary access points need to be DRC checked to ensure that the added auxiliary shapes do not bring additional DRC violations.

[0088] Specifically, in the present application, after setting the second temporary access point at the intersection of the guide line connecting the two original access points and the boundary line, the following steps 1328 to 1330 may be performed: Step 1328 : Generate a virtual metal line at the second temporary access point based on the metal line design rules defined in the basic process database.

[0089] Step 1329: Call the violation detection engine to detect whether the virtual metal line has any violation.

[0090] Step 1330: If the virtual metal line generates a violation, a new second temporary access point is generated on the boundary line at a position separated from the intersection position by the grid spacing, and the step of generating the virtual metal line at the second temporary access point is returned to be executed until the virtual metal line generates no violation.

[0091] In the present application, after setting a second temporary access point at the intersection of the guide line connecting any two original access points and the dividing line, a virtual metal line can be generated at the second temporary access point based on the metal line design rules set in the basic process database. The parameters of the virtual metal line (width, spacing, coverage, layer, etc.) fully comply with the design specifications of the target process environment to ensure the correctness and determinability of subsequent DRC. The violation detection engine can then be automatically called to perform global and local DRC checks on the newly generated virtual metal line. The inspection content includes but is not limited to metal spacing, width, and legal relationships with other structures (such as through-holes, other metal lines, cell boundaries, etc.). In addition, for FinFET processes, complex 3D and process-related special rule detection can also be performed.

[0092] If the current virtual metal line triggers any DRC violation at the second temporary access point, the temporary access point is immediately deemed invalid. The system then moves forward along the boundary line, one grid spacing away from the original intersection point. A new second temporary access point is set, and the virtual metal line is regenerated, repeating the DRC check process. This adaptive search process continues until the newly generated virtual metal line at a certain location fully complies with all DRC rules (i.e., there are no violations). At this point, the point is confirmed as the final valid second temporary access point.

[0093] The technical solution based on the above steps 1328 to 1329 has the advantage of being able to fully ensure that the physical interfaces and path splicing between multiple areas of distributed parallel wiring will not increase the risk of new design violations due to the introduction of auxiliary structures. The DRC-driven automated temporary access point / virtual metal line iterative search mechanism can greatly improve the wiring compliance efficiency and the stability of the entire process automation, and avoid to the greatest extent the later rework and failed convergence caused by improper interface management. In particular, the rules under complex processes such as FinFET can be adaptively judged and adjusted, which can greatly improve the adaptability to various advanced processes and large-scale high-performance chip physical design, expand the design scale upper limit of the tool platform, and improve the efficiency of R&D and engineering implementation.

[0094] Continue to refer to Figure 1 In step 140, based on the access points of the signal paths in each routing partition, the signal paths in each routing partition are routed in parallel by routing threads respectively configured for each routing partition.

[0095] In the present application, based on the access points of the signal paths in each routing partition, the signal paths in each routing partition are routed in parallel by using routing threads configured for each routing partition. This can be performed according to the following steps 141 to 144: Step 141: configure a routing thread for each routing partition.

[0096] Step 142: Based on the original access points and temporary access points of each signal path in each routing partition, the routing thread calls the routing engine to route the signal paths falling into each routing partition, and calls the violation detection engine to detect whether the routing of the signal paths in each routing partition generates violations.

[0097] Step 143: If a violation occurs in the wiring of the signal path in each wiring partition, the wiring that causes the violation is removed and re-wired.

[0098] Step 144 : When all signal paths falling into each routing partition are routed without generating any violation, the routing of the signal paths in each routing partition is terminated.

[0099] In this application, each routing zone is first assigned a dedicated routing thread. By establishing a thread pool mechanism, the design plan is managed according to multiple pre-divided routing zones, and resources and execution processes are independently scheduled for each zone. This enables parallel routing preparation at the regional level, ensuring that subsequent routing zones can carry out routing work simultaneously and efficiently without interfering with each other.

[0100] Subsequently, based on the original and temporary access points of the signal paths within each routing partition, the routing thread dedicated to that partition invokes the routing engine to automatically perform routing for all signal paths within that partition. Furthermore, after each routing step, the violation detection engine is automatically invoked to perform a design rule check (DRC) on each signal path within that partition, ensuring that the routing of each signal path does not violate process rules.

[0101] If a violation of the design rules is detected in the routing of a signal path during the routing process, that is, a violation occurs, the routing result of the signal path can be automatically revoked and the automatic rerouting operation can be started immediately. This process is executed cyclically by the dedicated thread of the routing partition until the routing of all signal paths in the current routing partition can pass the DRC check, ensuring the comprehensive compliance of the routing in the routing partition. When all the signal paths involved in a routing partition are routed and all pass the design rule check without any violations, the corresponding routing thread automatically terminates the routing operation of the current routing partition. Only under this condition is the partition routing process considered to be successfully completed, laying a solid foundation for the subsequent merging of the full-chip routing results and overall convergence.

[0102] In this application, by dividing the routing layer area into multiple routing partitions and assigning independent routing threads to each partition, parallel computing resources such as multi-core CPUs or GPUs can be fully utilized, greatly improving overall routing efficiency and significantly reducing total routing time. This partitioned parallelization strategy not only enables efficient and scalable routing, but also ensures that each routing partition performs routing and design rule checking independently and without interference, improving the stability and robustness of the routing process. Furthermore, within each routing partition, routing and DRC (design rule checking) form a real-time closed loop, quickly identifying and correcting violations, reducing later rework and achieving high-quality, process-compliant routing results. The automatic fallback and rerouting mechanism for violations instantly and locally resolves potential design issues, effectively enhancing the automation and intelligence of the routing process. Ultimately, the process is terminated only when all partitions fully comply with process rules. This strategy not only ensures the correctness and usability of the full-chip physical design but also provides a solid foundation for subsequent full-chip assembly and comprehensive optimization. Therefore, this method can greatly improve chip design efficiency, convergence speed and final design quality, and is a key technical means to achieve high performance, intelligence and reliability in the field of large-scale chip automatic wiring.

[0103] Continue to refer to Figure 1 In step 170, the wiring of the signal paths in each wiring partition is merged to obtain a complete wiring of the digital circuit.

[0104] In the present application, the merging of the wiring of the signal paths in each wiring partition may be performed according to the following steps 151 to 153: Step 151 , traverse each signal path in the digital circuit, delete the invalid wiring generated by the temporary access point in each signal path, and merge the wirings of each signal path in different wiring partitions.

[0105] Step 152: Calling a violation detection engine to detect whether a violation occurs in the wiring of each signal path.

[0106] Step 153: If a violation occurs in the wiring of each signal path, the wiring of each signal path is removed and re-wired until no violation occurs in the wiring of each signal path.

[0107] In this application, after the routing tasks of all routing partitions are completed and pass the partition-level DRC check, each signal path in the entire digital circuit can be traversed. For each signal path, first delete the virtual access points and their corresponding invalid metal wiring (such as virtual vias or virtual metal lines) temporarily generated during the partition routing stage to assist the partition routing, so as to prevent these temporary structures from interfering with the subsequent overall integration and DRC check. Subsequently, the routing segments of the same signal path in different routing partitions are spliced ​​and merged to establish a globally consistent and complete physical-level wire connection, and the metal lines that need to cross multiple routing partitions are structurally merged and optimized. The merged signal path will be included in the global violation detection process as an integrated data structure.

[0108] Specifically, the violation detection engine can be called to perform DRC (design rule checking) on ​​the complete routing after all signal paths are merged, including but not limited to cross-region seams, long metal lines, 3D connections and specific process rules (such as long traces, resistance, capacitance coupling and other requirements of FinFET devices), to ensure that after the regional level routing to the global splicing, the overall routing will not introduce new process violations.

[0109] In this application, if any signal path is found to have a wiring violation during the DRC check process, the wiring structure corresponding to the signal path will be immediately dismantled or rolled back to a critical legal state, and the incremental wiring algorithm will be started based on the merged global wiring. Incremental routing will re-optimize the wiring for local areas with violations until all signal paths can pass the DRC check globally. In this way, violations caused by cross-partition splicing can be efficiently repaired and the final convergence of the overall design rules can be achieved. After completion, the final compliant wiring results are synchronously written back to the DesignDatabase, 3D Route database, and DRCDatabase to ensure the complete closed loop and data consistency of the design process.

[0110] Based on the technical solutions described in steps 151 through 153 above, the merging and violation repair process ensures the flexibility and speed of efficient distributed parallel routing in the early stages, while also ensuring the physical integrity, process reliability, and electrical performance of the full-chip routing through rigorous merging and global DRC checking. Furthermore, mechanisms such as automatic splicing of partitioned routing, timely cleaning of invalid structures, and incremental repair effectively compensate for potential integration issues caused by the local nature of independent partitioned routing, providing solid technical support for the manufacturability and functional robustness of large-scale chip designs.

[0111] Based on the technical solution proposed in this application, by introducing the concept of parallel routing within routing partitions, the overall efficiency of digital circuit routing can be significantly improved. First, the grid parameters of each routing layer are used to divide the circuit to be routed into several routing partitions that adapt to physical characteristics and have adjustable area sizes, thereby achieving regional resource management. This partitioning method fully considers the size differences between different routing layers in different areas, making the partitions more suitable for actual design needs and optimizing the routing difficulty distribution from the source. Secondly, within each routing partition, by traversing all signal paths and accurately defining access points as indexes for routing tasks, the routing engine can greatly improve its focus on signal paths, which is beneficial for ensuring the performance and reliability of critical signal paths. Furthermore, by assigning independent routing threads to each routing partition, parallel routing within multiple routing partitions is supported on multi-core or multi-processor platforms. This can greatly improve resource utilization and routing speed, effectively reducing the overall design cycle. In addition, based on partition-level routing, by efficiently merging and resolving conflicts between routing results of cross-region signal paths, seamless integration of global routing is achieved, avoiding process and rule violations that may be caused by partition boundaries. The combination of this series of measures enables this method to not only improve the concurrency and automation of digital circuit routing, but also enhance the convergence efficiency and design quality of the final physical implementation, greatly meeting the actual needs of large-scale complex circuits in terms of design cycle, reliability and performance, and has outstanding technical application value.

[0112] The following describes an embodiment of the device of the present application, which can be used to implement the digital circuit wiring method in the above embodiment of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the digital circuit wiring method in the above embodiment of the present application.

[0113] See also Figure 6 , shows a block diagram of a digital circuit wiring device in an embodiment of the present application.

[0114] like Figure 6 As shown, the digital circuit routing device 600 according to an embodiment of the present application includes: an acquisition unit 601 , a segmentation unit 602 , a determination unit 603 , a routing unit 604 and a merging unit 605 .

[0115] Among them, the acquisition unit 601 is used to obtain the wiring grid parameters of each wiring layer in the digital circuit to be wired, wherein the grid lines of the wiring grid are used to constrain the wiring track; the segmentation unit 602 is used to segment the digital circuit into multiple wiring partitions based on the wiring grid parameters of each wiring layer, wherein the area size of each wiring layer in each wiring partition is different; the determination unit 603 is used to traverse each signal path and determine the access point of each signal path, and the access point is used to perform wiring indexing on each signal path; the wiring unit 604 is used to parallelly route the signal paths in each wiring partition based on the access point of the signal path in each wiring partition through the wiring threads respectively configured for each wiring partition; the merging unit 605 is used to merge the wiring of the signal paths in each wiring partition to obtain the complete wiring of the digital circuit.

[0116] In some embodiments of the present application, based on the aforementioned scheme, the wiring grid parameters include a grid spacing, and the segmentation unit 602 is configured to: traverse each wiring layer, and segment each wiring layer into multiple wiring layer areas, the length and width of each wiring layer area are both integer multiples of the grid spacing of each wiring layer, and the number of wiring layer areas of each wiring layer is the same as the number of wiring partitions; define a set of wiring layer areas of each wiring layer that are relative to each other in the vertical direction as a wiring partition, and obtain the multiple wiring partitions.

[0117] In some embodiments of the present application, based on the aforementioned scheme, the access points include original access points and temporary access points, and the determining unit 603 is configured to: obtain the original access points pre-set on each signal path; and set temporary access points on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition.

[0118] In some embodiments of the present application, based on the aforementioned solution, each signal path includes a metal pin, which is used to send and / or receive signals; the determining unit 603 is configured to: if any metal pin on each signal path spans multiple routing partitions, and the any metal pin does not have an original access point set in any of the multiple routing partitions spanned by the any metal pin, set a first temporary access point on the any metal pin, where the first temporary access point falls within the any routing partition.

[0119] In some embodiments of the present application, based on the aforementioned scheme, the device further includes: a generation unit, configured to, after setting a first temporary access point on any one of the metal pins, generate a virtual through hole for the any one of the metal pins at the first temporary access point based on the through hole design rules defined in the basic process database; call a violation detection engine to detect whether the virtual through hole generates a violation; if the virtual through hole does not generate a violation, determine an evaluation prediction value of the first temporary access point, wherein the evaluation prediction value is used to characterize the probability that the first temporary access point will not be selected in a future actual wiring process.

[0120] In some embodiments of the present application, based on the aforementioned scheme, the generation unit is further configured to: if the virtual through hole generates a violation, then based on the through hole design rule, generate a virtual metal line for the virtual through hole in the target wiring layer, and the target wiring layer is the next wiring layer of the wiring layer where the virtual through hole is located, and the projection of the virtual metal line in the vertical direction is surrounded by the projection of any one of the metal pins in the vertical direction.

[0121] In some embodiments of the present application, based on the aforementioned scheme, the determination unit 603 is further configured to: if any two adjacent original access points on each signal path fall into two wiring partitions respectively, determine the boundary line of the wiring layer where the any two original access points are located between the two wiring partitions; set a second temporary access point at the intersection of the guide line connecting the any two original access points and the boundary line, and the second temporary access point is used to eliminate violations generated when wiring each signal path separately in the two wiring partitions.

[0122] In some embodiments of the present application, based on the aforementioned scheme, the generation unit is further configured to: after setting a second temporary access point at the intersection position of the guide line connecting any two original access points and the dividing line, generate a virtual metal line at the second temporary access point based on the metal line design rules defined in the basic process database; call the violation detection engine to detect whether the virtual metal line generates a violation; if the virtual metal line generates a violation, generate a new second temporary access point at a position on the dividing line that is separated from the intersection position by the grid spacing, and return to execute the step of generating the virtual metal line at the second temporary access point until the virtual metal line does not generate a violation.

[0123] In some embodiments of the present application, based on the aforementioned scheme, the wiring unit 604 is configured to: configure a wiring thread for each wiring partition; based on the original access points and temporary access points of each signal path in each wiring partition, call the wiring engine through the wiring thread to route the signal paths falling into each wiring partition, and call the violation detection engine to detect whether the wiring of the signal paths in each wiring partition generates violations; if the wiring of the signal paths in each wiring partition generates violations, remove the wiring that generates violations and re-route; when all signal paths falling into each wiring partition complete routing and no violations are generated, terminate the routing of the signal paths in each wiring partition.

[0124] In some embodiments of the present application, based on the aforementioned scheme, the merging unit 605 is configured to: traverse each signal path in the digital circuit, delete the invalid wiring generated by the temporary access point in each signal path, and merge the wiring of each signal path in different wiring partitions; call the violation detection engine to detect whether the wiring of each signal path generates a violation; if the wiring of each signal path generates a violation, remove the wiring of each signal path and rewire until the wiring of each signal path does not generate a violation.

[0125] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device with the processor executes to implement the operations performed by the digital circuit wiring method described above.

[0126] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer program instruction. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the digital circuit wiring method described above.

[0127] Based on the same inventive concept, the present application also provides an electronic device, referring to Figure 7 , shows a structural schematic diagram of an electronic device in an embodiment of the present application, wherein the electronic device includes one or more memories 704, one or more processors 702, and at least one computer program (computer program instruction) stored in the memory 704 and executable on the processor 702. When the processor 702 executes the computer program, the digital circuit wiring method described above is implemented.

[0128] Among them, Figure 7In the present invention, a bus architecture (represented by bus 700) is shown. Bus 700 may include any number of interconnected buses and bridges. Bus 700 links various circuits, including one or more processors represented by processor 702 and memory represented by memory 704. Bus 700 may also link various other circuits, such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and, therefore, will not be described further herein. Bus interface 705 provides an interface between bus 700 and receiver 701 and transmitter 703. Receiver 701 and transmitter 703 may be the same component, namely a transceiver, which provides a means for communicating with various other devices over a transmission medium. Processor 702 is responsible for managing bus 700 and general processing, while memory 704 may be used to store data used by processor 702 when performing operations.

[0129] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Furthermore, the functional units may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0131] The units described as separate components may or may not be physically separate, and the components of the control device may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0132] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store computer program instructions, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0133] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of the claims of the present application.

Claims

1. A digital circuit wiring method, characterized in that: The method comprises: Obtaining routing grid parameters of each routing layer in the digital circuit to be routed, wherein the grid lines of the routing grid are used to constrain routing tracks; Based on the wiring grid parameters of each wiring layer, the digital circuit is divided into a plurality of wiring partitions, wherein the area size of each wiring layer in each wiring partition is different; Traversing each signal path and determining an access point of each signal path, wherein the access point is used to perform routing indexing on each signal path; Based on access points of the signal paths in each routing partition, routing the signal paths in each routing partition in parallel by routing threads respectively configured for each routing partition; The wiring of the signal paths in each wiring partition is merged to obtain a complete wiring of the digital circuit.

2. The method according to claim 1, characterized in that The wiring grid parameters include a grid spacing, and the digital circuit is divided into a plurality of wiring partitions based on the wiring grid parameters of each wiring layer, including: Traversing each wiring layer, dividing each wiring layer into a plurality of wiring layer regions, wherein the length and width of each wiring layer region are both integer multiples of the grid spacing of each wiring layer, and the number of wiring layer regions in each wiring layer is the same as the number of wiring partitions; A set of wiring layer regions of each wiring layer that are opposite to each other in the vertical direction is defined as a wiring partition, thereby obtaining the plurality of wiring partitions.

3. The method according to claim 2, characterized in that The access points include original access points and temporary access points, and determining the access point of each signal path includes: Obtaining a preset original access point on each signal path; and A temporary access point is set on each signal path according to the distribution characteristics of the original access point of each signal path in each wiring partition.

4. The method according to claim 3, characterized in that Each of the signal paths includes a metal pin, and the metal pin is used to send a signal and / or receive a signal; The step of setting a temporary access point on each signal path according to the distribution characteristics of the original access point of each signal path in each wiring partition includes: If any metal pin on each signal path spans multiple routing partitions, and no original access point is set for any metal pin in any of the multiple routing partitions spanned by the metal pin, a first temporary access point is set on the metal pin, and the first temporary access point falls into the any routing partition.

5. The method according to claim 4, characterized in that After setting the first temporary access point on any one of the metal pins, the method further includes: generating a virtual through hole for the arbitrary metal pin at the first temporary access point based on a through hole design rule defined in a basic process database; Invoking a violation detection engine to detect whether the virtual through hole generates a violation; If the virtual via does not generate a violation, an evaluation prediction value of the first temporary access point is determined, where the evaluation prediction value is used to represent a probability that the first temporary access point will not be selected in a future actual routing process.

6. The method according to claim 5, characterized in that The method further comprises: If the virtual through hole generates a violation, a virtual metal line is generated for the virtual through hole in a target wiring layer based on the through hole design rule, and the target wiring layer is the next wiring layer of the wiring layer where the virtual through hole is located, and the projection of the virtual metal line in the vertical direction is surrounded by the projection of any one of the metal pins in the vertical direction.

7. The method according to claim 3, characterized in that The step of setting a temporary access point on each signal path according to the distribution characteristics of the original access point of each signal path in each wiring partition includes: If any two adjacent original access points on each signal path fall into two wiring partitions respectively, determining a boundary line between the wiring layers where the two original access points are located and the two wiring partitions; A second temporary access point is set at an intersection of a guide line connecting the arbitrary two original access points and the boundary line, and the second temporary access point is used to eliminate violations generated when routing each signal path in the two routing partitions.

8. The method according to claim 7, characterized in that After setting a second temporary access point at an intersection of a guide line connecting the arbitrary two original access points and the dividing line, the method further includes: generating a virtual metal line at the second temporary access point based on a metal line design rule defined in a basic process database; Invoking a violation detection engine to detect whether a violation occurs on the virtual metal line; If the virtual metal line generates a violation, a new second temporary access point is generated at a position on the boundary line that is separated from the intersection position by the grid spacing, and the step of generating the virtual metal line at the second temporary access point is returned to and executed until the virtual metal line generates no violation.

9. The method according to claim 3, characterized in that The method of routing the signal paths in each routing partition in parallel based on the access points of the signal paths in each routing partition by using routing threads respectively configured for each routing partition includes: configuring a routing thread for each routing partition; Based on original access points and temporary access points of each signal path in each routing partition, the routing thread calls a routing engine to route the signal paths falling into each routing partition, and calls a violation detection engine to detect whether the routing of the signal paths in each routing partition generates a violation; If a violation occurs in the wiring of the signal path in each of the wiring partitions, the wiring that causes the violation is removed and re-wiring is performed; When all signal paths falling into each routing partition are routed without generating any violation, the routing of the signal paths in each routing partition is terminated.

10. The method according to claim 3, characterized in that The merging of the wiring of the signal paths in each wiring partition includes: traversing each signal path in the digital circuit, deleting invalid wiring generated by the temporary access point in each signal path, and merging wirings in different wiring partitions of each signal path; Invoking a violation detection engine to detect whether a violation occurs in the wiring of each signal path; If a violation occurs in the wiring of each signal path, the wiring of each signal path is removed and re-wired until no violation occurs in the wiring of each signal path.

11. A digital circuit wiring device, characterized in that: The device comprises: An acquisition unit, configured to acquire routing grid parameters of each routing layer in a digital circuit to be routed, wherein the grid lines of the routing grid are used to constrain routing tracks; a segmentation unit, configured to segment the digital circuit into a plurality of wiring partitions based on wiring grid parameters of each wiring layer, wherein the area size of each wiring layer in each wiring partition is different; a determining unit, configured to traverse each signal path and determine an access point of each signal path, wherein the access point is used to perform routing indexing on each signal path; a routing unit, configured to route the signal paths in each routing partition in parallel based on access points of the signal paths in each routing partition by using routing threads respectively configured for each routing partition; The merging unit is used to merge the wiring of the signal paths in each wiring partition to obtain a complete wiring of the digital circuit.

12. A computer program product, characterized in that The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor, so as to enable a computer device having the processor to perform the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that At least one program code is stored in the computer-readable storage medium, and the at least one program code is loaded and executed by a processor to implement the operations performed by the method according to any one of claims 1 to 10.

14. An electronic device, characterized in that: The electronic device includes one or more processors and one or more memories, wherein at least one program code is stored in the one or more memories, and the at least one program code is loaded and executed by the one or more processors to implement the method according to any one of claims 1 to 10.

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