Semiconductor device

Abstract

An integrated circuit device includes: a cell region in which a plurality of memory banks are disposed, each memory bank including a respective memory cell array having a plurality of memory cells therein; a row decoder connected to the memory cell array; and a sense amplifier circuit. A peripheral circuit region is provided that includes a logic circuit that controls a plurality of memory banks. The logic circuitry includes at least one queue configured to store a row hammer address of at least one of the plurality of memory banks, and controls: (i) a target memory bank to perform a row hammer refresh operation in the target memory bank indicated by the row hammer address when the row hammer address stored in the queue exists, and (ii) a plurality of memory banks to perform a normal refresh operation when the row hammer address stored in the queue does not exist.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the patent application number of Korean Patent Application No.

[0003] 10-2024-0036589, the disclosure of which is incorporated herein by reference. Technical Field

[0004] The inventive concept relates to an integrated circuit memory device and an operating method thereof. Background Art

[0005] An integrated circuit memory device includes a semiconductor device that can store and read stored data. The memory device may include a memory cell array in which memory cells storing data are arranged, a row decoder connected to the memory cells via word lines, and a sense amplifier connected to the memory cells via bit lines. To prevent the loss of data written to the memory cells, the integrated circuit device may perform a refresh operation to reprogram the data written to the memory cells. Furthermore, the refresh operation may be performed to prevent data fluctuations in memory cells connected to adjacent word lines due to a phenomenon called row hammering, in which accesses to a specific word line occur in a concentrated manner among the word lines. Summary of the Invention

[0006] Example embodiments provide an integrated circuit memory device in which a row hammer refresh operation for preventing data fluctuation due to a row hammer phenomenon and a normal refresh operation for preventing data loss in a memory cell can be dynamically scheduled according to circumstances, thereby optimizing power consumption due to the refresh operation and increasing defense against the row hammer phenomenon.

[0007] According to an example embodiment, an integrated circuit device includes: a cell region in which a plurality of memory banks are arranged, each of the plurality of memory banks including a memory cell array including a plurality of memory cells, a row decoder connected to the memory cell array via a plurality of word lines, and a sense amplifier circuit connected to the memory cell array via a plurality of bit lines; and a peripheral circuit region in which logic circuitry for controlling the plurality of memory banks is arranged. The logic circuitry includes at least one queue for storing a row hammer address for at least one of the plurality of memory banks. When a row hammer address is stored in the queue, the logic circuitry controls a target memory bank to perform a row hammer refresh operation in the target memory bank indicated by the row hammer address, and when no row hammer address is stored in the queue, the logic circuitry controls the plurality of memory banks to perform a normal refresh operation.

[0008] According to another example embodiment, an integrated circuit device includes: a cell region in which a plurality of memory banks are arranged, each of the plurality of memory banks including a memory cell array containing a plurality of memory cells, a row decoder connected to the memory cell array via a plurality of word lines, and a sense amplifier circuit connected to the memory cell array via a plurality of bit lines; and a peripheral circuit region configured to perform a row hammer refresh operation, a first normal refresh operation, and a second normal refresh operation for each of the plurality of memory banks, wherein the row hammer refresh operation detects an attacking word line among the plurality of word lines and refreshes target memory cells connected to target word lines adjacent to the attacking word line, the first normal refresh operation activates n word lines at a time, and the second normal refresh operation activates m word lines at a time, where m is greater than n. The peripheral circuit region includes a counter for storing the number of executions of the row hammer refresh operation. Advantageously, when the number of executions stored in the counter is greater than 0, the peripheral circuit region performs the second normal refresh operation until the number of executions stored in the counter reaches 0.

[0009] According to another embodiment, an integrated circuit device includes a cell region in which a plurality of memory banks are arranged, wherein each of the plurality of memory banks includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, and a peripheral circuit region in which logic circuitry is arranged. The logic circuit performs a row hammer refresh operation for each of the plurality of memory banks by detecting an aggressor word line among the plurality of word lines and refreshing memory cells connected to victim word lines adjacent to the aggressor word line, and performs a normal refresh operation by refreshing memory cells connected to at least one selected word line among the plurality of word lines. The peripheral circuit region includes a queue and a counter, wherein the queue stores a row hammer address indicating at least one of the aggressor word line and the victim word line, and the counter stores the number of times the row hammer refresh operation has been performed. The logic circuit performs one of a row hammer refresh operation and a normal refresh operation at each refresh timing that arrives at a predetermined refresh cycle based on at least one of a state of the queue and a value stored in the counter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram schematically illustrating a system including an integrated circuit device according to example embodiments;

[0012] Figure 2 and Figure 3 is a diagram schematically illustrating a structure of an integrated circuit device according to example embodiments;

[0013] Figure 4 and Figure 5 is a schematic diagram of an integrated circuit device according to an example embodiment;

[0014] Figure 6 is a flowchart illustrating the operation of an integrated circuit device according to an example embodiment;

[0015] Figures 7 to 9 is a diagram illustrating a refresh operation of an integrated circuit device according to example embodiments;

[0016] Figures 10 to 13 is a diagram illustrating the operation of an integrated circuit device according to example embodiments;

[0017] Figure 14 is a diagram illustrating the operation of an integrated circuit device according to example embodiments;

[0018] Figure 15 is a flowchart illustrating the operation of an integrated circuit device according to an example embodiment;

[0019] Figure 16 is a diagram illustrating the operation of an integrated circuit device according to example embodiments;

[0020] Figure 17 is a diagram illustrating the operation of an integrated circuit device according to example embodiments; and

[0021] Figure 18 is a diagram illustrating the operation of an integrated circuit device according to example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram schematically illustrating a system including an integrated circuit device according to example embodiments. Figure 1 , the system 10 may include a memory device 20 and a memory controller 30. Figure 1 In the example embodiment shown in , the integrated circuit device according to the example embodiment may be provided as the memory device 20 , and the memory device 20 and the memory controller 30 may be connected through a memory interface to exchange signals with each other.

[0024] As will be understood by those skilled in the art, the memory device 20 may operate based on signals received from the memory controller 30. For example, as shown, the memory controller 30 may transmit a command signal CMD and an address signal ADDR to the memory device 20; and the memory device 20 may perform control operations such as write operations, read operations, and refresh operations based on the command signal CMD. The control operation is performed on at least one target memory cell among the plurality of memory cells included in the memory device 20, and the target memory cell may be specified by the address signal ADDR. The memory controller 30 may transmit a data signal DATA to be recorded in the memory device 20 to the memory device 20, and may receive data stored in the memory device 20 from the memory device 20 as the data signal DATA.

[0025] The memory device 20 may include a cell area 21 and a peripheral circuit area 22. A plurality of memory cells storing data are arranged in the cell area 21, and a logic circuit for controlling the cell area 21, an input / output circuit for exchanging signals with the memory controller 30, and a refresh control circuit 23 for controlling a refresh operation may be provided in the peripheral circuit area 22. For example, each of the memory cells provided in the cell area 21 may include a cell capacitor capable of charging an electric charge, and data may be written to the memory cell by charging and discharging the cell capacitor. However, as time passes after the data is written to the memory cell, the data may be lost due to charge leakage from the cell capacitor. To prevent this, a refresh operation for overwriting data may be performed in the memory device 20.

[0026] In the cell area 21, a plurality of memory cells may be connected to a row decoder through a plurality of word lines (WL) and to a sense amplifier circuit through a plurality of bit lines (BL). Unfortunately, when a specific word line is centrally selected from among the plurality of word lines and a control operation such as a write operation or a read operation is performed, the data of the memory cells connected to other adjacent word lines may change during the process of activating the word line. In some cases, this phenomenon may be referred to as a row hammer phenomenon. When the row hammer phenomenon occurs, the word line that is centrally selected as the execution target of the control operation may be defined as an attacking word line, and other word lines adjacent to the attacking word line may be defined as victim word lines. Considering the trend of increasing density of memory cells arranged in the cell area 21 and decreasing spacing between word lines, it is necessary to minimize data fluctuations due to the row hammer phenomenon.

[0027] For example, during a typical refresh operation in a DRAM-type integrated circuit memory device, which can be performed independently of the row hammer phenomenon, each of a plurality of word lines can be activated, and data in memory cells connected to the activated word lines can be rewritten. On the other hand, in the case of a row hammer refresh operation to prevent data fluctuation in memory cells connected to a victim word line due to row hammering, the victim word line can be designated as a target word line, and data in memory cells connected to the victim word line can be rewritten to increase data reliability.

[0028] When a row hammer refresh operation is performed, a normal refresh operation may have to be skipped. Therefore, if the row hammer refresh operation is performed too frequently, as the number of skips in the normal refresh operation accumulates, data loss may occur in memory cells connected to word lines unrelated to row hammering. Alternatively, if the number of executions of the row hammer refresh operation is excessively limited, data fluctuations due to the row hammer phenomenon may occur in memory cells connected to the victim word line(s). Thus, if the row hammer refresh operation and the normal refresh operation are not properly scheduled and adjusted, the reliability of the data stored in the cell region 21 and the performance of the memory device 20 may be degraded.

[0029] In some example embodiments, a row hammer address, which is an address of an attacking word line that causes row hammering, is stored in a separate queue included in the peripheral circuit region 22, and a row hammer refresh operation may be performed when the row hammer address stored in the queue exists. Furthermore, when the row hammer refresh operation is performed continuously in bursts, the number of consecutive executions of the row hammer refresh operation may be stored in a counter. Then, when the number stored in the counter reaches a predetermined reference number, a normal refresh operation is performed regardless of whether the row hammer address stored in the queue exists, thereby preventing data loss that may occur due to excessive skipping of normal refresh operations.

[0030] Figure 2 and Figure 3 is a diagram schematically showing the structure of an integrated circuit device according to an example embodiment. Figure 2 , the integrated circuit device 40 according to the example embodiment may include a cell region in which a plurality of memory banks 50 are provided, a peripheral circuit region 60, and the like. Each of the plurality of memory banks 50 may include a memory cell array 51, a row decoder 52, a sense amplifier circuit (SA) 53, and a column decoder 54. The plurality of memory cells included in the memory cell array 51 may be connected to the row decoder 52 through a plurality of word lines, and connected to the sense amplifier circuit 53 through a plurality of bit lines. On the other hand, in Figure 2In the example embodiment shown in FIG, eight memory banks 50 are shown as included in the integrated circuit device 40, but the number of memory banks 50 may vary depending on the example embodiment.

[0031] In the peripheral circuit area 60, a logic circuit for controlling the plurality of memory banks 50, an input / output circuit for exchanging signals with another external device such as a memory controller, and the like may be provided. For example, the peripheral circuit area 60 may control a write operation, a read operation, a refresh operation, and the like of each of the plurality of memory banks 50 based on a command signal and an address signal received from the memory controller.

[0032] Reference Figure 2 The queue 61 and the counter 62 may be provided in the peripheral circuit region 60. The queue 61 is a storage space implemented using a flip-flop, a latch, a buffer circuit, a static random access memory (SRAM), etc., and may operate in a first-in-first-out (FIFO) method. For example, when row hammering occurs in at least one of the plurality of memory banks 50, the address of the attacking word line causing the row hammering may be stored in the queue 61 as a row hammering address.

[0033] The counter 62 may store the number of times the row hammer refresh operation is performed in the plurality of memory banks 50 in response to the row hammer. According to example embodiments, the queues 61 and / or the counters 62 may be provided in the peripheral circuit region 60 as many as the number of the memory banks 50 to correspond to the plurality of memory banks 50. For example, eight counters 62 corresponding to eight memory banks 50 may be included in the peripheral circuit region 60, and each of the counters 62 may be provided in a position close to the corresponding memory bank 50 in the peripheral circuit region 60.

[0034] The peripheral circuit region 60 can control the refresh operation of each of the plurality of memory banks 50 based on the values ​​stored in the queue 61 and the counter 62. For example, if a row hammer address is stored in the queue 61, the peripheral circuit region 60 can identify the target memory bank indicated by the row hammer address among the plurality of memory banks 50 and control the target memory bank to perform a row hammer refresh operation. On the other hand, if no row hammer address is stored in the queue 61, the peripheral circuit region 60 can control the plurality of memory banks 50 to perform a normal refresh operation at the refresh timing.

[0035] For example, a row hammer refresh operation may include reprogramming data of memory cells connected to each of a pair of victim word lines adjacent to an aggressor word line indicated by a row hammer address. In the row hammer refresh operation, data of memory cells connected to a first victim word line are read and reprogrammed at a first refresh timing, and after the first refresh timing, data from memory cells connected to a second victim word line may be read and reprogrammed at a second refresh timing.

[0036] The peripheral circuit area 60 may schedule a row hammer refresh operation and a normal refresh operation with reference to a value stored in the counter 62. In an example embodiment, the value stored in the counter 62 may correspond to the number of times the row hammer refresh operation is continuously performed in each of the plurality of memory banks 50. For example, if three row hammer refresh operations are continuously performed in one memory bank 50, the counter 62 may store a count value of 3 for the one memory bank 50.

[0037] In order to perform a row hammer refresh operation, it is necessary to sacrifice the refresh timing of a normal refresh operation. If the row hammer refresh operation is only performed excessively, the data retention characteristics of memory cells connected to word lines other than the victim word line may deteriorate. Therefore, in the example embodiment, when the value stored in counter 62 reaches a predetermined reference value, a normal refresh operation can be performed in the corresponding memory bank 50, regardless of whether the row hammer address is stored in queue 61. In this way, by dynamically scheduling row hammer refresh operations and normal refresh operations, it is possible to effectively prevent the degradation of the retention characteristics of data stored in multiple memory banks 50.

[0038] Next, refer to Figure 3 , the memory device 100 may include a memory cell array 111 to 118 (110), a row decoder 121 to 128 (120), a sense amplifier circuit 131 to 138 (130), a column decoder 141 to 148 (140), an input / output (I / O) circuit 150, an I / O buffer 151, a refresh control circuit 170, a command decoder 180, an address decoder 190, etc. The memory cell array 111 to 118 (110), the row decoder 121 to 128 (120), the sense amplifier circuit 131 to 138 (130), and the column decoder 141 to 148 (140) may provide a plurality of memory banks.

[0039] The memory cell array 110 includes a plurality of memory cells MC, and each of the plurality of memory cells MC may be connected to a row decoder 120 via a word line WL and may be connected to a sense amplifier circuit 130 via a bit line BL. The command decoder 180 may receive a command signal CMD from an external memory controller, etc., and control the plurality of memory banks based on the command signal CMD. For example, when the command signal CMD includes a refresh command REF, the command decoder 180 may decode the command signal CMD to generate the refresh command REF.

[0040] The address decoder 190 may receive an address signal ADDR and the like from the memory controller. The address decoder 190 decodes the address signal ADDR and generates a memory bank address BA indicating a target memory bank among a plurality of memory banks, a row address RA indicating a target word line included in a target memory bank among a plurality of word lines WL, and a column address CA indicating a target bit line included in a target memory bank among a plurality of bit lines BL. The row address RA may be provided to the refresh control circuit 170 or may be provided to the row decoder 120 via the multiplexer 160. The column address CA may be provided to the column decoder 140, and the memory bank address BA may be provided to the memory bank control circuit 161.

[0041] The refresh control circuit 170 may output a refresh row address REF_RA in response to a refresh command REF, the refresh row address REF_RA indicating a target word line on which a refresh operation is to be performed. Figure 3 In the example embodiment shown in , the multiplexer 160 may select one of the row address RA and the refresh row address REF_RA and transmit it to the row decoder 120. The row decoder 120 may activate a target word line included in a target memory bank among the plurality of word lines WL by referring to the row address RA or the refresh row address REF_RA output by the multiplexer 160.

[0042] Column decoder 140 can select a target bit line from a plurality of bit lines BL based on a column address CA. Column decoder 140 can activate a sense amplifier corresponding to column address CA among the sense amplifiers included in sense amplifier circuit 130 through I / O circuit 150. I / O circuit 150 gates input / output data and can include a data latch for storing data read from memory cell array 110 and a write driver for writing data to memory cell array 110. The sense amplifier can read data from a memory cell connected to a target word line and a target bit line in memory cell array 110 and store the data in the data latch of I / O circuit 150.

[0043] In example embodiments, data acquired from the memory cell array 110 by the sense amplifier through a read operation may be output as a data signal DATA through the I / O buffer 151 and provided to the memory controller. Data to be stored in the memory cell array is received by the memory controller as the data signal DATA and provided to the I / O buffer 151, and the data provided to the I / O buffer 151 may be provided to the I / O circuit 150.

[0044] The refresh control circuit 170 can send a refresh row address REF_RA for performing a refresh operation to the multiplexer 160 in response to the refresh command REF. When the multiplexer 160 selects the refresh row address REF_RA, the row decoder 120 can activate the word line on which the refresh operation is to be performed. For example, the refresh control circuit 170 can determine the address of the aggressor word line that generated the row hammer by referring to the row hammer address stored in a separate queue. The refresh control circuit 170 can determine the address of the victim word line based on the address of the aggressor word line and generate the refresh row address REF_RA. As a result, the victim word line is activated by the row decoder 120 as the target word line, and a row hammer refresh operation can be performed.

[0045] On the other hand, if the row hammer address is not stored in the separate queue, the refresh control circuit 170 may generate a refresh row address REF_RA including the address of the target word line for which a normal refresh operation is to be performed. Thus, the target word line is activated by the row decoder 120, and a normal refresh operation may be performed.

[0046] Figure 4 and Figure 5 is a schematic diagram of an integrated circuit device according to an example embodiment. Figure 4 and Figure 5 FIG2 is a diagram schematically illustrating a memory cell array 210, a row decoder 220, a sense amplifier circuit 230, etc. included in an integrated circuit device 200 according to example embodiments. Figure 4 and Figure 5 , the memory cell array 210 may be connected to the row decoder 220 through a plurality of word lines WL1 to WLN, and may be connected to the sense amplifier circuit 230 through a plurality of bit lines BL1 to BLM.

[0047] A plurality of word lines WL1 to WLN and a plurality of bit lines BL1 to BLM may be connected to a plurality of memory cells MC. Each of the plurality of memory cells MC may include a switching element SW and a cell capacitor CC. The gate of the switching element SW may be connected to one of the plurality of word lines WL1 to WLN. Therefore, when a selected word line among the plurality of word lines WL1 to WLN is activated and the switching element SW is turned on, a read operation for reading the charge charged in the cell capacitor CC or a write operation for charging (or removing) the charge in the cell capacitor CC can be performed through the selected bit line among the plurality of bit lines BL1 to BLM.

[0048] When the row decoder 220 repeatedly selects and activates a specific word line among the plurality of word lines WL1 to WLN, a row hammer phenomenon may occur in which data in memory cells connected to other adjacent word lines are unintentionally changed. Figure 5 , when the row decoder 220 repeatedly selects and activates the third word line WL3, data in memory cells connected to each of the second word line WL2 and the fourth word line WL4 adjacent to the third word line WL3 may be changed (and destroyed by the row hammering phenomenon). Figure 5 In the example embodiment shown in FIG, the third word line WL3 may be defined as the aggressor word line 201, and the second word line WL2 and the fourth word line WL4 (and possibly the first word line and the fifth word line) may be defined as the victim word lines 202 and 203. As the integration density of the integrated circuit device 200 increases, this row hammering phenomenon may become more severe.

[0049] In order to prevent data fluctuations in the victim word lines 202 and 203 due to the row hammer phenomenon, a row hammer refresh operation can be performed at refresh timing. Unlike a normal refresh operation in which word lines WL1 to WLN are typically activated sequentially and data is overwritten / restored in memory cells MC, in the row hammer refresh operation, victim word lines 202 and 203 can be designated and data can be overwritten / restored in memory cells MC connected to the victim word lines 202 and 203 (in order to thwart a row hammer attack).

[0050] However, if the row hammer refresh operation is performed repeatedly, the normal refresh operation may not be performed frequently enough, and data loss may occur in the memory cells MC connected to word lines other than the victim word lines 202 and 203. In an example embodiment, the normal refresh operation and the row hammer refresh operation can be dynamically scheduled based on whether the row hammer phenomenon has occurred and the number of skips of the normal refresh operation. Therefore, in addition to preventing data fluctuation in the memory cells MC connected to the victim word lines 202 and 203, data loss in the memory cells MC connected to word lines other than the victim word lines 202 and 203 can also be effectively prevented.

[0051] Figure 6 is a flow chart illustrating the operation of an integrated circuit device according to an example embodiment. Figure 6 The operation of the integrated circuit device according to example embodiments may begin with the integrated circuit device receiving a command signal and an address signal from a memory controller (S10). The integrated circuit device may be a memory device that stores data and may perform a control operation based on the command signal and the address signal (S11). The control operation may include a write operation to save data, a read operation to output the stored data to the memory controller, and a refresh operation to rewrite / restore the stored data.

[0052] When executing the control operation, the logic circuit of the integrated circuit device may determine whether the refresh timing has arrived (S12). For example, when a refresh command is received from the memory controller, the logic circuit of the integrated circuit device may determine that the refresh timing has arrived and execute the refresh operation. If it is determined that the refresh timing has not arrived, the logic circuit of the integrated circuit device may process the control operation based on the command signal and address signal received from the memory controller (S10-S11).

[0053] When it is determined that the refresh timing has arrived, the logic circuit may determine whether a row hammer address exists in a queue provided in the peripheral circuit area (S13). The row hammer address may include at least one of an address of an attacking word line generating the row hammer phenomenon and an address of a victim word line adjacent to the attacking word line.

[0054] As a result of the determination in operation S13, if the row hammer address does not exist in the queue, the logic circuit may perform a first normal refresh operation (S14). In the first normal refresh operation, the logic circuit of the integrated circuit device may activate at least one of the plurality of word lines by referring to an address received with a refresh command or an address determined as a target for a next refresh operation within the integrated circuit device. A refresh operation may be performed in which data from memory cells connected to the activated word line is read and rewritten. In an example embodiment, in the first normal refresh operation, n word lines may be activated simultaneously (n is a natural number of 2 or greater).

[0055] On the other hand, if the row hammer address is present in the queue as determined in operation S13, the logic circuit of the integrated circuit device may perform a row hammer (RH) refresh operation (S15). In the row hammer refresh operation, the logic circuit may refer to the row hammer address stored in the queue and designate a victim word line adjacent to the aggressor word line as a target word line. For example, the logic circuit of the integrated circuit device may designate a pair of victim word lines adjacent to the aggressor word line as target word lines.

[0056] In an example embodiment, during a row hammer refresh operation, one of the target word lines may be activated at a time. For example, the logic circuit of the integrated circuit device may activate a first victim word line adjacent to the aggressor word line at a first refresh timing and overwrite data in memory cells connected to the first victim word line. At a second refresh timing immediately following the first refresh timing, the logic circuit of the integrated circuit device may activate a second victim word line adjacent to the aggressor word line and overwrite / restore data in memory cells connected to the second victim word line.

[0057] When the row hammer refresh operation is completed and the next refresh timing arrives, the logic circuit of the integrated circuit device may perform a second normal refresh operation (S16). The second normal refresh operation may be similar to the first normal refresh operation. However, the number of word lines activated at one time in the second normal refresh operation may be greater than the number of word lines activated at one time in the first normal refresh operation.

[0058] For example, the logic circuit may simultaneously activate m word lines (m is a natural number greater than n) in the second normal refresh operation. In this way, by simultaneously activating a greater number of word lines in the second normal refresh operation than in the first normal refresh operation, the first normal refresh operation that was not performed at the first refresh timing and the second refresh timing can be compensated.

[0059] Figures 7 to 9 is a diagram provided for explaining a refresh operation of an integrated circuit device according to example embodiments. Figure 7 1 is a diagram for explaining the first normal refresh operation. Figure 7 , a memory cell array included in one memory bank includes N word lines WL1 to WLN, and a plurality of memory cells may be connected to each of the word lines WL1 to WLN. Figure 7 In the first normal refresh operation of the example embodiment shown in FIG, two word lines may be activated simultaneously. The peripheral circuit region of the integrated circuit device may overwrite data in memory cells connected to the two activated word lines. Figure 7 , two word lines adjacent to each other are shown as being activated simultaneously. Alternatively, two word lines that are not consecutive to each other may be activated simultaneously.

[0060] Figure 8 It can be a diagram for explaining the second normal refresh operation. Figure 8 In the second normal refresh operation of the example embodiment shown in FIG, four word lines may be activated simultaneously. The peripheral circuit region of the integrated circuit device may overwrite data in memory cells connected to the four activated word lines. Figure 8In FIG, four adjacent word lines are shown as being activated simultaneously. However, unlike this, at least some of the four simultaneously activated word lines may not be continuous with each other. Since the four word lines are activated simultaneously, the power consumption in the second normal refresh operation may be greater than the power consumption in the first normal refresh operation.

[0061] Figure 9 It can be a diagram for explaining a row hammer refresh operation. Figure 9 In the row hammer refresh operation of the example embodiment shown in , a refresh operation can be performed on a pair of victim word lines VR1 and VR2 adjacent to the attack word line AR. The peripheral circuit region of the integrated circuit device can first control the row decoders connected to the word lines WL1 to WLN to activate the first victim word line VR1. Then, data from the memory cells connected to the first victim word line VR1 can be read and written again. Next, the peripheral circuit region can control the row decoders to activate the second victim word line VR2, read data from the memory cells connected to the second victim word line VR2, and write data again. The first victim word line VR1 can be activated at a first refresh timing, and the second victim word line VR2 can be activated at a second refresh timing. The time between the first refresh timing and the second refresh timing can be defined as a refresh period. For example, the refresh period can be several microseconds.

[0062] If a row hammer refresh operation is performed, a normal refresh operation may not be performed at two refresh timings, and the normal refresh operation may be skipped. Therefore, at at least one refresh timing among the refresh timings that come after the row hammer refresh operation, a second normal refresh operation may be performed to compensate for the normal refresh operation that was skipped due to the row hammer refresh operation. Figures 10 to 13 Describe in more detail.

[0063] Figures 10 to 13 is a diagram illustrating the operation of an integrated circuit device according to example embodiments. Figure 10 FIG. 1 is a diagram schematically illustrating a timing of a refresh operation of an integrated circuit device according to example embodiments. Figure 10 After the first time point T1, each time a refresh timing arrives, a refresh operation may be performed in the integrated circuit device. A refresh operation may be selected between a normal refresh operation and a row hammer refresh operation according to whether a row hammer address is stored in the queue QUEUE.

[0064] Refresh timing occurs every predetermined refresh cycle TC, and the refresh cycle TC may vary depending on the retention characteristics of the memory cells, the number of word lines included in the memory cell array, and the like. For example, the time required to refresh in consideration of the retention characteristics of the memory cells may be defined as a refresh window time, and may be, for example, 64 milliseconds. Alternatively, the refresh cycle TC may be determined based on the number of times a word line is activated for refresh during one refresh window time. The refresh cycle TC may vary depending on the exemplary embodiment, and may be, for example, 7.8 microseconds, 3.9 microseconds, and the like.

[0065] Reference Figure 10 At the first time point T1, no row hammer address is stored in the queue QUEUE, and the logic circuit of the integrated circuit device may perform a first normal refresh operation NR1. Figure 10 and Figure 11 In the first normal refresh operation, two word lines WL1 to WLN can be activated at a time. Therefore, at the first refresh timing, the memory cells connected to the first word line WL1 and the second word line WL2 can be refreshed, and at the second refresh timing, the memory cells connected to the third word line WL3 and the fourth word line WL4 can be refreshed.

[0066] On the other hand, at the second time point T2, the row hammer address stored in the queue may be detected. Therefore, at the refresh timing that arrives after the second time point T2, the logic circuit of the integrated circuit device may perform a row hammer refresh operation RR instead of the first normal refresh operation NR1. As previously explained, in the row hammer refresh operation RR, the logic circuit may select a pair of victim word lines adjacent to the aggressor word line one at a time.

[0067] Referring to FIG. 1 , which shows an example of a row hammer refresh operation RR Figure 12 , the attacking word line may be the eighth word line WL8. The logic circuit may refresh the memory cell connected to the seventh word line WL7, which is the first victim word line VR1, at the third refresh timing. In addition, the logic circuit may refresh the memory cell connected to the ninth word line WL9, which is the second victim word line VR2, at the fourth refresh timing.

[0068] When the row hammer refresh operation RR is completed, as Figure 10 As shown, from the third time point T3 onwards, the row hammering address stored in the queue may no longer exist. On the other hand, since the first normal refresh operation NR1 is skipped to perform the row hammering refresh operation at the third refresh timing and the fourth refresh timing, in order to compensate for it, the second normal refresh operation NR2 may be performed at the fifth refresh timing and the sixth refresh timing.

[0069] Reference Figure 10 Together Figure 13In the second normal refresh operation NR2, four word lines WL1 to WLN can be activated at a time. Since the refresh of the memory cells connected to the fourth word line WL4 was completed at the second refresh timing when the previous normal refresh operation was performed, the logic circuit can refresh the memory cells connected to the fifth to eighth word lines WL5 to WL8 at the fifth refresh timing. On the other hand, the logic circuit can refresh the memory cells connected to the ninth to twelfth word lines WL9 to WL12 at the sixth refresh timing.

[0070] In this manner, the first normal refresh operation NR1 can be compensated by performing the second normal refresh operation NR2 at least once or a plurality of times after the row hammering refresh operation RR. Figure 10 In the example embodiment shown in , the row hammer refresh operation RR is not performed at each of the first to sixth refresh timings, and the first normal refresh operation NR1 is performed. At the sixth refresh timing, the memory cells connected to the eleventh word line WL11 and the twelfth word line WL12 can be refreshed. Therefore, while the row hammer refresh operation RR is performed to minimize data fluctuation due to the row hammer phenomenon, refresh operations of the memory cells connected to the other word lines can also be guaranteed, and data loss in the memory cells connected to the other word lines can be effectively prevented.

[0071] When the first normal refresh operation NR1 is compensated by executing the second normal refresh operation NR2, the first normal refresh operation NR1 may be executed again. Thus, in example embodiments, the row hammering refresh operation RR, the first normal refresh operation NR1, and the second normal refresh operation NR2 may be dynamically scheduled based on whether the row hammering address is stored in the queue QUEUE. Therefore, data fluctuations due to the row hammering phenomenon and data loss due to omission of refresh operations may be minimized, and power consumption may be reduced by executing the second normal refresh operation NR2 only when necessary.

[0072] Figure 14 is a diagram schematically illustrating the timing of a refresh operation of an integrated circuit device according to example embodiments. Figure 14 , whenever the refresh timing is reached after the first time point T1, a refresh operation may be performed in the integrated circuit device. Figure 10 In the example embodiment described, the row hammer address may be stored in the queue QUEUE at the second time point T2. Therefore, the first normal refresh operation NR1 may be performed at each of the first refresh timing and the second refresh timing, and the row hammer refresh operation RR may be performed at each of the third refresh timing and the fourth refresh timing. The refresh cycle TC may be as previously described with reference to Figure 10 Determined as described.

[0073] The second normal refresh operation NR2 may be performed at each of the fifth and sixth refresh timings, which may make up for the normal refresh operation not performed to perform the row hammering refresh operation RR at the third and fourth refresh timings.

[0074] exist Figure 14 In the exemplary embodiment shown, the second normal refresh operation NR2 may also be performed at the sixth refresh timing and the seventh refresh timing. Figure 10 Compared to the example embodiment shown in , power consumption may further increase; however, by increasing the number of executions of the second normal refresh operation NR2, the number of refreshes of memory cells connected to each word line may be increased, and data stability may be improved.

[0075] Figure 15 is a flow chart illustrating the operation of an integrated circuit device according to an example embodiment. Figure 15 The operation of the integrated circuit device according to example embodiments may begin with the integrated circuit device receiving a command signal and an address signal from a memory controller (S20). The integrated circuit device may be a memory device that stores data and may perform a control operation according to the command signal and the address signal (S21). The control operation may include a write operation to save data, a read operation to output the stored data to the memory controller, and a refresh operation to rewrite the stored data.

[0076] When performing the control operation, the logic circuit of the integrated circuit device may determine whether the refresh timing has arrived (S22). If it is determined that the refresh timing has not arrived, the logic circuit of the integrated circuit device may process the control operation according to the command signal and address signal received from the memory controller (S20-S21). On the other hand, when it is determined that the refresh timing has arrived, the logic circuit may determine whether a row hammer address exists in a queue arranged in the peripheral circuit area (S23). The row hammer address may include at least one of the address of the attacking word line that caused the row hammer phenomenon and the address of a victim word line adjacent to the attacking word line.

[0077] As a result of the determination in operation S23, if the row hammer address is not present in the queue, the logic circuit may perform a first normal refresh operation (S24). In the first normal refresh operation, the logic circuit of the integrated circuit device may activate at least one of the plurality of word lines and perform a refresh operation of reading data from and rewriting data in memory cells connected to the activated word line. In an example embodiment, in the first normal refresh operation, n word lines may be activated at once (n is a natural number of 2 or greater).

[0078] On the other hand, if the row hammer address is present in the queue as determined in operation S23, the logic circuit of the integrated circuit device may perform a row hammer (RH) refresh operation (S25). In the row hammer refresh operation, the logic circuit may refer to the row hammer address stored in the queue and designate a victim word line adjacent to the aggressor word line as a target word line. For example, the logic circuit of the integrated circuit device may designate a pair of victim word lines adjacent to the aggressor word line as target word lines.

[0079] In an example embodiment, in a row hammer refresh operation, target word lines may be activated one at a time. For example, the logic circuit of the integrated circuit device may activate a first victim word line adjacent to the aggressor word line at a first refresh timing and overwrite data in memory cells connected to the first victim word line. At a second refresh timing immediately following the first refresh timing, the logic circuit of the integrated circuit device may activate a second victim word line adjacent to the aggressor word line and overwrite data in memory cells connected to the second victim word line.

[0080] When the row hammer refresh operation is completed, the row hammer address stored in the queue before the row hammer refresh operation is performed may be deleted from the queue. Alternatively, the logic circuit may determine whether the row hammer address remains in the queue (S26). Assuming that the first row hammer address and the second row hammer address are stored in the queue in operation S23, the first row hammer address may be deleted from the queue when the row hammer refresh operation is completed. Therefore, the second row hammer address stored in the queue may be detected in operation S26.

[0081] If it is determined in operation S26 that the row hammer address is stored in the queue, the logic circuit may additionally perform a row hammer refresh operation (S25). On the other hand, if it is determined in operation S26 that the row hammer address is not stored in the queue, the logic circuit may perform a second normal refresh operation at the next refresh timing (S27). The second normal refresh operation is similar to the first normal refresh operation, but the number of word lines activated at one time in the second normal refresh operation may be greater than the number of word lines activated at one time in the first normal refresh operation.

[0082] For example, the logic circuit may simultaneously activate m word lines (m is a natural number greater than n) in the second normal refresh operation. In this way, by simultaneously activating a greater number of word lines in the second normal refresh operation than in the first normal refresh operation, the first normal refresh operation that was not performed at the first refresh timing and the second refresh timing can be compensated.

[0083] In reference Figure 15In the described example embodiment, each time the row hammer refresh operation is performed in operation S25, the value stored in the counter included in the peripheral circuit region may be increased by 1. As previously explained, the row hammer refresh operation is performed by activating a pair of victim word lines one by one, and therefore, in the case where the row hammer refresh operation is performed while refresh timing occurs twice, the value stored in the counter may be increased by 1.

[0084] In operation S27, each time the second normal refresh operation is performed twice, the logic circuit of the integrated circuit device decrements the value stored in the counter by 1. After the second normal refresh operation is performed, it can be determined whether the value stored in the counter is 0 (S28). As described above, in the second normal refresh operation, a larger number of word lines can be activated simultaneously compared to the first normal refresh operation. For example, the number of word lines activated at one time in the second normal refresh operation can be twice the number of word lines activated at one time in the first normal refresh operation, and by performing the second normal refresh operation twice, the first normal refresh operation that was skipped due to the row hammer refresh operation can be compensated. Therefore, when the second normal refresh operation is performed while the refresh timing has passed twice, the value stored in the counter can be decreased by 1.

[0085] If the value stored in the counter is 0, the logic circuit can determine that all first normal refresh operations that were skipped to perform the row hammer refresh operation have been compensated. Therefore, the first normal refresh operation can be executed starting from the next refresh timing (S24). On the other hand, if the value stored in the counter is greater than 0, the second normal refresh operation can be further executed (S27) until the value stored in the counter becomes 0.

[0086] Figure 16 is a diagram illustrating the operation of an integrated circuit device according to example embodiments.

[0087] Reference Figure 16 After the first time point T1, each time a refresh timing arrives at a predetermined refresh period TC, a refresh operation can be performed in the integrated circuit device. The refresh operation can be selected between the normal refresh operation and the row hammer refresh operation according to whether the row hammer address is stored in the queue QUEUE.

[0088] Similar to the previous reference Figure 10 In the example embodiment described above, the row hammering address may be stored in the queue at the second time point T2. Therefore, the first normal refresh operation NR1 may be performed at each of the first refresh timing and the second refresh timing, and the row hammering refresh operation RR may be performed at each of the third refresh timing and the fourth refresh timing. In addition, when the row hammering refresh operation RR is performed at each of the third refresh timing and the fourth refresh timing, the value stored in the counter CNT may be incremented from 0 to 1.

[0089] The second normal refresh operation NR2 may be performed at each of the fifth and sixth refresh timings, and this may be performed to compensate for the normal refresh operation not being performed at the third and fourth refresh timings so that the row hammering refresh operation RR may be performed instead.

[0090] In an example embodiment, the number of word lines activated at one time in the second normal refresh operation NR2 may be twice the number of word lines activated at one time in the first normal refresh operation NR1. Therefore, the first normal refresh operation not performed at the third refresh timing and the fourth refresh timing may be compensated by the second normal refresh operation NR2 performed at the fifth refresh timing and the sixth refresh timing, respectively.

[0091] At a fourth time point T4 after the sixth refresh timing, the value stored in the counter CNT may be decreased back to 0. After the fourth time point T4, since the value stored in the counter CNT is 0 and no row hammer address is stored in the queue QUEUE, the logic circuit of the integrated circuit device may perform the first normal refresh operation NR1 again at each refresh timing.

[0092] Figure 17 is a diagram illustrating the operation of an integrated circuit device according to an example embodiment. Figure 17 After a first time point T1, each time a refresh timing arrives at a predetermined refresh period TC, a refresh operation can be performed in the integrated circuit device. A refresh operation can be selected from normal refresh operations NR1 and NR2 and a row hammer refresh operation RR based on whether a row hammer address is stored in the queue QUEUE. Furthermore, one of the first normal refresh operation NR1 and the second normal refresh operation NR2 can be selected based on a value stored in a counter CNT. The value stored in the counter CNT can increase the number of times the row hammer refresh operation RR is performed and decrease the number of times the second normal refresh operation NR2 is performed.

[0093] Reference Figure 17 , the first row hammer address and the second row hammer address may be stored in the queue QUEUE at the second time point T2. Therefore, the first normal refresh operation NR1 may be performed at each of the first refresh timing and the second refresh timing, and the row hammer refresh operation RR based on the first row hammer address may be performed at each of the third refresh timing and the fourth refresh timing. When the row hammer refresh operation RR is performed at each of the third refresh timing and the fourth refresh timing, the value stored in the counter CNT at the third time point T3 may be increased to 1. On the other hand, at the third time point T3, the first row hammer address stored in the queue may be deleted.

[0094] A row hammer refresh operation RR based on the second row hammer address may be performed at each of the fifth and sixth refresh timings. At the fourth time point T4, after the sixth refresh timing has elapsed, the second row hammer address stored in the queue QUEUE may also be deleted. Furthermore, since the row hammer refresh operation RR is performed at the third to sixth refresh timings, the value stored in the counter CNT may be set to 2 at the fourth time point T4.

[0095] Considering the situation where there are no remaining row hammer addresses in the queue QUEUE, the logic circuit of the integrated circuit device may execute a normal refresh operation instead of the row hammer refresh operation RR starting from the seventh refresh timing after the fourth time point T4. In addition, the logic circuit may execute a second normal refresh operation NR2 until the value stored in the counter CNT becomes 0, which can be used to compensate for the first normal refresh operation NR1 that was skipped in order to execute the row hammer refresh operation RR in the third to sixth refresh timings.

[0096] Refer again Figure 17 , after the second normal refresh operation NR2 is performed at each of the seventh refresh timing and the eighth refresh timing, the value stored in the counter CNT at the fifth time point T5 can be decremented from 2 to 1. As described above, by performing the second normal refresh operation NR2 twice, the first normal refresh operation NR1 that was skipped due to the row hammer refresh operation RR on a pair of victim word lines adjacent to an attacking word line can be compensated. Therefore, by performing the second normal refresh operation NR2 at the seventh refresh timing and the eighth refresh timing, the first normal refresh operation NR1 that was skipped due to the row hammer refresh operation RR previously performed at the third refresh timing and the fourth refresh timing can be compensated, and the value stored in the counter CNT can be decremented by 1.

[0097] Next, the second normal refresh operation NR2 may be performed at each of the ninth refresh timing and the tenth refresh timing, and the value stored in the counter CNT may be subtracted from 1 to obtain 0. Therefore, at the sixth time point T6, since the value stored in the counter CNT is 0 and the row hammer address is not stored in the queue QUEUE, the logic circuit may perform the first normal refresh operation NR1 again.

[0098] Table 1 below can be a diagram showing the occurrence of line hammering Figure 17 FIG1 is a table of word lines refreshed at each refresh timing in an example embodiment of FIG1 and in a case where row hammering does not occur. In Table 1, the first victim word line VR1 and the second victim word line VR2 are word lines adjacent to the attacking word line of the first row hammering address, and the third victim word line VR3 and the fourth victim word line VR4 may be word lines adjacent to the attacking word line of the second row hammering address.

[0099] In the first normal refresh operation NR1, two word lines can be activated at a time, and in the second normal refresh operation NR2, four word lines can be activated at a time. As shown in Table 1, by determining the number of executions of the second normal refresh operation NR2 based on the value stored in the counter CNT, the skipping of the first normal refresh operation NR1 due to the row hammering refresh operation RR can be compensated. In addition, by limiting the number of executions of the second normal refresh operation NR2 to the required number, power consumption during refresh operations can be effectively managed.

[0100] [Table 1]

[0101] Refresh Timing Hammering occurs ( Figure 17 ) No hammering occurs 1st WL1, WL2 WL1, WL2 2nd WL3, WL4 WL3, WL4 3rd VR1 WL5, WL6 4th VR2 WL7, WL8 5th VR3 WL9, WL10 6th VR4 WL11, WL12 7th WL5-WL8 WL13, WL14 8th WL9-WL12 WL15, WL16 9th WL13-WL16 WL17, WL18 No. 10 WL17-WL20 WL19, WL20 11th WL21, WL22 WL21, WL22

[0102] Therefore, if Figure 17 As shown, the first normal refresh operation NR1 may be performed when the value stored in the counter CNT is 0 and the queue QUEUE is empty. On the other hand, the second normal refresh operation NR2 may be performed when the value stored in the counter CNT is greater than 0.

[0103] Figure 18 is a diagram illustrating the operation of an integrated circuit device according to an example embodiment. Figure 18 After a first time point T1, each time a refresh timing arrives at a predetermined refresh period TC, a refresh operation can be performed in the integrated circuit device. A refresh operation can be selected from normal refresh operations NR1 and NR2 and a row hammer refresh operation RR based on whether a row hammer address is stored in the queue QUEUE. Furthermore, one of the first normal refresh operation NR1 and the second normal refresh operation NR2 can be selected based on a value stored in a counter CNT. The value stored in the counter CNT can increase the number of times the row hammer refresh operation RR is performed and decrease the number of times the second normal refresh operation NR2 is performed.

[0104] Reference Figure 18 At the second time point T2, the first row hammer address, the second row hammer address, and the third row hammer address may be stored in the queue QUEUE in this order. Therefore, the first normal refresh operation NR1 may be performed at the first refresh timing, and the row hammer refresh operation RR based on the first row hammer address may be performed at each of the second refresh timing and the third refresh timing. When the row hammer refresh operation RR is performed at each of the second refresh timing and the third refresh timing, the value stored in the counter CNT at the third time point T3 may be increased to 1. On the other hand, the first row hammer address stored in the queue QUEUE may be deleted at the third time point T3.

[0105] A row hammer refresh operation RR based on the second row hammer address may be performed at each of the fourth refresh timing and the fifth refresh timing. At the fourth time point T4, after the fifth refresh timing has elapsed, the second row hammer address stored in the queue QUEUE may also be deleted. In addition, since the row hammer refresh operation RR is performed at the second to fifth refresh timings, the value stored in the counter CNT may be set to 2 at the fourth time point T4.

[0106] exist Figure 18 In the illustrated example embodiment, when the value stored in the counter CNT reaches a predetermined reference value, the logic circuit of the integrated circuit device may perform a normal refresh operation regardless of whether the row hammer address is stored in the queue QUEUE. Figure 17 Similar to the example embodiments described, Figure 18 In the illustrated example embodiment, the value stored in the counter CNT may be increased by 1 according to the number of executions of the row hammering refresh operation RR, and may be decreased by 1 according to the number of executions of the second normal refresh operation NR2. Therefore, a case where the value stored in the counter CNT reaches a predetermined reference value may indicate that the number of consecutive executions of the row hammering refresh operation RR has reached the predetermined reference number.

[0107] For example, when the number of consecutive executions of the row hammer refresh operation RR reaches a reference number, and when the value stored in the counter CNT reaches a predetermined reference value, the logic circuit may execute the second normal refresh operation NR2 regardless of the state of the queue QUEUE. For example, the second normal refresh operation NR2 may be executed continuously until the value stored in the counter CNT becomes 0. Specifically, the logic circuit may execute the second normal refresh operation NR2 continuously as many times as the row hammer refresh operation RR is executed continuously.

[0108] Still refer to Figure 18 , although the third row hammering address is stored in the queue QUEUE at the fourth time point T4, the logic circuit may perform the second normal refresh operation NR2 instead of the row hammering refresh operation RR starting from the sixth refresh timing. Figure 18 As shown, the second normal refresh operation NR2 may be continuously performed as many times as the row hammering refresh operation RR has been continuously performed. The second normal refresh operation NR2 is performed as many times as the row hammering refresh operation RR is continuously performed, so that the value stored in the counter CNT at the sixth time point T6 may be reduced to 0.

[0109] When the value stored in the counter CNT decreases to 0, the logic circuit may again refer to the third row hammer address stored in the queue QUEUE and perform a row hammer refresh operation RR. Performing the row hammer refresh operation RR at the tenth and eleventh refresh timings after the sixth time point T6 may cause the value stored in the counter CNT at the seventh time point T7 to increase back to 1. Therefore, at the twelfth and thirteenth refresh timings, the logic circuit may perform a second normal refresh operation NR2. While the second normal refresh operation NR2 is being performed at the twelfth and thirteenth refresh timings, the value stored in the counter CNT at the eighth time point T8 may decrease back to 0.

[0110] When referring to Figure 18 When the refresh operation described above is compared with a case where row hammering does not occur, the results can be shown in Table 2 below. In Table 2, the first victim word line VR1 and the second victim word line VR2 can be word lines adjacent to the attacking word line of the first row hammering address, and the third victim word line VR3 and the fourth victim word line VR4 can be word lines adjacent to the attacking word line of the second row hammering address. The fifth victim word line VR5 and the sixth victim word line VR6 can be word lines adjacent to the attacking word line of the third row hammering address. On the other hand, two word lines can be activated at a time in the first normal refresh operation NR1, and four word lines can be activated at a time in the second normal refresh operation NR2.

[0111] [Table 2]

[0112] Refresh Timing Hammering occurs ( Figure 18 ) No hammering occurs 1st WL1, WL2 WL1, WL2 2nd VR1 WL3, WL4 3rd VR2 WL5, WL6 4th VR3 WL7, WL8 5th VR4 WL9, WL10 6th WL3-WL6 WL11, WL12 7th WL7-WL10 WL13, WL14 8th WL11-WL14 WL15, WL16 9th WL15-WL18 WL17, WL18 No. 10 VR5 WL19, WL20 11th VR6 WL21, WL22 12th WL19-WL22 WL23, WL24 13th WL23-WL26 WL25, WL26

[0113] Refer again Figure 18 The first normal refresh operation NR1 may be performed when the value stored in the counter CNT is 0 and the row hammer address is not stored in the queue QUEUE. On the other hand, the second normal refresh operation NR2 may be performed when the value stored in the counter CNT is greater than 0.

[0114] In various embodiments of the present inventive concept, power consumption and refresh operation performance can be improved by dynamically scheduling refresh operations performed in an integrated circuit device. For example, when row hammering occurs and a row hammering address is stored in a queue, data fluctuation in memory cells connected to the victim word line can be minimized by preferentially performing a row hammering refresh operation at a refresh timing rather than a normal refresh operation.

[0115] In an example embodiment, the number of times a row hammer refresh operation is performed may be stored in a counter, and a refresh operation may be scheduled based on the number of times the row hammer refresh operation is performed. For example, when a row hammer refresh operation is performed, the value stored in the counter may be increased by 1, and when a second normal refresh operation is performed to compensate for the first normal refresh operation that was skipped due to the row hammer refresh operation, the value stored in the counter may be decreased by 1. As described above, when a row hammer refresh operation is performed at two consecutive refresh timings, the value stored in the counter may be increased by 1, and when a second normal refresh operation is performed at two consecutive refresh timings, the value stored in the counter may be decreased by 1.

[0116] In example embodiments, when the value stored in the counter reaches a predetermined reference value, a second normal refresh operation may be performed regardless of whether a row hammering address is stored in the queue, and this may prevent data reliability issues that may occur if (one or more) normal refresh operations are skipped too many times within a relatively long time interval. When the value stored in the counter reaches a predetermined reference value, the second normal refresh operation may be performed until the value stored in the counter decreases to another reference value, and then the row hammering refresh operation or the first normal refresh operation may be performed again.

[0117] As described above, according to example embodiments, a normal refresh operation can be performed every predetermined cycle, and a row hammer refresh operation can be performed when a row hammer address stored in a queue exists. Therefore, the effectiveness of refresh operations can be improved by preventing unnecessary execution of row hammer refresh operations when a row hammer phenomenon is not detected. Furthermore, by counting the number of row hammer refresh operations performed in a row and scheduling normal refresh operations and row hammer refresh operations based on this count, power consumed in refresh operations can be reduced, and protection against row hammering can be effectively ensured.

[0118] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An integrated circuit device comprising: A cell area, wherein a plurality of memory banks are provided, each of the plurality of memory banks includes a corresponding memory cell array, and the memory cell array includes: multiple memory cells, a row decoder connected to the memory cell array through a plurality of word lines; and a sense amplifier circuit connected to the memory cell array via a plurality of bit lines; as well as a peripheral circuit area in which a logic circuit for controlling the plurality of memory banks is disposed; and wherein the logic circuit includes at least one queue configured to store a row hammer address of at least one of the plurality of memory banks, and controls: (i) a target memory bank to perform a row hammer refresh operation in the target memory bank indicated by the row hammer address when the row hammer address stored in the queue exists, and (ii) the plurality of memory banks to perform a normal refresh operation when the row hammer address stored in the queue does not exist.

2. The integrated circuit device according to claim 1, in, The normal refresh operation includes a first normal refresh operation and a second normal refresh operation; wherein the logic circuit is configured to activate n of the plurality of word lines at a time during the first normal refresh operation, and to activate m of the plurality of word lines at a time during the second normal refresh operation; and Here, each of m and n is a natural number of 2 or greater, and n is smaller than m.

3. The integrated circuit device according to claim 2, wherein: The logic circuit is configured to perform the second normal refresh operation at a refresh timing immediately following the row hammer refresh operation.

4. The integrated circuit device according to claim 3, wherein: The logic circuit is configured to perform the second normal refresh operation twice consecutively immediately after the row hammer refresh operation.

5. The integrated circuit device according to claim 1, wherein: The logic circuit includes a plurality of queues corresponding to the plurality of memory banks; and wherein the number of the plurality of memory banks is equal to the number of the plurality of queues.

6. The integrated circuit device according to claim 1, wherein: The logic circuit includes a counter configured to store a number of times the row hammer refresh operation has been continuously performed on at least one of the plurality of memory storage bodies; and wherein, when the number stored in the counter reaches a predetermined reference number, the logic circuit continuously performs the normal refresh operation with the predetermined reference number.

7. The integrated circuit device according to claim 6, wherein: The logic circuit includes a plurality of counters corresponding to the plurality of memory banks; and wherein the number of the plurality of memory banks is equal to the number of the plurality of counters.

8. The integrated circuit device according to claim 6, wherein: The logic circuit is configured to perform a first normal refresh operation of activating n word lines at a refresh timing before the row hammer refresh operation; When the number of times stored in the counter reaches a predetermined reference number, the logic circuit continuously performs a second normal refresh operation of activating m word lines for the predetermined reference number; and wherein m is greater than n.

9. An integrated circuit device comprising: a cell region in which a plurality of memory banks are provided, each of the plurality of memory banks including a memory cell array including a plurality of memory cells, a row decoder connected to the memory cell array through a plurality of word lines, and a sense amplifier circuit connected to the memory cell array through a plurality of bit lines; and a peripheral circuit region configured to: in response to detecting an attacking word line among the plurality of word lines, perform a row hammer refresh operation on each of the plurality of memory banks by refreshing target memory cells connected to a target word line adjacent to the attacking word line; perform a first normal refresh operation of activating n of the plurality of word lines; and perform a second normal refresh operation of activating m of the plurality of word lines, wherein the m number of word lines is greater than the n number of word lines; wherein the peripheral circuit area includes a counter storing the number of times the row hammer refresh operation is performed; and When the execution number stored in the counter is greater than 0, the peripheral circuit region performs the second normal refresh operation until the execution number stored in the counter becomes 0.

10. The integrated circuit device according to claim 9, wherein: n is 2 and m is 4.

11. The integrated circuit device according to claim 9, wherein: The peripheral circuit region is configured to perform one of the row hammering refresh operation, the first normal refresh operation, and the second normal refresh operation for each of the plurality of memory banks when a refresh timing reaches a predetermined refresh cycle.

12. The integrated circuit device according to claim 11, wherein: When the number of consecutive executions of the row hammering refresh operation reaches a predetermined reference number, the peripheral circuit region continuously executes the second normal refresh operation for the number of consecutive executions of the row hammering refresh operation.

13. The integrated circuit device according to claim 11, wherein: Within a refresh window time including a predetermined number of the refresh timings, the row hammering refresh operation is executed a number of times equal to the second normal refresh operation is executed a number of times.

14. The integrated circuit device according to claim 11, wherein: Within a refresh window time including a predetermined number of the refresh timings, the number of executions of the row hammering refresh operation is less than the number of executions of the second normal refresh operation.

15. The integrated circuit device according to claim 9, wherein: The peripheral circuit region includes a queue storing a row hammer address as an address of the attack word line, and performs the row hammer refresh operation when the row hammer address stored in the queue exists.

16. An integrated circuit device comprising: a cell region in which a plurality of memory banks are disposed, each of the plurality of memory banks including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; as well as a peripheral circuit region including a logic circuit configured to perform, for each of the plurality of memory banks: (i) a row hammer refresh operation that detects an aggressor word line among the plurality of word lines and refreshes memory cells connected to victim word lines adjacent to the aggressor word line, and (ii) a normal refresh operation that refreshes memory cells connected to at least one selected word line among the plurality of word lines; wherein the peripheral circuit area includes a queue and a counter, wherein the queue stores a row hammer address indicating at least one of the attacking word line and the victim word line, and the counter stores the number of times the row hammer refresh operation is performed; and The logic circuit is further configured to perform one of the row hammering refresh operation and the normal refresh operation at each refresh timing arriving in a predetermined refresh cycle based on at least one of a state of the queue and a value stored in the counter.

17. The integrated circuit device according to claim 16, wherein: The logic circuit is configured to perform the row hammer refresh operation when the refresh timing arrives while the row hammer address is stored in the queue.

18. The integrated circuit device according to claim 16, wherein: The logic circuit is configured to perform the normal refresh operation when the value stored in the counter is equal to a predetermined reference value.

19. The integrated circuit device according to claim 18, wherein: The logic circuit is configured to perform the normal refresh operation when the value stored in the counter is equal to a predetermined reference value regardless of a state of the queue.

20. The integrated circuit device according to claim 16, wherein The normal refresh operation includes a first normal refresh operation and a second normal refresh operation, wherein the first normal refresh operation includes activating n word lines at a time, and the second normal refresh operation includes activating m word lines, where m is greater than n; And wherein the logic circuit is configured to perform the first normal refresh operation when the queue is empty and the value stored in the counter is 0, and to perform the second normal refresh operation when the value stored in the counter is greater than 0.

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