Memory and operation method thereof, memory system and computer system

Abstract

The embodiment of the invention provides a memory, an operation method thereof, a memory system and a computer system. The memory comprises a memory cell array, the memory cell array comprises M memory bank groups, and each memory bank group comprises N memory banks; a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to: adjust the internal clock signal in response to a first access mode signal, and output a first clock signal; wherein the first clock signal comprises a plurality of spaced first sampling signals; the first access mode signal is used for indicating to access N memory banks; outputting a first data signal in response to a first clock signal and a first local data signal; wherein the first local data signal comprises a plurality of first data periods and a plurality of first interval periods which are alternated; two adjacent first sampling signals are respectively located in the adjacent first data period and the first interval period; and writing the first data signal into a target memory bank in the (M * N) memory banks.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and an operating method thereof, a memory system, and a computer system. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid growth. With the continuous advancement of semiconductor manufacturing processes, the feature size of semiconductor devices has continued to shrink, and the integration density of memory has become increasingly higher, and its performance has become increasingly powerful. For example, dynamic random access memory (DRAM), static random access memory (SRAM), and NAND memory are all commonly used semiconductor memory devices in computers.

[0003] The working mechanism of memory is relatively complex, involving the configuration and adjustment of numerous parameters. As users' demand for memory performance continues to increase, how to improve the compatibility of memory in various usage scenarios has become a pressing issue for the industry. Summary of the Invention

[0004] The present disclosure provides a memory and an operating method thereof, a memory system, and a computer system.

[0005] In a first aspect, the present disclosure provides a memory, comprising:

[0006] A memory cell array, wherein the memory cell array includes M memory bank groups, the memory bank groups include N memory banks, and M and N are both integers greater than 1;

[0007] a peripheral circuit coupled to the memory cell array;

[0008] The peripheral circuit is configured to: adjust an internal clock signal in response to a first access mode signal and output a first clock signal; wherein the first clock signal includes a plurality of spaced first sampling signals; and the first access mode signal is used to indicate access to the N memory banks;

[0009] Outputting a first data signal in response to the first clock signal and the first local data signal; wherein the first local data signal includes a plurality of alternating first data periods and a plurality of first interval periods; and two adjacent first sampling signals are respectively located within adjacent first data periods and first interval periods;

[0010] The first data signal is written into a target memory bank among the (M*N) memory banks.

[0011] In some embodiments, the internal clock signal includes a plurality of initial sampling signals spaced apart; the peripheral circuit includes a timing control circuit, and the timing control circuit is configured to:

[0012] adjusting a pulse width of the initial sampling signal in response to the first access mode signal;

[0013] The first clock signal is output in response to the adjusted pulse width of the initial sampling signal; wherein a clock period of the first clock signal is the same as a clock period of the internal clock signal.

[0014] In some embodiments, the timing control circuit includes:

[0015] a clock signal pulse width control circuit, the clock signal pulse width control circuit being configured to: reduce a pulse width of the initial sampling signal in response to the first access mode signal;

[0016] A clock signal output circuit is configured to output the first clock signal in response to the reduced pulse width of the initial sampling signal.

[0017] In some embodiments, the clock signal pulse width control circuit includes: a chopper circuit or a logic gate circuit.

[0018] In some embodiments, the logic gate circuit includes at least one of an AND gate, a NOR gate, a NOT gate, and a NAND gate.

[0019] In some embodiments, the timing control circuit is further configured to:

[0020] adjusting a delay time of the initial sampling signal in response to the first access mode signal;

[0021] The first clock signal is output in response to the adjusted delay time of the initial sampling signal.

[0022] In some embodiments, the timing control circuit is further configured to:

[0023] In response to a second access mode signal, the internal clock signal is adjusted and a second clock signal is output; wherein the second clock signal includes a plurality of spaced second sampling signals; and the second access mode signal is used to indicate access to the M memory bank groups;

[0024] The peripheral circuit is further configured to: output a second data signal in response to the second clock signal and the second local data signal; wherein the second local data signal includes a plurality of alternating second data periods and a plurality of second interval periods, the second data period is greater than the first data period, and the second interval period is greater than the first interval period; and two adjacent second sampling signals are respectively located within adjacent second data periods and second interval periods;

[0025] The second data signal is written into a target memory bank group among the M memory bank groups.

[0026] In some embodiments, the timing control circuit is specifically configured as follows:

[0027] delaying the internal clock signal in response to the second access mode signal;

[0028] In response to the delayed initial sampling signal, the second clock signal is output; wherein a clock period of the second clock signal is the same as a clock period of the internal clock signal.

[0029] In some embodiments, the timing control circuit includes:

[0030] A clock signal input circuit is configured to output the internal clock signal in response to a bank clock signal and an activation signal.

[0031] In some embodiments, the memory includes a fourth generation double data rate synchronous dynamic random access memory, a fifth generation double data rate synchronous dynamic random access memory, or an external random access memory.

[0032] In a second aspect, the present disclosure provides a method for operating a memory, wherein the memory includes a memory cell array, the memory cell array includes M memory bank groups, the memory bank groups include N memory banks, and M and N are both integers greater than 1; the operating method includes:

[0033] In response to a first access mode signal, the internal clock signal is adjusted and a first clock signal is output; wherein the first clock signal includes a plurality of first sampling signals spaced apart; and the first access mode signal is used to indicate access to the N memory banks;

[0034] Outputting a first data signal in response to the first clock signal and the first local data signal; wherein the first local data signal includes a plurality of alternating first data periods and a plurality of first interval periods; and two adjacent first sampling signals are respectively located within adjacent first data periods and first interval periods;

[0035] The first data signal is written into a target memory bank among the (M*N) memory banks.

[0036] In some embodiments, the internal clock signal includes a plurality of initial sampling signals spaced apart; and adjusting the internal clock signal in response to the first access mode signal and outputting the first clock signal comprises:

[0037] adjusting a pulse width of the initial sampling signal in response to the first access mode signal;

[0038] The first clock signal is output in response to the adjusted pulse width of the initial sampling signal; wherein a clock period of the first clock signal is the same as a clock period of the internal clock signal.

[0039] In some embodiments, adjusting the pulse width of the initial sampling signal in response to the first access mode signal includes:

[0040] In response to the first access mode signal, reducing the pulse width of the initial sampling signal;

[0041] Outputting the first clock signal in response to the adjusted pulse width of the initial sampling signal comprises:

[0042] The first clock signal is output in response to the reduced pulse width of the initial sampling signal.

[0043] In some embodiments, adjusting the internal clock signal in response to the first access mode signal and outputting the first clock signal includes:

[0044] adjusting a delay time of the initial sampling signal in response to the first access mode signal;

[0045] The first clock signal is output in response to the adjusted delay time of the initial sampling signal.

[0046] In some embodiments, the operating method further includes:

[0047] In response to a second access mode signal, the internal clock signal is adjusted and a second clock signal is output; wherein the second clock signal includes a plurality of spaced second sampling signals; and the second access mode signal is used to indicate access to the M memory bank groups;

[0048] outputting a second data signal in response to the second clock signal and the second local data signal; wherein the second local data signal includes a plurality of alternating second data periods and a plurality of second interval periods, the second data period is greater than the first data period, and the second interval period is greater than the first interval period; and two adjacent second sampling signals are respectively located within adjacent second data periods and second interval periods;

[0049] The second data signal is written into a target memory bank group among the M memory bank groups.

[0050] In some embodiments, adjusting the internal clock signal in response to the second access mode signal and outputting the second clock signal includes:

[0051] delaying the internal clock signal in response to the second access mode signal;

[0052] In response to the delayed initial sampling signal, the second clock signal is output; wherein a clock period of the second clock signal is the same as a clock period of the internal clock signal.

[0053] In some embodiments, the operating method further includes:

[0054] The internal clock signal is output in response to a bank clock signal and an activation signal.

[0055] In a third aspect, the present disclosure provides a memory system, comprising:

[0056] The memory according to any one of the above embodiments;

[0057] A memory controller is coupled to the memory; the memory controller is configured to control the memory.

[0058] In a fourth aspect, the present disclosure provides a computer system, comprising:

[0059] The memory system described in the above embodiment;

[0060] A host is coupled to the memory system.

[0061] In the disclosed embodiment, the peripheral circuit adjusts the internal clock signal in response to a first access mode signal and outputs the first clock signal. The peripheral circuit then outputs a first data signal in response to the first clock signal and a first local data signal, wherein the first local data signal includes alternating first data cycles and first interval cycles, and two adjacent first sampling signals in the first clock signal are respectively located within adjacent first data cycles and first interval cycles. Finally, the peripheral circuit writes the first data signal to a target memory bank. In this way, the peripheral circuit can adjust the timing of the internal clock signal in response to the first access mode signal, thereby meeting the write timing requirements of the memory in a direct access mode to the memory bank, thereby improving the memory's compatibility with various access modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of a memory provided in an embodiment of the present disclosure;

[0063] Figure 2 A timing diagram of various signals of a memory in a memory bank group mode provided by an embodiment of the present disclosure;

[0064] Figure 3 A timing diagram of various signals of a memory in 16-bank mode provided by an embodiment of the present disclosure;

[0065] Figure 4 A schematic diagram of another memory provided by an embodiment of the present disclosure;

[0066] Figure 5 A timing diagram of various signals of another memory in 16-bank mode provided by an embodiment of the present disclosure;

[0067] Figure 6 A schematic diagram of another timing control circuit in a memory provided by an embodiment of the present disclosure;

[0068] Figure 7 A schematic diagram of a chopper circuit in a timing control circuit provided by an embodiment of the present disclosure;

[0069] Figure 8 A schematic diagram of a logic gate circuit in a timing control circuit provided by an embodiment of the present disclosure;

[0070] Figure 9 A timing diagram of various signals of a logic gate circuit in a timing control circuit provided by an embodiment of the present disclosure;

[0071] Figure 10 A flowchart of a method for operating a memory provided by an embodiment of the present disclosure;

[0072] Figure 11 A schematic diagram of a memory system and a computer system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0075] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0076] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0078] In some embodiments, the memory includes, but is not limited to, a fourth-generation double data rate synchronous dynamic random access memory (Double Data Rate 4th-generation Synchronous DRAM, DDR4), a fifth-generation double data rate synchronous dynamic random access memory (Double Data Rate 5th-generation Synchronous DRAM, DDR5), or an external random access memory (on-chip expanded RAM, XRAM), etc. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, and the memory cell array may include a plurality of memory banks. It should be noted that the memory cell array in the present disclosure refers to a collection of all memory cells arranged in an array, and the memory cell array may include multiple sub-arrays, and multiple sub-arrays sharing the same set of word lines (WL) and the same set of bit lines (BL) constitute a memory bank, so the memory cell array may include several memory banks. Exemplarily, the number of memory banks in the memory may be 4, 8, 16, or other numbers.

[0079] In order to meet the requirements of memory read speed, write speed, and operating frequency in different usage scenarios, multiple mode registers (MRs) are set in the peripheral circuit of the memory. The mode registers are used to control different functions and operating modes of the memory. For example, the mode register can control the access mode of the memory, where the access mode includes but is not limited to 8-bank access mode (8B mode), 16-bank access mode (16B mode), and bank group access mode (BG mode). In the 8-bank access mode and 16-bank access mode, the peripheral circuit can address and access each bank individually; while in the bank group access mode, the peripheral circuit can address and access a bank group (Bank Group) containing multiple banks. For example, each bank group can include the same number of banks. Compared to the 16-bank access mode, in which the peripheral circuit accesses 16 banks individually, in the bank group access mode, the peripheral circuit can access 4 bank groups, and each bank group includes 4 banks. It should be noted that the 16-bank access mode is generally enabled in low-speed memory application scenarios (such as frequency less than or equal to 3200MHz), while the bank group access mode is generally enabled in high-speed memory application scenarios (such as frequency greater than or equal to 3200MHz).

[0080] In some embodiments, as Figure 1As shown, the memory 100 includes a memory cell array 110 and a peripheral circuit 120 coupled to the memory cell array 110. The memory cell array 110 includes M memory bank groups, each memory bank group includes N memory banks. The peripheral circuit 120 may include a local bank control circuit (LBC), which can generate a data clock signal based on a write clock signal in the memory to sample a local data signal, thereby generating and outputting a data signal to be written to a target memory bank. Specifically, refer to Figure 1 , the local storage control circuit includes:

[0081] The local bank write clock generating circuit 123 (Local Bank WR CK Generator) is configured to output a bank clock signal bk_ck according to the received bank address bk_address and the write clock signal wr_ck. Here, the bank address bk_address may be used to indicate a target bank to which a write operation is to be performed.

[0082] The clock signal input circuit 124 (DL CK Generator) is coupled to the local bank write clock generating circuit 123 . The clock signal input circuit 124 is configured to receive the bank clock signal bk_ck and output an internal clock signal in_ck according to the bank clock signal bk_ck and an activation signal dl_actv.

[0083] The timing control circuit 121 is coupled to the clock signal input circuit 124. The timing control circuit 121 is used to adjust the timing (including pulse width and delay, etc.) of the internal clock signal in_ck, thereby outputting a data clock signal dl_ck for data sampling. Specifically, the timing control circuit 121 includes a clock delay circuit 125 (DLY) and a clock signal output circuit 126 (DL CK Widener). The clock delay circuit 125 is coupled to the clock signal input circuit 124 and is used to delay the internal clock signal in_ck. The clock signal output circuit 126 is coupled to the clock delay circuit 125 and is used to adjust the pulse width of the delayed internal clock signal in_ck, such as increasing the pulse width of the internal clock signal in_ck, thereby outputting the data clock signal dl_ck. This is because the pulse width of the data clock signal required for data sampling when writing data to the target memory is larger, while the pulse width of the clock signal initially provided by the peripheral circuit (such as the write clock signal wr_ck) is smaller. Here, the data clock signal dl_ck may include a plurality of sampling signals at intervals (ie, high-level pulses of the data clock signal dl_ck), thereby implementing sampling of the local data signal lbdl.

[0084] The data sampling circuit 122 (Data Sampler) is coupled to the clock signal output circuit 126 . The data sampling circuit 122 can utilize the data clock signal dl_ck to sample the local data signal lbdl, thereby outputting a data signal dl.

[0085] The peripheral circuit 120 may further include a control logic circuit 127, and the control logic circuit 127 is configured to write the data signal d1 into a target memory bank among the (M*N) memory banks.

[0086] In some embodiments, regardless of whether the memory access mode determined by the mode register is a 16-bank access mode or a bank group access mode, the local bank control circuit in the peripheral circuit 120 uses the same timing strategy for data sampling. Figure 2 FIG. 1 shows a timing diagram of the local data signal lbdl, the data clock signal dl_ck, and the data signal dl in the bank group access mode. In the bank group access mode, the interval period tCCD of the local data signal lbdl can be four clock cycles tCK (tCK = 2.5 ns). Two adjacent sampling signals (high level of dl_ck) of the data clock signal dl_ck output by the timing control circuit 121 in the peripheral circuit 120 can fall within the data period (high level of lbdl) and the interval period (low level of lbdl), respectively, of the local data signal lbdl. It should be noted that the local data signal lbdl is continuously sampled during the sampling signal period (i.e., the high level period of dl_ck). That is, if the local data signal lbdl is high during the high level period of dl_ck, the output data signal dl is high; if the local data signal lbdl is low, the output data signal dl is low. That is, at the beginning (rising edge) of the previous sampling signal S1 of the data clock signal dl_ck, the high level corresponding to the data cycle of the local data signal lbdl can be sampled, thereby causing the output data signal dl to jump from a low level to a high level. At the end (falling edge) of the previous sampling signal S1 of the data clock signal dl_ck, the local data signal lbdl remains high, so the output data signal dl also remains high. At the beginning (rising edge) of the next sampling signal S2 of the data clock signal dl_ck, the low level corresponding to the interval cycle of the local data signal lbdl can be sampled, thereby causing the output data signal dl to jump from a high level to a low level. At the end (falling edge) of the next sampling signal S2 of the data clock signal dl_ck, the local data signal lbdl remains low, thereby causing the output data signal dl to jump from a high level to a low level. In this way, the data clock signal dl_ck can normally sample the local data signal lbdl in the bank group access mode, thereby generating the correct data signal dl.

[0087] like Figure 3 FIG. 1 shows a timing diagram of the local data signal lbdl, the data clock signal dl_ck, and the data signal dl in the 16-bank access mode. In the bank group access mode, the interval period tCCD of the local data signal lbdl can be two clock cycles tCK. The two adjacent sampling signals (high level of dl_ck) of the data clock signal dl_ck output by the timing control circuit 121 in the peripheral circuit 120 do not exactly fall within the data period (high level of lbdl) and the interval period (low level of lbdl) of the local data signal lbdl. In other words, at the beginning (rising edge) of the first sampling signal S1 of the data clock signal dl_ck, the high level corresponding to the data period of the local data signal lbdl can be sampled, thereby causing the output data signal dl to jump from a low level to a high level. However, within the duration of the first sampling signal S1, the data period of the local data signal lbdl ends and enters the interval period, i.e., the local data signal lbdl jumps from a high level to a low level, and thus the output data signal dl jumps from a high level to a low level (see FIG. 1 ). Figure 3 When the first sampling signal S1 ends (falling edge), the local data signal lbdl still maintains a low level, so the output data signal dl also maintains a low level; similarly, when the second sampling signal S2 starts, the local data signal lbdl is low, and the data signal dl maintains a low level; but during the duration of the second sampling signal S2, the local data signal lbdl jumps from a low level to a high level, so the output data signal dl jumps from a low level to a high level (refer to Figure 3 At the end of the second sampling signal S2, the local data signal lbdl is high, and the data signal dl remains high. During the duration of the third sampling signal S3, the local data signal lbdl transitions from high to low, and the data signal dl transitions from high to low. As a result, the data clock signal dl_ck cannot properly sample the local data signal lbdl in the 16-bank access mode, and thus cannot generate the correct data signal dl.

[0088] It is understandable that Figure 1 The illustrated memory 100 uses the same timing strategy for data sampling in both the 16-bank access mode and the bank group access mode. Although the memory 100 can meet the write timing requirements in the bank group access mode and thus perform data sampling normally, data sampling errors may occur in the 16-bank access mode. Therefore, the memory 100 is not compatible with various access modes.

[0089] like Figure 4As shown, the present disclosure provides a memory 200, comprising: a memory cell array 210, wherein the memory cell array 210 comprises M memory bank groups, wherein the memory bank group comprises N memory banks, wherein M and N are both integers greater than 1; a peripheral circuit 220, wherein the peripheral circuit 220 is coupled to the memory cell array 210; the peripheral circuit 220 is configured to: adjust the internal clock signal in_ck in response to a first access mode signal mod_sig_1, and output a first clock signal dl_ck_1; wherein the first clock signal dl_ck_1 comprises a plurality of first intervals. sampling signal; the first access mode signal mod_sig_1 is used to indicate access to the N storage bodies; a first data signal dl_1 is output in response to the first clock signal dl_ck_1 and the first local data signal lbdl_1; wherein the first local data signal lbdl_1 includes a plurality of alternating first data cycles and a plurality of first interval cycles; two adjacent first sampling signals are respectively located in adjacent first data cycles and first interval cycles; the first data signal dl_1 is written into a target storage body among the (M*N) storage bodies.

[0090] In some embodiments, the memory 200 includes a fourth generation double data rate synchronous dynamic random access memory, a fifth generation double data rate synchronous dynamic random access memory, or an external random access memory.

[0091] In the disclosed embodiment, memory 200 includes a memory cell array 210 and peripheral circuits 220. Peripheral circuits 220 include a local bank control circuit LBC. Local bank control circuit LBC generates a data clock signal based on a write clock signal within the memory, samples the local data signal, and thereby generates and outputs a data signal to be written to a target bank. Memory 200 includes, but is not limited to, a fourth-generation double-data-rate synchronous dynamic random access memory (DDRSDRAM), a fifth-generation double-data-rate synchronous dynamic random access memory (DDRSDRAM), or an external random access memory. It should be noted that memory 200 can be any memory that supports both a 16-bank access mode and a bank group access mode, without further limitation.

[0092] The local bank control circuit LBC in the peripheral circuit 220 can adjust the internal clock signal in_ck in response to the first access mode signal mod_sig_1 to output the first clock signal dl_ck_1. The first clock signal dl_ck_1 includes a plurality of first sampling signals (high level of dl_ck_1) spaced apart. The first access mode signal mod_sig_1 can be an indication signal in the peripheral circuit 220 for transmission to the mode register. Specifically, the first access mode signal mod_sig_1 can instruct the mode register to switch the access mode of the memory to the 16-bank access mode in the above embodiment. The first access mode signal mod_sig_1 can be a continuous high-level signal. The generation process of the internal clock signal in_ck can refer to the above Figure 1 Similar to the local data signal lbdl in the above embodiment, the first local data signal lbdl_1 may include a plurality of alternating first data periods (a high level of lbdl_1) and a plurality of first interval periods tCCD (a low level of lbdl_1). In the 16-bank access mode, the first interval period tCCD may be two clock cycles tCK.

[0093] like Figure 5 Figure 2 shows a timing diagram of the first local data signal lbdl_1, the first clock signal dl_ck_1, and the first data signal dl_1 in 16-bank access mode. The local bank control circuit LBC in the peripheral circuit 220 can adjust the delay duration, pulse width, and other parameters of the internal clock signal in_ck in response to the first access mode signal mod_sig_1, so that two adjacent first sampling signals (a high level of dl_ck_1) of the output first clock signal dl_ck_1 fall within the first data cycle and first interval cycle of the first local data signal lbdl_1, respectively. In this way, the first clock signal dl_ck_1 can properly sample the first local data signal lbdl_1 in 16-bank access mode, thereby generating a correct first data signal dl_1. It should be noted that the local bank control circuit LBC in the peripheral circuit 220 can include any form of logic circuitry to implement the function of adjusting the delay duration and pulse width of the internal clock signal in_ck. The local bank control circuit LBC may further include a data sampling circuit 222 (Data Sampler). The data sampling circuit 222 may use the first clock signal dl_ck_1 to sample the first local data signal lbdl_1, thereby outputting the first data signal dl_1. The peripheral circuit 220 may further include a control logic circuit 227 (Control Logic), which is configured to write the first data signal dl_1 to a target bank among the (M*N) banks.

[0094] It will be appreciated that, in the present disclosure, by introducing the first access mode signal mod_sig_1 originally transmitted to the mode register into the local bank control circuit LBC of the peripheral circuit 220, the local bank control circuit LBC can adjust the internal clock signal in_ck in response to the first access mode signal mod_sig_1, thereby enabling the output first clock signal dl_ck_1 to properly sample the first local data signal lbdl_1 in the 16-bank access mode. In this way, the peripheral circuit 220 can meet the write timing requirements of the memory in the direct bank access mode, thereby improving the memory's compatibility with various access modes. It should be noted that, in the present disclosure, the first access mode signal mod_sig_1 can be input to both the mode register and the bank control circuit LBC simultaneously.

[0095] In some embodiments, the internal clock signal in_ck includes a plurality of initial sampling signals spaced apart; the peripheral circuit 220 includes a timing control circuit 221, and the timing control circuit 221 is configured to: adjust the pulse width of the initial sampling signal in response to the first access mode signal mod_sig_1; output the first clock signal dl_ck_1 in response to the adjusted pulse width of the initial sampling signal; wherein the clock period of the first clock signal dl_ck_1 is the same as the clock period of the internal clock signal in_ck.

[0096] In the disclosed embodiment, the internal clock signal in_ck includes multiple initial sampling signals spaced apart. The initial sampling signals may be high levels of the internal clock signal in_ck. It should be noted that the internal clock signal in_ck and the first clock signal dl_ck_1 have the same clock period. Here, a clock period refers to the period consisting of a high level and a low level in the clock signal. In other words, the timing control circuit 221 does not adjust the clock period of the internal clock signal in_ck.

[0097] Specifically, the timing control circuit 221 can be configured to adjust the pulse width of the initial sampling signal (i.e., a high level in_ck) in the internal clock signal in_ck in response to the first access mode signal mod_sig_1, so that two adjacent first sampling signals (a high level in_ck_1) of the output first clock signal dl_ck_1 fall within the first data cycle and the first interval cycle of the first local data signal lbdl_1, respectively. It will be appreciated that the pulse width of the initial sampling signal adjusted by the timing control circuit 221 is the pulse width of the first sampling signal.

[0098] For example, refer to Figure 3In the corresponding embodiment, the pulse width of the initial sampling signal in the internal clock signal in_ck is the same as the pulse width of the sampling signal in the data clock signal dl_ck. That is, precisely because the pulse width of the initial sampling signal in the internal clock signal in_ck is larger, if the pulse width of the initial sampling signal is not adjusted, then the two adjacent sampling signals of the data clock signal dl_ck output by the timing control circuit cannot accurately fall within the data period (high level of lbdl) and the interval period (low level of lbdl) of the local data signal lbdl. Therefore, referring to Figure 5 After the initial sampling signal in the internal clock signal in_ck undergoes pulse width adjustment by the timing control circuit 221, two adjacent first sampling signals of the first clock signal dl_ck_1 output by the timing control circuit 221 accurately fall within the first data period and the first interval period of the first local data signal lbdl_1. This allows the data sampling circuit 222 to properly sample the first local data signal lbdl_1 using the first clock signal dl_ck_1 and output the first data signal dl_1. In this way, the peripheral circuit 220 can meet the write timing requirements of the memory in the 16-bank access mode, improving the memory's compatibility with various access modes.

[0099] In some embodiments, as Figure 6 As shown, the timing control circuit 221 includes: a clock signal pulse width control circuit 225, and the clock signal pulse width control circuit 225 is configured to: reduce the pulse width of the initial sampling signal in response to the first access mode signal mod_sig_1; a clock signal output circuit 226, and the clock signal output circuit 226 is configured to: output the first clock signal dl_ck_1 in response to the reduced pulse width of the initial sampling signal.

[0100] In the embodiment of the present disclosure, the timing control circuit 221 includes a clock signal pulse width control circuit 225 and a clock signal output circuit 226. The clock signal pulse width control circuit 225 can reduce the pulse width of the initial sampling signal (i.e., in_ck high level) in the internal clock signal in_ck in response to the first access mode signal mod_sig_1. The clock signal pulse width control circuit 225 can be any circuit for reducing the clock signal pulse width, and there are no excessive restrictions here. The clock signal output circuit 226 (DL CK Widener) can refer to Figure 1In the corresponding embodiment, the clock signal output circuit 226 can be used to significantly increase the pulse width of the internal clock signal in_ck. This is because the pulse width of the first clock signal for data sampling required to write data to the target memory bank is relatively large, while the pulse width of the clock signal initially provided by the peripheral circuit (such as the write clock signal wr_ck) is relatively small. It is understandable that the clock signal output circuit 226 cannot accurately adjust the pulse width of the internal clock signal in_ck. Therefore, the present disclosure requires the clock signal pulse width control circuit 225 to accurately reduce the pulse width of the initial sampling signal in the internal clock signal in_ck to meet the write timing requirements in the 16-bank access mode.

[0101] In this way, two adjacent first sampling signals of the first clock signal dl_ck_1 output by the timing control circuit 221 fall within the first data period and the first interval period of the first local data signal lbdl_1, respectively, so that the data sampling circuit 222 can use the first clock signal dl_ck_1 to normally sample the first local data signal lbdl_1 to output the first data signal dl_1.

[0102] In some embodiments, the timing control circuit 221 includes a clock signal input circuit 224 (DL CKGenerator), and the clock signal input circuit 224 is configured to output the internal clock signal in_ck in response to the bank clock signal bk_ck and the activation signal dl_actv.

[0103] In the embodiment of the present disclosure, Figure 6 As shown, the timing control circuit 221 further includes a clock signal input circuit 224, which is used to receive the memory clock signal bk_ck and the activation signal dl_actv, and output the internal clock signal in_ck in response to the memory clock signal bk_ck and the activation signal dl_actv. Figure 1The corresponding embodiment understands the memory clock signal bk_ck. Specifically, the write clock generating circuit 223 (LocalBank WR CK Generator) of the timing control circuit 221 is used to output the memory clock signal bk_ck according to the memory address bk_address and the write clock signal wr_ck. Here, the memory address bk_address can be used to indicate the target memory that needs to be written. Therefore, the memory clock signal bk_ck can be applied to operations related to the target memory. The activation signal dl_actv can control whether the clock signal input circuit 224 outputs the internal clock signal in_ck. It can be understood that in the present disclosure, the pulse widths of the write clock signal wr_ck, the memory clock signal bk_ck and the internal clock signal in_ck are the same, that is, the pulse widths of the three are not adjusted.

[0104] In some embodiments, the clock signal pulse width control circuit 225 includes a chopper circuit or a logic gate circuit.

[0105] In the embodiment of the present disclosure, Figure 7 As shown, the clock signal pulse width control circuit 225 may include a chopper circuit CK_Width_Chopper, which can reduce the pulse width of the initial sampling signal (i.e., in_ck high level) in the internal clock signal in_ck. Specifically, the clock signal pulse width control circuit 225 includes the chopper circuit CK_Width_Chopper and a selector circuit MUX, wherein the two input terminals of the selector circuit MUX are respectively connected to the chopper circuit CK_Width_Chopper and the clock signal input circuit 224, and the selection terminal of the selector circuit MUX is used to receive the first access mode signal mod_sig_1. In this way, the chopper circuit can output the clock signal whose pulse width is reduced by the chopper circuit CK_Width_Chopper, that is, the first clock signal dl_ck_1, when receiving the first access mode signal mod_sig_1 (the input end is at a high level); or, the chopper circuit can output the internal clock signal in_ck when not receiving the first access mode signal mod_sig_1 (the input end is at a low level), that is, without reducing the pulse width of the initial sampling signal in the internal clock signal in_ck.

[0106] like Figure 8 As shown, the clock signal pulse width control circuit 225 may further include a logic gate circuit, and perform various logic operations on the first access mode signal mod_sig_1 and the internal clock signal in_ck to reduce the pulse width of the initial sampling signal in the internal clock signal in_ck, thereby outputting the first clock signal dl_ck_1 with a suitable pulse width.

[0107] In some embodiments, the logic gate circuit includes at least one of an AND gate, a NOR gate, a NOT gate, and a NAND gate.

[0108] In the embodiment of the present disclosure, the logic gate circuit in the clock signal pulse width control circuit 225 includes but is not limited to at least one of an AND gate, a NOR gate, a NOT gate, and a NAND gate. Specifically, Figure 8 As shown, the logic gate circuit in the clock signal pulse width control circuit 225 is composed of a first inverter NOT_g1, a first delay circuit DLY1, a second delay circuit DLY2, a NAND gate NAND_g, a second inverter NOT_g2, a NOR gate NOR_g, a third inverter NOT_g3, and a fourth inverter NOT_g4. Among them, the input end of the first inverter NOT_g1 is used to receive the internal clock signal in_ck, one of the input ends of the NAND gate NAND_g is used to receive the first access mode signal mod_sig_1, and the fourth inverter NOT_g4 is used to output the first clock signal dl_ck_1 after pulse width adjustment. The process of reducing the pulse width of the initial sampling signal in the internal clock signal in_ck by the logic gate circuit can be referred to. Figure 9 It should be noted that the third inverter NOT_g3 and the fourth inverter NOT_g4 do not adjust the pulse width of the clock signal, and the level of the clock signal does not flip after passing through the third inverter NOT_g3 and the fourth inverter NOT_g4. Figure 9 Only the timing of the output signal of NOR gate NOR_g is shown in the figure. It can be seen that if NAND gate NAND_g does not receive the first access mode signal mod_sig_1 (the input terminal is at a low level), the pulse width of the clock signal output by NOR gate NOR_g is large. That is, the pulse width of the clock signal output by NOR gate NOR_g is the same as the pulse width of the internal clock signal in_ck and does not decrease. If NAND gate NAND_g receives the first access mode signal mod_sig_1 (the input terminal is at a high level), the pulse width of the clock signal output by NOR gate NOR_g decreases, so that the two adjacent first sampling signals of the final output first clock signal dl_ck_1 fall within the first data period and the first interval period of the first local data signal lbdl_1, respectively.

[0109] In some embodiments, the timing control circuit 221 is further configured to: adjust the delay time of the initial sampling signal in response to the first access mode signal mod_sig_1; and output the first clock signal dl_ck_1 in response to the adjusted delay time of the initial sampling signal.

[0110] In the disclosed embodiment, the timing control circuit 221 can adjust the delay time of the initial sampling signal in the internal clock signal in_ck in response to the first access mode signal mod_sig_1. Thus, although the timing control circuit 221 does not adjust the pulse width of the initial sampling signal in the internal clock signal in_ck, by adjusting the delay time of the internal clock signal in_ck, it can ensure that two adjacent first sampling signals of the output first clock signal dl_ck_1 fall within the first data cycle and the first interval cycle of the first local data signal lbdl_1, respectively, thereby meeting the write timing requirements of the memory 200 in the 16-bank access mode.

[0111] In some embodiments, the timing control circuit 221 can also respond to the first access mode signal mod_sig_1 and simultaneously adjust the delay time and pulse width of the initial sampling signal in the internal clock signal in_ck, so that the two adjacent first sampling signals of the output first clock signal dl_ck_1 fall within the first data period and the first interval period of the first local data signal lbdl_1 respectively.

[0112] In some embodiments, the timing control circuit 221 is further configured to: adjust the internal clock signal in_ck in response to a second access mode signal and output a second clock signal; wherein the second clock signal includes a plurality of second sampling signals spaced apart; the second access mode signal is used to indicate access to the M memory body groups; the peripheral circuit is further configured to: output a second data signal in response to the second clock signal and a second local data signal; wherein the second local data signal includes a plurality of alternating second data cycles and a plurality of second interval cycles, the second data cycle is greater than the first data cycle, and the second interval cycle is greater than the first interval cycle; two adjacent second sampling signals are respectively located in adjacent second data cycles and second interval cycles; and the second data signal is written into a target memory body group among the M memory body groups.

[0113] In the embodiment of the present disclosure, the timing control circuit 221 can also adjust the internal clock signal in_ck in response to the second access mode signal and output a second clock signal. Here, the second access mode signal can instruct the mode register to switch the access mode of the memory to the memory group access mode in the above embodiment, and the second access mode signal can be a continuous low-level signal. Similar to the first local data signal in the above embodiment, the second local data signal may include alternating multiple second data cycles (high level) and multiple second interval cycles tCCD (low level). In the memory group access mode, the second interval cycle tCCD may be 4 clock cycle periods tCK. It can be understood that the second interval cycle in the memory group access mode is greater than the first interval cycle in the 16-memory access mode, and the second data cycle in the memory group access mode is greater than the first data cycle in the 16-memory access mode. The second clock signal includes multiple second sampling signals (i.e., the high level of the second clock signal) at intervals, and the timing of the second clock signal and the first clock signal can refer to Figure 2 and Figure 3 Understand the data clock signal dl_ck in.

[0114] The timing of the second local data signal, the second clock signal and the second data signal can refer to Figure 2 It is understood that the second local data signal, the second clock signal and the second data signal correspond to Figure 2 In other words, the timing control circuit 221 can also adjust the internal clock signal in_ck to output the second clock signal, and make two adjacent second sampling signals of the second clock signal fall within the adjacent second data period and second interval period, respectively, thereby meeting the write timing requirements of the memory 200 in the bank group access mode and improving the compatibility of the memory with various access modes.

[0115] In some embodiments, the timing control circuit 221 is specifically configured to: delay the internal clock signal in response to the second access mode signal; output the second clock signal in response to the delayed initial sampling signal; wherein the clock period of the second clock signal is the same as the clock period of the internal clock signal.

[0116] In the embodiments of the present disclosure, reference Figure 8 The logic circuit shown in FIG. 2 shows that the timing control circuit 221 can delay the internal clock signal in_ck in response to the second access mode signal (continuous low level) to output the second clock signal. Specifically, Figure 8The input end of the first inverter NOT_g1 is used to receive the internal clock signal in_ck, one input end of the NAND gate NAND_g is used to receive the second access mode signal mod_sig_2, and the fourth inverter NOT_g4 is used to output the second clock signal dl_ck_2. Figure 9 As shown in the timing, when the second access mode signal is at a continuous low level (corresponding to the NAND gate NAND_g not receiving the first access mode signal in the above embodiment), the pulse width of the second clock signal dl_ck_2 finally outputted does not decrease, that is, the second clock signal is obtained only by delaying the internal clock signal in_ck, so the clock period of the second clock signal is the same as the clock period of the internal clock signal in_ck.

[0117] like Figure 10 As shown, the present disclosure provides a method for operating a memory, wherein the memory includes a memory cell array, the memory cell array includes M memory bank groups, the memory bank groups include N memory banks, and M and N are both integers greater than 1; the operating method includes the following steps:

[0118] Step S10: adjusting the internal clock signal in response to the first access mode signal and outputting a first clock signal; wherein the first clock signal includes a plurality of spaced first sampling signals; and the first access mode signal is used to indicate access to the N memory banks;

[0119] Step S20: outputting a first data signal in response to the first clock signal and the first local data signal; wherein the first local data signal includes a plurality of alternating first data periods and a plurality of first interval periods; and two adjacent first sampling signals are respectively located within adjacent first data periods and first interval periods;

[0120] Step S30: Write the first data signal into a target memory bank among the (M*N) memory banks.

[0121] It should be understood that Figure 10 The steps shown in the operations are not exclusive, and other steps may be performed before, after, or between any steps in the operations shown.

[0122] It is understood that the present disclosure adjusts the internal clock signal in response to the first access mode signal, thereby enabling the output first clock signal to properly sample the first local data signal in the 16-bank access mode. In this way, the peripheral circuit can meet the write timing requirements of the memory in the direct bank access mode, thereby improving the memory's compatibility with various access modes.

[0123] In some embodiments, the internal clock signal includes a plurality of initial sampling signals at intervals; the internal clock signal is adjusted in response to the first access mode signal and the first clock signal is output, including: adjusting the pulse width of the initial sampling signal in response to the first access mode signal; outputting the first clock signal in response to the adjusted pulse width of the initial sampling signal; wherein the clock period of the first clock signal is the same as the clock period of the internal clock signal.

[0124] In some embodiments, adjusting the pulse width of the initial sampling signal in response to the first access mode signal includes: reducing the pulse width of the initial sampling signal in response to the first access mode signal; outputting the first clock signal in response to the adjusted pulse width of the initial sampling signal includes: outputting the first clock signal in response to the reduced pulse width of the initial sampling signal.

[0125] In some embodiments, the internal clock signal is adjusted in response to the first access mode signal and the first clock signal is output, including: adjusting the delay time of the initial sampling signal in response to the first access mode signal; and outputting the first clock signal in response to the adjusted delay time of the initial sampling signal.

[0126] In some embodiments, the operating method further includes: adjusting the internal clock signal in response to a second access mode signal and outputting a second clock signal; wherein the second clock signal includes a plurality of spaced second sampling signals; the second access mode signal is used to indicate access to the M memory body groups; outputting a second data signal in response to the second clock signal and a second local data signal; wherein the second local data signal includes a plurality of alternating second data cycles and a plurality of second interval cycles, the second data cycle is greater than the first data cycle, and the second interval cycle is greater than the first interval cycle; two adjacent second sampling signals are respectively located in adjacent second data cycles and second interval cycles; and writing the second data signal into a target memory body group among the M memory body groups.

[0127] In some embodiments, the internal clock signal is adjusted in response to the second access mode signal and the second clock signal is output, including: delaying the internal clock signal in response to the second access mode signal; outputting the second clock signal in response to the delayed initial sampling signal; wherein the clock period of the second clock signal is the same as the clock period of the internal clock signal.

[0128] In some embodiments, the operating method further includes: outputting the internal clock signal in response to a bank clock signal and an activation signal.

[0129] like Figure 11 As shown, the present disclosure provides a memory system 300 , comprising: the memory 200 according to any one of the above embodiments; a memory controller 301 coupled to the memory 200 ; the memory controller 301 is configured to control the memory 200 .

[0130] In the embodiment of the present disclosure, the memory controller 301 is coupled to the memory 200 and is used to control the memory 200 to perform operations such as reading and writing. The memory controller 301 may include a processor, a microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0131] like Figure 11 As shown, the present disclosure provides a computer system 400 , including: the memory system 300 described in the above embodiment; and a host 401 coupled to the memory system 300 .

[0132] In the embodiment of the present disclosure, the host 401 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 401 may be configured to send data to the memory system 300 or receive data from the memory system 300.

[0133] It is understood that the present disclosure adjusts the internal clock signal in response to the first access mode signal, thereby enabling the output first clock signal to properly sample the first local data signal in the 16-bank access mode. In this way, the peripheral circuit can meet the write timing requirements of the memory in the direct bank access mode, thereby improving the memory's compatibility with various access modes.

[0134] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0135] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A memory cell array, wherein the memory cell array includes M memory bank groups, the memory bank groups include N memory banks, and M and N are both integers greater than 1; a peripheral circuit coupled to the memory cell array; The peripheral circuit is configured to: adjust an internal clock signal in response to a first access mode signal and output a first clock signal; wherein the first clock signal includes a plurality of spaced first sampling signals; and the first access mode signal is used to indicate access to the N memory banks; Outputting a first data signal in response to the first clock signal and the first local data signal; wherein the first local data signal includes a plurality of alternating first data periods and a plurality of first interval periods; and two adjacent first sampling signals are respectively located within adjacent first data periods and first interval periods; The first data signal is written into a target memory bank among the (M*N) memory banks.

2. The memory according to claim 1, wherein The internal clock signal includes a plurality of initial sampling signals spaced apart; the peripheral circuit includes a timing control circuit, and the timing control circuit is configured to: adjusting a pulse width of the initial sampling signal in response to the first access mode signal; The first clock signal is output in response to the adjusted pulse width of the initial sampling signal; wherein a clock period of the first clock signal is the same as a clock period of the internal clock signal.

3. The memory according to claim 2, wherein: The timing control circuit includes: a clock signal pulse width control circuit, the clock signal pulse width control circuit being configured to: reduce a pulse width of the initial sampling signal in response to the first access mode signal; A clock signal output circuit is configured to output the first clock signal in response to the reduced pulse width of the initial sampling signal.

4. The memory according to claim 3, wherein: The clock signal pulse width control circuit includes: a chopper circuit or a logic gate circuit.

5. The memory according to claim 4, wherein: The logic gate circuit includes at least one of an AND gate, a NOR gate, a NOT gate, and a NAND gate.

6. The memory according to claim 2, wherein: The timing control circuit is further configured to: adjusting a delay time of the initial sampling signal in response to the first access mode signal; The first clock signal is output in response to the adjusted delay time of the initial sampling signal.

7. The memory according to claim 2, wherein: The timing control circuit is further configured to: In response to a second access mode signal, the internal clock signal is adjusted and a second clock signal is output; wherein the second clock signal includes a plurality of spaced second sampling signals; and the second access mode signal is used to indicate access to the M memory bank groups; The peripheral circuit is further configured to: output a second data signal in response to the second clock signal and the second local data signal; wherein the second local data signal includes a plurality of alternating second data periods and a plurality of second interval periods, the second data period is greater than the first data period, and the second interval period is greater than the first interval period; and two adjacent second sampling signals are respectively located within adjacent second data periods and second interval periods; The second data signal is written into a target memory bank group among the M memory bank groups.

8. The memory according to claim 7, wherein: The timing control circuit is specifically configured as follows: delaying the internal clock signal in response to the second access mode signal; In response to the delayed initial sampling signal, the second clock signal is output; wherein a clock period of the second clock signal is the same as a clock period of the internal clock signal.

9. The memory according to claim 2, wherein: The timing control circuit includes: A clock signal input circuit is configured to output the internal clock signal in response to a bank clock signal and an activation signal.

10. The memory according to claim 1, wherein: The memory includes a fourth-generation double data rate synchronous dynamic random access memory, a fifth-generation double data rate synchronous dynamic random access memory or an external random access memory.

11. A method for operating a memory, characterized in that: The memory includes a memory cell array, the memory cell array includes M memory bank groups, the memory bank groups include N memory banks, and M and N are both integers greater than 1; the operating method includes: In response to a first access mode signal, the internal clock signal is adjusted and a first clock signal is output; wherein the first clock signal includes a plurality of first sampling signals spaced apart; and the first access mode signal is used to indicate access to the N memory banks; Outputting a first data signal in response to the first clock signal and the first local data signal; wherein the first local data signal includes a plurality of alternating first data periods and a plurality of first interval periods; and two adjacent first sampling signals are respectively located within adjacent first data periods and first interval periods; The first data signal is written into a target memory bank among the (M*N) memory banks.

12. The operating method according to claim 11, characterized in that: The internal clock signal includes a plurality of initial sampling signals spaced apart; The step of adjusting the internal clock signal in response to the first access mode signal and outputting the first clock signal comprises: adjusting a pulse width of the initial sampling signal in response to the first access mode signal; The first clock signal is output in response to the adjusted pulse width of the initial sampling signal; wherein a clock period of the first clock signal is the same as a clock period of the internal clock signal.

13. The operating method according to claim 12, characterized in that: The step of adjusting the pulse width of the initial sampling signal in response to the first access mode signal comprises: In response to the first access mode signal, reducing the pulse width of the initial sampling signal; Outputting the first clock signal in response to the adjusted pulse width of the initial sampling signal comprises: The first clock signal is output in response to the reduced pulse width of the initial sampling signal.

14. The operating method according to claim 12, characterized in that: The step of adjusting the internal clock signal in response to the first access mode signal and outputting the first clock signal comprises: adjusting a delay time of the initial sampling signal in response to the first access mode signal; The first clock signal is output in response to the adjusted delay time of the initial sampling signal.

15. The operating method according to claim 12, characterized in that: The operation method further includes: In response to a second access mode signal, the internal clock signal is adjusted and a second clock signal is output; wherein the second clock signal includes a plurality of spaced second sampling signals; and the second access mode signal is used to indicate access to the M memory bank groups; outputting a second data signal in response to the second clock signal and the second local data signal; wherein the second local data signal includes a plurality of alternating second data periods and a plurality of second interval periods, the second data period is greater than the first data period, and the second interval period is greater than the first interval period; and two adjacent second sampling signals are respectively located within adjacent second data periods and second interval periods; The second data signal is written into a target memory bank group among the M memory bank groups.

16. The operating method according to claim 15, characterized in that: The adjusting the internal clock signal in response to the second access mode signal and outputting the second clock signal comprises: delaying the internal clock signal in response to the second access mode signal; In response to the delayed initial sampling signal, the second clock signal is output; wherein a clock period of the second clock signal is the same as a clock period of the internal clock signal.

17. The operating method according to claim 12, characterized in that: The operation method further includes: The internal clock signal is output in response to a bank clock signal and an activation signal.

18. A memory system, characterized in that: include: The memory according to any one of claims 1 to 10; a memory controller coupled to the memory; The memory controller is configured to control the memory.

19. A computer system, characterized in that: include: The memory system according to claim 18; A host is coupled to the memory system.

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