Self-checking circuit and method for memory specified address injection faults

Abstract

The application relates to the technical field of integrated circuit design, in particular to a self-checking circuit and method for memory specified address error injection, which comprises a processor, a memory, a read-write control module, an error injection control module and an error injection configuration module, the memory and the read-write control module are respectively connected with an ECC generator and an ECC verifier; the processor is connected with the error injection configuration module and the read-write control module corresponding to the memory; the processor is used for controlling the read-write control module to perform data writing and reading operation on the memory, and configuring error injection addresses and error injection data of specified addresses through the error injection configuration module according to the space use condition of the memory; the error injection control module is used for judging whether the address of the read data of the memory matches the error injection address in response to the data reading operation of the processor on the memory, and if yes, the error injection data is injected with errors, and the ECC verifier is used for verifying the data after error injection. The application can support the accurate and controllable error injection self-checking function.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a self-checking circuit and method for memory specified address error injection. BACKGROUND

[0002] In the design of integrated circuits, the program code of a processor CPU is saved in the memory in the form of data. In order to improve the reliability of the data in the memory, an ECC check is usually used in the circuit. The principle of the ECC check is that, in the process of writing data, an ECC generator generates an ECC code according to the written data, and then writes the data and the ECC code into the memory; in the process of reading data, the data and the ECC code in the memory are read out, an ECC checker recalculates the ECC code according to the read data, and compares it with the ECC code read out from the memory. If they are the same, the check is successful, and the data is correct. Otherwise, the check fails, and the data is incorrect. In some circuits with higher functional safety requirements, in order to prevent the ECC checker circuit from failing, a circuit for error injection self-checking is further added on this basis. The principle of the error injection self-checking circuit is to inject an error at a specified bit position by injecting an error at the data output end of the memory, and performing an exclusive OR operation on the injected error data and the read data+ECC code, so as to inject a single-bit or multi-bit error at the specified bit position. If the ECC checker fails to check, it indicates that the ECC checker function is normal.

[0003] REFERENCE Figure 1 The above error injection self-checking scheme needs to involve a software program, and the process of executing the error injection self-checking program also needs to read data from the memory. If the error injection self-checking program is stored in the memory 1 that is to be injected with an error, the output end of the memory 1 is directly injected with an error, which will also inject an error into the error injection self-checking program, and easily cause the program to run abnormally. Therefore, in order to avoid the influence of the error injection on the normal running of the self-checking program itself, when the memory 1 is subjected to error injection self-checking, the program code of the error injection self-checking is first stored in the memory 2, and after the memory 1 is self-checked, the program code of the error injection self-checking is moved to the memory 1, and the memory 2 is subjected to error injection self-checking.

[0004] However, the existing error injection self-checking scheme still has two problems: firstly, the data at the output end of the memory is continuously injected with an error, and it is unable to identify whether the currently injected error data belongs to the self-checking program itself, and thus there is a risk of mistakenly injecting an error into the self-checking program itself, thereby causing the program to execute abnormally; secondly, the self-checking program needs to be repeatedly moved to different memories, which significantly increases the complexity of software development. Moreover, some problems are likely to occur in actual projects, such as incomplete moving of the program causing the error injection program to be unable to run, configuration error of the moving address causing the original data to be overwritten, or insufficient space in the target memory for storing the error injection self-checking program. SUMMARY

[0005] The application provides a self-checking circuit and method for memory specified address error injection, which can realize specified address error injection of a specified memory, and does not need to carry an error injection program to other memories in an error injection self-checking process, thereby supporting accurate and controllable error injection self-checking functions. The application provides the following technical solutions.

[0006] In a first aspect, the application provides a self-checking circuit for memory specified address error injection, comprising a processor, at least one memory, and a read-write control module, the data write-in end of the memory being connected with an ECC generator, the data output end of the memory being connected with an ECC verifier, and the read-write control module being connected with the ECC generator and the ECC verifier respectively; the self-checking circuit for memory specified address error injection further comprises an error injection control module and an error injection configuration module, the memory corresponding to the read-write control module and the error injection control module one by one, and the processor being connected with the error injection configuration module and the read-write control module corresponding to the memory respectively; the error injection control module is connected with the memory and the error injection configuration module respectively.

[0007] The processor is used to control the read-write control module to perform data write-in and read-out operations on the memory, and configure error injection addresses and error injection data of specified addresses through the error injection configuration module according to the space usage of the memory; the error injection control module is used to judge whether the address of the read data of the memory matches the error injection address in the error injection configuration module in response to the data read-out operation of the processor on the memory, and if yes, the error injection data is injected, and if not, no error injection is performed; and the ECC verifier is used to verify the error-injected data.

[0008] In a specific implementable scheme, the error injection configuration module comprises a global control register, at least one error injection control register, and at least one register group, the global control register being a total switch of the error injection configuration module, the error injection control register being used to specify a register group, select the number of error injection positions, and control whether the reverse configuration of the error injection address is needed, and the register group being used to store the start address, error injection range, and error injection bit position required by the error injection operation; the error injection control register corresponds to the memory one by one.

[0009] In a specific implementable scheme, each register group comprises an address register, a range register, and a position register; the address register is used to configure the start address of error injection, the range register is used to configure the error injection range, and the position register is used to configure the error injection position.

[0010] In one specific implementation, the bit field in the error injection control register includes SEL[1:0], POS1_EN, POS0_EN, and INV.

[0011] SEL[1:0] is used to specify the register group.

[0012] POS1_EN and POS0_EN are used to select the number of error injection positions. If POS1_EN = 1 and POS0_EN = 1, it means that 2-bit error injection is performed. If either POS0_EN or POS1_EN is configured as 1 and the other is configured as 0, it means that single-bit error injection is performed. If both POS0_EN and POS1_EN are configured as 0, it means that no error injection is performed.

[0013] INV is used to control the reverse configuration of the error injection address. If INV = 0, it means that the reverse error injection function is not enabled, and the error injection operation is only performed at the start address configured by the error injection address register and within the range set by the range register. If INV = 1, it means that the reverse error injection function is enabled, and the address interval defined by the error injection address register and the range register is considered as an excluded area without error injection, and the remaining address interval is all error injection range.

[0014] In one specific implementation, the processor selects, before system startup or self-checking, an idle address interval that has not been used or can be used for error injection self-checking as the error injection address according to the space usage of each memory; the processor writes error injection configuration information to the register group, writes the start error injection address in the selected target memory to the address register, writes the range to the range register, and then writes the position of the bit to be injected to the position register.

[0015] In one specific implementation, after the processor writes error injection configuration information to the register group, it further includes:

[0016] The processor specifies the register group corresponding to the target memory in the error injection control register and sets single-bit, double-bit, or no error injection operation through the error injection position enable bit, then judges whether to perform reverse configuration on the error injection address, and after completing the configuration, the processor sets the control bit in the global control register to the enabled state.

[0017] In a specific embodiment, when the processor controls the read-write control module to read data from the memory, the error injection control module synchronously acquires the chip select signal of the memory, the address in the memory where the data is read, and the read-write control signal. If the error injection control module detects that the chip select signal of the memory is valid and the read-write control signal indicates a read operation, it indicates that the memory corresponding to the error injection control module is performing a data read operation. The error injection control module determines whether the address in the memory where the data is read matches the error injection address in the error injection configuration module. If the addresses match, the error injection operation is performed. Otherwise, the error injection operation is not performed.

[0018] In a specific embodiment, if the address in the memory where the data is read is within the range of the error injection address when the error injection control register does not enable the reverse error injection function, the error injection operation is performed. If the address in the memory where the data is read is not within the range of the error injection address when the error injection control register enables the reverse error injection function, the error injection operation is performed.

[0019] In a specific embodiment, the ECC checker receives the error-injected data and performs a check. If the ECC checker detects an error, it indicates that the ECC checker circuit is functioning normally and the self-check is passed. Otherwise, it indicates that the ECC checker circuit is abnormal and cannot work normally, and the self-check fails.

[0020] In a second aspect, the application provides a self-checking method for memory address error injection, which uses the following technical solution:

[0021] A self-checking method for memory address error injection is applied to any one of the self-checking circuits for memory address error injection described in the first aspect. The method includes:

[0022] The processor configures the error injection address and error injection data of the specified address in the error injection configuration module based on the space usage of the specified memory.

[0023] In response to the data read operation of the processor on the specified memory, the error injection control module acquires the address where the data is read, the chip select signal, and the read-write control signal. When the chip select signal is valid and the read-write control signal indicates a read operation, the error injection control module determines whether the address where the data is read matches the error injection address.

[0024] If the addresses match, the error injection data is injected with an error, and the error-injected data is checked by the ECC checker. If an error is detected, it indicates that the ECC checker circuit is functioning normally. Otherwise, it indicates that the ECC checker circuit is abnormal. If the addresses do not match, the error injection operation of the error injection data is not performed.

[0025] In summary, the application has at least the following beneficial effects:

[0026] (1) By setting the error injection configuration module, the user can configure the starting address, range and bit position of the error injection, so that the error injection behavior is triggered only in a specific address range of a specific memory, avoiding interference with data at non-target addresses, especially preventing false error injection of the error injection self-checking program. Compared with the traditional solution of moving the error injection program to other memories for execution, the present application can complete the error injection process in the original memory, avoiding address conflicts, insufficient space and incomplete programs that may be caused during program transfer, effectively improving system stability and self-checking accuracy.

[0027] (2) The error injection self-checking function completes the error injection address and range setting through register configuration. The developer only needs to set the address register and range register to complete the error injection parameter setting. The error injection control logic can automatically determine whether the current read access hits the configured range and inject the corresponding error data when it hits, thereby completing the error injection process. The entire error injection process does not require complex program control or additional instruction intervention, significantly reducing software development burden, reducing human configuration errors, and improving the automation level and development efficiency of the error injection self-checking process.

[0028] (3) To reduce resource occupation while retaining sufficient error injection flexibility, a structure scheme of multiple error injection control registers sharing a small number of error injection configuration register groups is designed. By introducing a group selection bit (SEL field) in the error injection control register, different memories can choose to use the same group or different groups of error injection configuration parameters, thereby realizing flexible error injection strategy deployment. This design method greatly saves register resources while ensuring independent error injection requirements for multiple memories, contributing to system integration and area optimization, and has good hardware implementation and application value.

[0029] The self-checking circuit for memory specified address error injection includes a processor, a plurality of memories, a read-write control module, an error injection configuration module and an error injection control module. The error injection configuration module flexibly configures the starting address, range and bit position of the error injection through programmable method, and the error injection control module determines whether to trigger the error injection condition in real time according to the read operation, only performs error injection operation on data matching the specified address range and position information, and supports batch error injection control outside the exclusion area through reverse error injection function. This design avoids the problem that the existing technology continuously injects errors at the memory data output end and cannot distinguish whether it is the self-checking program itself, effectively preventing the execution exception caused by false error injection of the self-checking program. At the same time, this scheme does not need to repeatedly move the self-checking program to different memories for execution, but realizes centralized control and triggering through hardware error injection configuration, reducing development cost, avoiding running risks caused by program transfer errors, address configuration conflicts or insufficient space, and improving the reliability and engineering adaptation efficiency of the self-checking mechanism.

[0030] The above description is only a summary of the technical scheme of the present application. In order to make the technical means of the present application more clearly understood and implemented according to the content of the description, the preferred embodiments of the present application are described in detail as follows with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a structural block diagram of the existing error injection self-checking scheme in the embodiments of the present application.

[0032] Figure 2 is a structural block diagram of the self-checking circuit for memory specified address error injection in the embodiments of the present application.

[0033] Figure 3 is a structural block diagram of the error injection configuration module in the embodiments of the present application.

[0034] Figure 4 is a flowchart of the self-checking method for memory specified address error injection in the embodiments of the present application.

[0035] Figure 5 is a structural block diagram of the error injection self-checking circuit in one specific embodiment of the embodiments of the present application.

[0036] Figure 6 is a space and address status diagram of the memory in one specific embodiment of the embodiments of the present application.

[0037] Figure 7 is a signal interaction diagram of the error injection control module and the read control module in one specific embodiment of the embodiments of the present application. DETAILED DESCRIPTION

[0038] The specific embodiments of the present application are described in further detail below with reference to the accompanying drawings and embodiments. The following embodiments are used to illustrate the present application but are not used to limit the scope of the present application.

[0039] REFERENCE Figure 2, is a structural block diagram of a self-checking circuit for memory specified address error injection provided by an embodiment of the present application. The self-checking circuit for memory specified address error injection comprises a processor, at least one memory, a read-write control module, an error injection control module, and an error injection configuration module. An ECC generator is connected to a data write-in end of the memory, and an ECC checker is connected to a data output end of the memory. A write-in data end of the read-write control module is connected to an input end of the ECC generator, and a read data end of the read-write control module is connected to an output end of the ECC checker. The memory, the read-write control module, and the error injection control module are one-to-one corresponding. The processor is connected to each read-write control module corresponding to each memory through a read-write bus, wherein the read-write bus comprises but is not limited to an APB, an AHB, or an AXI bus. The processor is also connected to the error injection configuration module through a bus, and the error injection control module is connected to the memory and the error injection configuration module respectively.

[0040] The processor is configured to control the read-write control module to perform data write-in and read-out operations on the memory, and to configure an error injection address and error injection data of a specified address through the error injection configuration module according to a space usage of each memory.

[0041] Optionally, in the embodiment of the present application, the processor is a CPU, and other processor types can also be selected. The type of the processor is not limited in the present application.

[0042] Reference Figure 3 , is a structural block diagram of the error injection configuration module in the embodiment of the present application. The error injection configuration module comprises a global control register, at least one error injection control register, and at least one register group. The number of the error injection control registers is one-to-one corresponding to the number of the memories. The global control register is a total switch of the error injection configuration module, and is configured to control start and stop of the error injection function module. When a control bit in the global control register is in an enabled state, the error injection configuration and control function takes effect. The error injection control register is configured to specify a register group, select a number of error injection positions, and control whether to perform reverse configuration of an error injection address. The register group is configured to store a start address, an error injection range, and an error injection bit position required by the error injection operation. Each register group comprises an address register, a range register, and a position register. The address register is configured to configure a start address of the error injection, the range register is configured to configure an error injection range, and the position register is configured to configure an error injection position.

[0043] The error injection control register comprises four different bit fields, SEL[1:0], POS1_EN, POS0_EN and INV, in the embodiment of the present application. SEL[1:0] is used to select one of the four register groups. POS1_EN and POS0_EN are used to select the number of error injection positions. If POS1_EN=1 and POS0_EN=1, it means that two-bit error injection is performed. If either POS0_EN or POS1_EN is configured as 1 and the other is configured as 0, it means that single-bit error injection is performed. If both POS0_EN and POS1_EN are configured as 0, it means that no error injection is performed. INV is used to control whether to enable the reverse error injection function, i.e., whether to perform logical reverse configuration on the error injection address range. If INV=0, it means that the reverse error injection function is not enabled, and the error injection operation is only performed at the start address configured by the error injection address register and within the range set by the range register, i.e., only the specified address interval is subjected to error injection operation. If INV=1, it means that the reverse error injection function is enabled, and the specified address interval defined by the error injection address register and the range register is regarded as an excluded area without error injection, and the remaining address interval is all the error injection range. When most of the address interval of the target memory needs to perform error injection operation, but contains a few reserved areas that are not allowed to be subjected to error injection, it is troublesome or inconvenient to directly configure the error injection address and range. At this time, the reverse configuration of the error injection address is performed by enabling the reverse error injection function, and all addresses except the excluded area are subjected to error injection, thereby simplifying the configuration.

[0044] In the implementation, the processor selects an idle address interval that has not been used or can be used for error injection self-checking as the specified address, i.e., the error injection address, according to the usage of the address interval of each memory before system startup or self-checking. Then, the processor writes the error injection configuration information to the error injection configuration module through the bus, writes the selected start error injection address in the target memory to the address register in the corresponding register group, and sets the error injection coverage range starting from the start address according to the self-checking requirement and writes it to the range register, thereby defining the error injection address interval. Then, the position of the bit to be injected is written into the position register, so that the position register can store the bit number of the specific error injection position.

[0045] Subsequently, the processor implements further configuration of the fault injection behavior of each memory by accessing the fault injection control register. Specifically, the processor sets a register group selection bit in the fault injection control register to specify the register group to be used by the target memory, and sets whether single-bit, double-bit or no fault injection operation is to be performed by the fault injection position enable bit, and flexibly specifies whether the fault injection address range is within the configuration interval or outside the interval by the reverse fault injection control bit, thereby completing unified control of the fault injection position, quantity and range logic. In order to reduce resource occupation while retaining sufficient fault injection flexibility, a structure scheme in which multiple fault injection control registers share a small number of fault injection configuration register groups is designed. By introducing a group selection bit (SEL field) in the fault injection control register, different memories can select to use the same group or different groups of fault injection configuration parameters, thereby realizing flexible fault injection strategy deployment. This design method greatly saves register resources while ensuring the independent fault injection needs of multiple memories, is helpful for system integration and area optimization, and has good hardware implementation and application value. After completing the configuration of the register group and control information as described above, the processor sets the control bit in the global control register to an enabled state to activate the entire fault injection control logic, so that the fault injection control module begins to implement fault injection on the matching address data.

[0046] Optionally, the number of register groups is determined according to the actual circuit needs, and in the embodiment of the present application, the number of register groups is 4, but the number of register groups is not limited in the present application.

[0047] The fault injection control module is configured to determine whether the address of the memory read data matches the fault injection address in the fault injection configuration module in response to the data read operation of the processor on the memory, and if it matches, the fault injection data is injected, and if it does not match, no fault injection is performed.

[0048] Specifically, when the processor controls the read-write control module to perform data read on the memory, the fault injection control module synchronously acquires the chip select signal of the memory, the address of the memory where the read data is located, and the read-write control signal. If the fault injection control module detects that the chip select signal of the memory is valid and the read-write control signal indicates a read operation, it proves that the memory corresponding to the fault injection control module is performing a data read operation. At this time, the fault injection control module further determines whether the address of the memory where the read data is located matches the fault injection address in the fault injection configuration module. If the reverse fault injection function is not enabled in the fault injection control register, the address of the memory where the read data is located is within the range of the fault injection address, and the fault injection operation is performed. If the reverse fault injection function is enabled in the fault injection control register, the address of the memory where the read data is located is not within the range of the fault injection address, and the fault injection operation is performed.

[0049] The ECC generator is configured to generate the corresponding error correction code according to the original data information before the data is written into the memory, and store the error correction code into the memory together with the original data.

[0050] The ECC checker is configured to check the error-injected data. Specifically, the error-injected data is input into the ECC checker. If the ECC checker checks an error, it indicates that the ECC checker circuit functions normally, and the self-checking passes. Otherwise, it indicates that the ECC checker circuit is abnormal and cannot function normally, and the self-checking fails.

[0051] In summary, the self-checking circuit for injecting errors into a specified address of a memory includes a processor, a plurality of memories, a read-write control module, an error injection configuration module and an error injection control module. The error injection configuration module flexibly configures the start address, range and bit position of the error injection through programmable manner. The error injection control module determines whether to trigger the error injection condition in real time according to the read operation, and only performs the error injection operation on the data matching the specified address range and position information, and supports the batch error injection control outside the exclusion area through the reverse error injection function. The design avoids the problem that the existing technology continuously injects errors at the data output end of the memory and cannot distinguish whether it is the self-checking program itself, effectively prevents the execution exception caused by the misinjection of the self-checking program. At the same time, the scheme does not need to repeatedly move the self-checking program to different memories for execution, but realizes the centralized control and triggering through the hardware error injection configuration, reduces the development cost, avoids the running risks caused by the program moving error, address configuration conflict or insufficient space, and improves the reliability and engineering adaptation efficiency of the self-checking mechanism.

[0052] In addition, as a preferred, the error injection control module in the present application does not directly inject errors into the storage unit of the memory, but after the processor controls the read-write control module to read the data from the memory, the error injection control module outputs the error injection data and the data read from the memory to perform the bitwise XOR operation, thereby realizing the error injection, and thus the valid data in the memory is not changed, and there is no need to additionally restore the data in the memory after the error injection self-checking is completed. In summary, the method realizes the dynamic interference to the target data without modifying the actual storage content of the memory, thereby completing the error injection test of the ECC function. Since the valid data in the memory always remains unchanged, there is no need to perform the additional data recovery operation after the error injection self-checking is completed, which simplifies the test process and improves the verification efficiency.

[0053] Figure 4 is a flowchart of a self-checking method for injecting errors into a specified address of a memory provided by an embodiment of the present application. The method includes:

[0054] In step S1, the processor configures the error injection address and error injection data of the specified address in the error injection configuration module based on the space usage of the specified memory.

[0055] In step S1, the processor selects an idle address interval which has not been used or which can be used for error injection self-checking as an error injection address according to the space usage of each memory before system startup or self-checking, and then the processor writes error injection configuration information to the register group, the address register configures the error injection start address, the range register configures the error injection range, and the position register configures the error injection bit position. The error injection control register specifies the register group corresponding to the target memory, and sets the error injection position enable bit to perform single-bit, double-bit or no error injection operation, and judges whether the error injection address needs to be reversely configured. After the configuration is completed, the processor sets the control bit in the global control register to the enabled state to start the error injection module.

[0056] In step S2, in response to the data read operation of the processor on the specified memory, the error injection control module obtains the address where the read data is located, the chip select signal and the read-write control signal. When the chip select signal is valid and the read-write control signal indicates a read operation, it is judged whether the address where the read data is located matches the error injection address.

[0057] In step S2, if the error injection control register does not start the reverse error injection function, the address in the memory where the read data is located is within the range of the error injection address, and the error injection operation is performed. If the error injection control register starts the reverse error injection function, the address in the memory where the read data is located is not within the range of the error injection address, and the error injection operation is performed.

[0058] In step S3, if it is matched, the error injection data is error injected, and the error injected data is checked by the ECC. If the check is incorrect, it indicates that the ECC checker circuit function is normal, otherwise it indicates that the ECC checker circuit is abnormal. If it is not matched, the error injection operation of the error injection data is not performed.

[0059] The related details refer to the above-mentioned circuit embodiment.

[0060] Next, an example is given. In a specific embodiment, the chip has five memories, namely memory A, memory B, memory C, memory D and memory E. The five memories all support ECC checking and ECC error injection self-checking, and the data format is 32-bit data + 7-bit ECC code. The structure block diagram of the circuit based on the technical solution of the present application is as follows: Figure 5As shown, it is to be noted that only the circuit of memory A / B is drawn, and the memory C / D / E has the same circuit structure as the memory A / B, so it is omitted. When the processor controls the read-write control module to write data to the memory, the 32-bit write data generates a 7-bit ECC check code through the ECC generator, and the write data and the check code are written into the memory together. When the processor controls the read-write control module to read data from the memory, the chip select signal is valid and the read-write signal is read, and the output end of the memory will output 32-bit data and 7-bit ECC check code according to the address signal, a total of 39-bit data. The ECC check circuit checks the 39-bit data according to the ECC algorithm and outputs the check result.

[0061] The technical solution of the present application adds an error injection self-checking circuit on the basis of the above-mentioned circuit, including error injection configuration and error injection control two parts, and the processor configures the register group in the error injection configuration module. The error injection configuration module includes: a global control register, four error injection control registers, four address registers, four range registers and four error injection position control registers. One address register, one range register and one error injection position register are called one error injection register group, and there are four error injection register groups in the embodiment of the present application. Each memory is equipped with an error injection control module, and the error injection control module obtains error injection information such as error injection address, error injection range and error injection position from the register group of the error injection configuration module. In response to the read operation of the processor to the memory, the read-write control module reads data from the memory, and the chip select signal, address and read-write control signal of the memory are also sent to the error injection control module. When the memory has data reading, the error injection control module matches the reading sequence and the reading address, and if the two are matched successfully, the error injection data_i is assigned to the error injection data_o, thereby realizing the function of error injection at a specified address.

[0062] It is assumed that the program code is stored in the five memory blocks in the embodiment and part of the space is not used, and the address of the memory and the specific use are as shown in Figure 6 The flow of the entire memory error injection self-checking is described in detail below. Taking memory A as an example, the error injection configuration module needs to be configured according to the use of memory A. Specifically:

[0063] First, register group 0 is configured. The address range of memory A that is not used is 0x0002_0000~0x0003_FFFF, and the value of address register 0 can be configured as 0x0002_0000, indicating that the starting address of error injection is 0x0002_0000. The value of range register 0 is configured as 0x10, indicating that the error injection range is 0x0002_0000~0x0002_000F. The value of position register 0 is configured as 0x0000_0701, indicating that error injection will be performed at bit 1 and bit 7 of the read data, a total of 2 bits.

[0064] Next, configure the error injection control register 0 of memory A, where SEL = 0x0, indicating that the error injection information of error injection register group 0 is selected as the error injection information of memory A. INV = 0, indicating that the reverse error injection function is not enabled. POS1_EN = 1, POS0_EN = 1, indicating that 2-bit error injection is enabled, and the output error injection data _i value is 0x00_0000_0082. If single-bit error injection is required, either POS0_EN or POS1_EN can be configured as 1 and the other as 0, and the output error injection data _i value is 0x00_0000_0002 or 0x00_0000_0080. When both POS0_EN and POS1_EN are configured as 0, it indicates no error injection.

[0065] Finally, configure the global control register, GLOBAL_EN = 1, to enable the error injection function. After the configuration is completed, the processor in the error injection self-check program reads the data in the range of 0x0002_0000 to 0x0002_000F through the read-write control module, as Figure 7 shown. The read-write control module of memory A outputs addr[17:0] as 0x2_0004, and at the same time pulls down the chip select signal cs_n and raises the read-write control signal we_n. Memory A outputs the data corresponding to the address (data[31:0] is 0x02003fe0) and the ECC code (data[38:32] is 0x2a). The error injection control module detects that the chip select signal of memory A is pulled down and the read-write control signal is raised, proving that the read sequence is successfully matched; at this time, the error injection control module judges whether the intercepted error injection address addr_ij[17:0] satisfies addr_ij[17:0] <= addr[17:0] < addr_ij[17:0] + size_ij[15:0]. If the error injection address range is satisfied, the error injection control module will assign the error injection data _i to the error injection data _o (data_ij_o), with a value of 0x00_0000_0082. The error injection data _o is XORed with the output data of memory A, and bit 7 and bit 1 of 0x2a_02003fe0 will be inverted to become 0x2a_02003f62.

[0066] After the error injection is completed, the data after the error injection is input to the ECC checker. If the ECC check is incorrect, it indicates that the ECC checker circuit is functioning normally, and the self-check is passed. Otherwise, it indicates that the ECC checker circuit is abnormal and cannot work normally, and the self-check fails. When the processor subsequently accesses the 0x0002_0088 address, the address is not in the error injection range 0x0002_0000~0x0002_000F, and the value of data_ij_o is 0x0, so the output data of the memory A will not be error injected. After the error injection self-check of the memory A is completed, the error injection self-check of the remaining memories can be continued according to the above process.

[0067] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as falling within the scope of the present disclosure.

[0068] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A self-checking circuit for memory specified address error injection, comprising a processor, at least one memory, and a read-write control module, a data write end of the memory being connected with an ECC generator, a data output end of the memory being connected with an ECC checker, the read-write control module being connected with the ECC generator and the ECC checker respectively; characterized in that, The self-checking circuit for memory specified address error injection further comprises an error injection control module and an error injection configuration module, the memory is one-to-one corresponding to the read-write control module and the error injection control module respectively, and the processor is connected with the error injection configuration module and the read-write control module corresponding to the memory respectively; the error injection control module is connected with the error injection configuration module; The processor is used for controlling the read-write control module to perform data writing and reading operation on the memory, and configuring the error injection address and error injection data of the specified address through the error injection configuration module according to the space usage of the memory; the error injection control module is used for judging whether the address of the data read by the memory matches the error injection address in the error injection configuration module in response to the data reading operation of the processor on the memory, if yes, the error injection data is injected, if not, no error injection is performed; and the ECC checker is used for checking the error injected data.

2. The self-test circuit for memory specified address injection faults according to claim 1, wherein, The error injection configuration module comprises a global control register, at least one error injection control register and at least one register group, the global control register is the total switch of the error injection configuration module, the error injection control register is used for specifying the register group, selecting the number of error injection positions and controlling whether the reverse configuration of the error injection address is needed, and the register group is used for storing the start address, error injection range and error injection bit position required by the error injection operation; the error injection control register is one-to-one corresponding to the memory.

3. The self-test circuit for memory specified address injection faults according to claim 2, wherein, Each register group comprises an address register, a range register and a position register; the address register is used for configuring the start address of the error injection, the range register is used for configuring the error injection range, and the position register is used for configuring the error injection position.

4. The self-test circuit for memory specified address injection faults according to claim 3, wherein, The bit field in the error injection control register comprises SEL[1:0], POS1_EN, POS0_EN and INV; SEL[1:0] is used for specifying the register group; POS1_EN and POS0_EN are used for selecting the number of error injection positions, if POS1_EN=1 and POS0_EN=1, 2-bit error injection is performed, if POS0_EN or POS1_EN is configured as 1 and the other is configured as 0, single-bit error injection is performed, and if POS0_EN and POS1_EN are both configured as 0, no error injection is performed; INV is used for controlling the reverse configuration of the error injection address, if INV=0, the reverse error injection function is not started, and the error injection operation is only performed at the start address configured by the error injection address register and in the range set by the range register; if INV=1, the reverse error injection function is started, the address interval defined by the error injection address register and the range register is regarded as the excluded area without error injection, and the rest of the address interval is all the error injection range.

5. The self-test circuit for memory specified address injection faults according to claim 4, wherein, The processor selects an idle address interval which has not been used or can be used for error injection self-checking as an error injection address according to the space usage of each memory before system startup or self-checking; the processor writes error injection configuration information to the register group, writes the starting error injection address in the selected target memory to the address register, writes the range to the range register, and then writes the position of the bit to be injected to the position register.

6. The self-test circuit for memory specified address injection faults according to claim 5, wherein, The processor writes error injection configuration information to the register group, writes the starting error injection address in the selected target memory to the address register, writes the range to the range register, and then writes the position of the bit to be injected to the position register. The processor specifies the register group corresponding to the target memory in the error injection control register, and sets the error injection position enable bit to perform single-bit, double-bit or no error injection operation, and then judges whether to perform reverse configuration on the error injection address. After the configuration is completed, the processor sets the control bit in the global control register to the enabled state.

7. The self-test circuit for memory specified address injection faults according to claim 4, wherein, When the processor controls the read-write control module to read data from the memory, the error injection control module synchronously acquires the chip select signal of the memory, the address of the memory where the data is read, and the read-write control signal. If the error injection control module detects that the chip select signal of the memory is valid and the read-write control signal indicates a read operation, it means that the memory corresponding to the error injection control module is performing a data read operation. The error injection control module judges whether the address of the memory where the data is read matches the error injection address in the error injection configuration module. If it matches, error injection is performed; otherwise, no error injection is performed.

8. The self-test circuit for memory specified address injection faults according to claim 7, wherein, If the address of the memory where the data is read is within the range of the error injection address when the reverse error injection function of the error injection control register is not enabled, error injection is performed; if the address of the memory where the data is read is not within the range of the error injection address when the reverse error injection function of the error injection control register is enabled, error injection is performed.

9. The self-test circuit for memory specified address injection faults according to claim 1, wherein, The ECC checker receives the error-injected data and performs verification. If the ECC checker detects an error, it means that the ECC checker circuit is functioning normally and the self-checking is passed; otherwise, it means that the ECC checker circuit is abnormal and cannot work normally, and the self-checking fails.

10. A method for memory specified address fault injection self-test, applied in the memory specified address fault injection self-test circuit according to any one of claims 1-9, characterized in that, The method comprises: The processor configures the error injection address and error injection data of the specified address in the error injection configuration module based on the space usage of the specified memory; In response to the data read operation of the processor on the specified memory, the error injection control module acquires the address where the data is read, the chip select signal, and the read-write control signal. When the chip select signal is valid and the read-write control signal indicates a read operation, it is judged whether the address where the data is read matches the error injection address; If it matches, the error injection data is injected, and the error-injected data is verified by the ECC checker. If an error is detected, it means that the ECC checker circuit is functioning normally; otherwise, it means that the ECC checker circuit is abnormal. If it does not match, no error injection operation is performed on the error injection data.

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