Manufacturing method of semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure, and the method comprises the steps: providing a first bonding structure which comprises a first wafer and a second wafer, the first wafer comprises a first semiconductor layer, and the second wafer comprises a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are located on the two opposite sides of the first bonding structure in the bonding direction respectively; carrying out thinning treatment on the first semiconductor layer and / or the second semiconductor layer; and forming a modified region in the thinned first semiconductor layer and / or the thinned second semiconductor layer through a laser irradiation process.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] In the semiconductor manufacturing process, after the integrated circuit is formed on the wafer, the wafer needs to be cut into several independent dies, and then the independent dies are stacked, bonded and packaged to form independent chips.

[0003] However, using a blade to cut the wafer is prone to cracks on the edge of the die, and a large amount of broken particles will be generated at the cutting position and adhere to the surface of the die, resulting in low cleanliness of the die surface, affecting the yield of the die.

[0004] In addition, stacking and bonding the cut dies is not conducive to improving the bonding efficiency. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.

[0006] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a first bonding structure, the first bonding structure comprising a first wafer and a second wafer, the first wafer comprising a first semiconductor layer, and the second wafer comprising a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are respectively located on opposite sides of the first bonding structure along a bonding direction; thinning the first semiconductor layer and / or the second semiconductor layer; and forming a modified region in the thinned first semiconductor layer and / or the second semiconductor layer through a laser irradiation process.

[0008] In some embodiments, the method also includes: providing a second bonding structure, the second bonding structure includes a third wafer and a fourth wafer, the third wafer includes a third semiconductor layer, and the fourth wafer includes a fourth semiconductor layer; the third semiconductor layer and the fourth semiconductor layer are respectively located on opposite sides of the second bonding structure along the bonding direction; thinning the third semiconductor layer and / or the fourth semiconductor layer, and forming a modified region in the thinned third semiconductor layer and / or the fourth semiconductor layer through a laser irradiation process; and bonding the first bonding structure and the second bonding structure.

[0009] In some embodiments, bonding the first bonding structure to the second bonding structure includes bonding the thinned first semiconductor layer or the second semiconductor layer to the thinned third semiconductor layer or the fourth semiconductor layer.

[0010] In some embodiments, when the thinned second semiconductor layer and the thinned third semiconductor layer are bonded, the method further includes: thinning the first semiconductor layer and the fourth semiconductor layer; and forming a modified region in the thinned first semiconductor layer and the thinned fourth semiconductor layer through a laser irradiation process.

[0011] In some embodiments, the second semiconductor layer is thinned, including: thinning the second semiconductor layer to expose the contact structure in the second semiconductor layer; the third semiconductor layer is thinned, including: thinning the third semiconductor layer to expose the contact structure in the third semiconductor layer; the thinned second semiconductor layer and the thinned third semiconductor layer are bonded, including: bonding the contact structure in the thinned second semiconductor layer and the contact structure in the thinned third semiconductor layer.

[0012] In some embodiments, thinning the first semiconductor layer and the fourth semiconductor layer includes: thinning the first semiconductor layer; temporarily bonding the thinned first semiconductor layer to a carrier; and thinning the fourth semiconductor layer.

[0013] In some embodiments, a first bonding interface is included between the first wafer and the second wafer; along the bonding direction, the first wafer also includes a first device layer arranged between the first bonding interface and the first semiconductor layer, and the second wafer also includes a second device layer arranged between the first bonding interface and the second semiconductor layer; a second bonding interface is included between the third wafer and the fourth wafer; along the bonding direction, the third wafer also includes a third device layer arranged between the second bonding interface and the third semiconductor layer, and the fourth wafer also includes a fourth device layer arranged between the second bonding interface and the fourth semiconductor layer.

[0014] In some embodiments, the contact structure includes a vertical interconnect structure.

[0015] In some embodiments, the bonding comprises hybrid bonding.

[0016] In a second aspect, an embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, the method comprising: providing a first bonding structure and a second bonding structure; the first bonding structure comprises a first wafer and a second wafer, and the second bonding structure comprises a third wafer and a fourth wafer; forming a modified region in the second wafer and the third wafer through a laser irradiation process; and bonding the second wafer and the third wafer.

[0017] In some embodiments, after bonding the second wafer and the third wafer, the method further includes: forming modified regions in the first wafer and the fourth wafer through a laser irradiation process.

[0018] In some embodiments, before forming the modified regions in the second wafer and the third wafer through a laser irradiation process, the method further includes: performing a thinning process on the second wafer and the third wafer.

[0019] In some embodiments, before forming the modified regions in the first wafer and the fourth wafer through a laser irradiation process, the method further includes: performing a thinning process on the first wafer and the fourth wafer.

[0020] In some embodiments, thinning the first wafer and the fourth wafer includes: thinning the first wafer; temporarily bonding the thinned first wafer to a carrier; and thinning the fourth wafer.

[0021] In some embodiments, the first wafer, the second wafer, the third wafer, and the fourth wafer each include a plurality of chip regions and saw streets located between adjacent chip regions; and the modified region is formed in the saw streets.

[0022] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a first bonding structure, the first bonding structure including a first wafer and a second wafer, the first wafer including a first semiconductor layer, and the second wafer including a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are respectively located on opposite sides of the first bonding structure along a bonding direction; thinning the first semiconductor layer and / or the second semiconductor layer; and forming a modified region in the thinned first semiconductor layer and / or the second semiconductor layer through a laser irradiation process. In the embodiment of the present disclosure, by providing a first wafer and a second wafer that are bonded, then thinning the first wafer and / or the second wafer, and then forming a modified region in the first semiconductor layer in the first wafer and / or the second semiconductor layer in the second wafer through a laser irradiation process, a stacked bonded bare chip can be obtained after the first bonding structure is expanded and separated, thereby improving the bonding efficiency; and the edges of the stacked bonded bare chip separated by the laser irradiation process will basically not have cracks, which can effectively improve the yield of the bare chip; at the same time, it can avoid stacking bonding after the modified region is formed, which will cause the modified region to expand and have an adverse effect on the stacking bonding effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the steps of a manufacturing method for a first semiconductor structure provided in one embodiment of the present disclosure;

[0024] Figure 2 A schematic top view of a wafer provided in one embodiment of the present disclosure;

[0025] Figures 3 to 8 Schematic diagram of the structure of the semiconductor structure at various stages in the first embodiment of the method for manufacturing the semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 9 A schematic cross-sectional view of a semiconductor device including a first chip stack structure provided in accordance with an embodiment of the present disclosure;

[0027] Figures 10 to 18 Schematic diagram of the structure of the semiconductor structure at various stages in the second embodiment of the method for manufacturing the semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 19 A schematic cross-sectional view of a semiconductor device including a second chip stack structure provided in accordance with an embodiment of the present disclosure;

[0029] Figure 20 A schematic diagram of the steps of a second method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0031] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0032] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0033] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0037] Figure 1 A schematic diagram of the steps of a manufacturing method for a first semiconductor structure provided in one embodiment of the present disclosure.

[0038] See also Figure 1 , the manufacturing method comprises the following steps:

[0039] S10: Providing a first bonding structure, the first bonding structure includes a first wafer and a second wafer, the first wafer includes a first semiconductor layer, and the second wafer includes a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are respectively located on two opposite sides of the first bonding structure along a bonding direction.

[0040] S20: performing a thinning process on the first semiconductor layer and / or the second semiconductor layer.

[0041] S30: forming a modified region in the thinned first semiconductor layer and / or the second semiconductor layer through a laser irradiation process.

[0042] In the embodiment of the present disclosure, by providing a first wafer and a second wafer that are bonded, then thinning the first wafer and / or the second wafer, and then forming a modified region in the first semiconductor layer in the first wafer and / or the second semiconductor layer in the second wafer through a laser irradiation process, a stacked bonded bare chip can be obtained after the first bonding structure is expanded and separated, thereby improving the bonding efficiency; and the edges of the stacked bonded bare chip separated by the laser irradiation process will basically not have cracks, which can effectively improve the yield of the bare chip; at the same time, it can avoid stacking bonding after the modified region is formed, which will cause the modified region to expand and have an adverse effect on the stacking bonding effect.

[0043] Here, it should be noted that the laser irradiation process in the embodiment of the present disclosure includes a laser stealth dicing (SD) process.

[0044] It should be noted that for ease of description, various directions that may be used in the following description are first defined. Intersecting X and Y directions are defined in a plane perpendicular to the bonding direction (Z direction). The X, Y, and Z directions may be perpendicular to each other.

[0045] Figure 2 This is a top view of a wafer provided by an embodiment of the present disclosure. Figure 2 The wafer W includes a plurality of chip regions 11 arranged in an array and dicing streets 12 located between adjacent chip regions 11 .

[0046] It should be noted that the first wafer, the second wafer, the third wafer and the fourth wafer mentioned below may have a structure substantially the same as that of the wafer W.

[0047] Figures 3 to 8 This is a schematic diagram of the structure of the semiconductor structure at various stages in the first embodiment of the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure. It should be noted that: Figures 3 to 8 This is a complete schematic diagram reflecting the implementation process of the manufacturing method of the semiconductor structure. The unmarked parts in some drawings can be shared with each other. Figure 1 、 Figures 3 to 8 , the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0048] It should be noted that Figures 3 to 8 The schematic diagram of the partial cross section of the semiconductor structure at various stages is shown. It can be understood that Figures 3 to 8 Only two adjacent chip areas in each wafer and a cross-sectional schematic diagram of the dicing road therebetween are shown.

[0049] Figure 3 A partial cross-sectional diagram of a first bonding structure provided in one embodiment of the present disclosure. Figure 3 The first bonding structure includes a first wafer W1 and a second wafer W2. The first wafer W1 includes a first semiconductor layer 101, and the second wafer W2 includes a second semiconductor layer 201. The first semiconductor layer 101 and the second semiconductor layer 201 are stacked along the Z direction.

[0050] In some embodiments, the first wafer W1 and the second wafer W2 include a first bonding interface 100. Along the Z direction, the first wafer W1 further includes a first device layer 102 disposed between the first semiconductor layer 101 and the first bonding interface 100, and the second wafer W2 further includes a second device layer 202 disposed between the second semiconductor layer 201 and the first bonding interface 100.

[0051] The device layers involved in the embodiments of the present disclosure may include a sub-device layer arranged near the semiconductor layer and a sub-interconnect layer arranged near the bonding layer. Among them, the sub-device layer of each device layer may be provided with a device structure such as a memory array or a peripheral circuit, for example, the portion of the sub-device layer located in the chip area may be provided with a device structure; each sub-interconnect layer may be provided with an interconnect structure, and each sub-interconnect layer may be, for example, a redistribution layer (RDL). It is understood that the device structure in each chip area is separated from the device structure in other adjacent chip areas.

[0052] In some embodiments, a first bonding layer 103 may be formed on a surface of the first device layer 102 away from the first semiconductor layer 101, and a second bonding layer 203 may be formed on a surface of the second device layer 202 away from the second semiconductor layer 201. Here, the first wafer W1 and the second wafer W2 may be bonded via the first bonding layer 103 and the second bonding layer 203. This embodiment employs, for example, a face-to-face bonding method.

[0053] The bonding layer materials involved in the embodiments of the present disclosure may include dielectric materials and bonding structures disposed in the dielectric materials. The bonding layers of different wafers may be bonded using hybrid bonding (HB), direct bonding (DB), microbump bonding (MB), or thermal compression bonding (TCB).

[0054] In some embodiments, bonding comprises hybrid bonding.

[0055] In the embodiments of the present disclosure, all bonding involved in forming a semiconductor structure may include hybrid bonding.

[0056] Figure 4A schematic partial cross-sectional view of a structure obtained after thinning the first semiconductor layer according to an embodiment of the present disclosure. Figure 4 The first semiconductor layer 101 can be thinned by grinding, dry etching, wet etching, or any combination thereof. For example, grinding is first used to reduce a portion of the thickness of the first semiconductor layer 101, and then the first semiconductor layer 101 is further thinned by dry etching or wet etching. It is understood that the first semiconductor layer 101 can also be thinned directly by grinding, dry etching, or wet etching. It should be noted that the degree of thinning of the first semiconductor layer 101 can be adjusted according to needs.

[0057] In some embodiments, the first semiconductor layer 101 may include a contact structure 104 , which may be a vertical interconnect structure (Through Silicon Via, TSV).

[0058] In some embodiments, thinning the first semiconductor layer 101 may include thinning the first semiconductor layer 101 until the contact structure 104 is exposed.

[0059] Figure 5 This is a partial cross-sectional diagram of the structure obtained after forming a bonding bump according to an embodiment of the present disclosure. Figure 5 A bonding bump 105 and a bonding pad 106 disposed between the bonding bump 105 and the contact structure 104 may be formed on the contact structure 104 .

[0060] The contact structures, bonding bumps, and bonding pads involved in the embodiments of the present disclosure may include conductive materials.

[0061] Figure 6 A schematic partial cross-sectional view of a structure obtained after thinning the second semiconductor layer according to an embodiment of the present disclosure. Figure 6 , you can Figure 5 The semiconductor structure is flipped over, and the first wafer W1 is temporarily bonded to the carrier 107 via the bonding bumps 105. The second semiconductor layer 201 can then be thinned by grinding, dry etching, wet etching, or any combination thereof.

[0062] In some embodiments, the second semiconductor layer 201 may include a contact structure 204 , and the contact structure 204 may be a TSV.

[0063] In some embodiments, thinning the second semiconductor layer 201 may include thinning the second semiconductor layer 201 to expose the contact structure 204 .

[0064] Figure 7This is a partial cross-sectional diagram of the structure obtained after forming a bonding pad according to an embodiment of the present disclosure. Figure 7 , a bonding pad 205 may be formed on the contact structure 204 .

[0065] Figure 8 A partial cross-sectional view of a structure obtained after forming modified regions in the thinned first semiconductor layer and the second semiconductor layer according to an embodiment of the present disclosure. Figure 8 The carrier 107 and the first wafer W1 can be debonded, and then a laser irradiation process can be used to form modified regions A1 and A2 in the thinned first semiconductor layer 101 and second semiconductor layer 201, respectively. Here, the modified regions A1 are formed in the scribe lines of the first wafer W1, and the modified regions A2 are formed in the scribe lines of the second wafer W2.

[0066] In some embodiments, a modified region A1 and a modified region A2 can be simultaneously formed in the thinned first semiconductor layer 101 and the second semiconductor layer 201 through a laser irradiation process; or the modified region A1 can be first formed in the thinned first semiconductor layer 101 through a laser irradiation process, and then the modified region A2 can be formed in the thinned second semiconductor layer 201 through a laser irradiation process; or the modified region A2 can be first formed in the thinned second semiconductor layer 201 through a laser irradiation process, and then the modified region A1 can be formed in the thinned first semiconductor layer 101 through a laser irradiation process.

[0067] In some embodiments, the depth of the modified region in the Z direction and the size range in the XOY plane can be controlled by adjusting the parameters of the laser irradiation process. Laser irradiation process parameters may include, for example, irradiation time, power, focus position, pulse scanning speed, and pulse repetition frequency. Specifically, the depth of the modified region in the Z direction can be adjusted by controlling the focus position, and the size of the modified region in the XOY plane can be adjusted by controlling the scanning speed.

[0068] In some embodiments, the second semiconductor layer 201 may be thinned before forming the bonding bump 105 .

[0069] In some embodiments, after forming the modified region in the first semiconductor layer 101 and / or the second semiconductor layer 201 , a bonding bump may be formed on the contact structure 104 in the first semiconductor layer 101 or the contact structure 204 in the second semiconductor layer 201 .

[0070] In some embodiments, after forming the modified region in the first semiconductor layer 101 and / or the second semiconductor layer 201 , a bonding pad may be formed on the contact structure 104 in the first semiconductor layer 101 or the contact structure 204 in the second semiconductor layer 201 .

[0071] In some embodiments, the film can be expanded to Figure 8 The semiconductor structure shown is expanded to obtain a first chip stack structure. Here, when expanding the semiconductor structure, the semiconductor structure can be fractured along the modified region A1 and the modified region A2 to obtain the first chip stack structure. Here, each first chip stack structure includes four layers of chips stacked along the Z direction, and each chip can include a memory array, such as a DRAM memory array.

[0072] In other embodiments, the Figure 8 The semiconductor structure shown is expanded to obtain a first chip stacking structure.

[0073] like Figure 8 As shown, in this embodiment, the first wafer W1 and the second wafer W2 are first bonded, and then the first semiconductor layer 101 is thinned to expose the contact structure 104 in the first semiconductor layer 101, and then a bonding pad 106 and a bonding bump 105 are formed on the contact structure 104, and then the bonding bump 105 is temporarily bonded to the carrier 107, and then the second semiconductor layer 201 is thinned to expose the contact structure 204 in the second semiconductor layer 201, and a bonding pad 205 is formed on the contact structure 204, and then a laser stealth cutting process is used to form a modified region A1 and a modified region A2 in the first semiconductor layer 101 and the second semiconductor layer 201 respectively, and then the modified region A1 and the modified region A2 are expanded or split to form a stacked chip stacking structure (i.e., a first chip stacking structure). In this embodiment, bonding is performed first and then the laser stealth cutting process is performed, which can improve the influence of the modified region formed by the laser stealth cutting process on hybrid bonding. If the modified region is formed first and then hybrid bonding is performed, factors such as temperature and pressure involved in the hybrid bonding process will further expand the modified region, thereby affecting the bonding effect.

[0074] Figure 9 A schematic cross-sectional view of a semiconductor device including a first chip stack structure provided by an embodiment of the present disclosure. Figure 9The first chip stacking structure 501 is a top chip stacking structure, and the first chip stacking structure 502 is a middle chip stacking structure. One surface of the first chip stacking structure 501 along the Z direction may include a bonding bump (e.g., the bonding bump 105 described above); and two surfaces of the first chip stacking structure 502 along the Z direction may respectively include a bonding bump (e.g., the bonding bump 105 described above) and a bonding pad (e.g., the bonding pad 205 described above).

[0075] In some embodiments, the first chip stack structure 501, the at least one first chip stack structure 502 and the logic chip 503 may be bonded along the Z direction to obtain Figure 9 The semiconductor device shown is a high bandwidth memory (HBM). Specifically, bonding bumps on a first chip stack structure may be thermally compressed and bonded to bonding pads on another adjacent first chip stack structure or logic chip.

[0076] here, Figure 9 The chip shown has 12 stacked layers.

[0077] It should be noted that the number of chip stacking layers of the semiconductor device in the embodiment of the present disclosure is not limited to Figure 9 The number of stacked layers shown.

[0078] Figures 10 to 18 This is a schematic diagram of the structure of the semiconductor structure at various stages in the second embodiment of the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure. It should be noted that: Figures 10 to 18 This is a complete schematic diagram reflecting the implementation process of the manufacturing method of the semiconductor structure. The unmarked parts in some drawings can be shared with each other. Figure 1 、 Figures 10 to 18 , the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0079] It should be noted that Figures 10 to 18 The schematic diagram of the partial cross section of the semiconductor structure at various stages is shown. It can be understood that Figures 10 to 18 Only two adjacent chip areas and a cross-sectional schematic diagram of the cutting path therebetween are shown.

[0080] In some embodiments, the manufacturing method also includes: providing a second bonding structure, the second bonding structure includes a third wafer and a fourth wafer, the third wafer includes a third semiconductor layer, and the fourth wafer includes a fourth semiconductor layer; the third semiconductor layer and the fourth semiconductor layer are respectively located on opposite sides of the second bonding structure along the bonding direction; thinning the third semiconductor layer and / or the fourth semiconductor layer, and forming a modified region in the thinned third semiconductor layer and / or the fourth semiconductor layer through a laser irradiation process; and bonding the first bonding structure and the second bonding structure.

[0081] In some embodiments, a first bonding interface 100 is included between the first wafer W1 and the second wafer W2; along the Z direction, the first wafer W1 also includes a first device layer 102 arranged between the first bonding interface 100 and the first semiconductor layer 101, and the second wafer W2 also includes a second device layer 202 arranged between the first bonding interface 100 and the second semiconductor layer 201; a second bonding interface 200 is included between the third wafer W3 and the fourth wafer W4; along the Z direction, the third wafer W3 also includes a third device layer 302 arranged between the second bonding interface 200 and the third semiconductor layer 301, and the fourth wafer W4 also includes a fourth device layer 402 arranged between the second bonding interface 200 and the fourth semiconductor layer 401.

[0082] In the embodiment of the present disclosure, by providing a first wafer and a second wafer that are bonded and a third wafer and a fourth wafer that are bonded, and then forming a modified region in the first semiconductor layer in the first wafer and / or the second semiconductor layer in the second wafer and the third semiconductor layer in the third wafer and / or the fourth semiconductor layer in the fourth wafer through a laser irradiation process, a four-layer stacked bonded bare chip can be obtained after the first bonding structure and the second bonding structure that are bonded are expanded and separated, thereby improving the bonding efficiency; and there will be basically no cracks on the edges of the four-layer stacked bonded bare chips separated by the laser irradiation process, which can effectively improve the yield of the bare chip; at the same time, it can avoid stacking bonding after the modified region is formed, which will cause the modified region to expand and have an adverse effect on the stacking bonding effect.

[0083] Figure 10 A partial cross-sectional diagram of a first bonding structure and a second bonding structure provided in one embodiment of the present disclosure. Figure 10 The first bonding structure includes a first wafer W1 and a second wafer W2. Here, the specific structures of the first wafer W1 and the second wafer W2 are the same as Figure 3 In the first bonding structure shown, the specific structures of the first wafer W1 and the second wafer W2 may be the same.

[0084] See also Figure 10The second bonding structure includes a third wafer W3 and a fourth wafer W4. The third wafer W3 includes a third semiconductor layer 301, and the fourth wafer W4 includes a fourth semiconductor layer 401. The third semiconductor layer 301 and the fourth semiconductor layer 401 are stacked along the Z direction.

[0085] In some embodiments, the third wafer W3 and the fourth wafer W4 include a second bonding interface 200. Along the Z direction, the third wafer W3 further includes a third device layer 302 disposed between the third semiconductor layer 301 and the second bonding interface 200, and the fourth wafer W4 further includes a fourth device layer 402 disposed between the fourth semiconductor layer 401 and the second bonding interface 200.

[0086] In some embodiments, a third bonding layer 303 may be formed on a surface of the third device layer 302 away from the third semiconductor layer 301, and a fourth bonding layer 403 may be formed on a surface of the fourth device layer 402 away from the fourth semiconductor layer 401. The third wafer W3 and the fourth wafer W4 may be bonded via the third bonding layer 303 and the fourth bonding layer 403.

[0087] Figure 11 A partial cross-sectional view of a structure obtained after thinning the second semiconductor layer and the third semiconductor layer according to an embodiment of the present disclosure. Figure 11 The second semiconductor layer 201 and the third semiconductor layer 301 may be thinned respectively by grinding, dry etching, wet etching or any combination thereof.

[0088] In some embodiments, the second semiconductor layer 201 may include a contact structure 204, and the third semiconductor layer 301 may include a contact structure 304. Both the contact structure 204 and the contact structure 304 may be TSVs.

[0089] In some embodiments, thinning the second semiconductor layer 201 and the third semiconductor layer 301 may include thinning the second semiconductor layer 201 and the third semiconductor layer 301 to expose the contact structure 204 and the contact structure 304 , respectively.

[0090] Figure 12 A partial cross-sectional view of a structure obtained after forming a modified region in the thinned second semiconductor layer and the third semiconductor layer according to an embodiment of the present disclosure. Figure 12 , a laser irradiation process can be used to form modified regions A2 and A3 in the thinned second semiconductor layer 201 and the third semiconductor layer 301, respectively. Here, the modified regions A2 are formed in the scribe lines of the second wafer W2, and the modified regions A3 are formed in the scribe lines of the third wafer W3.

[0091] In some embodiments, the modified region A2 and the modified region A3 can be simultaneously formed in the thinned second semiconductor layer 201 and the third semiconductor layer 301 through a laser irradiation process; the modified region A2 can be first formed in the thinned second semiconductor layer 201 through a laser irradiation process, and then the modified region A3 can be formed in the thinned third semiconductor layer 301 through a laser irradiation process; or the modified region A3 can be first formed in the thinned third semiconductor layer 301 through a laser irradiation process, and then the modified region A2 can be formed in the thinned second semiconductor layer 201 through a laser irradiation process.

[0092] In some embodiments, bonding the first bonding structure to the second bonding structure includes bonding the thinned first semiconductor layer 101 or the second semiconductor layer 201 to the thinned third semiconductor layer 301 or the fourth semiconductor layer 401. This embodiment is described by bonding the thinned second semiconductor layer 201 to the thinned third semiconductor layer 301.

[0093] In some embodiments, the second semiconductor layer 201 is thinned, including: thinning the second semiconductor layer 201 to expose the contact structure 204 in the second semiconductor layer 201; the third semiconductor layer 301 is thinned, including: thinning the third semiconductor layer 301 to expose the contact structure 304 in the third semiconductor layer 301; the thinned second semiconductor layer 201 and the thinned third semiconductor layer 301 are bonded, including: bonding the contact structure 204 in the thinned second semiconductor layer 201 and the contact structure 304 in the thinned third semiconductor layer 301.

[0094] In some embodiments, the first semiconductor layer 101 and the fourth semiconductor layer 401 may be thinned and then hybrid-bonded.

[0095] In some embodiments, the first semiconductor layer 101 and the third semiconductor layer 301 may be thinned and then hybrid-bonded.

[0096] In some embodiments, the second semiconductor layer 201 and the fourth semiconductor layer 401 may be thinned and then hybrid-bonded.

[0097] Figure 13 A partial cross-sectional diagram of a structure obtained after bonding the second wafer and the third wafer according to an embodiment of the present disclosure. Figure 13 , the second wafer W2 and the third wafer W3 can be bonded by hybrid bonding.

[0098] In some embodiments, the first wafer and the second wafer are not thinned before the first bonding structure and the second bonding structure are bonded, so that the first bonding structure and the second bonding structure before bonding have a larger thickness along the Z direction. Therefore, before the first bonding structure and the second bonding structure are bonded, forming a modified area in the second wafer and the third wafer through the laser irradiation process will basically not affect the bonding of the first bonding structure and the second bonding structure.

[0099] In addition, in the embodiment of the present disclosure, before bonding the first bonding structure and the second bonding structure, a modified region is formed in the semiconductor layer (for example, the second semiconductor layer 201 and the third semiconductor layer 301) instead of forming a modified region in the device layer (for example, the second device layer 202 and the third device layer 303), so that the first bonding structure and the second bonding structure before bonding have a certain strength, thereby preventing the formed modified region from affecting the bonding of the first bonding structure and the second bonding structure.

[0100] Figure 14 A schematic partial cross-sectional view of a structure obtained after thinning the first semiconductor layer according to an embodiment of the present disclosure. Figure 14 The first semiconductor layer 101 can be thinned by grinding, dry etching, wet etching or any combination thereof.

[0101] In some embodiments, the contact structure includes a vertical interconnect structure.

[0102] The contact structures involved in the embodiments of the present disclosure may all include TSVs. For example, the first semiconductor layer 101 may include a contact structure 104 , which extends along the Z direction and is connected to the device structure in the first device layer 102 .

[0103] In some embodiments, thinning the first semiconductor layer 101 may include thinning the first semiconductor layer 101 until the contact structure 104 is exposed.

[0104] Figure 15 This is a partial cross-sectional diagram of the structure obtained after forming a bonding bump according to an embodiment of the present disclosure. Figure 15 , a bonding bump 105 and a bonding pad 106 disposed between the bonding bump 105 and the contact structure 104 may be formed on the contact structure 104 .

[0105] In some embodiments, thinning the first semiconductor layer 101 and the fourth semiconductor layer 401 includes: thinning the first semiconductor layer 101; temporarily bonding the thinned first semiconductor layer 101 to the carrier 107; and thinning the fourth semiconductor layer 401.

[0106] Figure 16 This is a partial cross-sectional diagram of a structure obtained after thinning the fourth semiconductor layer according to an embodiment of the present disclosure. Figure 16 , you can Figure 15 The semiconductor structure is flipped over, and the first wafer W1 is temporarily bonded to the carrier 107 via the bonding bumps 105. The fourth semiconductor layer 401 can then be thinned by grinding, dry etching, wet etching, or any combination thereof.

[0107] In some embodiments, the fourth semiconductor layer 401 may include a contact structure 404 , and the contact structure 404 may be a TSV.

[0108] In some embodiments, thinning the fourth semiconductor layer 401 may include thinning the fourth semiconductor layer 401 until the contact structure 404 is exposed.

[0109] Figure 17 This is a partial cross-sectional diagram of the structure obtained after forming a bonding pad according to an embodiment of the present disclosure. Figure 17 , a bonding pad 405 may be formed on the contact structure 404 .

[0110] In some embodiments, when the thinned second semiconductor layer 201 and the thinned third semiconductor layer 301 are bonded, the manufacturing method further includes: thinning the first semiconductor layer 101 and the fourth semiconductor layer 401; and forming a modified region in the thinned first semiconductor layer 101 and the thinned fourth semiconductor layer 401 through a laser irradiation process.

[0111] Figure 18 A partial cross-sectional view of a structure obtained after forming a modified region in the thinned first semiconductor layer and the fourth semiconductor layer according to an embodiment of the present disclosure. Figure 18 The carrier 107 and the first wafer W1 can be debonded, and then a laser irradiation process can be used to form modified regions A1 and A4 in the thinned first semiconductor layer 101 and fourth semiconductor layer 401, respectively. Here, the modified regions A1 are formed in the scribe lines of the first wafer W1, and the modified regions A4 are formed in the scribe lines of the fourth wafer W4.

[0112] In some embodiments, the modified region A1 and the modified region A4 can be simultaneously formed in the thinned first semiconductor layer 101 and the fourth semiconductor layer 401 through a laser irradiation process; the modified region A1 can be first formed in the thinned first semiconductor layer 101 through a laser irradiation process, and then the modified region A4 can be formed in the thinned fourth semiconductor layer 401 through a laser irradiation process; or the modified region A4 can be first formed in the thinned fourth semiconductor layer 401 through a laser irradiation process, and then the modified region A1 can be formed in the thinned first semiconductor layer 101 through a laser irradiation process.

[0113] In some embodiments, before bonding the first bonding structure and the second bonding structure, the second semiconductor layer 201 and the third semiconductor layer 301 may be thinned, and the first semiconductor layer 101 and / or the fourth semiconductor layer 401 may be thinned.

[0114] In some embodiments, before bonding the first bonding structure and the second bonding structure, a modified region A2 and a modified region A3 can be respectively formed in the thinned second semiconductor layer 201 and the third semiconductor layer 301 by a laser irradiation process, and a modified region A3 and / or a modified region A4 can be respectively formed in the first semiconductor layer 101 and / or the fourth semiconductor layer 401 by a laser irradiation process.

[0115] In some embodiments, before bonding the first bonding structure and the second bonding structure, a bonding bump may be formed on the contact structure 204 of the second semiconductor layer 201 .

[0116] In some embodiments, after forming the modified region in the first semiconductor layer 101 and / or the second semiconductor layer 201 , a bonding bump may be formed on the contact structure 104 in the first semiconductor layer 101 or the contact structure 204 in the second semiconductor layer 201 .

[0117] In some embodiments, after forming the modified region in the third semiconductor layer 301 and / or the fourth semiconductor layer 401 , a bonding pad may be formed on the contact structure 304 in the third semiconductor layer 301 or the contact structure 404 in the fourth semiconductor layer 401 .

[0118] In some embodiments, the film can be expanded to Figure 18 The semiconductor structure shown is expanded to obtain a first chip stack structure. Here, when expanding the semiconductor structure, the semiconductor structure can be fractured along the modified regions A1, A2, A3, and A4 to obtain a second chip stack structure. Here, each first chip stack structure includes chips stacked in a Z direction, and each chip can include a memory array, such as a DRAM memory array.

[0119] In other embodiments, the Figure 18 The semiconductor structure shown is expanded to obtain a second chip stacking structure.

[0120] like Figure 18 As shown, in this embodiment, the first wafer W1 and the second wafer W2 are first bonded and the third wafer W3 and the fourth wafer W4 are bonded. Then, the second semiconductor layer 201 and the third semiconductor layer 301 are thinned to expose the contact structure 204 in the second semiconductor layer 201 and the contact structure 304 in the third semiconductor layer 301. Then, a laser stealth cutting process is performed to form a modified region A2 and a modified region A3 in the second semiconductor layer 201 and the third semiconductor layer 301, respectively. Then, the second semiconductor layer 201 and the third semiconductor layer 301 are bonded. Then, the first semiconductor layer 101 is thinned to expose the contact structure 104 in the first semiconductor layer 101. , then forming a bonding pad 106 and a bonding bump 105 on the contact structure 104, then temporarily bonding the bonding bump 105 to the carrier 107, then thinning the fourth semiconductor layer 401 to expose the contact structure 404 in the fourth semiconductor layer 401, and forming a bonding pad 405 on the contact structure 404, then forming a modified region A1 and a modified region A4 in the first semiconductor layer 101 and the fourth semiconductor layer 401 respectively through a laser stealth cutting process, and then expanding or splitting the modified region A1, modified region A2, modified region A3 and modified region A4 to form a stacked chip stacking structure (i.e., a second chip stacking structure). The embodiment of the present disclosure can improve the influence of the modified region formed by the laser stealth cutting process on hybrid bonding by first providing the bonded first wafer and second wafer and the bonded second wafer and third wafer. If the modified region is formed first and then hybrid bonding is performed, factors such as temperature and pressure involved in the hybrid bonding process will further expand the modified region, thereby affecting the bonding effect. In addition, in the embodiment of the present disclosure, the second semiconductor layer and the third semiconductor layer are first subjected to a laser stealth cutting process, and then the second semiconductor layer and the third semiconductor layer are bonded, and then the first semiconductor layer and the fourth semiconductor layer are thinned and subjected to a laser stealth cutting process. Because the first semiconductor layer and the fourth semiconductor layer are not thinned before the first bonding structure and the second bonding structure are bonded, the first bonding structure and the second bonding structure both have a large thickness. Therefore, when the second semiconductor layer and the third semiconductor layer are bonded, the influence of the modified region on the bonding process can be reduced.

[0121] Figure 19 A schematic cross-sectional view of a semiconductor device including a second chip stack structure provided by an embodiment of the present disclosure. Figure 19The second chip stacking structure 601 is a top chip stacking structure, and the second chip stacking structure 602 is a middle chip stacking structure. One surface of the second chip stacking structure 601 along the Z direction may include a bonding bump (e.g., the bonding bump 105 described above); and two surfaces of the second chip stacking structure 602 along the Z direction may respectively include a bonding bump (e.g., the bonding bump 105 described above) and a bonding pad (e.g., the bonding pad 405 described above).

[0122] In some embodiments, the second chip stack structure 601, the at least one second chip stack structure 602 and the logic chip 603 may be bonded along the Z direction to obtain Figure 19 The semiconductor device shown in FIG. may specifically be a process of thermocompression bonding of the bonding bumps on the second chip stack structure to the bonding pads on the adjacent other second chip stack structures or logic chips.

[0123] here, Figure 19 The chip shown has 12 stacked layers.

[0124] It should be noted that the number of chip stacking layers of the semiconductor device in the embodiment of the present disclosure is not limited to Figure 19 The number of stacked layers shown.

[0125] Figure 20 This is a schematic diagram of the steps of a second method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Figure 20 , the manufacturing method comprises the following steps:

[0126] S100: providing a first bonding structure and a second bonding structure; the first bonding structure includes a first wafer and a second wafer, and the second bonding structure includes a third wafer and a fourth wafer.

[0127] S200: forming modified regions in the second wafer and the third wafer through a laser irradiation process.

[0128] S300: Bonding the second wafer and the third wafer.

[0129] The following will be combined Figure 1 、 Figures 10 to 18 , the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0130] In some embodiments, after bonding the second wafer W2 and the third wafer W3 , the manufacturing method further includes: forming modified regions in the first wafer W1 and the fourth wafer W4 through a laser irradiation process.

[0131] In some embodiments, before forming the modified regions in the second wafer W2 and the third wafer W3 through the laser irradiation process, the manufacturing method further includes: performing a thinning process on the second wafer W2 and the third wafer W3.

[0132] In some embodiments, before forming the modified regions in the first wafer W1 and the fourth wafer W4 through the laser irradiation process, the manufacturing method further includes: performing a thinning process on the first wafer W1 and the fourth wafer W4.

[0133] In some embodiments, thinning the first wafer W1 and the fourth wafer W4 includes: thinning the first wafer W1; temporarily bonding the thinned first wafer W1 to a carrier; and thinning the fourth wafer W4.

[0134] In some embodiments, the first wafer W1 , the second wafer W2 , the third wafer W3 , and the fourth wafer W4 each include a plurality of chip regions 11 and scribe lines 12 located between adjacent chip regions 11 ; the modified regions are formed in the scribe lines 12 .

[0135] It should be noted that the description of the second method for manufacturing a semiconductor structure is similar to the description of the first embodiment of the method for manufacturing a semiconductor structure, and has similar beneficial effects as the first embodiment of the method for manufacturing a semiconductor structure. For technical details not disclosed in the second embodiment of the method for manufacturing a semiconductor structure of the present disclosure, please refer to the description of the first embodiment of the method for manufacturing a semiconductor structure of the present disclosure for an understanding.

[0136] like Figure 18As shown, in this embodiment, the first wafer and the second wafer are first bonded and the third wafer and the fourth wafer are bonded, and then the second wafer and the third wafer are thinned, and then a laser invisible cutting process is used to form a modified area A2 and a modified area A3 in the second wafer and the third wafer respectively, and then the second wafer and the third wafer are bonded, and then the first wafer is thinned to expose the contact structure in the first wafer, and then a bonding pad and a bonding bump are formed on the contact structure, and then the bonding bump is temporarily bonded to the carrier, and then the fourth wafer is thinned to expose the contact structure in the fourth wafer, and a bonding pad is formed on the contact structure, and then a laser invisible cutting process is used to form a modified area A1 and a modified area A4 in the first wafer and the fourth wafer respectively, and then the modified area A1, the modified area A2, the modified area A3 and the modified area A4 are expanded or split to form a stacked chip stacking structure (i.e., a second chip stacking structure). The embodiment of the present disclosure can improve the influence of the modified area formed by the laser stealth cutting process on the hybrid bonding by first providing the first wafer and the second wafer after bonding and the second wafer and the third wafer after bonding. If the modified area is formed first and then the hybrid bonding is performed, the temperature, pressure and other factors involved in the hybrid bonding process will further expand the modified area, thereby affecting the bonding effect. In addition, the embodiment of the present disclosure first performs a laser stealth cutting process on the second wafer and the third wafer, then bonds the second wafer and the third wafer, and then thins and performs a laser stealth cutting process on the first wafer and the fourth wafer. Since the first wafer and the fourth wafer are not thinned before the first bonding structure and the second bonding structure are bonded, the first bonding structure and the second bonding structure both have a large thickness. Therefore, when the second wafer and the third wafer are bonded, the influence of the modified area on the bonding process can be reduced.

[0137] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a first bonding structure, the first bonding structure including a first wafer and a second wafer, the first wafer including a first semiconductor layer, and the second wafer including a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are respectively located on opposite sides of the first bonding structure along a bonding direction; thinning the first semiconductor layer and / or the second semiconductor layer; and forming a modified region in the thinned first semiconductor layer and / or the second semiconductor layer through a laser irradiation process. In the embodiment of the present disclosure, by providing a first wafer and a second wafer that are bonded, then thinning the first wafer and / or the second wafer, and then forming a modified region in the first semiconductor layer in the first wafer and / or the second semiconductor layer in the second wafer through a laser irradiation process, a stacked bonded bare chip can be obtained after the first bonding structure is expanded and separated, thereby improving the bonding efficiency; and the edges of the stacked bonded bare chip separated by the laser irradiation process will basically not have cracks, which can effectively improve the yield of the bare chip; at the same time, it can avoid stacking bonding after the modified region is formed, which will cause the modified region to expand and have an adverse effect on the stacking bonding effect.

[0138] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0139] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing a first bonding structure, the first bonding structure comprising a first wafer and a second wafer, the first wafer comprising a first semiconductor layer, the second wafer comprising a second semiconductor layer; the first semiconductor layer and the second semiconductor layer are respectively located on opposite sides of the first bonding structure along a bonding direction; performing a thinning process on the first semiconductor layer and / or the second semiconductor layer; A modified region is formed in the thinned first semiconductor layer and / or the second semiconductor layer through a laser irradiation process.

2. The method according to claim 1, characterized in that The method further comprises: Providing a second bonding structure, the second bonding structure comprising a third wafer and a fourth wafer, the third wafer comprising a third semiconductor layer, and the fourth wafer comprising a fourth semiconductor layer; the third semiconductor layer and the fourth semiconductor layer are respectively located on opposite sides of the second bonding structure along the bonding direction; Thinning the third semiconductor layer and / or the fourth semiconductor layer, and forming a modified region in the thinned third semiconductor layer and / or the fourth semiconductor layer through a laser irradiation process; The first bonding structure and the second bonding structure are bonded.

3. The method according to claim 2, characterized in that Bonding the first bonding structure and the second bonding structure includes: The thinned first semiconductor layer or the second semiconductor layer is bonded to the thinned third semiconductor layer or the fourth semiconductor layer.

4. The method according to claim 3, characterized in that When the thinned second semiconductor layer and the thinned third semiconductor layer are bonded together, the method further includes: performing a thinning process on the first semiconductor layer and the fourth semiconductor layer; A modified region is formed in the thinned first semiconductor layer and the thinned fourth semiconductor layer through a laser irradiation process.

5. The method according to claim 4, characterized in that performing a thinning process on the second semiconductor layer, comprising: thinning the second semiconductor layer until a contact structure in the second semiconductor layer is exposed; Performing a thinning process on the third semiconductor layer, comprising: thinning the third semiconductor layer until a contact structure in the third semiconductor layer is exposed; Bonding the thinned second semiconductor layer and the thinned third semiconductor layer includes: bonding a contact structure in the thinned second semiconductor layer and a contact structure in the thinned third semiconductor layer.

6. The method according to claim 4, characterized in that The first semiconductor layer and the fourth semiconductor layer are thinned, comprising: performing a thinning process on the first semiconductor layer; Temporarily bonding the thinned first semiconductor layer to the carrier; The fourth semiconductor layer is thinned.

7. The method according to claim 2, characterized in that The first wafer and the second wafer include a first bonding interface between them; along the bonding direction, the first wafer further includes a first device layer disposed between the first bonding interface and the first semiconductor layer, and the second wafer further includes a second device layer disposed between the first bonding interface and the second semiconductor layer; The third wafer and the fourth wafer include a second bonding interface; along the bonding direction, the third wafer also includes a third device layer arranged between the second bonding interface and the third semiconductor layer, and the fourth wafer also includes a fourth device layer arranged between the second bonding interface and the fourth semiconductor layer.

8. The method according to claim 5, characterized in that The contact structure includes a vertical interconnect structure.

9. The method according to claim 2, characterized in that The bonding includes mixed bonding.

10. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing a first bonding structure and a second bonding structure; the first bonding structure includes a first wafer and a second wafer, and the second bonding structure includes a third wafer and a fourth wafer; forming modified regions in the second wafer and the third wafer through a laser irradiation process; The second wafer and the third wafer are bonded.

11. The method according to claim 10, characterized in that After bonding the second wafer and the third wafer, the method further includes: Modified regions are formed in the first wafer and the fourth wafer through a laser irradiation process.

12. The method according to claim 10, characterized in that Before forming the modified regions in the second wafer and the third wafer through the laser irradiation process, the method further includes: performing a thinning process on the second wafer and the third wafer.

13. The method according to claim 11, characterized in that Before forming the modified regions in the first wafer and the fourth wafer through the laser irradiation process, the method further includes: performing a thinning process on the first wafer and the fourth wafer.

14. The method according to claim 13, characterized in that performing a thinning process on the first wafer and the fourth wafer, comprising: performing a thinning process on the first wafer; Temporarily bonding the thinned first wafer to a carrier; The fourth wafer is thinned.

15. The method according to claim 10, characterized in that The first wafer, the second wafer, the third wafer and the fourth wafer each include a plurality of chip areas and dicing lanes between adjacent chip areas; The modified region is formed in the scribe line.

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