Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an isolation structure and an active region isolated by the isolation structure; the material of the isolation structure comprises oxide; executing an ion implantation process, and forming a well region in the active region; and carrying out annealing treatment on the active region in a mixed atmosphere comprising an oxidizing gas and an inert gas, so that the surface layer of the active region is oxidized into an oxide layer in the annealing treatment process. Therefore, the stress pulling effect of the isolation structure on the active region under the high temperature condition can be remarkably eliminated through the oxide layer, lattice damage caused by deformation of the active region is greatly reduced, and the product yield can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] As electronic products continue to miniaturize, increasing the integration density of semiconductor devices has become a key technological requirement in semiconductor device manufacturing. To achieve this goal, a strategy is often adopted to fabricate multiple electronic components on a single wafer. Specifically, multiple active regions for core components are formed within the wafer, and adjacent active regions are insulated and isolated by isolation structures to ensure electrical independence between components.

[0003] In the semiconductor device fabrication process, ion implantation is a key step in forming doped regions with specific concentrations and depth distributions within the active region, enabling the construction of basic electronic components such as transistors and diodes within the active region. After ion implantation, annealing is a key subsequent step. Its role is to promote further diffusion and redistribution of the implanted ions in a high-temperature environment (also known as "high-temperature push-in" in the industry), thereby optimizing the concentration, depth, and uniformity of the doped regions, ultimately improving the overall performance of the semiconductor device.

[0004] However, during the annealing process, the active area is easily damaged, which in turn affects the product yield. Therefore, how to reduce the damage to the active area during the high-temperature annealing process is an urgent problem that needs to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising:

[0007] Providing a substrate, wherein the substrate includes an isolation structure and an active area isolated by the isolation structure; the material of the isolation structure includes oxide;

[0008] performing an ion implantation process to form a well region in the active region;

[0009] The active region is annealed in a mixed atmosphere including an oxidizing gas and an inert gas, so that a surface layer of the active region is oxidized into an oxide layer during the annealing process.

[0010] In combination with the first aspect of the present application, in an optional embodiment, the volume fraction of the oxidizing gas in the mixed atmosphere is less than or equal to 10%.

[0011] In combination with the first aspect of the present application, in an optional embodiment, the oxidizing gas includes at least one of O2, O3, H2O2 steam, and H2O steam.

[0012] In conjunction with the first aspect of the present application, in an optional embodiment, the temperature of the annealing treatment is 500°C to 1200°C.

[0013] In conjunction with the first aspect of the present application, in an optional embodiment, the annealing treatment time is less than or equal to 10 minutes.

[0014] In conjunction with the first aspect of the present application, in an optional embodiment, the thickness of the oxide layer is 10 angstroms to 100 angstroms.

[0015] In conjunction with the first aspect of the present application, in an optional embodiment,

[0016] Before performing the ion implantation, the method further includes: forming a sacrificial oxide layer on the surface of the active area;

[0017] Before performing the annealing process on the active area, the method further includes performing a cleaning process on the surface of the active area, and the sacrificial oxide layer is removed during the cleaning process.

[0018] In conjunction with the first aspect of the present application, in an optional implementation manner, after performing the annealing treatment on the active region, the method further includes:

[0019] The oxide layer is removed.

[0020] In conjunction with the first aspect of the present application, in an optional implementation manner, after performing the annealing treatment on the active region, the method further includes:

[0021] A source region and a drain region are formed in the active region.

[0022] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the preparation method of the semiconductor structure described in any one of the first aspects.

[0023] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0024] The embodiments of the present application provide a method for preparing a semiconductor structure and a semiconductor structure, wherein the method for preparing the semiconductor structure comprises: providing a substrate, wherein the substrate comprises an isolation structure and an active area isolated by the isolation structure; the material of the isolation structure comprises an oxide; performing an ion implantation process to form a well area in the active area; and annealing the active area in a mixed atmosphere comprising an oxidizing gas and an inert gas, so that during the annealing process, the surface layer of the active area is oxidized into an oxide layer. In an embodiment of the present application, an annealing treatment is performed by introducing a mixed atmosphere including an oxidizing gas and an inert gas. Under the premise of not affecting the original annealing process, the surface layer of the active area can be oxidized into an oxide layer during the annealing process. On the one hand, the oxide layer is connected to the isolation structure and can generate a reverse force to reduce the magnitude of the tensile stress on the active area caused by the shrinkage of the isolation structure at high temperature. On the other hand, the oxide layer formed on the surface of the active area can alleviate the tensile stress generated by the isolation structure. The stress concentration phenomenon on the surface of the active area is caused, so as to avoid lattice damage such as defects from occurring on the surface of the active area and extending to the interior of the active area, thereby significantly reducing the lattice damage caused by deformation of the active area under the action of tensile stress, thereby effectively improving the product yield. Additional aspects and advantages of the present application will be partially given in the following description, and some will become apparent from the following description or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0026] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor structure preparation method provided in the related art during the preparation process;

[0027] Figure 2 A cross-sectional electron microscope image of a semiconductor structure prepared by a method for preparing a semiconductor structure provided in the related art;

[0028] Figure 3 A cross-sectional electron microscope image of another semiconductor structure prepared by the semiconductor structure preparation method provided in the related art;

[0029] Figure 4 A cross-sectional electron microscope image of another semiconductor structure prepared by the method for preparing a semiconductor structure provided in the related art;

[0030] Figure 5 A schematic cross-sectional view of a semiconductor structure prepared by a method for preparing a semiconductor structure provided in the related art;

[0031] Figure 6A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0032] Figures 7 to 10 A schematic diagram of the cross-sectional structure of a semiconductor structure during the preparation process of the method for preparing the semiconductor structure provided in an embodiment of the present application;

[0033] Figure 11 A defect distribution map obtained by detecting defects in a semiconductor structure produced in the related art;

[0034] Figure 12 The defect distribution map is obtained by detecting defects in the semiconductor structure manufactured in this application. DETAILED DESCRIPTION

[0035] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0036] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0037] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0038] When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as the second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present application.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. In addition to the orientations shown in the figures, spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0042] For related technologies, please refer to Figure 1 The method for preparing a semiconductor structure includes: first, forming an isolation structure 200 in a substrate 100, the isolation structure 200 isolates an active area 300, and the isolation structure 200 provides electrical isolation for the active area 300 to prevent leakage and interference between different devices. Its material is specifically silicon oxide; next, ion implantation is performed on the active area 300 to form a well area (not shown); next, the substrate 100 is annealed in an inert gas atmosphere. The inventor found in the study that after the substrate 100 was annealed, the active area 300 had different degrees of lattice damage from the surface to the inside. For details, please refer to Figures 2 to 4 , Figure 2 In the cross-sectional electron microscope image of the semiconductor structure shown, dislocation defects (such as Figure 2 shown in the middle circle), Figure 3 In the cross-sectional electron microscope image of the semiconductor structure shown in FIG, dislocation defects and obvious lattice damage (such as Figure 3 shown in the middle circle), Figure 4 In the cross-sectional electron microscope image of the semiconductor structure shown in FIG, a cavity appears in the active region 300 (e.g. Figure 4 The inventors further studied and analyzed that during the annealing process after ion implantation, as the temperature rises rapidly, the isolation structure 200 made of silicon oxide will shrink sharply, causing the active area 300 exposed on the surface to be pulled by the stress of the isolation structures 200 on both sides (as shown in the figure). Figure 5 The active region 300 is deformed, thereby causing lattice damage to the active region 300 , which is manifested macroscopically as dislocations or even voids in the active region 300 of the final semiconductor structure, which greatly reduces the product yield.

[0043] Based on this, the present invention provides a method for preparing a semiconductor structure. Figure 6 The method for preparing a semiconductor structure provided in an embodiment of the present application includes:

[0044] Step S101, providing a substrate, wherein the substrate includes an isolation structure and an active area isolated by the isolation structure; the isolation structure is made of an oxide;

[0045] Step S102, performing an ion implantation process to form a well region in the active region;

[0046] Step S103 , performing an annealing treatment on the active region in a mixed atmosphere including an oxidizing gas and an inert gas, so that the surface layer of the active region is oxidized into an oxide layer during the annealing treatment.

[0047] It is understandable that during the annealing process, as the temperature rises rapidly, the isolation structure will shrink sharply and produce stress pulling on the active area. The surface of the active area is the boundary of stress transfer. Due to the uneven stress distribution, stress concentration is prone to occur on the surface of the active area. Moreover, under the action of stress pulling, the surface of the active area is more likely to deform uncoordinatedly, thereby causing lattice damage from the surface of the active area to the inside. In an embodiment of the present application, an annealing treatment is performed by introducing a mixed atmosphere including an oxidizing gas and an inert gas. Under the premise of not affecting the original annealing process, the surface layer of the active area can be oxidized into an oxide layer during the annealing process. On the one hand, the oxide layer is connected to the isolation structure and can generate a reverse force to reduce the magnitude of the tensile stress on the active area caused by the contraction of the isolation structure. On the other hand, the oxide layer formed on the surface of the active area can alleviate the tensile stress generated by the isolation structure and cause stress concentration on the surface of the active area, so as to avoid lattice damage such as defects from occurring on the surface of the active area and extending to the interior of the active area, thereby greatly reducing the lattice damage caused by deformation of the active area under the action of tensile stress, thereby effectively improving the product yield.

[0048] Next, combine Figures 7 to 10 , the preparation method of the semiconductor structure and the semiconductor structure provided in the embodiments of the present application and the corresponding beneficial effects are further described in detail.

[0049] First, please refer to Figure 7 , performing step S101, providing a substrate 100, the substrate 100 includes an isolation structure 200 and an active area 300 isolated by the isolation structure 200; the material of the isolation structure 200 includes oxide.

[0050] In the embodiment of the present application, the substrate 100 may include, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Although several examples of substrate 100 types are described here, any other substrate whose surface layer can be oxidized to form an oxide layer in an oxidizing gas environment falls within the spirit and scope of the present application. The isolation structure 200 is mainly used to achieve insulation isolation between adjacent active areas 300. In the actual preparation process, for example, a thermal oxidation process or an etching combined with deposition process can be used to form the isolation structure 200.

[0051] In some specific embodiments, the substrate 100 includes a silicon substrate. In the actual preparation process, the isolation structure 200 can be formed by a local oxidation of silicon (LOCOS) process. Specifically, a silicon nitride material layer (not shown) can be first formed on the surface of the substrate 100; then, part of the silicon nitride material layer is removed to form a silicon nitride mask layer to expose the area where the isolation structure 200 is to be formed; then, using the silicon nitride mask layer as a mask, the isolation structure 200 is grown in the area not covered by the silicon nitride mask layer by thermal oxidation. In the LOCOS process, due to the lateral diffusion of the oxidant and the edge effect of the silicon nitride mask layer, the two ends of the formed isolation structure 200 will form a sharp-angle structure similar to a bird's beak (such as Figure 7 This isolation structure 200 is also known as a field oxide layer. When used as the isolation structure 200, the field oxide layer shrinks during high-temperature annealing. The unique sharp corners at both ends of the field oxide layer exert a stronger stress-pulling effect on the active area 300, making it more likely to cause severe damage to the active area 300.

[0052] It should be noted that Figure 7 The fact that the upper surface of the isolation structure 200 protrudes from the surface of the substrate 100 is merely an example. In some other embodiments of the present application, the upper surface of the isolation structure 200 may be flush with the surface of the substrate 100 .

[0053] In some embodiments, please refer to Figure 8 Before performing ion implantation, the method for preparing the semiconductor structure may further include: forming a sacrificial oxide layer 400 on the surface of the active area 300 .

[0054] In the embodiment of the present application, before ion implantation, a sacrificial oxide layer 400 is formed on the surface of the active region 300. This sacrificial oxide layer 400 facilitates control of the ion implantation depth. Furthermore, the sacrificial oxide layer 400 can also be used to reduce direct impact of high-energy ions on the active region 300 during implantation, thereby protecting the crystal lattice of the active region 300 from damage. In actual fabrication processes, for example, a thermal oxidation process and / or a deposition process can be used to form the sacrificial oxide layer 400.

[0055] Next, step S102 is performed to perform an ion implantation process to form a well region (not shown) in the active region 300 .

[0056] In the embodiments of the present application, the conductivity type, shape, and number of the well regions are not limited. For example, the well region can be a P-type well region or an N-type well region; the shape of the well region can be any regular or irregular shape, such as a ring or a column; the number of well regions can be one or more, and when there are multiple well regions, the conductivity types of the well regions can be the same or different. Specifically, the appropriate well region type can be formed based on the type of device to be manufactured.

[0057] In an actual manufacturing process, a patterned photoresist layer can first be formed on the active area 300. The patterned photoresist layer exposes the area to be ion implanted. Then, ion implantation is performed on the active area 300 using the patterned photoresist layer as a mask to form a well region. After the ion implantation is completed, the patterned photoresist layer is removed. It will be understood that when forming the sacrificial oxide layer 400, the patterned photoresist layer is formed on the sacrificial oxide layer 400. When the patterned photoresist layer is removed using a wet process, the sacrificial oxide layer 400 may be partially or even substantially completely removed.

[0058] In some embodiments, please refer to Figure 9 Before annealing the active area 300 , the method for preparing the semiconductor structure may further include cleaning the surface of the active area 300 . During the cleaning process, the sacrificial oxide layer 400 is completely removed.

[0059] In the embodiment of the present application, by cleaning the surface of the active area 300, contaminants on the surface of the active area 300 can be removed, and the sacrificial oxide layer 400 can be completely removed to keep the surface of the active area 300 clean and flat, thereby preventing contaminants from entering the active area 300 during the subsequent annealing treatment and avoiding affecting the oxidation of the surface of the active area 300 during the subsequent annealing treatment.

[0060] The cleaning process may be performed using a cleaning process well known to those skilled in the art, and this application does not limit this.

[0061] Finally, please refer to Figure 10 , performing step S103 , performing annealing treatment on the active area 300 in a mixed atmosphere including an oxidizing gas and an inert gas, so that the surface layer of the active area 300 is oxidized into an oxide layer 500 during the annealing treatment.

[0062] In the embodiment of the present application, an annealing treatment is performed by introducing a mixed atmosphere including an oxidizing gas and an inert gas. During the annealing process, the surface layer of the active region 300 is oxidized into an oxide layer 500. On the one hand, the oxide layer 500 is connected to the isolation structure 200, which can generate a reverse force to reduce the tensile stress (such as the tensile stress) generated by the contraction of the isolation structure 200 on the active region 300. Figure 10On the other hand, the oxide layer 500 formed on the surface of the active area 300 can alleviate the tensile stress generated by the isolation structure 200, which causes stress concentration on the surface of the active area 300, thereby preventing lattice damage such as defects from occurring on the surface of the active area 300 and extending into the interior of the active area 300, thereby significantly reducing the lattice damage caused by deformation of the active area under the action of tensile stress, thereby avoiding device leakage and effectively improving product yield.

[0063] Generally, during the annealing process, it is necessary to set the annealing parameters according to the type of device to be prepared, so as to facilitate the control of the depth of the push-in junction during the annealing process, and thus better control the depth and doping concentration of the well region finally formed. In the embodiment of the present application, the surface layer of the active area 300 is oxidized into an oxide layer 500 during the annealing process. This will not affect the annealing itself. It only requires the addition of oxidizing gas, and there is no need to adjust other process parameters of the annealing process. If the oxide layer 500 is formed in advance before the annealing process, so as to utilize the oxide layer 500 to eliminate the stress pulling effect of the isolation structure 200 shrinking under high temperature conditions on the active area 300, it will not only increase the process cost, but also be equivalent to an annealing process for the well region in advance during the process of forming the oxide layer 500. In this way, when the annealing process is performed later, the process parameters of the annealing process need to be adjusted again, which makes it difficult to control the depth of the annealing push-in junction, which in turn affects the performance of the device finally obtained.

[0064] The oxidizing gas in the embodiment of the present application includes a gas containing O. In some specific implementations, the oxidizing gas may include at least one of O2, O3, H2O2 vapor, and H2O vapor.

[0065] When the volume fraction of the oxidizing gas in the mixed atmosphere is too high, the thickness of the surface layer of the active region 300 oxidized increases, which results in a greater loss of the active region 300. Therefore, in some embodiments, the volume fraction of the oxidizing gas in the mixed atmosphere may be less than or equal to 10%.

[0066] In some embodiments, the temperature of the annealing process may be 500°C to 1200°C.

[0067] In some embodiments, the annealing treatment time is less than or equal to 10 minutes. The annealing treatment in the embodiments of the present application can be rapid thermal annealing. Rapid thermal annealing can activate the doping elements in the active area 300 and repair the lattice damage that may be caused to the active area 300 during ion implantation; at the same time, it can avoid the problem that long-term high-temperature annealing causes excessive diffusion of impurities, which is not conducive to the formation of a steep doping concentration gradient. In some more specific embodiments, the annealing treatment time can be less than or equal to 5 minutes. Further, in a specific example, the annealing treatment time is less than or equal to 1 minute.

[0068] It can be understood that in the rapid thermal annealing process, the annealing time is short and the adjustment space of the process parameters is small. Since a mixed atmosphere including an oxidizing gas and an inert gas is introduced into the present application for annealing, it does not affect the original annealing process. Therefore, it is very suitable for use in the rapid thermal annealing process after ion implantation.

[0069] During the annealing process, if the thickness of the oxide layer 500 formed by oxidation of the surface of the active area 300 is too thin, it will not be conducive to forming a stable connection with the edge of the isolation structure 200, which may affect the ability of the oxide layer 500 to eliminate the stress pulling effect of the isolation structure 200 shrinking under high temperature conditions on the active area 300. If the thickness of the oxide layer 500 formed by oxidation of the surface of the active area 300 is too thick, it will cause excessive loss of the active area 300. Therefore, in some embodiments, the thickness of the oxide layer 500 can be 10 angstroms to 100 angstroms. In some more specific embodiments, the thickness of the oxide layer 500 can be 10 angstroms to 20 angstroms. This can effectively eliminate the stress pulling effect of the isolation structure 200 shrinking under high temperature conditions on the active area 300 through the oxide layer 500, while also avoiding excessive loss of the doped surface of the active area 300.

[0070] In some embodiments, after annealing the active region 300 , the method for preparing the semiconductor structure may further include: removing the oxide layer 500 .

[0071] In the embodiment of the present application, the oxide layer 500 is removed to avoid affecting the subsequent device fabrication steps. In the actual fabrication process, the oxide layer 500 can be removed using a dry or wet process. The present application does not exclude the possibility of removing the oxide layer 500 simultaneously in a subsequent step of the device fabrication process, thus eliminating the need for a separate step of removing the oxide layer 500.

[0072] In some embodiments, after annealing the active region 300 , the method for preparing the semiconductor structure may further include: forming a source region and a drain region (not shown) in the active region 300 .

[0073] By forming a source region and a drain region in the active region 300, a field effect transistor can be formed in the active region 300. Since the oxide layer 500 in the embodiment of the present application can effectively eliminate the stress pulling effect of the shrinkage of the isolation structure 200 under high temperature conditions on the active region 300, the lattice damage of the active region 300 is reduced, and thus the problem of leakage or even breakdown between the drain and the source can be avoided, thereby improving the performance and reliability of the device and improving the yield of the product.

[0074] Figure 11 The defect distribution map is obtained by detecting defects in the semiconductor structure manufactured in the related art. Figure 12 The defect distribution map is obtained by detecting defects in the semiconductor structure prepared in this application. Figure 11 and Figure 12 It can be seen from the comparison that in the related art, the substrate is annealed in an inert gas atmosphere, resulting in damage to the active area lattice and defects in the semiconductor structure ( Figure 11 In the present application, the active area is annealed in a mixed atmosphere including an oxidizing gas and an inert gas, which greatly reduces the lattice damage of the active area and the defects in the semiconductor structure ( Figure 12 This indicates that, in this application, by introducing a small amount of oxidizing gas during the annealing process, the exposed surface layer of the active area is rapidly oxidized to form an oxide layer, thereby effectively reducing damage to the active area during the high-temperature annealing process.

[0075] Based on this, an embodiment of the present application further provides a semiconductor structure, which is prepared using the steps in the method for preparing a semiconductor structure provided in any of the aforementioned embodiments.

[0076] It should be noted that the semiconductor structure embodiments and the semiconductor structure preparation method embodiments provided in this application belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict.

[0077] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementation methods. Various modifications and changes may be made to the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments merely express several implementation methods of the present application and do not limit the scope of protection of the patent application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a substrate, wherein the substrate includes an isolation structure and an active area isolated by the isolation structure; the material of the isolation structure includes oxide; performing an ion implantation process to form a well region in the active region; The active region is annealed in a mixed atmosphere including an oxidizing gas and an inert gas, so that a surface layer of the active region is oxidized into an oxide layer during the annealing process.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The volume fraction of the oxidizing gas in the mixed atmosphere is less than or equal to 10%.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The oxidizing gas includes at least one of O2, O3, H2O2 steam, and H2O steam.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The temperature of the annealing treatment is 500°C to 1200°C.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The annealing treatment time is less than or equal to 10 minutes.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the oxide layer is 10 angstroms to 100 angstroms.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: Before performing the ion implantation, the method further includes: forming a sacrificial oxide layer on the surface of the active area; Before performing the annealing process on the active area, the method further includes performing a cleaning process on the surface of the active area, and the sacrificial oxide layer is removed during the cleaning process.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: After performing the annealing process on the active area, the method further includes: The oxide layer is removed.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: After performing the annealing process on the active area, the method further includes: A source region and a drain region are formed in the active region.

10. A semiconductor structure, characterized in that The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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