Formation method of semiconductor structure

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a semiconductor substrate; forming a groove on the semiconductor substrate; forming a first metal barrier layer, wherein the first metal barrier layer covers the side wall and the bottom surface of the groove in a shape-preserving manner; forming a first anti-reflection layer which covers the first metal barrier layer and fills the groove; forming a patterned mask layer on the first anti-reflection layer, and etching the first anti-reflection layer and the first metal barrier layer by taking the patterned mask layer as a mask; and etching the semiconductor substrate by taking the patterned mask layer as a mask and the first metal barrier layer as a protective layer so as to form a hole at the bottom of the groove. By adopting the technical scheme, the problems that the etching depth of the groove is difficult to accurately control, organic residues are left in the hole and plasma of the dielectric layer is damaged can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor process flow, the Damascene process based on copper metal planarization (Cu-CMP) is the only mature and successfully used copper patterning process in IC manufacturing. Commonly used damascene methods for copper interconnects include trench / via all-in-one (AIO) etching (i.e., a one-step process) and via-first etching.

[0003] However, because the one-step method etches both the trench and the hole simultaneously, over-etching can easily make it difficult to precisely control the trench etch depth. Using the hole-first method, organic residues may remain in the hole after the trench is etched. In both processes, the dielectric layer is repeatedly exposed to the plasma environment, potentially causing plasma damage to the dielectric layer.

[0004] Therefore, how to provide a technical solution to address the problems of difficult to accurately control trench etching depth, residual organic residues in holes, and plasma damage to the dielectric layer has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a method for forming a semiconductor structure, which can accurately control the trench etching depth and address the problems of organic residues in the holes and plasma damage to the dielectric layer.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a trench on the semiconductor substrate; forming a first metal barrier layer, wherein the first metal barrier layer conformally covers the sidewalls and bottom surface of the trench; forming a first anti-reflection layer, wherein the first anti-reflection layer covers the first metal barrier layer and fills the trench; forming a patterned mask layer on the first anti-reflection layer, and etching the first anti-reflection layer and the first metal barrier layer using the patterned mask layer as a mask; etching the semiconductor substrate using the patterned mask layer as a mask and the first metal barrier layer as a protective layer to form a hole at the bottom of the trench.

[0007] Optionally, the semiconductor substrate has a metal interconnection layer and a first dielectric layer; wherein the first dielectric layer covers the metal interconnection layer, the metal interconnection layer includes a metal interconnection structure and an interlayer dielectric layer, and the upper surfaces of the interlayer dielectric layer and the metal interconnection structure are flush.

[0008] Optionally, the interlayer dielectric layer includes: a stack of silicon oxide and silicon nitride, silicon oxide, silicon nitride; and / or the material of the metal interconnect structure includes one or more combinations of the following: copper, aluminum, cobalt, titanium, silver, gold.

[0009] Optionally, the step of forming the first dielectric layer includes: forming a nitrogen-doped silicon carbide layer on the metal interconnect layer; forming a low dielectric constant layer on the nitrogen-doped silicon carbide layer; and forming an oxide dielectric layer on the low dielectric constant layer.

[0010] Optionally, the step of forming the groove on the semiconductor substrate includes: forming a second anti-reflection layer, the second anti-reflection layer covering the first dielectric layer; forming a patterned mask layer on the second anti-reflection layer, and using the patterned mask layer as a mask, sequentially etching the second anti-reflection layer, the oxide dielectric layer of the first dielectric layer, and a portion of the low dielectric constant layer of the first dielectric layer to form the groove; wherein the plane where the bottom of the groove is located is located between the upper surface and the lower surface of the low dielectric constant layer.

[0011] Optionally, the step of forming a hole at the bottom of the groove includes: using the patterned mask layer as a mask, etching the first anti-reflection layer, the first metal barrier layer, the low dielectric constant layer, and the nitrogen-doped silicon carbide layer in sequence to obtain the hole.

[0012] Optionally, it also includes: forming a second metal barrier layer, the second metal barrier layer conformally covering the sidewalls and bottom surface of the hole; removing the second metal barrier layer covering the bottom surface of the hole, exposing the metal interconnection layer in the hole; forming a seed layer, the seed layer conformally covering the second metal barrier layer and the bottom surface of the hole; forming a first metal layer based on the seed layer, the first metal layer filling the hole and the trench.

[0013] Optionally, a chemical mechanical planarization process is used to grind the first metal layer and the first dielectric layer so that the surface of the first metal layer is flush with the surface of the low dielectric constant layer.

[0014] Optionally, the material of the low dielectric constant layer includes: silicon carbon hydroxide; and / or the material of the oxide dielectric layer includes: tetraethyl orthosilicate and silicon oxide.

[0015] Optionally, the material of the second anti-reflection layer includes one or more combinations of the following: silicon nitride, silicon oxide, and silicon oxynitride.

[0016] Optionally, the first metal barrier layer and the second metal barrier layer satisfy one or more of the following: the thickness range of the first metal barrier layer and the second metal barrier layer is taken from [50 angstroms, 100 angstroms]; the material of the first metal barrier layer and the second metal barrier layer is the same, and is tantalum nitride; the second metal barrier layer covers the first metal barrier layer.

[0017] Optionally, the process parameters for etching the first metal barrier layer are selected from one or more of the following: the low-frequency power ranges from 450W to 500W; the high-frequency power ranges from 40W to 45W; the etching gas includes: chlorine and argon, and the molar ratio of chlorine and argon in the etching gas ranges from 1:4 to 1:2; the gas flow rate of chlorine in the etching gas is selected from [25sccm, 50sccm], and the gas flow rate of argon is selected from [50sccm, 200sccm].

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0019] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a groove is formed on a semiconductor substrate; and a first metal barrier layer is formed to conformally cover the sidewalls and bottom surface of the groove. The first metal barrier layer can protect the morphology of the groove, so that the groove etching depth does not change when etching holes, and can also protect the dielectric layer and reduce the probability of plasma damage. With the first metal barrier layer as a protective layer, holes are etched in the semiconductor substrate, that is, at the bottom of the groove. Since the groove is etched first and then the hole, filling the hole with organic material is avoided. Therefore, the method has the opportunity to accurately control the trench etching depth and deal with the problems of organic residues in the hole and plasma damage to the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the invention of this specification, the following briefly introduces the drawings required for use in the embodiments of the invention of this specification or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figures 1 to 3 is a schematic diagram of some steps of a method for forming a semiconductor structure;

[0022] Figures 4 to 6 is a schematic diagram of some steps of another method for forming a semiconductor structure;

[0023] Figure 7 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0024] Figures 8 to 15 It is a schematic diagram of the device cross-sectional structure disclosed in each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0025] Description of reference numerals:

[0026] Figures 1 to 6 : initial trench pattern 101, initial hole pattern 102, trench 103, hole 104, metal interconnection layer 110, dielectric layer 120, mask layer 130, photoresist 131, first anti-reflection layer 141, second anti-reflection layer 142, metal barrier layer 150, first metal layer 160;

[0027] Figures 8 to 15 : initial groove pattern 201, initial hole pattern 202, groove 203, hole 204, metal interconnection layer 210, metal interconnection structure 211, interlayer dielectric layer 212, first dielectric layer 220, nitrogen-doped silicon carbide layer 221, low dielectric constant layer 222, oxide dielectric layer 223, mask layer 230, photoresist 231, first anti-reflective layer 241, second anti-reflective layer 242, metal barrier layer 250, first metal barrier layer 251, second metal barrier layer 252, first metal layer 260. DETAILED DESCRIPTION

[0028] The technical solutions of the present invention are described in detail below in conjunction with specific embodiments and the accompanying drawings. The embodiments described herein are specific embodiments of the present invention and are used to illustrate the concept of the present invention. These descriptions are all illustrative and exemplary and should not be construed as limiting the embodiments of the present invention and the scope of protection of the present invention. In addition to the embodiments described herein, those skilled in the art can also adopt obvious other technical solutions based on the contents disclosed in the claims of this application and the specification thereof, including technical solutions that adopt any obvious replacements and modifications to the embodiments described herein.

[0029] It should be noted that the drawings in this embodiment are schematic diagrams to assist in illustrating the concept of the present invention and schematically illustrate the shapes of the various components and their interrelationships. It should be understood that in order to clearly illustrate the structure of the various components of the present invention, the drawings are not drawn to the same scale, and the same reference numerals are used to represent the same parts in the drawings.

[0030] As mentioned in the background, the Damascene process based on copper metal planarization (Cu-CMP) is the only mature and successfully used copper patterning process in semiconductor manufacturing. Commonly used damascene methods for copper interconnects include the Trench / Via All-In-One (Trench / ViaAIO) etching method (i.e., a one-step process) and the Via First (Via First) etching method.

[0031] However, because the one-step method etches both the trench and the hole simultaneously, over-etching can easily make it difficult to precisely control the trench etch depth. Using the hole-first method, organic residues may remain in the hole after the trench is etched. In both processes, the dielectric layer is repeatedly exposed to the plasma environment, potentially causing plasma damage to the dielectric layer.

[0032] Specifically, with reference to Figures 1 to 6 Further description, Figures 1 to 3 The present invention is a schematic diagram of some steps of a method for forming a semiconductor structure.

[0033] Figures 1 to 3 The diagram shows some steps of a method for forming a semiconductor structure, which is a cross-sectional diagram of some steps of Trench / ViaAIO (one-step method).

[0034] exist Figure 1 In the process, a mask layer 130 having an initial groove pattern 101 is formed on a semiconductor substrate, and then a dielectric layer 120 in the semiconductor substrate is etched using the mask layer 130 as a mask to obtain a dielectric layer groove, and the dielectric layer groove is filled with an anti-reflective material to form a first anti-reflective layer 141, and a patterned photoresist 131 having an initial hole pattern 102 is formed on the first anti-reflective layer 141.

[0035] The semiconductor substrate may include a dielectric layer 120 .

[0036] Reference Figure 2 Using the photoresist 131 as a mask, the first anti-reflective layer 141 and the dielectric layer 120 are sequentially etched to form an initial hole (not shown). The photoresist 131 and the first anti-reflective layer 141 are then removed, and etching is continued downward based on the initial hole to form the trench 103 and the hole 104. To ensure that the hole exposes the metal structure of the metal interconnect layer 110, overetching is generally required. Therefore, the depth of the trench 103 cannot be precisely controlled, that is, the distance between the bottom of the trench 103 and the upper surface of the metal interconnect layer 110 or the distance between the bottom of the trench 103 and the upper surface of the dielectric layer 120 cannot be precisely controlled.

[0037] Reference Figure 3 , the trench 103 and the hole 104 are filled, for example, the metal barrier layer 150 and the first metal layer 160 may be filled in sequence.

[0038] However, since the depth of the trench 103 cannot be precisely controlled, the thickness and uniformity of the first metal layer 160 are poor.

[0039] Combined with reference Figures 4 to 6 , Figures 4 to 6 It is a schematic diagram of some steps of another method for forming a semiconductor structure, and is a cross-sectional schematic diagram of some steps of a Via First method.

[0040] exist Figure 4 In the embodiment, a photoresist 131 having an initial hole pattern 102 is formed on a semiconductor substrate.

[0041] Reference Figure 5 , using the photoresist 131 as a mask, a hole 104 is etched, and then a first anti-reflection layer 141 is filled in the hole 104 and on the surface of the semiconductor substrate, a second anti-reflection layer 142 is formed above the first anti-reflection layer 141, and a photoresist 131 with an initial groove pattern 101 is formed above the second anti-reflection layer 142.

[0042] Reference Figure 6 , using the photoresist 131 as a mask, etching the groove 103 and removing the first anti-reflection layer 141 .

[0043] However, since the hole 104 often has a large aspect ratio, the material of the first anti-reflection layer 141 may still remain in the hole 104 .

[0044] After research, it was found that, in addition to the above-mentioned disadvantages, the above two methods of forming the groove 103 and the hole 104 both expose the dielectric layer 120 repeatedly to a plasma environment, so that the dielectric layer 120 may be damaged by the plasma.

[0045] Therefore, how to provide a technical solution to address the problems of difficult to accurately control trench etching depth, residual organic residues in holes, and plasma damage to the dielectric layer has become a technical problem that needs to be solved urgently.

[0046] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a groove is formed on a semiconductor substrate; and a first metal barrier layer is formed to conformally cover the sidewalls and bottom surface of the groove. The first metal barrier layer can protect the morphology of the groove, so that the groove etching depth does not change when etching holes, and can also protect the dielectric layer and reduce the probability of plasma damage. With the first metal barrier layer as a protective layer, holes are etched in the semiconductor substrate, that is, at the bottom of the groove. Since the groove is etched first and then the hole, filling the hole with organic material is avoided. Therefore, the method has the opportunity to deal with the problems of difficult to accurately control the trench etching depth, residual organic residues in the hole, and plasma damage to the dielectric layer.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is described clearly and completely below with reference to the accompanying drawings.

[0048] See also Figure 7 , Figure 7 FIG. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method may include steps S11 to S16, each of which is described below.

[0049] In step S11 , a semiconductor substrate is provided.

[0050] In step S12, a trench is formed on the semiconductor substrate.

[0051] In step S13 , a first metal barrier layer is formed, wherein the first metal barrier layer conformally covers the sidewalls and bottom surface of the trench.

[0052] In step S14 , a first anti-reflection layer is formed, where the first anti-reflection layer covers the first metal barrier layer and fills the trench.

[0053] In step S15 , a patterned mask layer is formed on the first anti-reflection layer, and the first anti-reflection layer and the first metal barrier layer are etched using the patterned mask layer as a mask.

[0054] In step S16 , the semiconductor substrate is etched using the patterned mask layer as a mask and the first metal barrier layer as a protection layer to form a hole at the bottom of the trench.

[0055] The following combination Figures 8 to 15 , the above method is explained.

[0056] Figures 8 to 15 It is a schematic diagram of the device cross-sectional structure disclosed in each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0057] See also Figure 8 , providing a semiconductor substrate having a metal interconnection layer 210 and a first dielectric layer 220.

[0058] In some embodiments, the semiconductor substrate may be a silicon substrate made of single-crystal silicon. In other embodiments, the semiconductor substrate may be made of one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of semiconductor substrates. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the semiconductor substrate may be formed on the surface of the semiconductor substrate to improve pattern transfer quality.

[0059] In this embodiment, the semiconductor substrate has formed a source-gate-drain semiconductor structure (not shown), and the metal interconnection layer 210 and the first dielectric layer 220 are located above the semiconductor structure. The first dielectric layer 220 provides physical protection for the semiconductor structure, and the metal interconnection layer 210 provides power for the semiconductor structure.

[0060] The first dielectric layer 220 covers the metal interconnection layer 210 , and the metal interconnection layer 210 may include a metal interconnection structure 211 and an interlayer dielectric layer 212 .

[0061] The interlayer dielectric layer 212 provides physical support and protection for the metal interconnect structure 211 .

[0062] In a specific embodiment, the upper surfaces of the interlayer dielectric layer 212 and the metal interconnect structure 211 may be flush.

[0063] There are at least two metal interconnect structures 211 for connecting devices below the metal interconnect structures 211. The semiconductor substrate may further include a semiconductor device layer located below the metal interconnect structures 211.

[0064] The interlayer dielectric layer 212 may be made of a stack of silicon oxide and silicon nitride, silicon oxide, or silicon nitride.

[0065] In this embodiment, the interlayer dielectric layer 212 is made of silicon oxide.

[0066] The material of the metal interconnect structure 211 includes one or more of the following: copper, aluminum, cobalt, titanium, silver, and gold. In this embodiment, the material of the metal interconnect structure 211 is copper.

[0067] In some embodiments, a metal barrier layer (not shown) is formed between the interlayer dielectric layer 212 and the metal interconnect structure 211 to prevent the metal interconnect structure 211 from diffusing.

[0068] The first dielectric layer 220 may be a stack of multiple dielectric layers.

[0069] The first dielectric layer 220 adopts a multi-layer stacked structure design, and achieves multiple performance optimizations through the synergistic combination of different materials: this structure can accurately control the electric field distribution and signal transmission characteristics, such as enhancing the local electric field control capability for high-k dielectric layers, and effectively reducing the overall parasitic capacitance and signal delay for low-k material layers; the stress compensation effect between the layers of material significantly improves the mechanical stability of the film and prevents cracking or peeling. At the same time, the embedded etch stop layer (such as SiN) and metal barrier layer (such as TaN) provide precise etching nodes and charge diffusion barriers for complex processes, ultimately synergistically achieving better thermal stability, stronger process compatibility and more flexible functional design freedom at the nanoscale.

[0070] In this embodiment, the first dielectric layer 220 includes a nitrogen-doped silicon carbide layer 221 , a low dielectric constant (Low-K) layer 222 , and an oxide dielectric layer 223 .

[0071] The steps of forming the first dielectric layer 220 include:

[0072] forming a nitrogen-doped silicon carbide layer 221 on the metal interconnection layer 210;

[0073] forming a low dielectric constant layer 222 on the nitrogen-doped silicon carbide layer 221;

[0074] An oxide dielectric layer 223 is formed on the low dielectric constant layer 222 .

[0075] The nitrogen-doped silicon carbide layer 221 covers the metal interconnection layer 210 , the low dielectric constant layer 222 covers the nitrogen-doped silicon carbide layer 221 , and the oxide dielectric layer 223 covers the low dielectric constant layer 222 .

[0076] In some embodiments, the thickness of the low-k dielectric layer 222 is greater than the thickness of the nitrogen-doped silicon carbide layer 221 and the oxide dielectric layer 223. The thickness of the nitrogen-doped silicon carbide layer 221, the low-k dielectric layer 222, and the oxide dielectric layer 223 is the distance between the upper and lower surfaces of each dielectric layer, with the area closer to the metal interconnect layer 210 being the lower surface and the area farther from the metal interconnect layer 210 being the upper surface.

[0077] The nitrogen-doped silicon carbide layer 221 is an etch stop layer. In subsequent etching processes (such as hole or trench etching), the high selectivity of nitrogen-doped silicon carbide (relative to low-k dielectric constant materials) is conducive to precisely controlling the etching depth, avoiding excessive etching and damaging the underlying metal interconnection, and preventing metal (such as copper) atoms from diffusing upward to the low-k dielectric constant layer 222, avoiding electromigration and contamination, and can enhance the stability of the structure and alleviate the mechanical weaknesses (such as brittleness) of the low-k dielectric constant material.

[0078] The low dielectric constant layer 222 uses a low dielectric constant material, such as SiCOH, whose dielectric constant (k value) is significantly lower than that of traditional silicon oxide, which can reduce capacitive coupling between layers, reduce parasitic capacitance, increase device speed and reduce power consumption, thereby optimizing signal transmission speed.

[0079] In some embodiments, the k value may be 3.9, and thus the low-k material may have a dielectric constant (k) less than or equal to 3.9, whereas the high-k material may have a dielectric constant (k) greater than 3.9.

[0080] The oxide dielectric layer 223 can serve as a hard mask / protective layer. During etching or chemical mechanical polishing (CMP) processes, the oxide dielectric layer 223 can be made of silicon dioxide and thus can serve as a hard mask to protect the underlying low-k dielectric layer 222 from mechanical or chemical damage. Furthermore, the oxide dielectric layer 223 provides a flat surface for subsequent photolithography and metal deposition, ensuring pattern transfer accuracy. The oxide dielectric layer 223 can also withstand high-temperature processes (such as annealing) and chemical treatments, ensuring the reliability of the overall structure.

[0081] The material of the low dielectric constant layer 222 includes silicon carbon hydroxide.

[0082] In some embodiments, the material of the oxide dielectric layer 223 is selected from tetraethyl orthosilicate, silicon nitride, silicon oxide, titanium nitride, and tantalum nitride, and the oxide dielectric layer 223 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0083] In this embodiment, the material of the oxide dielectric layer 223 is silicon oxide.

[0084] In this embodiment, the nitrogen-doped silicon carbide layer 221 , the low-k dielectric layer 222 , and the oxide dielectric layer 223 are all formed by plasma-enhanced chemical vapor deposition.

[0085] In some embodiments, the oxide dielectric layer 223 may also be oxidized using a thermal oxidation method, which is not intended to limit the present application.

[0086] In step S12, a trench is formed on the semiconductor substrate.

[0087] The step of forming the trench on the semiconductor substrate comprises:

[0088] forming a second anti-reflection layer 242 , wherein the second anti-reflection layer 242 covers the first dielectric layer 220 ;

[0089] A patterned mask layer is formed on the second anti-reflection layer 242 . Using the patterned mask layer as a mask, the second anti-reflection layer 242 , the oxide dielectric layer 223 of the first dielectric layer 220 , and a portion of the low dielectric constant layer 222 of the first dielectric layer 220 are sequentially etched to form the trench 203 .

[0090] Specifically, the material of the second anti-reflection layer 242 includes one or more of the following combinations: silicon nitride, silicon oxide, and silicon oxynitride.

[0091] The second anti-reflective layer 242, also known as a dielectric anti-reflective coating (DARC), is a dielectric film deposited above the hard mask layer or below the photoresist. It is primarily used to reduce reflection interference during the photolithography process, improving pattern resolution and critical dimension (CD) control accuracy. The term "above" refers to a direction away from the metal interconnect layer 210, and the term "below" refers to a direction toward the metal interconnect layer 210.

[0092] In this embodiment, the second anti-reflection layer 242 covers the first dielectric layer 220 .

[0093] The second anti-reflection layer 242 covers the oxide dielectric layer 223 .

[0094] Combined with reference Figure 8 and Figure 9 Furthermore, a photoresist 231 is coated on the second anti-reflective layer 242, and a mask with a groove pattern is used to photoetch a mask layer with a groove pattern to obtain an initial groove pattern 201. Using the mask layer with the groove pattern as a mask, the second anti-reflective layer 242, the oxide dielectric layer 223 of the first dielectric layer 220, and a portion of the low-k dielectric constant layer 222 of the first dielectric layer 220 are sequentially etched.

[0095] In some embodiments, etching a portion of the low dielectric constant layer 222 of the first dielectric layer 220 means etching the low dielectric constant layer 222 to a depth that accounts for half of the thickness of the low dielectric constant layer 222 .

[0096] In this embodiment, after etching the groove 203, the photoresist 231 and the second anti-reflection layer 242 are removed to obtain Figure 9 A cross-sectional view of a semiconductor structure is shown.

[0097] The bottom of the trench 203 is located between the upper and lower surfaces of the low dielectric constant layer 222. The lower surface of the low dielectric constant layer 222 is close to the metal interconnection layer 210, and the upper surface is away from the metal interconnection layer 210.

[0098] In other words, the trench 203 extends into the low-k dielectric layer 222 but does not penetrate the low-k dielectric layer 222 .

[0099] See also Figure 10 , a first metal barrier layer 251 is formed on the surface of the trench 203 , that is, the first metal barrier layer 251 conformally covers the sidewalls and bottom surface of the trench 203 .

[0100] In addition, the first metal barrier layer 251 also covers the surface of the first dielectric layer 220 .

[0101] The first metal barrier layer 251 also covers the upper surface of the oxide dielectric layer 223 of the first dielectric layer 220. The oxide dielectric layer 223 is perpendicular to the surface of the metal interconnection layer 210, and the upper surface is away from the metal interconnection layer 210.

[0102] The material of the first metal barrier layer 251 includes one or more of the following combinations: tantalum nitride, tantalum, titanium nitride, cobalt or ruthenium-based materials. In this embodiment, the material of the first metal barrier layer 251 is tantalum nitride.

[0103] The first metal barrier layer 251 can protect a portion of the bottom surface and sidewalls of the trench during subsequent hole formation, thereby improving the surface properties and morphology accuracy of the trench 203. Furthermore, the first metal barrier layer 251 conformally covers the trench and remains as part of the semiconductor structure.

[0104] It should be noted that, since core components such as source / drain doped regions and gate structures have already been formed in the semiconductor structure, the first metal barrier layer 251 can further improve the device performance of the semiconductor structure.

[0105] The first metal barrier layer 251 mainly functions to prevent metal diffusion, such as copper (Cu) atoms from diffusing into the surrounding dielectric material. That is, the first metal barrier layer 251 can prevent metal from diffusing into the first dielectric layer 220 .

[0106] The first metal barrier layer 251 protects the first dielectric layer 220 and can also reduce the probability of plasma damage to the first dielectric layer 220 in subsequent processes.

[0107] See also Figure 11 and Figure 12 , Figure 11 and Figure 12 Part of the process of forming the hole in steps S14 to S16 is shown.

[0108] exist Figure 11 In the embodiment, a first anti-reflection layer 241 may be formed on the first metal barrier layer 251 , where the first anti-reflection layer 241 covers the first metal barrier layer 251 and fills the trench 203 .

[0109] The first anti-reflective layer 241 may be a bottom anti-reflective coating (BARC). The first anti-reflective layer 241 is a key auxiliary layer in semiconductor photolithography. Coated between the substrate (such as a wafer surface or dielectric layer) and the photoresist (PR), its primary function is to reduce interference from reflected light during photoresist exposure, thereby improving image resolution and linewidth control accuracy. The material of the BARC should be selected based on the photolithography wavelength and process.

[0110] The material of the first anti-reflection layer 241 includes one or more of the following combinations: aromatic compounds (such as phenolic resin, polyimide), light-absorbing dyes (such as anthraquinones), crosslinking agents (such as melamine resins), carboxylates, fluorinated polymers, and photoacid generators.

[0111] In addition, the first anti-reflection layer 241 is used to fill the tiny concave and convex portions on the surface of the semiconductor substrate, thereby providing a flat coating base for the photoresist and reducing pattern distortion.

[0112] In some embodiments, the first anti-reflection layer 241 may serve as an etch stop layer or a buffer layer to protect the substrate from over-etching.

[0113] A patterned mask layer is formed on the first anti-reflection layer 241 , and the first anti-reflection layer 241 and the first metal barrier layer 251 are etched using the patterned mask layer as a mask.

[0114] Specifically, a photoresist 231 is coated on the first anti-reflection layer 241, and a mask with a hole pattern is used to photoetch a mask layer with a hole pattern to obtain an initial hole pattern 202. Using the mask layer with the hole pattern as a mask, the first anti-reflection layer 241 and the first metal barrier layer 251 are sequentially etched.

[0115] In some embodiments, process parameters for etching the first metal barrier layer 251 are selected from one or more of the following:

[0116] The low-frequency power range is 450W to 500W;

[0117] The high-frequency power range is 40W to 45W;

[0118] The etching gas includes: chlorine gas and argon gas, and the molar ratio of chlorine gas to argon gas in the etching gas ranges from 1:4 to 1:2;

[0119] The gas flow rate of the chlorine gas in the etching gas is selected from [25 sccm, 50 sccm], and the gas flow rate of the argon gas is selected from [50 sccm, 200 sccm].

[0120] In some embodiments, the etching gas is mixed before being injected into the reaction chamber, that is, the etching gas is injected into a mixing area and mixed thoroughly according to a certain proportion.

[0121] Reference Figure 12 , with the patterned mask layer 231 (refer to Figure 11 ) as a mask, and using the first metal barrier layer 251 as a protective layer, the semiconductor substrate is etched to form a hole at the bottom of the trench.

[0122] Specifically, the step of forming the hole 204 at the bottom of the groove 203 includes: using the patterned mask layer as a mask, etching the first anti-reflection layer 241, the first metal barrier layer 251, the low dielectric constant layer 222, and the nitrogen-doped silicon carbide layer 221 in sequence to obtain the hole 204.

[0123] The hole 204 is located above the metal interconnection structure 211 . In other words, the hole 204 is formed to expose the metal interconnection structure 211 .

[0124] When forming the hole, the first metal barrier layer 251 is used to protect the remaining bottom surface and sidewalls of the trench, thereby improving the surface performance and morphological accuracy of the trench. Furthermore, the first metal barrier layer 251 conformally covers the trench and is retained as part of the semiconductor structure. The first anti-reflective layer 241 protects the first metal barrier layer 251 during etching, improving the surface performance and morphological accuracy of the first metal barrier layer 251. This approach achieves "double protection" for the semiconductor structure during the formation of the trench and hole. In particular, since core components such as source and drain doping regions and gate structures are already formed in the semiconductor structure, this double protection can further improve the device performance of the semiconductor structure.

[0125] It should be noted that in the present application, the groove 203 is first etched and then the hole 204 is etched, thereby avoiding filling the hole with an anti-reflective coating, effectively preventing the hole 204 from having organic residues, and significantly improving the performance of the semiconductor device.

[0126] After etching the hole 204, the photoresist 231 and the first anti-reflection layer 241 can be removed to obtain Figure 12 A cross-sectional view of a semiconductor structure is shown.

[0127] See also Figure 13 After the hole 204 is etched, a second metal barrier layer 252 is formed, and the second metal barrier layer 252 conformally covers the sidewalls and bottom surface of the hole 204 .

[0128] The material of the second metal barrier layer 252 includes one or more of the following combinations: tantalum nitride, tantalum, titanium nitride, cobalt or ruthenium-based materials. In this embodiment, the material of the first metal barrier layer 251 is tantalum nitride.

[0129] It should be noted that, since core components such as source / drain doped regions and gate structures have already been formed in the semiconductor structure, the second metal barrier layer 252 can further improve the device performance of the semiconductor structure.

[0130] The second metal barrier layer 252 is mainly used to prevent metal diffusion, such as copper (Cu) atoms from diffusing into the surrounding dielectric material. That is, the second metal barrier layer 252 can prevent metal from diffusing into the first dielectric layer 220 .

[0131] The second metal barrier layer 252 also covers the first metal barrier layer 251 .

[0132] The first metal barrier layer 251 and the second metal barrier layer 252 meet one or more of the following requirements:

[0133] The thickness of the first metal barrier layer 251 and the second metal barrier layer 252 ranges from [50 angstroms, 100 angstroms];

[0134] The first metal barrier layer 251 and the second metal barrier layer 252 are made of the same material, tantalum nitride;

[0135] The second metal barrier layer 252 covers the first metal barrier layer 251 .

[0136] When the first metal barrier layer 251 and the second metal barrier layer 252 are made of the same material, a metal barrier layer 250 is formed. The thickness of the metal barrier layer 250 is in the range of [100 angstroms, 200 angstroms].

[0137] The second metal barrier layer 252 is mainly used to protect the sidewalls of the hole 204 to preserve the sidewall morphology and facilitate the formation of vertical sidewalls. The sidewalls of the hole 204 are the first dielectric layer 220, preventing metal from diffusing into the first dielectric layer 220.

[0138] It should be noted that the second metal barrier layer 252 covering the bottom surface of the hole 204 needs to be removed, and the metal interconnection layer 210 is exposed in the hole 204, so that the metal interconnection structure 211 of the metal interconnection layer 210 can form an electrical connection with the first metal layer formed subsequently.

[0139] Furthermore, a seed layer (not shown in the figure) is formed, and the seed layer conformally covers the second metal barrier layer 252 and the bottom surface of the hole 204 .

[0140] The material of the seed layer includes one or more of the following: copper, ruthenium, cobalt, nickel, titanium, molybdenum, and alloy seed layer. In this embodiment, the material of the seed layer is copper.

[0141] Specifically, the seed layer (Copper Seed Layer) is a key thin film layer in the semiconductor copper interconnection process, which is used to provide a conductive base for subsequent copper electroplating (Electroplating) to ensure that copper uniformly fills high aspect ratio structures (such as holes and trenches). Copper electroplating requires a conductive surface to drive the electrochemical reaction. The first dielectric layer 220 (such as SiO2) and the metal barrier layer (such as TaN) are both insulators and cannot be directly electroplated. Therefore, the seed layer is used as a conductive layer to evenly distribute the current and ensure that copper ions are reduced and deposited in the electrolyte. The seed layer can provide uniform nucleation points to guide copper to grow continuously along the side walls and bottom of the hole 204 and the trench 203 to achieve defect-free filling. The seed layer needs to be tightly adhered to the metal barrier layer (TaN) to prevent copper from peeling off or diffusing in subsequent processes.

[0142] In this embodiment, the seed layer is formed by physical vapor deposition (PVD). In a vacuum chamber, high-energy ions bombard a copper target, sputtering copper atoms. The copper atoms are deposited on the wafer surface, covering the sidewalls and bottom of the hole / trench.

[0143] Furthermore, a first metal layer 260 is formed based on the seed layer, and the first metal layer 260 fills the hole 204 and the trench 203 .

[0144] The material of the first metal layer 260 includes one or more of the following: copper, ruthenium, cobalt, nickel, titanium, molybdenum, and alloy seed layer. In this embodiment, the material of the first metal layer 260 is copper.

[0145] Specifically, see Figure 14 , forming the first metal layer 260. The first metal layer 260 also covers the metal barrier layer and the bottom of the hole 204.

[0146] In some embodiments, the first metal layer 260 may be formed by copper electroplating.

[0147] Copper electroplating is a key step in semiconductor manufacturing, used to deposit high-purity, low-resistance copper films on seed layers to achieve highly conductive interconnects.

[0148] For further information, see Figure 15 The first metal layer 260 and the first dielectric layer 220 are polished by a chemical mechanical planarization process so that the surface of the first metal layer 260 is flush with the surface of the low dielectric constant layer 222 .

[0149] Specifically, chemical mechanical planarization (CMP) is performed to achieve flushness between the surfaces of the first metal layer 260 (eg, copper interconnect) and the first dielectric layer 220 (the low dielectric constant layer) to ensure accuracy of subsequent photolithography and / or deposition processes.

[0150] In a specific embodiment, the polishing object is a portion of the first metal layer 260 , a portion of the first metal barrier layer, and a portion of the first dielectric layer.

[0151] Part of the first dielectric layer may include the oxide dielectric layer 223 and part of the low dielectric constant layer to achieve flushness between the surfaces of the first metal layer 260 and the first dielectric layer 220 .

[0152] In a specific embodiment, the height difference between the first metal layer 260 and the first dielectric layer 220 needs to be controlled within ±5 nm.

[0153] It can be understood that the above describes multiple embodiment schemes of the method for forming a semiconductor structure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open to the public by the present invention.

[0154] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.

[0155] The term "plurality" used in the embodiments of the present application refers to two or more.

[0156] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0157] It should be noted that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0158] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a semiconductor substrate; forming a trench on the semiconductor substrate; forming a first metal barrier layer, wherein the first metal barrier layer conformally covers the sidewalls and bottom surface of the trench; forming a first anti-reflection layer, wherein the first anti-reflection layer covers the first metal barrier layer and fills the trench; forming a patterned mask layer on the first anti-reflection layer, and etching the first anti-reflection layer and the first metal barrier layer using the patterned mask layer as a mask; The semiconductor substrate is etched using the patterned mask layer as a mask and the first metal barrier layer as a protection layer to form a hole at the bottom of the trench.

2. The method according to claim 1, characterized in that The semiconductor substrate has a metal interconnection layer and a first dielectric layer; The first dielectric layer covers the metal interconnection layer, the metal interconnection layer includes a metal interconnection structure and an interlayer dielectric layer, and the upper surfaces of the interlayer dielectric layer and the metal interconnection structure are flush.

3. The method according to claim 2, characterized in that The interlayer dielectric layer includes: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride; and / or, The material of the metal interconnect structure includes one or more of the following combinations: copper, aluminum, cobalt, titanium, silver, and gold.

4. The method according to claim 2, characterized in that The step of forming the first dielectric layer comprises: forming a nitrogen-doped silicon carbide layer on the metal interconnection layer; forming a low dielectric constant layer on the nitrogen-doped silicon carbide layer; An oxide dielectric layer is formed on the low dielectric constant layer.

5. The method according to claim 4, characterized in that The step of forming the trench on the semiconductor substrate comprises: forming a second anti-reflection layer, wherein the second anti-reflection layer covers the first dielectric layer; forming a patterned mask layer on the second anti-reflection layer, and using the patterned mask layer as a mask, sequentially etching the second anti-reflection layer, the oxide dielectric layer of the first dielectric layer, and a portion of the low dielectric constant layer of the first dielectric layer to form the trench; The bottom of the groove is located on a plane between the upper surface and the lower surface of the low dielectric constant layer.

6. The method according to claim 4, characterized in that The step of forming a hole at the bottom of the trench includes: using the patterned mask layer as a mask, etching the first anti-reflection layer, the first metal barrier layer, the low dielectric constant layer, and the nitrogen-doped silicon carbide layer in sequence to obtain the hole.

7. The method according to claim 4, characterized in that Also includes: forming a second metal barrier layer, wherein the second metal barrier layer conformally covers the sidewalls and bottom surface of the hole; removing the second metal barrier layer covering the bottom surface of the hole, exposing the metal interconnection layer in the hole; forming a seed layer, wherein the seed layer conformally covers the second metal barrier layer and the bottom surface of the hole; A first metal layer is formed based on the seed layer, and the first metal layer fills the hole and the trench.

8. The method according to claim 7, characterized in that The first metal layer and the first dielectric layer are polished by using a chemical mechanical planarization process, so that the surface of the first metal layer is flush with the surface of the low dielectric constant layer.

9. The method according to claim 4, characterized in that The material of the low dielectric constant layer includes: silicon carbon hydroxide; and / or, The material of the oxide dielectric layer includes: tetraethyl orthosilicate and silicon oxide.

10. The method according to claim 5, characterized in that The material of the second anti-reflection layer includes one or more of the following combinations: silicon nitride, silicon oxide, and silicon oxynitride.

11. The method according to claim 7, characterized in that The first metal barrier layer and the second metal barrier layer satisfy one or more of the following: The thickness of the first metal barrier layer and the second metal barrier layer is in the range of [50 angstroms, 100 angstroms]. The first metal barrier layer and the second metal barrier layer are made of the same material, tantalum nitride. The second metal barrier layer covers the first metal barrier layer.

12. The method according to claim 1, characterized in that The process parameters for etching the first metal barrier layer are selected from one or more of the following: The low-frequency power range is 450W to 500W; The high-frequency power range is 40W to 45W; The etching gas includes: chlorine gas and argon gas, and the molar ratio of chlorine gas to argon gas in the etching gas ranges from 1:4 to 1:2; The gas flow rate of the chlorine gas in the etching gas is selected from [25 sccm, 50 sccm], and the gas flow rate of the argon gas is selected from [50 sccm, 200 sccm].

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