Package structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a packaging structure and a manufacturing method thereof. The packaging structure comprises a substrate; the chip stacking piece is positioned in a first area on the substrate and comprises a plurality of stacked first chips; the plastic packaging layer is located on the substrate and covers the chip stacking piece; the covering layer is at least located on the plastic packaging layer; wherein the mechanical strength of the covering layer is greater than that of the plastic packaging layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a packaging structure and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth in recent years. Semiconductor packaging devices typically undergo two processing steps: chip manufacturing and chip packaging. Therefore, the chip's inherent characteristics and the quality of the packaging technology directly determine the final performance of the semiconductor packaging device product.

[0003] With the continuous advancement of semiconductor technology, the overall thickness of chips is decreasing, while the metal circuit layers within them are becoming thicker. Furthermore, as the functionality requirements of semiconductor devices continue to increase, the level of integration is increasing, and a wide variety of chips are being integrated into a single package. Therefore, improving the stability and reliability of chip packaging structures has become a pressing issue for the industry. Summary of the Invention

[0004] The present disclosure provides a packaging structure and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a packaging structure, comprising: a substrate; a chip stack located in a first area on the substrate, comprising: a plurality of stacked first chips; a plastic encapsulation layer located on the substrate and covering the chip stack; a covering layer located at least on the plastic encapsulation layer; wherein the mechanical strength of the covering layer is greater than the mechanical strength of the plastic encapsulation layer.

[0006] In some embodiments, a projection of the chip stack on the substrate is located within a projection of the cover layer on the substrate.

[0007] In some embodiments, the packaging structure further includes: a second chip located in a second area on the substrate; wherein the second area is different from the first area; and the plastic encapsulation layer covers the second chip.

[0008] In some embodiments, a projection of the second chip on the substrate is located within a projection of the cover layer on the substrate.

[0009] In some embodiments, the first chip includes a memory chip, and the second chip includes a logic chip; the package structure further includes: a stress detection circuit located in the cover layer and coupled to the logic chip.

[0010] In some embodiments, the stress detection circuit is configured to detect the stress applied to the covering layer and output a detection signal; the logic chip is configured to receive the detection signal and, when the detection signal indicates that the stress applied to the covering layer is greater than a preset threshold, suspend writing data to the memory chip or suspend reading data from the memory chip.

[0011] In some embodiments, the covering layer covers the top surface and side surfaces of the molding layer.

[0012] In some embodiments, the packaging structure further includes: an adhesive layer located between the plastic packaging layer and the cover layer.

[0013] In some embodiments, the material of the covering layer includes at least one of metal and metal alloy.

[0014] In a second aspect, the present disclosure provides a method for manufacturing a packaging structure, the manufacturing method comprising: providing a substrate; forming a chip stack in a first area on the substrate; wherein the chip stack comprises a plurality of stacked first chips; forming a plastic encapsulation layer on the substrate to cover the chip stack; and forming a covering layer at least on the plastic encapsulation layer; wherein the mechanical strength of the covering layer is greater than the mechanical strength of the plastic encapsulation layer.

[0015] In some embodiments, the manufacturing method further includes: forming a second chip in a second area on the substrate; wherein the second area is different from the first area; the manufacturing method further includes: forming the plastic encapsulation layer covering the second chip on the substrate.

[0016] In some embodiments, the first chip includes a memory chip, and the second chip includes a logic chip; the manufacturing method further includes: forming a stress detection circuit in the cover layer; wherein the stress detection circuit is coupled to the logic chip.

[0017] In the disclosed embodiments, a chip stack comprises a plurality of stacked first chips, with a plastic encapsulation layer covering the chip stack. The cover layer is located at least on the plastic encapsulation layer, and the mechanical strength of the cover layer is greater than that of the plastic encapsulation layer. Thus, the cover layer can improve the mechanical strength of the package structure and effectively reduce external stress on the chip stack, thereby reducing the risk of cracking and failure of the chips in the chip stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of another packaging structure provided by an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of a cover layer in another packaging structure provided by an embodiment of the present disclosure;

[0021] Figure 4 A schematic diagram of another packaging structure provided by an embodiment of the present disclosure;

[0022] Figure 5 A schematic diagram of a stress detection circuit in another packaging structure provided by an embodiment of the present disclosure;

[0023] Figure 6 A flowchart of a method for manufacturing a packaging structure provided by an embodiment of the present disclosure;

[0024] Figures 7a to 7i A schematic structural diagram of each step in a method for manufacturing a packaging structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0027] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0028] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0030] In some embodiments, as Figure 1 As shown in the present disclosure, a packaging structure 10 is provided, including: a substrate 100; a chip stack 110, located in a first area A1 on the substrate 100, the chip stack 110 including a plurality of first chips 111; a second chip 120, located in a second area A2 on the substrate 100, the second area being different from the first area; a plastic encapsulation layer 140, located on the substrate and covering the chip stack 110 and the second chip 120; a solder resist layer 150, covering two opposite surfaces of the substrate 100; a solder ball 160, located on the surface of the substrate 100 away from the chip stack 110; and a lead 170, connecting at least one first chip 111 and the substrate 100.

[0031] In an embodiment of the present disclosure, the package structure 10 may include a multi-chip package (MCP) structure. The substrate 100 may be a package substrate, including but not limited to organic substrates, ceramic substrates, and silicon substrates. The substrate 100 provides electrical connection, protection, support, heat dissipation, and integration for the chip, thereby achieving multi-pin, reducing the size of the packaged product, improving electrical performance and heat dissipation, and multi-chip modularization. The solder resist layer 150 covers the upper and lower surfaces of the substrate 100, used to protect areas on the substrate that do not require soldering and prevent short circuits and substrate oxidation. Multiple solder balls 160 can be located on the side of the substrate 100 away from the chip surface and form a ball grid array (BGA). The solder balls 160 are used to achieve electrical connection and fixation between the package structure 100 and other components. The leads 170 can be metal bonding wires. The leads 170 can be used to connect any two first chips 111 in the chip stack 110, or to connect the first chip 111 to the contacts and wiring layer of the substrate 100. The plastic encapsulation layer 140 covers the chip stack 110 and the second chip 120, thereby isolating the chip from the external environment. The plastic encapsulation layer 140 can be formed of any suitable material, such as a non-conductive polymer material. Exemplarily, the plastic encapsulation layer 140 can be a molding compound layer, the material of which includes but is not limited to one or more of silicon oxide, epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. Preferably, the plastic encapsulation layer 140 is an epoxy molding compound (EMC). The molding compound layer and the chip can have different thermal expansion coefficients and thermal conductivities.

[0032] The chip stack 110 is located in a first area A1 of the substrate 100, and the second chip 120 is located in a second area A2 of the substrate 100. The first area A1 and the second area A2 are two independent areas on the substrate 100, that is, the first area A1 and the second area A2 do not overlap. The chip stack 110 can include multiple first chips 111 stacked in a vertical direction. The second chip 120 can be electrically connected to the first chip 111 in the chip stack 110 via wires or through the wiring layer of the substrate 100.

[0033] Exemplarily, the first chip 111 can be a memory chip, including but not limited to high bandwidth memory (HBM), static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM) and flash memory (Flash), etc., wherein the flash memory includes NAND and NOR flash memory. The multiple first chips 111 in the chip stack 110 can be the same or different types of memory chips to meet the various storage requirements of the package structure 10. The multiple first chips 111 and the first chip 111 and the substrate 100 can be connected by through-silicon vias (TSV), micro bumps, etc. The second chip 120 may include a logic chip, such as a system on chip (SoC) chip, a controller chip, a processor chip, a graphics chip, etc. In this way, the first chip 111 and the second chip 120 can provide better functional scalability for the package structure 10 and reduce the area of ​​the package structure 10. In addition, the signal transmission delay of each chip in the package structure 10 is low and the performance is better.

[0034] In some embodiments, the chip stack 110 includes a plurality of first chips 111 of different sizes. With the development of semiconductor technology, the thickness of the chip gradually decreases, and the thickness of some of the first chips 111 in the chip stack 110 is relatively thin, such as less than or equal to 40 μm. In this way, under the action of external stress, the plurality of first chips 111 with relatively thin thickness and different sizes are prone to cracking, thereby causing chip failure and affecting the reliability and stability of the packaged product. Specifically, for the chip stack 110, the maximum stress is likely to occur in the top chip, so the first chip 111 on the top layer (relatively far away from the substrate) is most likely to crack due to stress. In some embodiments, the packaging structure 10 is applied to mobile devices such as mobile phones and tablets, which greatly increases the possibility of the chip in the packaging structure 10 cracking due to external stress.

[0035] like Figure 2As shown, the present disclosure provides a packaging structure 20, including: a substrate 200; a chip stack 210, located in a first area A1 on the substrate 200, including: a plurality of stacked first chips 211; a plastic encapsulation layer 240, located on the substrate 200 and covering the chip stack 210; a covering layer 230, located at least on the plastic encapsulation layer 240; wherein the mechanical strength of the covering layer 230 is greater than the mechanical strength of the plastic encapsulation layer 240.

[0036] In an embodiment of the present disclosure, the package structure 20 may include a multi-chip package structure, which may include one or more chip stacks and one or more individually arranged chips. The package structure 20 can be applied to mobile devices such as mobile phones, tablets, laptops, and car computers, which are susceptible to external stress. The substrate 200 can be a package substrate, including but not limited to organic substrates, ceramic substrates, and silicon substrates. The substrate 200 provides electrical connection, protection, support, heat dissipation, and integration for the chip, thereby achieving multi-pin, reducing the size of the packaged product, improving electrical performance and heat dissipation, and multi-chip modularization. The solder resist layer 250 covers the upper and lower surfaces of the substrate 200 to protect areas on the substrate that do not require soldering and prevent short circuits and substrate oxidation. Multiple solder balls 260 can be located on the side of the substrate 200 away from the chip and form a ball grid array (BGA). The solder balls 260 are used to achieve electrical connection and fixation between the package structure 20 and other components. The wire 270 may be a metal bonding wire, and may be used to connect any two first chips 211 in the chip stack 210 , or to connect the first chip 211 to the contacts and wiring layer of the substrate 200 .

[0037] The chip stack 210 is located in the first area A1 on the substrate 200, and the chip stack 210 may include a plurality of first chips 211 stacked in a vertical direction. Exemplarily, the first chip 211 may be a memory chip, including but not limited to high bandwidth memory, static random access memory, dynamic random access memory, magnetic random access memory and flash memory, wherein the flash memory includes NAND and NOR flash memory. The plurality of first chips 211 in the chip stack 210 may be memory chips of the same or different types to meet the various storage requirements of the package structure 20. The plurality of first chips 211 and the first chip 211 and the substrate 200 may be connected by through silicon vias, micro bumps, etc. In some embodiments, the plurality of first chips 211 in the chip stack 210 may also be chips other than memory chips (such as logic chips, controller chips, radio frequency chips, etc.), or include a combination of memory chips and other chips, and there are no excessive restrictions here.

[0038] The plastic encapsulation layer 240 covers the chip stack 210, thereby isolating the chip from the external environment. The plastic encapsulation layer 240 can be formed of any suitable material, such as a non-conductive polymer material. Exemplarily, the plastic encapsulation layer 240 can be a molding compound layer, the material of which includes but is not limited to one or more of silicon oxide, epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. Preferably, the plastic encapsulation layer 240 is an epoxy molding compound (EMC). The molding compound layer and the chip can have different thermal expansion coefficients and thermal conductivities.

[0039] The covering layer 230 is at least located on the plastic encapsulation layer 240, such as the covering layer 230 at least covers the top surface of the plastic encapsulation layer 240, where the top surface of the plastic encapsulation layer 240 refers to the surface of the plastic encapsulation layer 240 away from the substrate 200. The mechanical strength of the covering layer 230 is greater than the mechanical strength of the plastic encapsulation layer 240, where the mechanical strength includes but is not limited to one or more of tensile strength, compressive strength, and bending strength. The covering layer 230 can be any appropriate material with strong mechanical strength, such as metal, alloy, ceramic composite material, etc. In this way, the covering layer 230 can improve the overall mechanical strength of the packaging structure 20, and when subjected to external stress, it can effectively reduce the probability of cracking, failure, and other problems in the first chip 211 in the chip stack 210, especially for the first chip 211 located at the top layer of the chip stack 210, the protective effect of the covering layer 230 is most prominent.

[0040] In some embodiments, the material of the cover layer 230 includes at least one of metal and metal alloy.

[0041] In the embodiment of the present disclosure, the material of the covering layer 230 may include at least one of a metal and an alloy. For example, the covering layer 230 may include lightweight metal materials such as aluminum, aluminum alloy, titanium, and titanium alloy, thereby providing better mechanical strength without adding too much weight. In some embodiments, the covering layer 230 may be a single-layer structure or a multi-layer structure, and each layer in the multi-layer structure may be a different material, or the material composition of each layer is different. Exemplarily, the outermost layer in the covering layer 230 has the greatest mechanical strength and is used to resist external stress, while the inner layer of the covering layer 230 close to the plastic layer 240 may have a good elastic modulus as a stress buffer layer. It can be understood that the inner layer as a stress buffer layer may be a material other than metal and alloy.

[0042] In some embodiments, as Figure 3As shown, the covering layer 230 covers the top surface and side surfaces of the plastic layer 240 .

[0043] In some embodiments, the cover layer 230 may cover the top and side surfaces of the plastic encapsulation layer 240, that is, the cover layer 230 encapsulates the plastic encapsulation layer 240. In this way, the cover layer 230 may further increase the mechanical strength of the package structure 20 and reduce the impact of external stress on the chip in the package structure 20. In some embodiments, the cover layer 230 may include a plurality of holes or gaps to facilitate heat dissipation of the chip.

[0044] In some embodiments, a projection of the chip stack 210 on the substrate 200 is located within a projection of the cover layer 230 on the substrate 200 .

[0045] In the embodiment of the present disclosure, the projection of the chip stack 210 on the substrate 200 falls within the projection of the cover layer 230 on the substrate 200, that is, the cover layer 230 covers at least the area where the chip stack 210 is located. In this way, the cover layer 230 may not completely cover the top surface of the plastic layer 240, thereby saving materials and reducing costs while ensuring the mechanical strength of the package structure 20, and leaving redundant space for chip heat dissipation or the provision of other structures (such as lead-out structures, etc.). It can be understood that the larger the coverage area of ​​the cover layer 230, the greater the improvement in the mechanical strength of the package structure 20. In this way, the coverage area of ​​the cover layer 230 can be designed by comprehensively considering aspects such as mechanical strength, design redundancy, and cost.

[0046] In some embodiments, as Figure 4 As shown, the package structure 20 further includes: a second chip 220 located in a second area A2 on the substrate 200 ; wherein the second area A2 is different from the first area A1 ; and the plastic encapsulation layer 240 covering the second chip 220 .

[0047] In an embodiment of the present disclosure, the second chip 220 may include a logic chip, such as a system on chip (SoC) chip, a controller chip, a processor chip, a graphics chip, etc. It should be noted that the second chip 220 may also be a sensor chip, a radio frequency chip, or other types of chips, and the present disclosure does not make excessive restrictions. The second chip 220 is located in the second area A2 on the substrate 200, and the first area A1 and the second area A2 are two independent areas on the substrate 200, that is, the first area A1 and the second area A2 do not overlap. The second chip 220 can be electrically connected to the first chip 211 in the chip stack 210 through a lead or through the wiring layer of the substrate 200. In addition to covering the chip stack 210, the plastic layer 240 also covers the second chip 220. In this way, the first chip 211 and the second chip 220 can provide better functional scalability for the package structure 20 and reduce the area of ​​the package structure 20, and the signal transmission delay of each chip in the package structure 20 is low and the performance is better. It is understandable that the cover layer 230 can also reduce the problems of cracking and failure of the second chip 220 .

[0048] In some embodiments, the substrate 200 of the package structure 20 may have a plurality of second chips 220 disposed separately (ie, not stacked) and a plurality of chip stacks 210 , thereby further improving the functional scalability of the packaged product.

[0049] In some embodiments, a projection of the second chip 220 on the substrate 200 is located within a projection of the cover layer 230 on the substrate 200 .

[0050] In the embodiment of the present disclosure, the projections of the second chip 220 and the chip stack 210 on the substrate 200 both fall within the projection of the cover layer 230 on the substrate 200, that is, the cover layer 230 at least covers the area where the second chip 220 and the chip stack 210 are located. In this way, the cover layer 230 may not completely cover the top surface of the plastic layer 240, thereby saving materials and reducing costs while ensuring the mechanical strength of the packaging structure 20, and leaving redundant space for chip heat dissipation or setting other structures. It can be understood that the larger the coverage area of ​​the cover layer 230, the more the mechanical strength of the packaging structure 20 is improved, so the coverage area of ​​the cover layer 230 can be designed by comprehensively considering aspects such as mechanical strength, design redundancy and cost.

[0051] In some embodiments, as Figure 4 As shown, the packaging structure 20 further includes an adhesive layer 280 located between the molding layer 240 and the covering layer 230 .

[0052] In the embodiment of the present disclosure, the adhesive layer 280 is located between the molding layer 240 and the cover layer 230 and is used to bond the molding layer 240 and the cover layer 230 to improve the structural stability of the package structure 20. For example, the adhesive layer 280 can be any suitable material having an adhesive property, such as UV light curing adhesive, organic polymer material, alloy material (such as tin alloy), etc.

[0053] In some embodiments, as Figure 5 As shown, the first chip 211 includes a memory chip, and the second chip 220 includes a logic chip; the package structure 20 further includes a stress detection circuit 290 located in the cover layer 230 and coupled to the logic chip.

[0054] In the embodiment of the present disclosure, the first chip 211 in the chip stack 210 may include a memory chip. For example, the first chip 211 includes, but is not limited to, a high-bandwidth memory, a static random access memory, a dynamic random access memory, a magnetic random access memory, and a flash memory. The second chip 220 includes a logic chip. For example, the second chip 220 may be a memory controller chip, a processor chip, or the like.

[0055] The package structure 20 also includes a stress detection circuit 290 located in the cover layer 230, and the stress detection circuit 290 is coupled to the logic chip. For example, the stress detection circuit 290 may include a resistor made of stress-sensitive material, so that the stress detection circuit 290 can output a corresponding stress detection signal based on the amount of stress applied to the cover layer 230. The stress detection circuit 290 can be connected to the logic chip via conductive vias, leads, etc. In this way, the logic chip can determine the external stress applied to the package structure 20 based on the stress detection signal and control the memory chip to perform corresponding operations (such as power off, backup, etc.), thereby reducing the impact of external stress on the data accessed by the memory chip, such as reducing data errors and data loss. In some embodiments, multiple stress detection circuits 290 can be distributed in the cover layer 230. The logic chip can comprehensively determine the external stress applied to the package structure 20 based on the detection signals generated by the multiple stress detection circuits 290 and control the memory chip to perform corresponding operations.

[0056] In some embodiments, the stress detection circuit 290 is configured to detect the stress applied to the covering layer 230 and output a detection signal; the logic chip is configured to receive the detection signal and, when the detection signal indicates that the stress applied to the covering layer 230 is greater than a preset threshold, suspend writing data to the memory chip or suspend reading data from the memory chip.

[0057] In the disclosed embodiment, stress detection circuit 290 can detect stress on cover layer 230 and output a corresponding detection signal. If the detection signal indicates that the stress on cover layer 230 exceeds a preset threshold, the logic chip can suspend writing data to or reading data from the memory chip, thereby reducing data errors, data loss, and other issues and improving the data reliability of the packaged device. The preset threshold corresponding to the stress detection signal can be calibrated based on stress testing of actual products.

[0058] In some embodiments, the solder resist layer 250 can be made of a material with higher tensile strength, flexural strength, and compressive strength than conventional solder resist materials, such as a modified resin. The substrate 200 can also be made of a material with higher tensile strength, flexural strength, and compressive strength than conventional substrate materials, such as a composite fiber material or a ceramic composite material, or a high-strength metal / alloy core can be added to the substrate 200. This can further increase the mechanical strength of the package structure 20 and reduce problems such as chip cracking and failure caused by external stress.

[0059] like Figure 6 As shown, the present disclosure provides a method for manufacturing a packaging structure, the manufacturing method comprising the following steps:

[0060] Step S10: providing a substrate;

[0061] Step S20: forming a chip stack in a first area on the substrate; wherein the chip stack includes a plurality of stacked first chips;

[0062] Step S30: forming a plastic packaging layer covering the chip stack on the substrate;

[0063] Step S40: forming a covering layer at least on the plastic encapsulation layer; wherein the mechanical strength of the covering layer is greater than the mechanical strength of the plastic encapsulation layer.

[0064] It should be understood that Figure 6 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown. Figures 7a to 7i The manufacturing process of the packaging structure shown is described in detail with the structural schematic diagram corresponding to the manufacturing process of the packaging structure shown.

[0065] like Figure 7a As shown, a substrate 200 is provided and processed, such as forming a wiring layer, contacts, a solder resist layer, etc.; Figure 7b As shown, a second chip 220 is formed in the second area of ​​the substrate 200. For example, the second chip 220 can be fixed and electrically connected to the substrate 200 using a bonding process. Here, the second chip 220 can be electrically connected to the substrate 200 through micro bumps; Figure 7c As shown, a fixing material 221 is filled at the bottom of the second chip 220; Figure 7d As shown, a chip stack 210 is formed in the first area of ​​the substrate 200. For example, the chip stack 210 can be fixed by bonding, pasting, etc. The chip stack 210 can be electrically connected to the substrate 200 by through silicon vias, micro bumps, etc. Figure 7e As shown, a lead 270 is formed to connect each first chip 211, and the lead 270 can be a metal bonding wire; Figure 7f As shown, a plastic encapsulation layer 240 is formed to cover the second chip 220 and the chip stack 210; Figure 7g As shown, an adhesive layer 280 and a cover layer 230 are sequentially formed on the plastic layer 240. The adhesive layer 280 is used to bond the plastic layer 240 and the cover layer 230 to improve the stability of the packaging structure. Figure 7h As shown, solder balls 260 are formed on the surface of the substrate 200 away from the chip stack 210 and the second chip 220 by using a soldering process. Preferably, the material of the solder balls 260 can be tin; Figure 7i It should be noted that the present disclosure does not limit the order of forming the second chip 220 and forming the chip stack 210 on the substrate 200 .

[0066] In this way, the cover layer 230 can enhance the mechanical strength of the overall package structure and effectively reduce the probability of cracking or failure of the first chip 211 in the chip stack 210 when subjected to external stress. The cover layer 230 provides the most significant protection for the first chip 211 located at the top layer of the chip stack 210. Furthermore, the cover layer 230 can also reduce the probability of cracking or failure of the second chip 220.

[0067] In some embodiments, the manufacturing method further includes: forming a second chip in a second area on the substrate; wherein the second area is different from the first area; the manufacturing method further includes: forming the plastic encapsulation layer covering the second chip on the substrate.

[0068] In some embodiments, the first chip includes a memory chip, and the second chip includes a logic chip; the manufacturing method further includes: forming a stress detection circuit in the cover layer; wherein the stress detection circuit is coupled to the logic chip.

[0069] In an embodiment of the present disclosure, an etching process can be used to form a groove of a preset depth in the cover layer, and then a deposition process or other process can be used to form a stress detection circuit in the groove. The stress detection circuit can include a resistor composed of a stress-sensitive material, so that the stress detection circuit can output a corresponding stress detection signal based on the amount of stress applied to the cover layer. In addition, the stress detection circuit can be electrically connected to a logic chip by depositing a conductive structure, wire bonding, etc., so that the logic chip can determine the external stress applied to the package structure based on the stress detection signal and control the memory chip to perform corresponding operations (such as power off, backup, etc.), thereby reducing the impact of external stress on the data accessed by the memory chip, such as reducing data errors and data loss.

[0070] In the disclosed embodiments, a stress detection circuit can detect stress on the cover layer and output a corresponding detection signal. If the detection signal indicates that the stress on the cover layer exceeds a preset threshold, the logic chip can suspend writing data to or reading data from the memory chip, thereby reducing data errors, data loss, and other issues and improving the data reliability of the packaged device. The preset threshold corresponding to the stress detection signal can be calibrated based on stress testing of actual products.

[0071] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0072] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: substrate; A chip stack, located in a first area on the substrate, comprises: a plurality of stacked first chips; a plastic packaging layer, located on the substrate and covering the chip stack; The covering layer is at least located on the plastic sealing layer; wherein the mechanical strength of the covering layer is greater than the mechanical strength of the plastic sealing layer.

2. The packaging structure according to claim 1, wherein: A projection of the chip stack on the substrate is located within a projection of the cover layer on the substrate.

3. The packaging structure according to claim 1, wherein: The packaging structure further includes: A second chip is located in a second area on the substrate; wherein the second area is different from the first area; The plastic packaging layer covers the second chip.

4. The packaging structure according to claim 3, wherein: A projection of the second chip on the substrate is located within a projection of the cover layer on the substrate.

5. The packaging structure according to claim 3, wherein: The first chip includes a memory chip, and the second chip includes a logic chip; the package structure further includes: The stress detection circuit is located in the cover layer and coupled to the logic chip.

6. The packaging structure according to claim 5, wherein: The stress detection circuit is configured to detect the stress applied to the cover layer and output a detection signal; The logic chip is configured to receive the detection signal and, if the detection signal indicates that the stress on the cover layer is greater than a preset threshold, suspend writing data into the memory chip or suspend reading data from the memory chip.

7. The packaging structure according to claim 1, wherein: The covering layer covers the top surface and side surfaces of the plastic packaging layer.

8. The packaging structure according to claim 1, wherein: The packaging structure further includes: The adhesive layer is located between the plastic sealing layer and the covering layer.

9. The packaging structure according to claim 1, wherein: The material of the covering layer includes at least one of metal and metal alloy.

10. A method for manufacturing a packaging structure, characterized in that: The manufacturing method comprises: providing a substrate; forming a chip stack in a first area on the substrate; wherein the chip stack comprises a plurality of stacked first chips; forming a plastic packaging layer covering the chip stack on the substrate; A covering layer is formed at least on the plastic sealing layer; wherein the mechanical strength of the covering layer is greater than the mechanical strength of the plastic sealing layer.

11. The manufacturing method according to claim 10, characterized in that: The manufacturing method further comprises: forming a second chip in a second area on the substrate; wherein the second area is different from the first area; The manufacturing method further comprises: The plastic packaging layer covering the second chip is formed on the substrate.

12. The manufacturing method according to claim 11, characterized in that: The first chip includes a memory chip, and the second chip includes a logic chip; The manufacturing method further comprises: A stress detection circuit is formed in the cover layer; wherein the stress detection circuit is coupled to the logic chip.

Images