Short-circuit protection device and method for I-type three-level active filter

Abstract

The invention provides a short-circuit protection device and method for an I-type three-level active filter, which can perform quick protection after a fault is detected, and meet the requirement of three-level turn-off sequential logic. Comprising a detection driving circuit which is connected with a three-phase three-level topological circuit and is used for determining the fault state of the three-level topological circuit and outputting a short-circuit fault signal when a fault occurs; the fault feedback circuit is connected with the detection driving circuit and is used for meeting the requirement that a fault feedback signal can be output when any phase has a short-circuit fault; the driving protection circuit is connected with the fault feedback circuit and is used for outputting a driving protection signal; the transceiving circuit is connected with the driving protection circuit and the detection driving circuit and is used for outputting an outer tube driving signal and an inner tube driving signal to the detection driving circuit after receiving the driving protection signal so as to realize sequential logic that an outer tube is firstly turned off and then the inner tube is turned off in the three-phase three-level topological circuit; wherein the inner tube driving signal is delayed from the outer tube driving signal.

Description

Technical Field

[0001] The present invention relates to the technical field of power harmonic control, and in particular to a short-circuit protection device and method for an I-type three-level active filter. Background Art

[0002] In a typical two-level topology, when an IGBT short-circuit occurs, the IGBT desaturates and enters the amplification region. After the protection driver chip detects the short-circuit fault, it immediately blocks the pulse and sends a fault signal to the controller. After receiving the fault signal, the controller blocks other IGBTs. However, for the I-type three-level topology, the IGBT shutdown is controlled by timing logic. That is, when a fault occurs and the driver needs to be blocked, the IGBT shutdown timing of the I-type three-level IGBT must strictly follow the order of turning off the outer tube first and then the inner tube. Otherwise, the device will be damaged. Summary of the Invention

[0003] To address the above problems, the present invention provides a short-circuit protection device and method for a type I three-level active filter, which can provide rapid protection after detecting a fault and meet the three-level shutdown timing logic requirements.

[0004] The present invention adopts the following technical solution: a short-circuit protection device for an I-type three-level active filter, comprising a three-phase three-level topology circuit connected to a three-phase AC power grid; and further comprising:

[0005] a detection drive circuit connected to the three-phase three-level topology circuit, configured to detect whether a short circuit fault occurs in each phase of the three-level topology circuit, and output a short circuit fault signal of the corresponding phase when a short circuit fault occurs;

[0006] A fault feedback circuit is connected to the detection drive circuit, and is used to receive a short-circuit fault signal and output a fault feedback signal when a short-circuit fault occurs in any phase;

[0007] A driving protection circuit, connected to the fault feedback circuit, configured to receive a fault feedback signal and output a driving protection signal;

[0008] The transceiver circuit is connected to both the drive protection circuit and the detection drive circuit, and is configured to output an external tube drive signal and an internal tube drive signal to the detection drive circuit after receiving a drive protection signal, so as to implement a timing logic in which the external tube is turned off first and the internal tube is turned off later in the three-phase three-level topology circuit; wherein the internal tube drive signal is delayed relative to the external tube drive signal.

[0009] Furthermore, the three-phase three-level topology circuit is divided into a first-phase three-level topology circuit, a second-phase three-level topology circuit, and a third-phase three-level topology circuit. The first-phase three-level topology circuit includes resistors R1 to R12, switch tubes QA1 to QA4, and diodes CR1 to CR2; the second-phase three-level topology circuit includes resistors R13 to R24, switch tubes QB1 to QB4, and diodes CR3 to CR4; the third-phase three-level topology circuit includes resistors R25 to R36, switch tubes QC1 to QC4, and diodes CR5 to CR6; phase A of the three-phase AC power grid is connected to the terminal U of the first-phase three-level topology circuit. Phase B of the three-phase AC power grid is connected to endpoint V of the first-phase three-level topology circuit, phase C of the three-phase AC power grid is connected to endpoint W of the first-phase three-level topology circuit, endpoints BUSN on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to point N of the three-phase AC power grid, endpoints BUS+ on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the positive electrode of the bus, and endpoints BUS- on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the negative electrode of the bus;

[0010] Furthermore, the detection drive circuit includes three groups of detection drive units, which are divided into a first detection drive unit, a second detection drive unit, and a third detection drive unit; the first detection drive unit includes drivers U11, U21, U31, U41, a buffer U51, resistors R37-1 to R52-1, capacitors C1-1 to C20-1, diodes D11, D21, D31, and D41; the second detection drive unit includes drivers U12, U22, U32, and U42, a buffer U52, resistors R37-2 to R52-2, capacitors C1-2 to C20-2, diodes D12, D22, D32, and D42; the third detection drive unit includes drivers U13, U23, U33, U43, buffer U53, resistors R37-3 to R52-3, capacitors C1-3 to C20-3, diodes D13, D23, D33, and D43; the drivers U11, U21, U31, U41, U12, U22, U32, U42, U13, U23, U33, and U43 all use model 1ED3321MC12N magnetic isolation driver chip, and the buffers U51, U52, and U53 all use model SN74LVC2G17DBVR Schmidt buffer chip; the first detection drive unit, the second detection drive unit, and the third detection drive unit are respectively connected to the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit;

[0011] Furthermore, the fault feedback circuit includes logic AND gates U6 and U7, resistors R53 to R58, and capacitors C21 to C22. The logic AND gates U6 and U7 both use model SN74LVC1G11DBVR logic AND gate chip; the endpoint FAULT_A on the first detection drive unit is connected to pin 1 of the logic AND gate U7 and one end of the resistor R58, the endpoint FAULT_B on the second detection drive unit is connected to pin 3 of the logic AND gate U7 and one end of the resistor R57, the endpoint FAULT_C on the third detection drive unit is connected to pin 6 of the logic AND gate U7 and one end of the resistor R56, and the other ends of the resistors R56, R57, and R58 are connected and then connected to a power supply of 3.3V; The endpoint UVLO_A on the first detection drive unit is connected to pin 3 of the logic AND gate U6 and one end of the resistor R54. The endpoint UVLO_B on the second detection drive unit is connected to pin 1 of the logic AND gate U6 and one end of the resistor R55. The endpoint UVLO_C on the third detection drive unit is connected to pin 6 of the logic AND gate U6 and one end of the resistor R53. The other ends of the resistors R53, R54, and R55 are connected and then connected to a 3.3V power supply. Pin 5 of the logic AND gate U6 is connected to one end of the capacitor C21 and then to a 3.3V power supply. Pin 5 of the logic AND gate U7 is connected to one end of the capacitor C22 and then to a 3.3V power supply. The other ends of the capacitors C21 and C22 are connected and then to ground.

[0012] Furthermore, the drive protection circuit includes resistors R59 to R63, capacitors C23 to C5, MOS tubes Q1 to Q2, and diodes D5 to D10. The positive electrodes of the diodes D5 to D10 are connected to one end of the capacitor C25 and one end of the resistor R59. The other end of the capacitor C25 is grounded. The other end of the resistor R59 is connected to a 3.3V power supply. The negative electrode of the diode D7 is connected to pin 4 of the logic AND gate U6. The negative electrode of the diode D8 is connected to pin 4 of the logic AND gate U7. The negative electrode of the diode D9 is connected to the gate of the MOS tube Q1 and one end of the resistor R61. The MOS tube Q1 The drain of the MOS transistor Q1 is connected to one end of the resistor R60 and one end of the capacitor C23, and the other end of the resistor R60 is connected to a 3.3V power supply. The source of the MOS transistor Q1 is connected to the other end of the resistor R61 and the other end of the capacitor C23 and then to ground. The cathode of the diode D10 is connected to the gate of the MOS transistor Q2 and one end of the resistor R63. The drain of the MOS transistor Q2 is connected to one end of the resistor R62 and one end of the capacitor C24. The other end of the resistor R62 is connected to a 3.3V power supply. The source of the MOS transistor Q2 is connected to the other end of the resistor R62 and the other end of the capacitor C24 and then to ground.

[0013] Furthermore, the transceiver circuit includes transceivers U8~U9 and resistors R64~R80. The transceivers U8 and U9 both use model 74AHCT245D transceiver chips. The drain of the MOS tube Q1 is connected to pin 19 of the transceiver U8 through the resistor R64, and the drain of the MOS tube Q2 is connected to pin 19 of the transceiver U9 through the resistor R73. One end of the resistor R65 and the resistor R66 are respectively connected to pins 18 and 17 of the transceiver U8, and the other ends of the resistors R65 and R66 are connected to ground. , pin 12 of the transceiver U9 is grounded after being connected to the resistor R80, pins 11 to 16 of the transceiver U8 and pins 13 to 18 of the transceiver U9 are respectively connected to the control signal terminal of the DSP controller; pin 2 of the transceiver U8 is connected to the step-down control terminal of the DSP controller, pin 3 of the transceiver U8 is connected to the step-up control terminal of the DSP controller, and pins 4 to 9 of the transceiver U8 and pins 2 to 7 of the transceiver U9 are respectively connected to the drive signal input terminals of the first detection drive unit, the second detection drive unit, and the third detection drive unit;

[0014] The present invention also provides a short-circuit protection method for an I-type three-level active filter, comprising the following steps:

[0015] S1. Obtaining a fault detection voltage in a three-phase three-level topology circuit, and determining a fault state of the three-phase three-level topology circuit according to the fault detection voltage;

[0016] S2. When a short-circuit fault is detected in the three-level topology circuit, the short-circuit fault signal is fed back to the fault feedback circuit, and the fault feedback circuit is capable of outputting a fault feedback signal when a short-circuit fault occurs in any phase of the three-level topology circuit;

[0017] S3. Generate two drive protection signals according to the fault feedback signal. One drive protection signal generates an external transistor drive signal for shutting down the external transistor in the three-level topology circuit and transmits it to the detection drive circuit via the transceiver circuit. The other drive protection signal generates an internal transistor drive signal for shutting down the internal transistor in the three-level topology circuit and transmits it to the detection drive circuit after a set delay time via the transceiver circuit.

[0018] S4. The detection drive circuit sends the outer tube drive signal and the inner tube drive signal to the three-level topology circuit in sequence, thereby realizing the timing logic of turning off the outer tube first and the inner tube later in the three-level topology circuit.

[0019] Furthermore, in step S1, if the fault detection voltage is greater than a threshold voltage, it is determined that a short-circuit fault exists in the three-level topology circuit of the corresponding phase, and the detection drive circuit outputs a low-level short-circuit fault signal to the fault feedback circuit; if the fault detection voltage is not greater than the threshold voltage, it is determined that a short-circuit fault does not exist in the three-level topology circuit of the corresponding phase, and the detection drive circuit outputs a high-level short-circuit fault signal to the fault feedback circuit;

[0020] Furthermore, in step S2, the fault feedback circuit receives three short-circuit fault signals, and the three short-circuit fault signals are in a logical AND relationship. If any one of the short-circuit fault signals is at a low level, the fault feedback circuit will output a low-level fault feedback signal to the drive protection circuit.

[0021] Furthermore, the delay time calculation formula of the inner tube driving signal after the outer tube driving signal is: Among them, V CC is the power supply voltage 3.3V; R is the resistance of resistor R62; C is the capacitance of capacitor C24; t is the delay time; V OE It is the high level threshold action voltage of transceiver U8 and transceiver U9.

[0022] The beneficial effect of the present invention is that when a short-circuit fault occurs in a switching tube in a three-level topology circuit, the detection drive circuit, fault feedback circuit, drive protection circuit, and transceiver circuit can be set to distinguish the inner and outer tube drives, make rapid protection, and meet the timing logic of shutting down the outer tube first and the inner tube later, which has good use value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural block diagram of the present invention;

[0024] Figure 2 It is a circuit principle diagram of the three-phase three-level topology circuit in the present invention;

[0025] Figure 3 This is a circuit schematic diagram of the first part of the detection drive circuit of the present invention;

[0026] Figure 4 This is a circuit schematic diagram of the second part of the detection drive circuit of the present invention;

[0027] Figure 5 This is a circuit schematic diagram of the third part of the detection drive circuit of the present invention;

[0028] Figure 6 It is a circuit principle diagram of the fault feedback circuit in the present invention;

[0029] Figure 7 This is a circuit diagram of the driving protection circuit in the present invention;

[0030] Figure 8 It is a circuit principle diagram of the transceiver circuit in the present invention. DETAILED DESCRIPTION

[0031] like Figures 1 to 8 As shown, a short-circuit protection device of an I-type three-level active filter of the present invention includes a three-phase three-level topology circuit connected to a three-phase AC power grid; it also includes a detection drive circuit, a fault feedback circuit, a drive protection circuit, and a transceiver circuit; wherein,

[0032] A detection drive circuit is connected to the three-phase three-level topology circuit, and is used to detect whether a short circuit fault occurs in each phase of the three-level topology circuit, and output a short circuit fault signal of the corresponding phase when a short circuit fault occurs;

[0033] The fault feedback circuit is connected to the detection drive circuit, and is used to receive the short-circuit fault signal and output a fault feedback signal when a short-circuit fault occurs in any phase;

[0034] A driving protection circuit is connected to the fault feedback circuit, and is used to receive a fault feedback signal and output a driving protection signal;

[0035] The transceiver circuit is connected to the drive protection circuit and the detection drive circuit, and is used to output the external tube drive signal and the internal tube drive signal to the detection drive circuit after receiving the drive protection signal, so as to realize the timing logic of shutting down the external tube first and the internal tube later in the three-phase three-level topology circuit; wherein the internal tube drive signal is delayed compared to the external tube drive signal;

[0036] Specifically, the DSP controller sends a drive command, the transceiver circuit receives the instruction of the DSP controller, and sends a drive signal to the detection drive circuit, which then acts on the four switch tubes in the three-level topology circuit of the corresponding phase to realize controllable power conversion; that is, when the IGBT switch tube serving as the inner tube or the outer tube has a short circuit fault, the IGBT switch tube desaturates, and the CE voltage drop of the IGBT switch tube increases. Once the detection drive circuit detects that the IGBT switch tube is short-circuited, it outputs a short-circuit fault signal to the fault feedback circuit. After being summarized by the drive protection circuit, it outputs two drive signals of different speeds (i.e., the outer tube drive signal and the inner tube drive signal). The fast drive signal is given to the control pin of the outer tube, and the slow drive signal is given to the control pin of the inner tube, thereby realizing the timing logic of the outer tube being turned off first and the inner tube being turned off later.

[0037] The three-phase three-level topology circuit is divided into a first-phase three-level topology circuit, a second-phase three-level topology circuit, and a third-phase three-level topology circuit. The first-phase three-level topology circuit includes resistors R1-R12, switches QA1-QA4, and diodes CR1-CR2; the second-phase three-level topology circuit includes resistors R13-R24, switches QB1-QB4, and diodes CR3-CR4; the third-phase three-level topology circuit includes resistors R25-R36, switches QC1-QC4, and diodes CR5-CR6;

[0038] The switch tubes QA1 and QA4 in the first-phase three-level topology circuit serve as outer tubes, and the switch tubes QA2 and QA3 in the first-phase three-level topology circuit serve as inner tubes.

[0039] The switch tubes QB1 and QB4 in the second-phase three-level topology circuit serve as outer tubes, and the switch tubes QB2 and QB3 in the second-phase three-level topology circuit serve as inner tubes.

[0040] The switch tubes QC1 and QC4 in the third-phase three-level topology circuit serve as outer tubes, and the switch tubes QC2 and QC3 in the third-phase three-level topology circuit serve as inner tubes.

[0041] Phase A of the three-phase AC power grid is connected to terminal U of the first-phase three-level topology circuit, phase B of the three-phase AC power grid is connected to terminal V of the first-phase three-level topology circuit, phase C of the three-phase AC power grid is connected to terminal W of the first-phase three-level topology circuit, and terminal BUSN on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to point N of the three-phase AC power grid. Terminal BUS+ on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the positive pole of the bus, and terminal BUS- on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the negative pole of the bus.

[0042] The detection drive circuit includes three groups of detection drive units, which are divided into a first detection drive unit, a second detection drive unit, and a third detection drive unit; the first detection drive unit includes drivers U11, U21, U31, U41, a buffer U51, resistors R37-1 to R52-1, capacitors C1-1 to C20-1, diodes D11, D21, D31, and D41; the second detection drive unit includes drivers U12, U22, U32, and U42, a buffer U52, resistors R37-2 to R52-2, capacitors C1-2 to C20-2, diodes D12, D22, D32, and D42; the third detection drive unit includes drivers U13, U23, U33, and U4 3. Buffer U53, resistors R37-3 to R52-3, capacitors C1-3 to C20-3, diodes D13, D23, D33, and D43; drivers U11, U21, U31, U41, U12, U22, U32, U42, U13, U23, U33, and U43 all use model 1ED3321MC12N magnetic isolation driver chip, and buffers U51, U52, and U53 all use model SN74LVC2G17DBVR Schmidt buffer chip; the first detection drive unit, the second detection drive unit, and the third detection drive unit are respectively connected to the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit;

[0043] It should be noted that the endpoints UVLO_A, UVLO_B, and UVLO_C on the detection drive circuit all serve as the drive power undervoltage detection feedback pins. For example, when the primary power supply and secondary power supply of the driver U11 are lower than the set threshold of the driver U11, the 12th pin of the driver U11 will become a low level, and then after being shaped by the buffer U51, the undervoltage signal UVLO_A will be sent to the fault feedback circuit, thereby achieving the purpose of undervoltage protection. In the fault feedback circuit, the undervoltage signals UVLO_A, UVLO_B, and UVLO_C are summarized through the logic AND gate U6. In fact, the undervoltage signals UVLO_A, UVLO_B, and UVLO_C also have a logical AND relationship. Then, as long as any undervoltage signal is low, the fault feedback circuit will pull down the output terminal DRV_UVLO, and thus the timing logic of shutting down the external tube first and the internal tube later can also be realized.

[0044] The fault feedback circuit includes logic AND gates U6 and U7, resistors R53 to R58, and capacitors C21 to C22. The logic AND gates U6 and U7 both use model SN74LVC1G11DBVR logic AND gate chip; the terminal FAULT_A on the first detection drive unit is connected to pin 1 of the logic AND gate U7 and one end of the resistor R58; the terminal FAULT_B on the second detection drive unit is connected to pin 3 of the logic AND gate U7 and one end of the resistor R57; the terminal FAULT_C on the third detection drive unit is connected to pin 6 of the logic AND gate U7 and one end of the resistor R56; the other ends of the resistors R56, R57, and R58 are connected and then connected to the power supply 3.3V; The endpoint UVLO_A on the first detection drive unit is connected to pin 3 of the logic AND gate U6 and one end of the resistor R54. The endpoint UVLO_B on the second detection drive unit is connected to pin 1 of the logic AND gate U6 and one end of the resistor R55. The endpoint UVLO_C on the third detection drive unit is connected to pin 6 of the logic AND gate U6 and one end of the resistor R53. The other ends of the resistors R53, R54, and R55 are connected and then connected to a 3.3V power supply; pin 5 of the logic AND gate U6 is connected to one end of the capacitor C21 and then to a 3.3V power supply. Pin 5 of the logic AND gate U7 is connected to one end of the capacitor C22 and then to a 3.3V power supply. The other ends of the capacitors C21 and C22 are connected and then grounded.

[0045] The drive protection circuit includes resistors R59 to R63, capacitors C23 to C5, MOS tubes Q1 to Q2, and diodes D5 to D10. The positive electrodes of diodes D5 to D10 are connected to one end of capacitor C25 and one end of resistor R59. The other end of capacitor C25 is grounded. The other end of resistor R59 is connected to the power supply 3.3V. The negative electrode of diode D7 is connected to pin 4 of logic AND gate U6. The negative electrode of diode D8 is connected to pin 4 of logic AND gate U7. The negative electrode of diode D9 is connected to the gate of MOS tube Q1 and one end of resistor R61. The drain of MOS tube Q1 The diode D10 is connected to one end of the resistor R60 and one end of the capacitor C23. The other end of the resistor R60 is connected to a 3.3V power supply. The source of the MOS transistor Q1 is connected to the other end of the resistor R61 and the other end of the capacitor C23, and then to ground. The cathode of the diode D10 is connected to the gate of the MOS transistor Q2 and one end of the resistor R63. The drain of the MOS transistor Q2 is connected to one end of the resistor R62 and one end of the capacitor C24. The other end of the resistor R62 is connected to a 3.3V power supply. The source of the MOS transistor Q2 is connected to the other end of the resistor R62 and the other end of the capacitor C24, and then to ground.

[0046] In the drive protection circuit, the terminal INV_I_LIMIT+ serves as an overcurrent protection signal. When the output current of the short-circuit protection device of the I-type three-level active filter exceeds the set value, the signal of the terminal INV_I_LIMIT+ will become a low level.

[0047] The terminal BUS_LIMIT+ serves as a DC bus overvoltage protection signal. When the DC bus voltage peak of the short-circuit protection device of the I-type three-level active filter exceeds the voltage protection threshold, the signal of the terminal BUS_LIMIT+ will become low.

[0048] The endpoints INV_I_LIMIT+, BUS_LIMIT+, DRV_UVLO, and DRV_DESAT are respectively connected to the corresponding diodes D5 to D8. These four signals also have a logical AND relationship. Then, as long as any one of these four signals becomes a low level, the MOS tube Q1 and the MOS tube Q2 will be turned off, and the output drive protection signals INV_DISABLE+H and INV_DISABLE+L will become a high level, thereby turning off the transceiver U8 and transceiver U9. The control signal of the DSP controller will not be transmitted to the next level, and all IGBT switch tube drive signals will be turned off immediately, and the IGBT switch tube will return to the off state.

[0049] The transceiver circuit includes transceivers U8~U9 and resistors R64~R80. Both transceivers U8 and U9 use model 74AHCT245D transceiver chip. The drain of MOS tube Q1 is connected to pin 19 of transceiver U8 through resistor R64. The drain of MOS tube Q2 is connected to pin 19 of transceiver U9 through resistor R73. One end of resistor R65 and resistor R66 are connected to pins 18 and 17 of transceiver U8 respectively. The other ends of resistors R65 and R66 are connected to ground. Pin 12 of transceiver U9 is connected to resistor R80. Then grounded, pins 11 to 16 of transceiver U8 and pins 13 to 18 of transceiver U9 are respectively connected to the control signal end of the DSP controller, and the DSP controller can use the STM320F28377D chip; pin 2 of transceiver U8 is connected to the step-down control end of the DSP controller, and pin 3 of transceiver U8 is connected to the step-up control end of the DSP controller. Pins 4 to 9 of transceiver U8 and pins 2 to 7 of transceiver U9 are respectively connected to the drive signal input ends of the first detection drive unit, the second detection drive unit, and the third detection drive unit.

[0050] The present invention also provides a short-circuit protection method for an I-type three-level active filter, comprising the following steps:

[0051] S1. Obtaining a fault detection voltage in a three-phase three-level topology circuit, and determining a fault state of the three-phase three-level topology circuit according to the fault detection voltage;

[0052] Specifically, if the fault detection voltage is greater than the threshold voltage, it is determined that a short-circuit fault exists in the three-level topology circuit of the corresponding phase, and the detection drive circuit outputs a low-level short-circuit fault signal to the fault feedback circuit; if the fault detection voltage is not greater than the threshold voltage, it is determined that a short-circuit fault does not exist in the three-level topology circuit of the corresponding phase, and the detection drive circuit outputs a high-level short-circuit fault signal to the fault feedback circuit;

[0053] S2. When a short-circuit fault is detected in the three-level topology circuit, the short-circuit fault signal is fed back to the fault feedback circuit, and the fault feedback circuit is able to output a fault feedback signal when a short-circuit fault occurs in any phase of the three-level topology circuit;

[0054] Specifically, the fault feedback circuit receives three short-circuit fault signals, and the three short-circuit fault signals are in a logical AND relationship. If any one of the short-circuit fault signals is at a low level, the fault feedback circuit will output a low-level fault feedback signal to the drive protection circuit.

[0055] S3. Generate two drive protection signals based on the fault feedback signal. One drive protection signal will generate an external transistor drive signal for shutting down the external transistor in the three-level topology circuit through the transceiver circuit and transmit it to the detection drive circuit. The other drive protection signal will generate an internal transistor drive signal for shutting down the internal transistor in the three-level topology circuit through the transceiver circuit after a set delay time and transmit it to the detection drive circuit.

[0056] S4, the detection drive circuit sends the outer tube drive signal and the inner tube drive signal to the three-level topology circuit in sequence, thereby realizing the timing logic of turning off the outer tube first and the inner tube later in the three-level topology circuit;

[0057] Furthermore, the delay time calculation formula of the inner tube driving signal after the outer tube driving signal is: Among them, V CC is the power supply voltage 3.3V; R is the resistance of resistor R62; C is the capacitance of capacitor C24; t is the delay time; V OE The high level threshold voltage of transceiver U8 and transceiver U9. oe When the voltage is ≥2V, the corresponding transceiver is turned off and the output is high.

[0058] The present invention is described with specific embodiments: OE =2V,V CC =3.3V, the resistance of resistor R62 is 4.99k, and the capacitance of capacitor C24 is 10nF. The delay time t is 46uS, which can ensure that the external tube is reliably turned off. In addition, by adjusting the parameters of resistor R62 and capacitor C24, the shutdown delay time of the internal and external tubes can be adjusted accordingly to ensure that the shutdown timing logic of the switch tube meets the design requirements.

[0059] The working principle of the present invention is as follows: assuming that a short circuit fault occurs in the switch tube QA1 in the first-phase three-level topology circuit, the current of the switch tube QA1 will quickly rise to the maximum current, and then the switch tube QA1 will desaturate and enter the amplification region, and the collector terminal DESA1_Q1 of the switch tube QA1 will gradually rise. When the first detection drive unit detects that the saturation conduction voltage drop of the collector terminal DESA1_Q1 of the switch tube QA1 is greater than the threshold voltage 9V, the terminal FAULT_A on the first detection drive unit will become a low-level short-circuit fault signal and be fed back to the fault feedback circuit. Multiple short-circuit fault signals are summarized through the logic AND gate U7. If any switch tube is short-circuited, the fault feedback circuit will output the output terminal DRV_DESAT Pulled low, and then the output terminal DRV_DESAT (that is, the fault feedback signal) becomes a low level, and two drive protection signals INV_DISABLE+H and INV_DISABLE+L are output. Among them, the drive protection signal INV_DISABLE+H will be pulled high first, and then the external tube drive signal that turns off the external tube will be output immediately, and then the external tube in the three-level topology circuit will be turned off first. The drive protection signal INV_DISABLE+L needs to charge the capacitor C24 through the resistor R62. When it is charged to its threshold voltage, the internal tube drive signal that turns off the internal tube will be output. At this time, the inner tube in the three-level topology circuit can be turned off, thus realizing the timing logic of turning off the outer tube first and the inner tube later.

[0060] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0061] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A short-circuit protection device for a type I three-level active power filter, comprising a three-phase three-level topology circuit connected to a three-phase AC power grid; characterized in that: It also includes: a detection drive circuit connected to the three-phase three-level topology circuit, configured to detect whether a short circuit fault occurs in each phase of the three-level topology circuit, and output a short circuit fault signal of the corresponding phase when a short circuit fault occurs; A fault feedback circuit is connected to the detection drive circuit, and is used to receive a short-circuit fault signal and output a fault feedback signal when a short-circuit fault occurs in any phase; A driving protection circuit, connected to the fault feedback circuit, configured to receive a fault feedback signal and output a driving protection signal; The transceiver circuit is connected to both the drive protection circuit and the detection drive circuit, and is configured to output an external tube drive signal and an internal tube drive signal to the detection drive circuit after receiving a drive protection signal, so as to implement a timing logic in which the external tube is turned off first and the internal tube is turned off later in the three-phase three-level topology circuit; wherein the internal tube drive signal is delayed relative to the external tube drive signal.

2. The short-circuit protection device of a type I three-level active filter according to claim 1, characterized in that: The three-phase three-level topology circuit is divided into a first-phase three-level topology circuit, a second-phase three-level topology circuit, and a third-phase three-level topology circuit. The first-phase three-level topology circuit includes resistors R1-R12, switches QA1-QA4, and diodes CR1-CR2; the second-phase three-level topology circuit includes resistors R13-R24, switches QB1-QB4, and diodes CR3-CR4; the third-phase three-level topology circuit includes resistors R25-R36, switches QC1-QC4, and diodes CR5-CR6; phase A of the three-phase AC power grid is connected to the terminal U of the first-phase three-level topology circuit, and the three-phase Phase B of the AC power grid is connected to endpoint V of the first-phase three-level topology circuit, phase C of the three-phase AC power grid is connected to endpoint W of the first-phase three-level topology circuit, endpoints BUSN on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to point N of the three-phase AC power grid, endpoints BUS+ on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the positive electrode of the bus, and endpoints BUS- on the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit are all connected to the negative electrode of the bus.

3. The short-circuit protection device of a type I three-level active filter according to claim 2, characterized in that: The detection drive circuit includes three groups of detection drive units, which are divided into a first detection drive unit, a second detection drive unit, and a third detection drive unit; the first detection drive unit includes drivers U11, U21, U31, U41, a buffer U51, resistors R37-1 to R52-1, capacitors C1-1 to C20-1, diodes D11, D21, D31, and D41; the second detection drive unit includes drivers U12, U22, U32, and U42, a buffer U52, resistors R37-2 to R52-2, capacitors C1-2 to C20-2, diodes D12, D22, D32, and D42; the third detection drive unit includes drivers U13, U23, U33, and U4 3. Buffer U53, resistors R37-3 to R52-3, capacitors C1-3 to C20-3, diodes D13, D23, D33, and D43; the drivers U11, U21, U31, U41, U12, U22, U32, U42, U13, U23, U33, and U43 all use model 1ED3321MC12N magnetic isolation driver chip, and the buffers U51, U52, and U53 all use model SN74LVC2G17DBVR Schmidt buffer chip; the first detection drive unit, the second detection drive unit, and the third detection drive unit are respectively connected to the first-phase three-level topology circuit, the second-phase three-level topology circuit, and the third-phase three-level topology circuit.

4. The short-circuit protection device of a type I three-level active filter according to claim 3, characterized in that: The fault feedback circuit includes logic AND gates U6 and U7, resistors R53 to R58, and capacitors C21 to C22. The logic AND gates U6 and U7 both use model SN74LVC1G11DBVR logic AND gate chips. The endpoint FAULT_A on the first detection drive unit is connected to pin 1 of the logic AND gate U7 and one end of the resistor R58. The endpoint FAULT_B on the second detection drive unit is connected to pin 3 of the logic AND gate U7 and one end of the resistor R57. The endpoint FAULT_C on the third detection drive unit is connected to pin 6 of the logic AND gate U7 and one end of the resistor R56. The other ends of the resistors R56, R57, and R58 are connected and then connected to a 3.3V power supply. The endpoint UVLO_A on the first detection drive unit is connected to pin 3 of the logic AND gate U6 and one end of the resistor R54. The endpoint UVLO_B on the second detection drive unit is connected to pin 1 of the logic AND gate U6 and one end of the resistor R55. The endpoint UVLO_C on the third detection drive unit is connected to pin 6 of the logic AND gate U6 and one end of the resistor R53. The other ends of the resistors R53, R54, and R55 are connected and then connected to a 3.3V power supply. Pin 5 of the logic AND gate U6 is connected to one end of the capacitor C21 and then to a 3.3V power supply. Pin 5 of the logic AND gate U7 is connected to one end of the capacitor C22 and then to a 3.3V power supply. The other ends of the capacitors C21 and C22 are connected and then to ground.

5. The short-circuit protection device of a type I three-level active filter according to claim 4, characterized in that: The driving protection circuit includes resistors R59 to R63, capacitors C23 to C5, MOS tubes Q1 to Q2, and diodes D5 to D10. The positive electrodes of the diodes D5 to D10 are connected to one end of the capacitor C25 and one end of the resistor R59. The other end of the capacitor C25 is grounded. The other end of the resistor R59 is connected to a 3.3V power supply. The negative electrode of the diode D7 is connected to pin 4 of the logic AND gate U6. The negative electrode of the diode D8 is connected to pin 4 of the logic AND gate U7. The negative electrode of the diode D9 is connected to the gate of the MOS tube Q1 and one end of the resistor R61. The drain of the MOS tube Q1 is connected to the positive electrode of the diode D7. The cathode of the diode D10 is connected to the gate of the MOS transistor Q2 and one end of the resistor R63. The drain of the MOS transistor Q2 is connected to one end of the resistor R62 and one end of the capacitor C24. The other end of the resistor R62 is connected to the 3.3V power supply. The source of the MOS transistor Q2 is connected to the other end of the resistor R62 and the other end of the capacitor C24 and then grounded.

6. The short-circuit protection device of a type I three-level active filter according to claim 5, characterized in that: The transceiver circuit includes transceivers U8~U9 and resistors R64~R80. The transceiver U8 and transceiver U9 both use model 74AHCT245D transceiver chip. The drain of the MOS tube Q1 is connected to the 19th pin of the transceiver U8 through the resistor R64. The drain of the MOS tube Q2 is connected to the 19th pin of the transceiver U9 through the resistor R73. One end of the resistor R65 and the resistor R66 are respectively connected to the 18th and 17th pins of the transceiver U8. The other ends of the resistor R65 and the resistor R66 are connected to the ground. Pin 12 of the transceiver U9 is grounded after being connected to the resistor R80, and pins 11 to 16 of the transceiver U8 and pins 13 to 18 of the transceiver U9 are respectively connected to the control signal end of the DSP controller; pin 2 of the transceiver U8 is connected to the step-down control end of the DSP controller, and pin 3 of the transceiver U8 is connected to the boost control end of the DSP controller. Pins 4 to 9 of the transceiver U8 and pins 2 to 7 of the transceiver U9 are respectively connected to the drive signal input ends of the first detection drive unit, the second detection drive unit, and the third detection drive unit.

7. A short-circuit protection method for a type I three-level active filter, characterized in that: A short-circuit protection device for an I-type three-level active filter according to any one of claims 1 to 6 is used; the method comprising the following steps: S1. Obtaining a fault detection voltage in a three-phase three-level topology circuit, and determining a fault state of the three-phase three-level topology circuit according to the fault detection voltage; S2. When a short-circuit fault is detected in the three-level topology circuit, the short-circuit fault signal is fed back to the fault feedback circuit, and the fault feedback circuit is capable of outputting a fault feedback signal when a short-circuit fault occurs in any phase of the three-level topology circuit; S3. Generate two drive protection signals according to the fault feedback signal. One drive protection signal generates an external transistor drive signal for shutting down the external transistor in the three-level topology circuit and transmits it to the detection drive circuit via the transceiver circuit. The other drive protection signal generates an internal transistor drive signal for shutting down the internal transistor in the three-level topology circuit and transmits it to the detection drive circuit after a set delay time via the transceiver circuit. S4. The detection drive circuit sends the outer tube drive signal and the inner tube drive signal to the three-level topology circuit in sequence, thereby realizing the timing logic of turning off the outer tube first and the inner tube later in the three-level topology circuit.

8. The short-circuit protection device of a type I three-level active filter according to claim 7, characterized in that: In step S1, if the fault detection voltage is greater than the threshold voltage, it is determined that a short circuit fault exists in the three-level topology circuit of the corresponding phase, and the detection drive circuit outputs a low-level short circuit fault signal to the fault feedback circuit; If the fault detection voltage is not greater than the threshold voltage, it is determined that the three-level topology circuit of the corresponding phase does not have a short-circuit fault, and the detection drive circuit outputs a high-level short-circuit fault signal to the fault feedback circuit.

9. The short-circuit protection device of a type I three-level active filter according to claim 7, characterized in that: In step S2, the fault feedback circuit receives three short-circuit fault signals, and the three short-circuit fault signals are in a logical AND relationship. When any short-circuit fault signal is at a low level, the fault feedback circuit will output a low-level fault feedback signal to the drive protection circuit.

10. The short-circuit protection device of a type I three-level active filter according to claim 7, characterized in that: The calculation formula for the delay time of the inner tube driving signal compared to the outer tube driving signal is: Among them, V CC is the power supply voltage 3.3V; R is the resistance of resistor R62; C is the capacitance of capacitor C24; t is the delay time; V OE It is the high level threshold action voltage of transceiver U8 and transceiver U9.

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