Master-slave aot-controlled dual-phase buck converter

Abstract

The application provides a master-slave AOT controlled dual-phase buck converter, comprising: a dual-phase control module, used for providing a master phase switch signal and a slave phase switch signal, wherein the master phase switch signal comprises a master phase high side switch signal and a master phase low side switch signal, and the slave phase switch signal comprises a slave phase high side switch signal and a slave phase low side switch signal; a dynamic current sharing auxiliary module, used for detecting a phase difference of the master phase high side switch signal and the slave phase high side switch signal in real time and outputting a compensation current based on a detection result to perform phase compensation on the two-phase switch signals; and a dual-phase power module, connected with the dual-phase control module, used for performing switch control on corresponding high side power tubes and low side power tubes through the master phase switch signal and the slave phase switch signal to convert an input voltage into an output voltage. The application solves the problem that the traditional master-slave AOT controlled dual-phase buck converter cannot overcome systematic phase error caused by element parameter mismatch and comparator mismatch.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design, and particularly relates to a master-slave AOT controlled dual-phase step-down converter. BACKGROUND

[0002] Under the driving of cutting-edge technologies such as cloud computing and big data, data centers have an increasing demand for high-frequency and high-efficiency power supplies, which puts forward strict requirements on step-down DC-DC converters as point load power supply applications. In order to meet the technical requirements of high power density and high step-down ratio, the double-step-down (DSD) architecture has become an ideal choice for step-down converters because it can effectively reduce the voltage stress of power tubes and improve power density. Through the synergistic effect of flying capacitors, the double-phase inductor current can be self-balanced, which to some extent solves the current sharing problem of traditional multi-phase converters.

[0003] The traditional master-slave AOT (Adaptive Constant On-Time) controlled dual-phase step-down converter uses a fixed current source to charge and discharge the capacitor to obtain a main phase delay signal, thereby adjusting the phase every cycle. As long as the two-phase on-time is the same, the 180° phase-shifted slave phase switching signal is generated through the main phase switching signal to control the opening and closing of the power tube, and the current sharing effect is realized only by the self-balancing mechanism of the flying capacitor.

[0004] However, in high-frequency high-voltage step-down ratio large-current switching power supplies, this method has limited accuracy and is difficult to cope with systematic errors. Due to the difficulty of completely consistent parameters of the on-resistance, capacitance and inductance of the two-phase circuit, as well as the influence of factors such as the mismatch of the comparator input pair, systematic phase errors will be generated. These errors cannot be eliminated only by the self-balancing mechanism of the flying capacitor, resulting in increased output voltage ripple, inconsistent two-phase on-time, poor load current sharing effect, unbalanced phase current, and further causing problems such as local overload and efficiency reduction.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a master-slave AOT controlled dual-phase step-down converter to solve the problem that the traditional master-slave AOT controlled dual-phase step-down converter cannot overcome systematic phase errors caused by element parameter mismatch and comparator mismatch.

[0007] To achieve the above object and other related objects, the present application provides a dual-phase buck converter controlled by master-slave AOT, comprising:

[0008] a dual-phase control module for providing a master phase switch signal and a slave phase switch signal, wherein the master phase switch signal comprises a master phase high-side switch signal and a master phase low-side switch signal, and the slave phase switch signal comprises a slave phase high-side switch signal and a slave phase low-side switch signal;

[0009] a dynamic current sharing assistance module for detecting a phase difference between the master phase high-side switch signal and the slave phase high-side switch signal in real time and outputting a compensation current based on the detection result to perform phase compensation on the two-phase switch signals;

[0010] a dual-phase power module connected to the dual-phase control module, for switching control of corresponding high-side power tubes and low-side power tubes by the master phase switch signal and the slave phase switch signal to convert an input voltage into an output voltage.

[0011] Optionally, the dual-phase control module comprises:

[0012] a master phase control unit connected to the dual-phase power module, for outputting a master phase on signal based on voltage-current double-loop control;

[0013] a slave phase control unit connected to the dynamic current sharing assistance module, for detecting a period of the master phase high-side switch signal and outputting a slave phase on signal through delay, and adjusting a generation speed of the slave phase on signal by the compensation current to perform phase compensation;

[0014] an adaptive on-time control unit connected to the master phase control unit and the slave phase control unit, for outputting the master phase switch signal and the slave phase switch signal, wherein an on time of the two-phase switch signals is set based on the master phase on signal and the slave phase on signal, and an off time of the two-phase switch signals is set based on the output voltage.

[0015] Optionally, the master phase control unit comprises a current sampler, an error amplifier and a first comparator, wherein the current sampler is used for sampling a valley value current and generating a sampling voltage output to a first input terminal of the first comparator, a first input terminal of the error amplifier is connected to a first reference voltage, a second input terminal of the error amplifier is connected to the output voltage, an output terminal of the error amplifier is connected to a second input terminal of the first comparator, and an output terminal of the first comparator is used as an output terminal of the master phase control unit.

[0016] Optionally, the slave phase control unit comprises a period detection part and a delay generation part, wherein:

[0017] The cycle detection part includes a first current source, a first switch, a second switch, a first capacitor and a second capacitor, a first end of the first capacitor is connected to a reference ground via the first switch and connected to an output end of the first current source, the first end of the first capacitor is also connected to a first end of the second switch, a second end of the first capacitor is connected to the reference ground, a second end of the second switch is connected to the reference ground via the second capacitor and serves as an output end of the cycle detection part;

[0018] The delay generation part includes a second current source, a third switch, a third capacitor and a second comparator, a first end of the third capacitor is connected to a reference ground via the third switch and connected to an output end of the second current source, the first end of the third capacitor is also connected to an output end of the dynamic current sharing auxiliary module and a first input end of the second comparator, a second input end of the second comparator is connected to the output end of the cycle detection part, an output end of the second comparator serves as an output end of the slave phase control unit;

[0019] The control signals of the first switch, the second switch and the third switch are generated based on the master phase high side switch signal.

[0020] Optionally, the dynamic current sharing auxiliary module includes:

[0021] A phase frequency detection unit is configured to detect a phase difference between the master phase high side switch signal and the slave phase high side switch signal in real time and output a duty cycle signal with phase difference information.

[0022] A duty cycle-voltage conversion unit is connected to the phase frequency detection unit and configured to convert the duty cycle signal with phase difference information into a direct current voltage output with phase difference information.

[0023] An error amplification unit is connected to the duty cycle-voltage conversion unit and configured to output an error voltage by error amplifying the direct current voltage with phase difference information.

[0024] A voltage-current conversion unit is connected to the error amplification unit and configured to convert the error voltage into a compensation current output.

[0025] Optionally, the phase frequency detection unit includes a first D flip-flop, a second D flip-flop, an inverter and an OR gate, wherein a clock end of the first D flip-flop is connected to a working voltage, a data end of the first D flip-flop is connected to the master phase high side switch signal, an output end of the first D flip-flop is connected to a first input end of the OR gate via the inverter, a clock end of the second D flip-flop is connected to the working voltage, a data end of the second D flip-flop is connected to the slave phase high side switch signal, an output end of the second D flip-flop is connected to a second input end of the OR gate, and an output end of the OR gate serves as an output end of the phase frequency detection unit.

[0026] Alternatively, the frequency and phase discriminator unit further comprises an AND gate, wherein: a first input terminal of the AND gate is connected to an output terminal of the first D flip-flop, a second input terminal of the AND gate is connected to an output terminal of the second D flip-flop, and an output terminal of the AND gate is connected to a reset terminal of the first D flip-flop and a reset terminal of the second D flip-flop.

[0027] Optionally, the duty cycle-voltage conversion unit comprises a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, a fourth capacitor and a fifth capacitor, wherein: a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an output terminal of the frequency and phase discriminator unit, a source of the first PMOS transistor is connected to a power supply voltage, a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and a first terminal of the first resistor, a source of the first NMOS transistor is connected to a reference ground, a second terminal of the first resistor is connected to the reference ground via the fourth capacitor and connected to a first terminal of the second resistor, and a second terminal of the second resistor is connected to the reference ground via the fifth capacitor and serves as an output terminal of the duty cycle-voltage conversion unit.

[0028] Alternatively, the duty cycle-voltage conversion unit further comprises a voltage regulator, wherein: an output terminal of the voltage regulator is connected to the source of the first PMOS transistor for providing the power supply voltage.

[0029] Optionally, the error amplification unit is implemented by a folded common-source and common-gate operational amplifier; the error amplification unit comprises a third current source, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth capacitor, wherein: the gate of the second PMOS tube is connected to the output end of the duty cycle-voltage conversion unit, the source of the second PMOS tube and the source of the third PMOS tube are both connected to the output end of the third current source, the drain of the second PMOS tube is connected to the source of the third NMOS tube, the gate of the third PMOS tube is connected to a second reference voltage, the drain of the third PMOS tube is connected to the source of the second NMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube and the drain of the sixth PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to a working voltage, the drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are both connected to a first bias voltage, the drain of the sixth PMOS tube is connected to the drain of the second NMOS tube, the drain of the seventh PMOS tube is connected to the drain of the third NMOS tube, the drain of the seventh PMOS tube is also connected to a reference ground via the sixth capacitor and serves as the output end of the error amplification unit, the gate of the second NMOS tube and the gate of the third NMOS tube are both connected to a second bias voltage, the source of the second NMOS tube is connected to the drain of the fourth NMOS tube, the source of the third NMOS tube is connected to the drain of the fifth NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are both connected to a third bias voltage, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both connected to the reference ground.

[0030] Optionally, the voltage-current conversion unit comprises a fourth current source, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a ninth NMOS transistor, wherein: the gate of the eighth PMOS transistor is connected to the output terminal of the error amplifier unit, the source of the eighth PMOS transistor and the source of the ninth PMOS transistor are both connected to the output terminal of the fourth current source, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the ninth PMOS transistor is connected to a third reference voltage, the drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the sixth NMOS transistor is connected to its drain and the gate of the eighth NMOS transistor, the source of the sixth NMOS transistor is connected to a reference ground, the gate of the seventh NMOS transistor is connected to its drain and the gate of the ninth NMOS transistor, the source of the seventh NMOS transistor is connected to the reference ground, the gate of the tenth PMOS transistor is connected to its drain and the gate of the eleventh PMOS transistor, the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor are both connected to a working voltage, the drain of the tenth PMOS transistor is connected to the drain of the eighth NMOS transistor, the drain of the eleventh PMOS transistor is connected to the drain of the ninth NMOS transistor and serves as the output terminal of the voltage-current conversion unit, and the source of the eighth NMOS transistor and the source of the ninth NMOS transistor are both connected to the reference ground.

[0031] Optionally, the dual-phase power module comprises a main-phase high-side power transistor, a slave-phase high-side power transistor, a main-phase low-side power transistor, a slave-phase low-side power transistor, a main-phase inductor, a slave-phase inductor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a fifth current source, wherein: the first terminal of the seventh capacitor is connected to the drain of the main-phase high-side power transistor and connected to the input voltage, the second terminal of the seventh capacitor is connected to a reference ground, the gate of the main-phase high-side power transistor is connected to the main-phase high-side switching signal, the source of the main-phase high-side power transistor is connected to the first terminal of the eighth capacitor and the drain of the slave-phase high-side power transistor, the second terminal of the eighth capacitor is connected to the drain of the main-phase low-side power transistor and the first terminal of the main-phase inductor, the gate of the main-phase low-side power transistor is connected to the main-phase low-side switching signal, the source of the main-phase low-side power transistor is connected to the reference ground, the gate of the slave-phase high-side power transistor is connected to the slave-phase high-side switching signal, the source of the slave-phase high-side power transistor is connected to the drain of the slave-phase low-side power transistor and the first terminal of the slave-phase inductor, the gate of the slave-phase low-side power transistor is connected to the slave-phase low-side switching signal, the source of the slave-phase low-side power transistor is connected to the reference ground, the second terminal of the main-phase inductor and the second terminal of the slave-phase inductor are connected to each other and serve as the output terminal of the dual-phase power module, and are further connected to the reference ground via the ninth capacitor and the fifth current source, respectively.

[0032] As described above, the master-slave AOT controlled dual-phase buck converter of the present application, through the design of the dynamic current sharing auxiliary module, introduces a slow loop to detect and slowly adjust the phase difference of the two-phase switching signals in real time, realizes accurate phase compensation of the two-phase switching signals, and thus realizes accurate 180° phase locking, reduces the ripple of the output voltage, and effectively improves the current sharing effect. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A structure schematic diagram of the master-slave AOT controlled dual-phase buck converter in the embodiment of the present application is shown.

[0034] Figure 2 A structure schematic diagram of the period detection part and the delay generation part in the embodiment of the present application is shown.

[0035] Figure 3 A structure schematic diagram of the frequency and phase discriminator unit in the embodiment of the present application is shown.

[0036] Figure 4 A structure schematic diagram of the duty cycle-voltage conversion unit in the embodiment of the present application is shown.

[0037] Figure 5 A structure schematic diagram of the error amplifier unit in the embodiment of the present application is shown.

[0038] Figure 6 A structure schematic diagram of the voltage-current conversion unit in the embodiment of the present application is shown.

[0039] Figure 7 A simulation test waveform diagram of the conventional master-slave AOT controlled dual-phase buck converter is shown.

[0040] Figure 8 A simulation test waveform diagram of the master-slave AOT controlled dual-phase buck converter in the embodiment of the present application is shown.

[0041] Element number explanation: 10 master-slave AOT controlled dual-phase buck converter, 100 dual-phase control module, 110 main phase control unit, 111 current sampler, 112 error amplifier, 113 first comparator, 120 slave phase control unit, 121 period detection part, 122 delay generation part, 122a second comparator, 130 adaptive on-time control unit, 200 dynamic current sharing auxiliary module, 210 frequency and phase discriminator unit, 220 duty cycle-voltage conversion unit, 221 voltage stabilizer, 230 error amplifier unit, 240 voltage-current conversion unit, 300 dual-phase power module. DETAILED DESCRIPTION

[0042] Following, the embodiments of the present application will be described in detail by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from this disclosure. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application.

[0043] Please refer to Figures 1 to 8 . It is noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shapes, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complicated.

[0044] As shown in Figure 1 , the present embodiment provides a master-slave AOT controlled dual-phase buck converter 10, which includes a dual-phase control module 100, a dynamic current sharing auxiliary module 200 and a dual-phase power module 300.

[0045] The dual-phase control module 100 is configured to provide a master-phase switching signal and a slave-phase switching signal, wherein the master-phase switching signal includes a master-phase high-side switching signal S1A and a master-phase low-side switching signal S2A, and the slave-phase switching signal includes a slave-phase high-side switching signal S1B and a slave-phase low-side switching signal S2B. In an example, as shown in Figure 1 , the dual-phase control module 100 includes a master-phase control unit 110, a slave-phase control unit 120 and an adaptive on-time control unit 130.

[0046] The master-phase control unit 110 is connected to the dual-phase power module 300 and outputs a master-phase on signal VALM based on voltage-current double-loop control. Specifically, the master-phase on signal VALM is output based on voltage outer loop control and current inner loop control, wherein the voltage outer loop control includes error amplification of the output voltage VOUT to generate an error voltage VCOMP, and the current inner loop control includes sampling of the valley current to generate a sampling voltage VSEN, and finally the master-phase on signal VALM is output by comparing the sampling voltage VSEN and the error voltage VCOMP.

[0047] In an embodiment, as shown in Figure 1As shown, the main phase control unit 110 includes a current sampler 111, an error amplifier 112 and a first comparator 113; wherein the sampling end of the current sampler 111 is connected to the drain of the main phase low side power tube ML in the dual-phase power module 300 for sampling the valley value current and generating a sampling voltage VSEN output to the first input end (e.g. the same phase input end) of the first comparator 113, the first input end (e.g. the same phase input end) of the error amplifier 112 is connected to a first reference voltage VREF1, the second input end (e.g. the opposite phase input end) of the error amplifier 112 is connected to the output end of the dual-phase power module 300 for accessing the output voltage VOUT, the output end of the error amplifier 112 is connected to the second input end (e.g. the opposite phase input end) of the first comparator 113, and the output end of the first comparator 113 serves as the output end of the main phase control unit 110 for outputting the main phase on signal VALM.

[0048] The slave phase control unit 120 is connected to the dynamic current sharing auxiliary module 200 for detecting the period of the main phase high side switching signal S1A and outputting the slave phase on signal VALS through delay, and adjusting the generation speed of the slave phase on signal VALS through the compensation current IOS to perform phase compensation on the two-phase switching signals. Specifically, as shown in Figure 1 The slave phase control unit 120 includes a period detection part 121 and a delay generation part 122.

[0049] The period detection part 121 is used for detecting the period TSW of the main phase high side switching signal S1A. In an embodiment, as shown in Figure 2 The period detection part 121 includes a first current source I1, a first switch S1, a second switch S2, a first capacitor C1 and a second capacitor C2; wherein the first end of the first capacitor C1 is connected to the reference ground via the first switch S1 and connected to the output end of the first current source I1, the first end of the first capacitor C1 is also connected to the first end of the second switch S2, the second end of the first capacitor C1 is connected to the reference ground, the input end of the first current source I1 is connected to the working voltage, and the second end of the second switch S2 is connected to the reference ground via the second capacitor C2 and serves as the output end of the period detection part 121.

[0050] The delay generation part 122 is connected to the period detection part 121 and the dynamic current sharing auxiliary module 200 for performing TSW / 2 delay and outputting the slave phase on signal VALS, and adjusting the capacitor charging speed by injecting or extracting the compensation current IOS in the charging current to adjust the signal generation speed. In an embodiment, as shown in Figure 2As shown, the delay generating part 122 includes a second current source I2, a third switch S3, a third capacitor C3 and a second comparator 122a; wherein a first end of the third capacitor C3 is connected to a reference ground via the third switch S3 and connected to an output end of the second current source I2, the first end of the third capacitor C3 is also connected to an output end of the dynamic current sharing auxiliary module 200 and a first input end (e.g. a non-inverting input end) of the second comparator 122a, an input end of the second current source I2 is connected to a working voltage, a second input end (e.g. an inverting input end) of the second comparator 122a is connected to an output end of the period detecting part 121, and an output end of the second comparator 122a is used as an output end of the slave phase control unit 120 to output a slave phase on signal VALS.

[0051] In actual application, the control signals of the first switch S1, the second switch S2 and the third switch S3 are generated based on the main phase high side switch signal S1A, for example, two single pulse signals are generated based on rising edges of the main phase high side switch signal S1A, wherein the first single pulse signal is used as the first control signal, the second single pulse signal is used as the second control signal, the second switch S2 is controlled by the first control signal, and the first switch S1 and the third switch S3 are controlled by the second control signal; in addition, the first current source I1 outputs a first current, and the second current source I2 outputs a second current, wherein the second current is twice the first current, for example, the size of the first current is ID, and the size of the second current is 2ID.

[0052] Regarding the slave phase control unit 120: in the first stage, the first switch S1, the second switch S2 and the third switch S3 are all closed, the first current source I1 charges the first capacitor C1 by ID, and the second current source I2 charges the third capacitor C3 by 2ID combined with IOS; in the second stage, after the second switch S2 is opened and then closed, the charging voltage of the first capacitor C1 in the TSW period is sampled and held on the second capacitor C2, and compared with the charging voltage of the third capacitor C3, when the charging voltage of the third capacitor C3 reaches the sampling and holding voltage of the second capacitor C2, the slave phase on signal VALS is output by the second comparator 122a, at the same time, the first switch S1 and the third switch S3 are opened and then closed to discharge the first capacitor C1 and the third capacitor C3.

[0053] The adaptive on-time control unit 130 is connected with the main phase control unit 110 and the slave phase control unit 120, and of course, is also connected with the dual-phase power module 300, for outputting the main phase switch signal and the slave phase switch signal, i.e., outputting the main phase high-side switch signal S1A, the main phase low-side switch signal S2A, the slave phase high-side switch signal S1B and the slave phase low-side switch signal S2B; wherein the adaptive on-time control unit 130 sets the turn-on time of the two-phase switch signal based on the main phase turn-on signal VALM and the slave phase turn-on signal VALS, and sets the turn-off time of the two-phase switch signal based on the output voltage VOUT. In practical application, the adaptive on-time control unit 130 mainly sets the turn-on time of the main phase high-side switch signal S1A based on the main phase turn-on signal VALM and the slave phase turn-on signal VALS, and sets the turn-off time of the main phase high-side switch signal S1A based on the output voltage VOUT, while the main phase low-side switch signal S2A, the slave phase high-side switch signal S1B and the slave phase low-side switch signal S2B are generated based on the main phase high-side switch signal S1A, which is a technology known to those skilled in the art, and thus will not be described in detail.

[0054] The dynamic current sharing auxiliary module 200 is used for real-time detecting the phase difference between the main phase high-side switch signal S1A and the slave phase high-side switch signal S1B and outputting the compensation current IOS based on the detection result, so as to perform phase compensation on the two-phase switch signal. In an example, as shown in Figure 1 The dynamic current sharing auxiliary module 200 includes the frequency and phase detection unit 210, the duty ratio-voltage conversion unit 220, the error amplification unit 230 and the voltage-current conversion unit 240.

[0055] The frequency and phase detection unit 210 is used for real-time detecting the phase difference between the main phase high-side switch signal S1A and the slave phase high-side switch signal S1B and outputting the duty ratio signal Duty with the phase difference information.

[0056] In an embodiment, as shown in Figure 3 The frequency and phase detection unit 210 includes the first D flip-flop DFF1, the second D flip-flop DFF2, the inverter INV and the OR gate OR; wherein the clock end of the first D flip-flop DFF1 is connected with the working voltage VDD, the data end of the first D flip-flop DFF1 is connected with the main phase high-side switch signal S1A, the output end of the first D flip-flop DFF1 is connected with the first input end of the OR gate OR via the inverter INV, the clock end of the second D flip-flop DFF2 is connected with the working voltage VDD, the data end of the second D flip-flop DFF2 is connected with the slave phase high-side switch signal S1B, the output end of the second D flip-flop DFF2 is connected with the second input end of the OR gate OR, and the output end of the OR gate OR is used as the output end of the frequency and phase detection unit 210, for outputting the duty ratio signal Duty with the phase difference information. Further, as shown in Figure 3As shown, the phase-frequency demodulation unit 210 further comprises an AND gate; wherein a first input terminal of the AND gate is connected to an output terminal of the first D flip-flop DFF1, a second input terminal of the AND gate is connected to an output terminal of the second D flip-flop DFF2, and an output terminal of the AND gate is connected to a reset terminal of the first D flip-flop DFF1 and a reset terminal of the second D flip-flop DFF2.

[0057] In the embodiment, the rising edge of the main-phase high-side switch signal S1A is detected by the first D flip-flop DFF1, and the rising edge of the slave-phase high-side switch signal S1B is detected by the second D flip-flop DFF2; at the rising edges of the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B, the first D flip-flop DFF1 and the second D flip-flop DFF2 output two logic level signals with different phases and different pulse widths, and then the logic level signals are processed by the inverter INV and the OR gate OR to obtain a duty cycle signal Duty with phase difference information. When the phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is less than 180°, the high-level pulse width of the Duty increases, and the duty cycle increases; when the phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is greater than 180°, the high-level pulse width of the Duty decreases, and the duty cycle decreases.

[0058] The duty cycle-voltage conversion unit 220 is connected to the phase-frequency demodulation unit 210, and is configured to convert the duty cycle signal Duty with phase difference information into a direct current voltage VFLTR with phase difference information.

[0059] In an embodiment, as shown in Figure 4 The duty cycle-voltage conversion unit 220 comprises a first PMOS transistor MP1, a first NMOS transistor MN1, a first resistor R1, a second resistor R2, a fourth capacitor C4 and a fifth capacitor C5; wherein the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are both connected to the output terminal of the phase-frequency demodulation unit 210 to access the duty cycle signal Duty with phase difference information, the source of the first PMOS transistor MP1 accesses the supply voltage VLDO, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and the first terminal of the first resistor R1, the source of the first NMOS transistor MN1 is connected to the reference ground, the second terminal of the first resistor R1 is connected to the reference ground via the fourth capacitor C4 and is connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is connected to the reference ground via the fifth capacitor C5 and serves as the output terminal of the duty cycle-voltage conversion unit 220 to output the direct current voltage VFLTR with phase difference information. Further, as shown in Figure 4As shown, the duty cycle-to-voltage conversion unit 220 also includes a voltage regulator 221, whose output terminal is connected to the source of the first PMOS transistor MP1 to provide the supply voltage VLDO; as an optional solution, the voltage regulator 221 is implemented using a linear regulator.

[0060] In this embodiment, the first PMOS transistor MP1 and the first NMOS transistor MN1 form an inverter, and the first resistor R1, the second resistor R2, the fourth capacitor C4, and the fifth capacitor C5 form a second-order RC passive network. When the circuit is working, the voltage regulator 221 outputs the supply voltage VLDO. The duty cycle signal Duty, which carries phase difference information, is converted from high level to VLDO by the inverter, resulting in a duty cycle signal FDuty with opposite polarity. This signal is then filtered by the second-order RC passive network to obtain a DC voltage VFLTR with phase difference information. This solves the problem of traditional charge pump phase-locked loops having difficulty finding a reference voltage, thereby reducing the complexity of the control loop. When the phase difference between the main phase high-side switch signal S1A and the slave phase high-side switch signal S1B is less than 180°, the duty cycle of FDuty decreases, and VFLTR decreases; when the phase difference between the main phase high-side switch signal S1A and the slave phase high-side switch signal S1B is greater than 180°, the duty cycle of FDuty increases, and VFLTR increases.

[0061] Error amplification unit 230, connected to duty cycle-to-voltage conversion unit 220, amplifies the DC voltage VFLTR containing phase difference information and outputs error voltage EAOUT. Specifically, it amplifies the DC voltage VFLTR containing phase difference information using a second reference voltage VREF2 and outputs error voltage EAOUT. As an optional solution, error amplification unit 230 is implemented using a folded common-source cascode operational amplifier to achieve a larger input-output swing.

[0062] In one implementation, such as Figure 5As shown, the error amplification unit 230 comprises a third current source I3, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth capacitor C6; wherein the gate of the second PMOS transistor MP2 is connected to the output of the duty cycle-voltage conversion unit 220 to access the direct current voltage VFLTR with phase difference information, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are both connected to the output of the third current source I3 to access a bias current, the drain of the second PMOS transistor MP2 is connected to the source of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3 accesses a second reference voltage VREF2, the drain of the third PMOS transistor MP3 is connected to the source of the second NMOS transistor MN2, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5 and the drain of the sixth PMOS transistor MP6, the source of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5 both access a working voltage VDD, the drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6, the drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, the gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7 both access a first bias voltage VB1, the drain of the sixth PMOS transistor MP6 is connected to the drain of the second NMOS transistor MN2, the drain of the seventh PMOS transistor MP7 is connected to the drain of the third NMOS transistor MN3, the drain of the seventh PMOS transistor MP7 is also connected to a reference ground via the sixth capacitor C6 and serves as the output of the error amplification unit 230 to output an error voltage EAOUT, the gate of the second NMOS transistor MN2 and the gate of the third NMOS transistor MN3 both access a second bias voltage VB2, the source of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4, the source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5 both access a third bias voltage VB3, and the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5 are both connected to the reference ground.

[0063] In this embodiment, the second PMOS transistor MP2 and the third PMOS transistor MP3 serve as the input pair. The second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 form a common-source cascode current mirror. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 form a self-biased common-source cascode current mirror. The sixth capacitor C6 serves as a ground compensation capacitor to limit the loop bandwidth. When the circuit is operating normally, the DC voltage VFLTR, carrying phase difference information, is input from the inverting input terminal of the operational amplifier. Through the adjustment of the negative feedback loop, it continuously approaches the second reference voltage VREF2 and outputs the error voltage EAOUT. When the phase difference between the main phase high-side switching signal S1A and the slave phase high-side switching signal S1B is less than 180°, VFLTR decreases and the error voltage EAOUT increases. When the phase difference between the main phase high-side switching signal S1A and the slave phase high-side switching signal S1B is greater than 180°, VFLTR increases and the error voltage EAOUT decreases. In practical applications, since the phase difference between the main phase high-side switching signal S1A and the slave phase high-side switching signal S1B is 180° under steady-state operation, i.e., the duty cycle of FDuty is 50%, the value of the second reference voltage VREF2 should be designed to be VLDO / 2.

[0064] The voltage-to-current conversion unit 240 is connected to the error amplifier unit 230 and is used to convert the error voltage EAOUT into the compensation current IOS output.

[0065] In one implementation, such as Figure 6As shown, the voltage-current conversion unit 240 comprises a fourth current source I4, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; wherein the gate of the eighth PMOS transistor MP8 is connected to the output terminal of the error amplification unit 230 to access the error voltage EAOUT, the source of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9 are both connected to the output terminal of the fourth current source I4, the drain of the eighth PMOS transistor MP8 is connected to the drain of the sixth NMOS transistor MN6, the gate of the ninth PMOS transistor MP9 accesses the third reference voltage VREF3, the drain of the ninth PMOS transistor MP9 is connected to the drain of the seventh NMOS transistor MN7, the gate of the sixth NMOS transistor MN6 is connected to its drain and the gate of the eighth NMOS transistor MN8, the source of the sixth NMOS transistor MN6 is connected to the reference ground, the gate of the seventh NMOS transistor MN7 is connected to its drain and the gate of the ninth NMOS transistor MN9, the source of the seventh NMOS transistor MN7 is connected to the reference ground, the gate of the tenth PMOS transistor MP10 is connected to its drain and the gate of the eleventh PMOS transistor MP11, the source of the tenth PMOS transistor MP10 and the source of the eleventh PMOS transistor MP11 both access the working voltage VDD, the drain of the tenth PMOS transistor MP10 is connected to the drain of the eighth NMOS transistor MN8, the drain of the eleventh PMOS transistor MP11 is connected to the drain of the ninth NMOS transistor MN9 and serves as the output terminal of the voltage-current conversion unit 240, to inject or extract the compensation current IOS from the delay generation part 122 in the phase control unit 120, the source of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9 are both connected to the reference ground.

[0066] In this embodiment, the error voltage EAOUT and the third reference voltage VREF3 are input from the gates of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9, respectively, to control the current output by the fourth current source I4, and the polarity and magnitude of the compensation current IOS are regulated by two sets of current mirrors composed of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth PMOS transistor MP10, and the eleventh PMOS transistor MP11. When the phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is less than 180°, the compensation current IOS decreases due to the increase in the error voltage EAOUT and the decrease in the current flowing through the eighth PMOS transistor MP8, and at this time, the voltage-current conversion unit 240 extracts current from the delay generation portion 122; when the phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is greater than 180°, the compensation current IOS increases due to the decrease in the error voltage EAOUT and the increase in the current flowing through the eighth PMOS transistor MP8, and at this time, the voltage-current conversion unit 240 injects current into the delay generation portion 122.

[0067] The dual-phase power module 300 is connected to the dual-phase control module 100, and switches the corresponding high-side power transistor and low-side power transistor by the main-phase switch signal and the slave-phase switch signal, for example, switches the main-phase high-side power transistor MH by the main-phase high-side switch signal S1A, switches the main-phase low-side power transistor ML by the main-phase low-side switch signal S2A, switches the slave-phase high-side power transistor SH by the slave-phase high-side switch signal S1B, and switches the slave-phase low-side power transistor SL by the slave-phase low-side switch signal S2B, to convert the input voltage VIN into the output voltage VOUT.

[0068] In one embodiment, as Figure 1As shown, the dual-phase power module 300 includes a main-phase high-side power tube MH, a slave-phase high-side power tube SH, a main-phase low-side power tube ML, a slave-phase low-side power tube SL, a main-phase inductor LM, a slave-phase inductor LS, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a fifth current source I5; wherein a first end of the seventh capacitor C7 is connected to a drain of the main-phase high-side power tube MH and inputs a voltage VIN, a second end of the seventh capacitor C7 is connected to a reference ground, a gate of the main-phase high-side power tube MH inputs a main-phase high-side switch signal S1A, a source of the main-phase high-side power tube MH is connected to a first end of the eighth capacitor C8 and a drain of the slave-phase high-side power tube SH, a second end of the eighth capacitor C8 is connected to a drain of the main-phase low-side power tube ML and a first end of the main-phase inductor LM, a gate of the main-phase low-side power tube ML inputs a main-phase low-side switch signal S2A, a source of the main-phase low-side power tube ML is connected to the reference ground, a gate of the slave-phase high-side power tube SH inputs a slave-phase high-side switch signal S1B, a source of the slave-phase high-side power tube SH is connected to a drain of the slave-phase low-side power tube SL and a first end of the slave-phase inductor LS, a gate of the slave-phase low-side power tube SL inputs a slave-phase low-side switch signal S2B, a source of the slave-phase low-side power tube SL is connected to the reference ground, a second end of the main-phase inductor LM and a second end of the slave-phase inductor LS are connected to each other and serve as an output end of the dual-phase power module 300 to output an output voltage VOUT, and the second end of the main-phase inductor LM and the second end of the slave-phase inductor LS are respectively connected to the reference ground via the ninth capacitor C9 and the fifth current source I5.

[0069] In the master-slave AOT-controlled dual-phase buck converter 10 of the embodiment, when the dynamic current-sharing auxiliary module 200 is normally working: if a phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is less than 180°, a duty cycle of Duty increases, VFLTR decreases, EAOUT increases, and IOS decreases, at this time, a current is extracted from the delay generation part 122; if the phase difference between the main-phase high-side switch signal S1A and the slave-phase high-side switch signal S1B is greater than 180°, the duty cycle of Duty decreases, VFLTR increases, EAOUT decreases, and IOS increases, at this time, a current is injected into the delay generation part 122.

[0070] Taking the phase difference between the main phase high side switch signal S1A and the slave phase high side switch signal S1B greater than 180° as an example, the frequency and phase discrimination unit 210 outputs a Duty signal with a duty cycle less than 50%, which is converted into a VFLTR signal greater than VLDO / 2 by the duty cycle-voltage conversion unit 220, and then the VFLTR signal is error-amplified with the reference of VLDO / 2 by the error amplification unit 230 to reduce the EAOUT signal. Finally, the voltage-current conversion unit 240 increases the IOS signal according to the change amount of EAOUT, that is, injects current into the delay generation part 122, thereby speeding up the charging speed of the third capacitor C3 and generating the slave phase on signal VALS earlier. In this way, through the above-mentioned negative feedback adjustment mode, the phase difference between the main phase high side switch signal S1A and the slave phase high side switch signal S1B reaches 180°, and the 180° phase lock is accurately realized, thereby improving the current sharing effect.

[0071] Next, please refer to Figure 1 , refer to Figure 7 and Figure 8 , and simulate and test the traditional master-slave AOT controlled dual-phase buck converter and the master-slave AOT controlled dual-phase buck converter 10 in this embodiment with the dynamic current sharing auxiliary module 200 added, to demonstrate and illustrate the performance of each.

[0072] The traditional master-slave AOT controlled dual-phase buck converter (i.e. the structure of the circuit shown in Figure 1 after removing the dynamic current sharing auxiliary module 200), only realizes current sharing through the self-balancing mechanism of the flying capacitor; however, due to factors such as element parameter mismatch and comparator mismatch, there is a systematic phase error, the output voltage ripple is large, and the conduction time is not completely consistent, resulting in poor current sharing effect. The specific simulation test is shown in Figure 7 . Figure 7 In Figure 7 , taking the rising edge of the fourth voltage pulse in the drain voltage VD_SL of the slave phase low side power tube SL as the reference rising edge, the time from the rising edge of the third voltage pulse to the reference rising edge in the drain voltage VD_ML of the main phase low side power tube ML is about 546.703ns, and the time from the rising edge of the fourth voltage pulse to the reference rising edge is about 490.389ns, with a difference of about 56.314ns. In addition, the peak-to-peak current error between the main phase inductor current ILM and the slave phase inductor current ILS is about 237.588mA.

[0073] The master-slave AOT controlled dual-phase buck converter 10 of this embodiment realizes current sharing through the self-balancing mechanism of the flying capacitor, and also realizes phase detection and feedback compensation between the two phases from a global perspective through the dynamic current sharing auxiliary module 200, thereby solving the problem of current imbalance caused by systematic phase error. The specific simulation test is shown in Figure 8 . Figure 8In the master-slave AOT controlled dual-phase buck converter 10, the rising edge of the fourth voltage pulse in the drain voltage VD_SL of the slave low-side power tube SL is taken as the reference rising edge, the time from the rising edge of the fourth voltage pulse to the reference rising edge in the drain voltage VD_ML of the master low-side power tube ML is about 518.992 ns, the time from the rising edge of the fifth voltage pulse to the reference rising edge is about 517.055 ns, the difference is about 1.937 ns, and in addition, the peak-to-peak current error between the master inductor current ILM and the slave inductor current ILS is about 42.063 mA.

[0074] From Figure 7 And Figure 8 It can be seen that, compared with the conventional master-slave AOT controlled dual-phase buck converter, in the master-slave AOT controlled dual-phase buck converter 10 of the embodiment, the phase difference of the two phases is smaller, and the current is more balanced; for a working frequency of 1 MHz and a load of 50 A, the phase error of the embodiment is only about 2 ns, and the current error is reduced by about 80%.

[0075] In summary, the master-slave AOT controlled dual-phase buck converter of the present application introduces a slow loop to detect and slowly adjust the phase difference of the two-phase switching signals in real time through the design of the dynamic current-sharing auxiliary module, realizes accurate phase compensation of the two-phase switching signals, and realizes accurate 180° phase locking, reduces the ripple of the output voltage, and effectively improves the current-sharing effect. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0076] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A master-slave AOT-controlled dual-phase buck converter, characterized in that, The application relates to a dual-phase control module, a dynamic current-sharing auxiliary module and a dual-phase power module. The dual-phase control module comprises a main-phase control unit, a slave-phase control unit and an adaptive on-time control unit. The main-phase control unit is connected with the dual-phase power module and outputs a main-phase on signal based on voltage-current double-loop control. The slave-phase control unit is connected with the dynamic current-sharing auxiliary module and detects the period of the main-phase high-side switch signal and outputs a slave-phase on signal through delay.

2. The master-slave AOT-controlled dual-phase buck converter of claim 1, wherein, The adaptive on-time control unit is connected with the main-phase control unit and the slave-phase control unit and outputs the main-phase switch signal and the slave-phase switch signal. The main-phase control unit comprises a current sampler, an error amplifier and a first comparator. The current sampler samples a valley current and generates a sampling voltage output to the first input terminal of the first comparator. The first input terminal of the error amplifier is connected with a first reference voltage.

3. The master-slave AOT-controlled dual-phase buck converter of claim 2, wherein, The second input terminal of the error amplifier is connected with the output voltage.

4. The master-slave AOT-controlled dual-phase buck converter of claim 2, wherein, The output terminal of the error amplifier is connected with the second input terminal of the first comparator. The output terminal of the first comparator is used as the output terminal of the main-phase control unit. The slave-phase control unit comprises a period detection part and a delay generation part. The period detection part comprises a first current source, a first switch, a second switch, a first capacitor and a second capacitor. The first terminal of the first capacitor is connected with a reference ground via the first switch and connected with the output terminal of the first current source. The first terminal of the first capacitor is also connected with the first terminal of the second switch. The second terminal of the first capacitor is connected with the reference ground. The second terminal of the second switch is connected with the reference ground via the second capacitor and used as the output terminal of the period detection part. The delay generation part comprises a second current source, a third switch, a third capacitor and a second comparator. The first terminal of the third capacitor is connected with the reference ground via the third switch and connected with the output terminal of the second current source. The first terminal of the third capacitor is also connected with the output terminal of the dynamic current-sharing auxiliary module and the first input terminal of the second comparator. The second input terminal of the second comparator is connected with the output terminal of the period detection part. The output terminal of the second comparator is used as the output terminal of the slave-phase control unit. The control signals of the first switch, the second switch and the third switch are generated based on the main phase high-side switch signal.

5. The master-slave AOT-controlled dual-phase buck converter of claim 1, wherein, The dynamic current sharing auxiliary module comprises: a phase difference detection unit, configured to detect a phase difference between the main phase high-side switch signal and the slave phase high-side switch signal in real time and output a duty cycle signal with phase difference information; a duty cycle-voltage conversion unit, connected to the phase difference detection unit, configured to convert the duty cycle signal with phase difference information into a direct current voltage output with phase difference information; an error amplification unit, connected to the duty cycle-voltage conversion unit, configured to output an error voltage by error amplification on the direct current voltage with phase difference information; a voltage-current conversion unit, connected to the error amplification unit, configured to convert the error voltage into a compensation current output.

6. The master-slave AOT-controlled dual-phase buck converter of claim 5, wherein, The phase difference detection unit comprises a first D flip-flop, a second D flip-flop, an inverter and an OR gate, wherein: a clock end of the first D flip-flop is connected to a working voltage, a data end of the first D flip-flop is connected to the main phase high-side switch signal, an output end of the first D flip-flop is connected to a first input end of the OR gate via the inverter, a clock end of the second D flip-flop is connected to the working voltage, a data end of the second D flip-flop is connected to the slave phase high-side switch signal, an output end of the second D flip-flop is connected to a second input end of the OR gate, and an output end of the OR gate is an output end of the phase difference detection unit; alternatively, the phase difference detection unit further comprises an AND gate, wherein: a first input end of the AND gate is connected to an output end of the first D flip-flop, a second input end of the AND gate is connected to an output end of the second D flip-flop, and an output end of the AND gate is connected to a reset end of the first D flip-flop and a reset end of the second D flip-flop.

7. The master-slave AOT-controlled dual-phase buck converter of claim 5, wherein, The duty cycle-voltage conversion unit comprises a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, a fourth capacitor and a fifth capacitor, wherein: a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an output end of the phase difference detection unit, a source of the first PMOS transistor is connected to a power supply voltage, a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and a first end of the first resistor, a source of the first NMOS transistor is connected to a reference ground, a second end of the first resistor is connected to the reference ground via the fourth capacitor and connected to a first end of the second resistor, a second end of the second resistor is connected to the reference ground via the fifth capacitor and is an output end of the duty cycle-voltage conversion unit; alternatively, the duty cycle-voltage conversion unit further comprises a voltage stabilizer, wherein: an output end of the voltage stabilizer is connected to the source of the first PMOS transistor, for providing the power supply voltage.

8. The master-slave AOT-controlled dual-phase buck converter of claim 5, wherein, The error amplification unit is realized by a folded common-source and common-gate operational amplifier; the error amplification unit comprises a third current source, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth capacitor, wherein: the gate of the second PMOS tube is connected to the output end of the duty cycle-voltage conversion unit, the source of the second PMOS tube and the source of the third PMOS tube are both connected to the output end of the third current source, the drain of the second PMOS tube is connected to the source of the third NMOS tube, the gate of the third PMOS tube is connected to a second reference voltage, the drain of the third PMOS tube is connected to the source of the second NMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube and the drain of the sixth PMOS tube, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to a working voltage, the drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are both connected to a first bias voltage, the drain of the sixth PMOS tube is connected to the drain of the second NMOS tube, the drain of the seventh PMOS tube is connected to the drain of the third NMOS tube, the drain of the seventh PMOS tube is also connected to a reference ground via the sixth capacitor and serves as the output end of the error amplification unit, the gate of the second NMOS tube and the gate of the third NMOS tube are both connected to a second bias voltage, the source of the second NMOS tube is connected to the drain of the fourth NMOS tube, the source of the third NMOS tube is connected to the drain of the fifth NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are both connected to a third bias voltage, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both connected to the reference ground.

9. The master-slave AOT-controlled dual-phase buck converter of claim 5, wherein, The voltage-current conversion unit comprises a fourth current source, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein: the gate of the eighth PMOS tube is connected to the output terminal of the error amplifier unit, the source of the eighth PMOS tube and the source of the ninth PMOS tube are both connected to the output terminal of the fourth current source, the drain of the eighth PMOS tube is connected to the drain of the sixth NMOS tube, the gate of the ninth PMOS tube is connected to a third reference voltage, the drain of the ninth PMOS tube is connected to the drain of the seventh NMOS tube, the gate of the sixth NMOS tube is connected to the drain thereof and the gate of the eighth NMOS tube, the source of the sixth NMOS tube is connected to a reference ground, the gate of the seventh NMOS tube is connected to the drain thereof and the gate of the ninth NMOS tube, the source of the seventh NMOS tube is connected to the reference ground, the gate of the tenth PMOS tube is connected to the drain thereof and the gate of the eleventh PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are both connected to a working voltage, the drain of the tenth PMOS tube is connected to the drain of the eighth NMOS tube, the drain of the eleventh PMOS tube is connected to the drain of the ninth NMOS tube and serves as an output terminal of the voltage-current conversion unit, and the source of the eighth NMOS tube and the source of the ninth NMOS tube are both connected to the reference ground.

10. The master-slave AOT-controlled dual-phase buck converter of claim 1, wherein, The dual-phase power module comprises a main-phase high-side power tube, a slave-phase high-side power tube, a main-phase low-side power tube, a slave-phase low-side power tube, a main-phase inductor, a slave-phase inductor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a fifth current source, wherein: the first terminal of the seventh capacitor is connected to the drain of the main-phase high-side power tube and connected to the input voltage, the second terminal of the seventh capacitor is connected to a reference ground, the gate of the main-phase high-side power tube is connected to the main-phase high-side switching signal, the source of the main-phase high-side power tube is connected to the first terminal of the eighth capacitor and the drain of the slave-phase high-side power tube, the second terminal of the eighth capacitor is connected to the drain of the main-phase low-side power tube and the first terminal of the main-phase inductor, the gate of the main-phase low-side power tube is connected to the main-phase low-side switching signal, the source of the main-phase low-side power tube is connected to the reference ground, the gate of the slave-phase high-side power tube is connected to the slave-phase high-side switching signal, the source of the slave-phase high-side power tube is connected to the drain of the slave-phase low-side power tube and the first terminal of the slave-phase inductor, the gate of the slave-phase low-side power tube is connected to the slave-phase low-side switching signal, the source of the slave-phase low-side power tube is connected to the reference ground, the second terminal of the main-phase inductor and the second terminal of the slave-phase inductor are connected to each other and serve as an output terminal of the dual-phase power module, and are further connected to the reference ground via the ninth capacitor and the fifth current source, respectively.

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