Multi-bit flip-flop and control method thereof

Abstract

The present invention provides a multi-bit flip-flop and a method of controlling the same, the multi-bit flip-flop comprising a first flip-flop arranged to output a first data output signal, the first flip-flop comprising: a first selection circuit arranged to select a first data output signal; a first transmission circuit arranged to transmit a first data signal or a first test signal to an output node of the first selection circuit as a first input signal; a first latch circuit arranged to generate a first signal according to the first input signal; and a first data output stage circuit arranged to generate a first data output signal as a function of the first signal; when the multi-bit flip-flop operates in a test mode, the first selection circuit transmits the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit maintains a first data output signal at a fixed voltage level. By implementing the embodiment of the invention, power consumption can be reduced.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202110437732.7 filed on April 22, 2021, and invention name “Multi-bit trigger and its control method”. Technical Field

[0002] The present invention relates to a flip-flop design, and more particularly to a multi-bit flip-flop with power saving characteristics and a control method thereof. Background Art

[0003] Scan chains are used to detect various manufacturing faults in combinational logic blocks during the test process. Typically, a scan chain consists of multiple flip-flops connected in series. In normal mode, the data output of each flip-flop is connected to the combinational logic circuit for normal data transmission. However, in test mode, the data output of each flip-flop still transmits data, so the combinational logic circuit remains operational, resulting in unnecessary power consumption. Summary of the Invention

[0004] The present invention provides a multi-bit trigger and a control method thereof, which can reduce power consumption.

[0005] A multi-bit flip-flop provided by the present invention may include: a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops include a first flip-flop, arranged to output a first data output signal at a first data output terminal of the multi-bit flip-flop, the first flip-flop including: a first selection circuit, arranged to send a first data signal or a first test signal at the first data input terminal of the multi-bit flip-flop to an output node of the first selection circuit as a first input signal; a first latch circuit, coupled to the output node of the first selection circuit, arranged to generate a first signal based on the first input signal; and a first data output stage circuit, arranged to receive the first signal and generate the first data output signal based on the first signal; wherein, when the multi-bit flip-flop operates in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal.

[0006] A control method provided by the present invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops and respectively coupled to N data output terminals of the N flip-flops, wherein N is a positive integer not less than 1, and the control method includes: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, passing the external test signal through the internal scan chain; generating a scan output signal having a voltage level that changes with the voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; and regardless of the voltage level of the external test signal, maintaining each of (N-1) data output signals at a fixed voltage level, wherein the (N-1) data output signals are respectively output from the remaining (N-1) flip-flops in the N flip-flops to the remaining (N-1) output terminals of the N data output terminals.

[0007] Another control method provided by the present invention is applied to a multi-bit trigger connected with N triggers to form an internal scan chain, wherein the multi-bit trigger includes a scan input terminal coupled to one of the N triggers, a scan output terminal coupled to another of the N triggers, and N data output terminals respectively coupled to the N triggers, wherein N is a positive integer not less than 1; the control method includes: in response to receiving an external test signal at the scan input terminal of the multi-bit trigger, passing the external test signal through the internal scan chain; generating a scan output signal having a voltage level that changes with the voltage level of the external test signal, wherein the scan output signal is output from the other trigger of the N triggers to the scan output terminal; and regardless of the voltage level of the external test signal, maintaining the N data output signals at a fixed voltage level, wherein the N data output signals are respectively output from the N triggers to the N data output terminals of the multi-bit trigger.

[0008] As described above, the embodiments of the present invention maintain the data output signal at a fixed voltage level when a test signal is received, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a diagram illustrating a first multi-bit flip-flop (MBFF) having a power saving feature according to an embodiment of the present invention.

[0010] Figure 2 is a diagram showing a first circuit design of an MBFF according to an embodiment of the present invention.

[0011] Figure 3is a diagram showing a first alternative design of a data output stage circuit with a gating function according to an embodiment of the present invention.

[0012] Figure 4 is a diagram showing a second alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

[0013] Figure 5 is a diagram showing a third alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

[0014] Figure 6 is a diagram showing a fourth alternative design of the data output stage circuit with a hold function according to an embodiment of the present invention.

[0015] Figure 7 is a diagram showing a fifth alternative design of the data output stage circuit with a hold function according to an embodiment of the present invention.

[0016] Figure 8 FIG. 2 is a schematic diagram illustrating a second MBFF having a power saving feature according to an embodiment of the present invention.

[0017] Figure 9 is a diagram showing a second circuit design of an MBFF according to an embodiment of the present invention.

[0018] Figure 10 FIG. 1 is a diagram illustrating a third MBFF having power saving characteristics according to an embodiment of the present invention.

[0019] Figure 11 is a diagram showing a third circuit design of an MBFF according to an embodiment of the present invention.

[0020] Figure 12 is a diagram showing a first alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention.

[0021] Figure 13 is a diagram showing a second alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention.

[0022] Figure 14 is a diagram showing a third alternative design of the scan output stage circuit with a hold function according to an embodiment of the present invention.

[0023] Figure 15 is a diagram showing a fourth alternative design of the scan output stage circuit with a hold function according to an embodiment of the present invention.

[0024] Figure 16is a diagram showing a fifth alternative design of the scan output stage circuit with a hold function according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality. Throughout the specification and claims, the terms "including" and "comprising" are open-ended and should be interpreted as meaning "including, but not limited to." "Substantially" means that within an acceptable range of error, a person skilled in the art can solve the technical problem and achieve the desired technical effect. Furthermore, the term "coupled" encompasses any direct and indirect electrical connection. Therefore, if a first device is described as coupled to a second device, this means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device via other devices or connections. The following describes preferred embodiments of the present invention and is intended to illustrate the spirit of the invention rather than to limit its scope, which shall be determined by the claims.

[0026] The following description is intended to be the preferred embodiment of the present invention. These descriptions are intended to illustrate the general principles of the present invention and should not be used to limit the present invention. The scope of protection of the present invention should be determined based on the claims of the present invention.

[0027] Figure 1 1 is a schematic diagram illustrating a first multi-bit flip-flop (MBFF) with power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 100 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (i.e., N ≥ 2). The circuit layout of MBFF 100 can be a cell in a cell library used in integrated circuit (IC) design. Figure 1As shown, MBFF 100 has N data input terminals D1, D2, ..., D(N-1), and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, and N data output terminals Q1, Q2, ..., Q(N-1), and QN. Furthermore, MBFF 100 includes N connected flip-flops (FFs) 102_1, 102_2, ..., 102_(N-1), and 102_N to form an internal scan chain 104. This scan chain is formed by internally stitching flip-flops 102_1-102_N, as shown by the dotted lines. When MBFF 100 operates in normal mode, data input terminals D1-DN are used to receive data signals and are coupled to flip-flops 102_1-102_N, respectively. When the MBFF 100 operates in normal mode, data output terminals Q1-QN are used to output data output signals and are respectively coupled to flip-flops 102_1-102_N. Scan input terminal SI is used to receive external test signals. The external test signal at scan input terminal SI is transmitted through the internal scan chain 104, where the test signal of the current flip-flop 102_n (n≠1) is an internal test signal obtained from the previous flip-flop 102_(n-1). For example, the test signal INT2 of flip-flop 102_2 is obtained from flip-flop 102_1, the test signal INT3 of another flip-flop (not shown) is obtained from flip-flop 102_2, the test signal INT(N-1) of flip-flop 102_(N-1) is obtained from yet another flip-flop (not shown), and the test signal INTN of flip-flop 102_N is obtained from flip-flop 102_(N-1). Each of the flip-flops 102_1-102_(N-1) has a data output stage circuit (labeled as “L1”) 210_1, 210_2, ..., 210_(N-1) having a retention function that is enabled in a test mode and disabled in a normal mode.

[0028] When the MBFF 100 operates in normal mode, the data output stage circuit 210_1 generates and outputs a data output signal to data output terminal Q1, where the voltage level of the data output signal changes in response to the voltage level of the data signal at data input terminal D1. The data output stage circuit 210_2 generates and outputs a data output signal to data output terminal Q2, where the voltage level of the data output signal changes in response to the voltage level of the data signal at data input terminal D2. The data output stage circuit 210_(N-1) generates and outputs a data output signal to data output terminal Q(N-1), where the voltage level of the data output signal changes in response to the voltage level of the data signal at data input terminal D(N-1). Furthermore, the data output terminal QN is shared by both normal data transmission and test data transmission. Therefore, the flip-flop 102_N generates and outputs a data output signal to data output terminal QN, where the voltage level of the data output signal changes in response to the voltage level of the data signal at data input terminal DN.

[0029] In another case where the MBFF 100 operates in test mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the voltage level of the test signal at the scan input terminal SI. The data output stage circuit 210_2 generates and outputs a data output signal to the data output terminal Q2, wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the test signal INT2 obtained from the flip-flop 102_1. The data output stage circuit 210_(N-1) generates and outputs a data output signal to the data output terminal Q(N-1), wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the voltage level of the test signal INT(N-1) obtained from the previous stage flip-flop (not shown). In addition, the data output terminal QN is shared by both normal data transmission and test data transmission. Therefore, the flip-flop 102_N generates a scan output signal and outputs it to the data output terminal QN, wherein the voltage level of the scan output signal changes in response to the voltage level of the test signal INTN (which is obtained by the external test signal at the scan input terminal S1 being transmitted in the internal scan chain 104).

[0030] Figure 2 is a diagram illustrating a first circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 1 The MBFF 100 shown in the Figure 2In addition to the flip-flops 102_1-102_N, the MBFF 100 may further include a signal generating circuit 204 and a clock generating circuit 202. The signal generating circuit 204 receives the test enable signal STE (which is an external test enable signal) to generate another test enable signal STEB, which is inverse to the test enable signal STE. Figure 2 In the embodiment of FIG. 2 , the signal generating circuit 204 includes an inverter. In other embodiments, the signal generating circuit 204 may be implemented by any other circuit structure capable of receiving the test enable signal STE and generating the test enable signal STEB that is inverted from the test enable signal STE.

[0031] The clock generation circuit 110 receives a clock signal SCK (which is an external clock signal received via a clock terminal CK) and generates clock signals CLKB and CLK1 based on the clock signal SCK, wherein the clock signal CLKB is an inverse of the clock signal SCK and the clock signal CLK1 is an inverse of the clock signal CLKB. Figure 2 In the embodiment of FIG, the clock generation circuit 202 includes two inverters. In other embodiments, the clock generation circuit 202 may be implemented by any other circuit structure capable of receiving the clock signal SCK, generating a clock signal CLKB inverted from the clock signal SCK, and generating a clock signal CLK1 inverted from the clock signal CLKB.

[0032] Each of the flip-flops 102_1-102_(N-1) can have the same circuit structure. For example, flip-flop 102_1 is configured to output a data output signal S14 at a data output terminal Q1 of the MBFF 100 and includes a selection circuit 206_1, a latch circuit 208_1, and a data output stage circuit 210_1. Flip-flop 102_2 is configured to output a data output signal S24 at a data output terminal Q2 of the MBFF 100 and includes a selection circuit 206_2, a latch circuit 208_2, and a data output stage circuit 210_2. Regarding flip-flop 102_1, selection circuit 206_1 is configured to transmit data signal S10 at data input terminal D1 of MBFF 100 or test signal S11 at scan input terminal S1 of MBFF 100 to an output node of selection circuit 206_1 for use as input signal S12. Latch circuit 208_1 is coupled to the output node of selection circuit 206_1 and is configured to generate signal S13 based on input signal S12. Data output stage circuit 210_1 is configured to receive signal S13 and generate data output signal S14 based on signal S13. In this embodiment, selection circuit 206_1 may include an inverter and a transmission gate, each of which includes a P-type transistor (e.g., a P-channel metal oxide semiconductor (PMOS) transistor) and an N-type transistor (e.g., an N-channel metal oxide semiconductor (NMOS) transistor) and is controlled by test enable signals STE and STEB. In addition, the latch circuit 208_1 may include an inverter and a transmission gate, wherein each transmission gate includes a P-type transistor (e.g., a PMOS transistor) and an N-type transistor (e.g., an NMOS transistor), and is controlled by clock signals CLK1 and CLKB. Since the present invention does not focus on the circuit design of the selection circuit 206_1 and the latch circuit 208_1, a person with ordinary skill in the art should be able to easily understand Figure 2 The principles of the selection circuit 206_1 and the latch circuit 208_1 are shown. Therefore, for the sake of brevity, further description of the selection circuit 206_1 and the latch circuit 208_1 is omitted here.

[0033] The data output stage circuit 210_1 is equipped with a retention function that is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100. For example, when the MBFF 100 operates in the normal mode, the selection circuit 206_1 transmits the data signal S10 to the output node of the selection circuit 206_1 as the input signal S12, and the data output stage circuit 210_1 generates a data output signal S14 having a voltage level that changes in response to the voltage level of the data signal S10. Specifically, the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13, where the voltage level of the signal S13 changes in response to the voltage level of the data signal S10. When the MBFF 100 operates in test mode, the selection circuit 206_1 transmits the test signal S11 to the output node of the selection circuit 206_1 for use as the input signal S12, and the data output stage circuit 210_1 maintains the data output signal S14 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, while the voltage level of the signal S13 changes in response to the voltage level of the test signal S11.

[0034] In contrast to the first flip-flop 102_1, which receives the test signal S11 via the scan input terminal S1, the subsequent flip-flop 102_2 receives the test signal INT2 obtained from the previous flip-flop 102_1 (specifically, the latch circuit 208_1 of the flip-flop 102_1). Regarding the flip-flop 102_2, the selection circuit 206_2 is arranged to transmit the data signal S20 at the data input terminal D2 of the MBFF 100 or the test signal INT2 obtained from the latch circuit 208_1 to the output node of the selection circuit 206_2 as the input signal S22. The latch circuit 208_2 is coupled to the output node of the selection circuit 206_2 and is arranged to generate a signal S23 based on the input signal S22. The data output stage circuit 210_2 is arranged to receive the signal S23 and generate a data output signal S24 based on the signal S23. Similarly, the data output stage circuit 210_2 is equipped with the same retention function, which is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100 .

[0035] The final flip-flop 102_N is configured to generate an output signal SN4 at the data output terminal QN of the MBFF 100. It includes a selection circuit 206_N, a latch circuit 208_N, and an output stage circuit 212. Output stage circuit 212 is implemented using an inverter 213. The selection circuit 206_N is configured to transmit the data signal SN0 at the data input terminal DN of the MBFF 100 or the test signal INTN obtained from the previous stage flip-flop to the output node of the selection circuit 206_N for use as the input signal SN2. The latch circuit 208_N is coupled to the output node of the selection circuit 206_N and is configured to generate a signal SN3 based on the input signal SN2. The output stage circuit 212 is configured to receive the signal SN3 and generate an output signal SN4 based on the signal SN3. In this embodiment, the data output terminal QN is shared by both normal data transmission and test data transmission. When the MBFF 100 operates in normal mode, the selection circuit 206_N transmits the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as a data output signal, which has a voltage level that changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the output signal SN4 (data output signal) changes in response to the voltage level of the signal SN3, wherein the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0. When the MBFF 100 operates in test mode, the selection circuit 206_N transmits the test signal INTN to the output node of the selection circuit 206_N as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as a scan output signal, which has a voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the output signal SN4 (scan output signal) changes in response to the voltage level of the signal SN3 , which changes in response to the voltage level of the test signal INTN.

[0036] In this embodiment, each data output stage circuit having a retention function can be implemented using a NOR gate 211, wherein one input node of the NOR gate 211 is arranged to receive the output signal of the previous-stage latch circuit, the other input node of the NOR gate 211 is arranged to receive the test enable signal STE, and the output node of the NOR gate 211 is arranged to output the data output signal to the data output terminal of the MBFF 100. Taking the data output stage 210_1 as an example, one input node of the NOR gate 211 receives the signal S13 at the output node N1 of the latch circuit 208_1, the other input node of the NOR gate 211 receives the test enable signal STE, and the output node of the NOR gate 211 outputs the data output signal S14 to the data output terminal Q1 of the MBFF 100. When the MBFF 100 operates in normal mode (STE=0), the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13. Specifically, data output signal S14 is the inverse of signal S13, which is the inverse of data signal S10. When MBFF 100 operates in test mode (STE=1), the voltage level of data output signal S14 is maintained at a fixed voltage level (e.g., ground voltage) regardless of the voltage level of test signal S11. Specifically, the voltage level of data output signal S14 does not change in response to the voltage level of signal S13, which is the inverse of test signal S11.

[0037] Figure 2 The circuit structure shown is for illustrative purposes only and is not intended to limit the present invention. For example, the selection circuit can be implemented by any other circuit structure that can select one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure that can process the input signal obtained from the previous stage selection circuit to generate a signal and output the generated signal to the subsequent stage data output stage circuit with a hold function. For another example, the data output stage circuit with a hold function can be implemented by any other circuit structure that can maintain the data output signal at a fixed voltage level when the MBFF operates in test mode.

[0038] Figure 3is a diagram showing a first alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_(N-1) can be implemented using a data output stage circuit 300. The data output stage circuit 300 employs an OR gate 302, one of the input nodes of the OR gate 302 being coupled to the output node N1 of the previous stage latch circuit, the other input node of the OR gate 302 being arranged to receive a test enable signal STE, and the output node of the OR gate 302 being arranged to output a data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N-1). When the MBFF 100 operates in normal mode (STE=0), the voltage level of the data output signal generated by the OR gate 302 changes in response to the voltage at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STE=1), the data output signal generated by the OR gate 302 is maintained at a fixed voltage level (eg, the power supply voltage) regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

[0039] Figure 4 is a diagram showing a second alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_(N-1) can be implemented using a data output stage circuit 400. The data output stage circuit 400 employs a NAND gate 402, one of the input nodes of the NAND gate 402 being coupled to the output node N1 of the previous stage latch circuit, the other input node of the NAND gate 402 being arranged to receive a test enable signal STEB, and the output node of the NAND gate 402 being arranged to output the data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N-1). When the MBFF 100 operates in normal mode (STEB=1), the voltage level of the data output signal generated by the NAND gate 402 changes in response to the voltage of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STEB=0), the data output signal generated by the NAND gate 402 is maintained at a fixed voltage level (eg, the power supply voltage) regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

[0040] Figure 5is a diagram showing a third alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_(N-1) can be implemented using a data output stage circuit 500. The data output stage circuit 500 employs an AND gate 502, one of the input nodes of the AND gate 502 being coupled to the output node N1 of the previous stage latch circuit, the other input node of the AND gate 502 being arranged to receive a test enable signal STEB, and the output node of the AND gate 502 being arranged to output the data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N-1). When the MBFF 100 operates in normal mode (STEB=1), the voltage level of the data output signal generated by the AND gate 502 changes in response to the voltage of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STEB=0), the data output signal generated by the AND gate 502 is maintained at a fixed voltage level (eg, ground voltage) regardless of the signal voltage at the output node N1 of the previous stage latch circuit.

[0041] Figure 6 is a diagram illustrating a fourth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_(N-1) can be implemented using data output stage circuit 600. Data output stage circuit 600 includes PMOS transistors 602 and 604, an NMOS transistor 606, and an inverter 608. The gate of PMOS transistor 604 receives a test enable signal STEB, the source of PMOS transistor 604 is coupled to a reference voltage (e.g., a power supply voltage), and the drain of PMOS transistor 604 is coupled to the input node of inverter 608. PMOS transistor 602 and NMOS transistor 606 form a transmission gate. The gate of PMOS transistor 602 receives a test enable signal STE, the source of PMOS transistor 602 is coupled to the output node N1 of the previous latch circuit, and the drain of PMOS transistor 602 is coupled to the input node of inverter 608. A gate of the NMOS transistor 606 receives the test enable signal STEB, a drain of the NMOS transistor 606 is coupled to the output node N1 of the previous latch circuit, and a source of the NMOS transistor 606 is coupled to the input node of the inverter 608 .

[0042] When the MBFF 100 operates in normal mode (STE=0&STEB=1), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is enabled, and the PMOS transistor 604 is turned off, so that the voltage level of the data output signal at the data output terminal Qn (n is a positive integer from 1 to (N-1)) changes in response to the voltage level of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in test mode (STE=1&STEB=0), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is disabled, and the PMOS transistor 604 is turned on, so that the voltage level of the data output signal at the data output terminal Qn is maintained at a fixed voltage level (e.g., ground voltage) regardless of the voltage level of the signal at the output node N1 of the previous stage latch circuit.

[0043] Figure 7 7 is a diagram illustrating a fifth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_(N-1) can be implemented using data output stage circuit 700. Data output stage circuit 700 includes NMOS transistors 702 and 704, a PMOS transistor 706, and an inverter 708. The gate of NMOS transistor 704 receives a test enable signal STE, the source of NMOS transistor 704 is coupled to a reference voltage (e.g., ground), and the drain of NMOS transistor 704 is coupled to the input node of inverter 708. PMOS transistor 706 and NMOS transistor 702 form a transmission gate. The gate of PMOS transistor 706 receives the test enable signal STE, the source of PMOS transistor 706 is coupled to the output node N1 of the previous latch circuit, and the drain of PMOS transistor 706 is coupled to the input node of inverter 708. The gate of the NMOS transistor 702 receives the test enable signal STEB, the drain of the NMOS transistor 702 is connected to the output node N1 of the previous latch circuit, and the source of the NMOS transistor 702 is coupled to the input node of the inverter 708 .

[0044] When the MBFF 100 operates in normal mode (STE=0&STEB=1), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is enabled, and the NMOS transistor 704 is turned off, so that the voltage level of the data output signal at the data output terminal Qn (n is a positive integer from 1 to (N-1)) changes in response to the voltage level of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in test mode (STE=1&STEB=0), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is disabled, and the NMOS transistor 704 is turned on, so that the voltage level of the data output signal at the data output terminal Qn is maintained at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage level of the signal at the output node N1 of the previous latch circuit.

[0045] MBFF 100, which has N flip-flops 102_1-102_N connected to form an internal scan chain 104, is designed to have power-saving features. For example, when an external test signal S11 is received at scan input terminal S1 in test mode, MBFF 100 transmits external test signal S11 through internal scan chain 104 and generates scan output signal SN4, which is output from flip-flop 102_N to data output terminal QN. The voltage level of scan output signal SN4 changes in response to the voltage level of external test signal S11, while maintaining each of the (N-1) data output signals (output from flip-flops 102_1-102_(N-1) to output terminals Q1-Q(N-1), respectively) at a fixed voltage level regardless of the voltage level of external test signal S11. Because the (N-1) data output signals do not undergo signal level transitions in MBFF 100's test mode, power consumption of MBFF 100 and downstream combinational logic can be reduced.

[0046] exist Figure 1 and Figure 2 In the illustrated embodiment, MBFF 100 has a data output terminal QN shared by both normal data transmission and test data transmission. However, this is for illustrative purposes only and is not intended to limit the present invention. In alternative designs, the MBFF can be configured with an additional terminal that serves as a dedicated scan output terminal for outputting a scan output signal.

[0047] Figure 8 8 is a schematic diagram illustrating a second MBFF with power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 800 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (i.e., N ≥ 2). The circuit layout of MBFF 800 can be a cell in a cell library used in IC design. Figure 8 As shown, MBFF 800 has N data input terminals D1, D2, ..., D(N-1), and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, ..., Q(N-1), and QN, and a scan output terminal SQ. In addition, MBFF 800 includes N flip-flops (FFs) 802_1, 802_2, ..., 802_(N-1), and 802_N, which are connected to form an internal scan chain 104. The main difference between MBFF 100 and 800 is that the flip-flop 802_N of MBFF 800 has a scan output terminal SQ for outputting a scan output signal when MBFF 800 operates in test mode, and also has a data output stage circuit 210_N (labeled "L1") with a retention function, which is enabled in test mode and disabled in normal mode.

[0048] When the MBFF 800 operates in normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, wherein the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal DN. When the MBFF 800 operates in test mode, the scan output stage circuit (not shown) generates a scan output signal and outputs it to the scan output terminal SQ, wherein the voltage level of the scan output signal changes in response to the voltage level of the data signal at the data input terminal DN. In addition, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, wherein the voltage level of the data output signal is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal INTN obtained from the previous stage flip-flop 802_(N-1).

[0049] Figure 9 is a diagram illustrating a second circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 8 The MBFF 800 shown in the Figure 9 Each flip-flop 802_1-802_(N-1) can have the same Figure 2 For the sake of brevity, similar descriptions are omitted. Regarding the last flip-flop 802_N, it is arranged to output the data output signal SN4 at the data output terminal QN of the MBFF 800 and output the scan output signal SN5 at the scan output terminal SQ of the MBFF 800. Figure 9 As shown, the flip-flop 802_N includes a data output stage circuit 210_N, a scan output stage circuit 902, and the aforementioned selection circuit 206_N and latch circuit 208_N. Figure 2 As shown in the output stage circuit 212, the scan output stage circuit 902 is implemented by an inverter 213. Similar to the data output stage circuits 210_1 and 210_2, the data output stage circuit 210_N is equipped with a retention function that is enabled in the test mode of the MBFF 800 and disabled in the normal mode of the MBFF 800. When the MBFF 800 operates in the normal mode, the selection circuit 206_N transmits the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the data output stage circuit 210_N generates a data output signal SN4, the voltage level of which changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the data output signal SN4 changes in response to the voltage level of the signal SN3, wherein the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0. When the MBFF 800 operates in the test mode, the selection circuit 206_N transmits the test signal INTN to the output node of the selection circuit 206_N for use as the input signal SN2, and the data output stage circuit 210_N maintains the data output signal SN4 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal INTN. Specifically, the voltage level of the data output signal SN4 does not change in response to the voltage level of the signal SN3, while the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

[0050] Figure 9 The circuit structure shown is for illustrative purposes only and is not meant to limit the present invention. For example, the selection circuit can be implemented by any other circuit structure that can select one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure that can process the input signal obtained from the previous stage selection circuit to generate a signal and output the generated signal to the subsequent stage data output stage circuit with a holding function. For another example, the data output stage circuit with a holding function can be implemented by any other circuit structure that can maintain the data output signal at a fixed voltage level when the MBFF operates in test mode. Therefore, one or more of the flip-flops 802_1-802_N can be used Figure 3 The data output stage circuit 300 shown, Figure 4 The data output stage circuit 400 shown, Figure 5 The data output stage circuit 500 shown, Figure 6 The data output stage circuit 600 or Figure 7 The data output stage circuit 700 is shown to achieve this.

[0051] MBFF 800, which has N flip-flops 802_1-802_N connected to form an internal scan chain 104, is designed to have power-saving features. For example, when an external test signal S11 is received at scan input terminal S1, MBFF 800 passes the external test signal S11 through internal scan chain 104, generating a scan output signal SN4 that is output from flip-flop 802_N to scan output terminal SQ. The voltage level of scan output signal SN4 varies in response to the voltage level of external test signal S11, while maintaining the voltage level of each of the N data output signals (output from the N flip-flops 802_1-802_N to the N output terminals Q1-QN, respectively) at a fixed voltage level regardless of the external test signal S11. Because the N data output signals do not undergo signal level transitions during MBFF 800's test mode, power consumption of MBFF 800 and downstream combinational logic can be reduced.

[0052] exist Figure 9 In the illustrated embodiment, the scan output stage circuit 902 does not have a hold function. As a result, when the MBFF 800 operates in either normal mode or test mode, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3. In an alternative design, the MBFF can be configured to have a scan output stage circuit with a hold function.

[0053] Figure 10 1 is a schematic diagram illustrating a third MBFF with power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 1000 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (i.e., N ≥ 2). The circuit layout of MBFF 1000 can be a cell in a cell library used in IC design. Figure 10 As shown, MBFF 1000 has N data input terminals D1, D2, ..., D(N-1), and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, ..., Q(N-1), and QN, and a scan output terminal SQ. Furthermore, MBFF 1000 includes N flip-flops (FFs) 1002_1, 1002_2, ..., 1002_(N-1), 1002_N connected to form an internal scan chain 104. The main difference between MBFF 1000 and MBFF 800 is that the last flip-flop 1002_N of MBFF 1000 has a scan output stage circuit 1004 (labeled by "L2") with a retention function, which is enabled in normal mode and disabled in test mode.

[0054] When the MBFF 1000 operates in normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal DN; the scan output stage circuit 1004 generates and outputs a scan output signal to the scan output terminal SQ, where the voltage level of the scan output signal is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the data signal at the data input terminal DN.

[0055] When the MBFF 1000 operates in the test mode, the scan output stage circuit 1004 generates and outputs a scan output signal to the scan output terminal SQ, wherein the voltage level of the scan output signal varies in response to the voltage level of the test signal INTN obtained from the previous stage flip-flop 1002_(N-1). The data output stage circuit 210_N generates and outputs a data output signal to the data output terminal QN, wherein the voltage level of the data output signal is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal INTN obtained from the previous stage flip-flop 1002_(N-1).

[0056] Figure 11 is a diagram illustrating a third circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 10 The MBFF 1000 shown in the Figure 11 Each of the flip-flops 1002_1-1002_(N-1) may have Figure 2 or Figure 9Circuit structure shown. For the sake of brevity, further description is omitted. Regarding the last flip-flop 1002_N, it is arranged to output a data output signal SN4 at the data output terminal QN of the MBFF 1000 and output a scan output signal SN5 at the scan output terminal SQ of the MBFF 1000. The main difference between the flip-flops 802_N and 1002_N is that the flip-flop 1002_N adopts a scan output stage circuit 1004 with a holding function, which is enabled in the normal mode of the MBFF 1000 and disabled in the test mode of the MBFF 1000. When the MBFF 1000 operates in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N for use as the input signal SN2, and the scan output stage circuit 1004 generates a scan output signal SN5, which has a voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of scan output signal SN5 changes in response to the voltage level of signal SN3, wherein the voltage level of signal SN3 changes in response to the voltage level of test signal INTN. When MBFF 1000 operates in normal mode, selection circuit 206_N transmits data signal SN0 to the output node of selection circuit 206_N for use as input signal SN2, and scan output stage circuit 1004 maintains scan output signal SN5 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of data signal SN0. Specifically, the voltage level of scan output signal SN5 does not change in response to the voltage level of signal SN3, while the voltage level of signal SN3 changes in response to the voltage level of data signal SN0.

[0057] Like the data output stage circuits 210_1, 210_2, and 210_N, the scan output stage circuit 1004 is implemented by a NOR gate, wherein one input node of the NOR gate is arranged to receive the signal SN3 at the output node N2 of the latch circuit 208_N, the other input node of the NOR gate is arranged to receive the test enable signal STEB, and the output node of the NOR gate is arranged to output the scan output signal SN5 to the scan output terminal SQ of the MBFF 1000. Therefore, when the MBFF 1000 operates in normal mode (STEB=1), the retention function is enabled at the NOR gate. When the MBFF 1000 operates in test mode (STEB=0), the retention function is disabled at the NOR gate.

[0058] Figure 11The circuit structure shown is for illustrative purposes only and is not intended to limit the present invention. For example, the selection circuit can be implemented by any other circuit structure that can select one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure that can process the input signal obtained from the previous stage selection circuit to generate a signal and output the generated signal to the subsequent stage data output stage circuit with a holding function. For another example, the data output stage circuit with a holding function can be implemented by any other circuit structure that can maintain the data output signal at a fixed voltage level when the MBFF operates in test mode. For another example, the scan output stage circuit with a holding function can be implemented by any other circuit structure that can maintain the scan output signal at a fixed voltage level when the MBFF operates in normal mode.

[0059] Figure 12 1 is a diagram illustrating a first alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1004 can be implemented using a scan output stage circuit 1200. The scan output stage circuit 1200 employs an OR gate 1202, wherein one input node of the OR gate 1202 is coupled to the output node N2 of the latch circuit of the front end, the other input node of the OR gate 1202 is arranged to receive a test enable signal STEB, and the output node of the OR gate 1202 is arranged to output the scan output signal to the output terminal SQ of the scan MBFF 1000. When the MBFF 1000 operates in test mode (STEB=0), the voltage level of the scan output signal generated by the OR gate 1202 changes in response to the voltage of the signal at the output node N2 of the latch circuit of the front end. When the MBFF 1000 operates in normal mode (STEB=1), the scan output signal generated by the OR gate 1202 remains at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage of the signal at the output node N2 of the latch circuit of the front end.

[0060] Figure 131 is a diagram illustrating a second alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1004 can be implemented using a scan output stage circuit 1300. The scan output stage circuit 1300 employs a NAND gate 1302, wherein one input node of the NAND gate 1302 is coupled to the output node N2 of the previous stage latch circuit, the other input node of the NAND gate 1302 is arranged to receive a test enable signal STE, and the output node of the NAND gate 1302 is arranged to output a scan output signal to the scan terminal SQ of the MBFF 1000. When the MBFF 1000 operates in test mode (STE=1), the voltage level of the scan output signal generated by the NAND gate 1302 varies in response to the voltage of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in normal mode (STE=0), the scan output signal generated by the NAND gate 1302 remains at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage of the signal at the output node N2 of the previous stage latch circuit.

[0061] Figure 14 1 is a diagram illustrating a third alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1004 can be implemented using a scan output stage circuit 1400. The scan output stage circuit 1400 employs an AND gate 1402, wherein one input node of the AND gate 1402 is coupled to the output node N2 of the previous latch circuit, the other input node of the AND gate 1402 is arranged to receive a test enable signal STE, and the output node of the AND gate 1402 is arranged to output a scan output signal to the scan output terminal SQ of the MBFF 1000. When the MBFF 1000 operates in test mode (STE=1), the voltage level of the scan output signal generated by the AND gate 1402 changes in response to the voltage of the signal at the output node N2 of the previous latch circuit. When the MBFF 1000 operates in normal mode (STE=0), the scan output signal generated by the AND gate 1402 is maintained at a fixed voltage level (e.g., a ground voltage) regardless of the voltage of the signal at the output node N2 of the previous latch circuit.

[0062] Figure 15is a diagram illustrating a fourth alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, scan output stage circuit 1004 can be implemented using scan output stage circuit 1500. Scan output stage circuit 1500 includes PMOS transistors 1502 and 1504, an NMOS transistor 1506, and an inverter 1508. The gate of PMOS transistor 1504 receives a test enable signal STE, the source of PMOS transistor 1504 is coupled to a reference voltage (e.g., a power supply voltage), and the drain of PMOS transistor 1504 is coupled to the input node of inverter 1508. PMOS transistor 1502 and NMOS transistor 1506 form a transmission gate. The gate of PMOS transistor 1502 receives a test enable signal STEB, the source of PMOS transistor 1502 is coupled to the output node N2 of the previous stage latch circuit, and the drain of PMOS transistor 1502 is coupled to the input node of inverter 1508. A gate of the NMOS transistor 1506 receives a test enable signal STE, a drain of the NMOS transistor 1506 is connected to an output node N2 of a previous latch circuit, and a source of the NMOS transistor 1506 is coupled to an input node of the inverter 1508 .

[0063] When the MBFF 1000 operates in the test mode (STE=1&STEB=0), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is enabled, and the PMOS transistor 1504 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE=0&STEB=1), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is disabled, and the PMOS transistor 1504 is turned on, so that the voltage level of the scan output signal at the scan output terminal SQ is maintained at a fixed voltage level (e.g., a ground voltage) regardless of the voltage level of the signal at the output node N2 of the previous stage latch circuit.

[0064] Figure 161 is a diagram illustrating a fifth alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, scan output stage circuit 1004 can be implemented using scan output stage circuit 1600. Scan output stage circuit 1600 includes NMOS transistors 1602 and 1604, a PMOS transistor 1606, and an inverter 1608. The gate of NMOS transistor 1604 receives a test enable signal STEB, the source of NMOS transistor 1604 is coupled to a reference voltage (e.g., a ground voltage), and the drain of NMOS transistor 1604 is coupled to the input node of inverter 1608. PMOS transistor 1606 and NMOS transistor 1602 form a transmission gate. The gate of PMOS transistor 1606 receives the test enable signal STEB, the source of PMOS transistor 1606 is coupled to the output node N2 of the previous stage latch circuit, and the drain of PMOS transistor 1606 is coupled to the input node of inverter 1608. A gate of the NMOS transistor 1602 receives a test enable signal STE, a drain of the NMOS transistor 1602 is connected to an output node N2 of a previous latch circuit, and a source of the NMOS transistor 1602 is coupled to an input node of the inverter 1608 .

[0065] When the MBFF 1000 operates in the test mode (STE=1&STEB=0), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is enabled, and the NMOS transistor 1604 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE=0&STEB=1), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is disabled, and the NMOS transistor 1604 is turned on, so that the scan output signal at the scan output terminal SQ is maintained at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage level of the signal at the output node N2 of the previous stage latch circuit.

[0066] MBFF 1000, which has N flip-flops 1002_1-1002_N connected to form an internal scan chain 104, is designed to have power-saving features. For example, when MBFF 1000 receives an external test signal S11 at scan input terminal S1, MBFF 1000 transmits the external test signal S11 through internal scan chain 104, generating a scan output signal SN5 that is output from flip-flop 1002_N to scan output terminal SQ. The voltage level of scan output signal SN5 changes in response to the voltage level of external test signal S11, while maintaining each of the N data output signals (output from the N flip-flops 1002_1-1002_N to the N data output terminals Q1-QN) at a fixed voltage level regardless of the voltage level of external test signal S11. Because the N data output signals do not undergo signal level conversion during MBFF 1000's test mode, power consumption of MBFF 1000 and downstream combinational logic can be reduced.

[0067] In addition, when the data signal SN0 is received at the data input terminal DN, the MBFF 1000 generates a data output signal SN4 output from the flip-flop 1002_N to the data output terminal QN, and the voltage level of the data output signal SN4 changes in response to the voltage level of the data signal SN0, and maintains the scan output signal SN5 (output from the flip-flop 1002_N to the scan output terminal SQ) at a fixed voltage level regardless of the voltage level of the data signal SN0. Since the scan output signal does not undergo signal level conversion in the normal mode of the MBFF 1000, the power consumption of the MBFF 1000 and downstream logic can be reduced.

[0068] Although the present invention is disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A multi-bit trigger, characterized in that: include: a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops include a first flip-flop arranged to output a first data output signal at a first data output terminal of the multi-bit flip-flop, the first flip-flop comprising: a first selection circuit arranged to send a first data signal or a first test signal at a first data input terminal of the multi-bit flip-flop to an output node of the first selection circuit as a first input signal; a first latch circuit coupled to the output node of the first selection circuit, arranged to generate a first signal according to the first input signal; and a first data output stage circuit arranged to receive the first signal and generate the first data output signal according to the first signal; wherein, when the multi-bit flip-flop operates in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal; a signal generating circuit arranged to receive a first test enable signal at a test enable terminal of the multi-bit flip-flop to generate a second test enable signal inverted to the first test enable signal; The first data output stage circuit is further arranged to receive the first test enable signal and the second test enable signal which is inverted from the first test enable signal, and is controlled by the first test enable signal and the second test enable signal to generate the first data output signal according to the first signal.

2. The multi-bit trigger according to claim 1, wherein: The first test signal is an external test signal received at a scan input terminal of the multi-bit flip-flop.

3. The multi-bit trigger according to claim 1, wherein: The plurality of flip-flops further include a second flip-flop configured to output a second data output signal at a second data output terminal of the multi-bit flip-flop, the second flip-flop comprising: a second selection circuit arranged to send a second data signal or a second test signal at a second data input terminal of the multi-bit flip-flop to an output node of the second selection circuit as a second input signal; a second latch circuit coupled to the output node of the second selection circuit and arranged to generate the first test signal and a second signal according to the second input signal; and The second data output stage circuit is arranged to receive the second signal and generate the second data output signal according to the second signal.

4. The multi-bit trigger according to claim 3, wherein: When the multi-bit flip-flop operates in the test mode, the second selection circuit is arranged to transmit the second test signal to the output node of the second selection circuit for use as the second input signal, and the second data output stage circuit is arranged to maintain the second data output signal at a fixed voltage level regardless of the voltage level of the second test signal.

5. The multi-bit flip-flop according to claim 4, wherein: The second data output stage circuit is further arranged to receive a test enable signal at a test enable terminal of the multi-bit flip-flop and to be controlled by the test enable signal to generate the second data output signal according to the second signal.

6. The multi-bit flip-flop according to claim 4, wherein: The second data output stage circuit is further arranged to receive the second test enable signal and be controlled by the second test enable signal to generate the second data output signal according to the second signal.

7. The multi-bit flip-flop according to claim 4, wherein: The second data output stage circuit is further arranged to receive the first test enable signal and the second test enable signal which is inverted from the first test enable signal, and is controlled by the first test enable signal and the second test enable signal to generate the second data output signal according to the second signal.

8. The multi-bit flip-flop according to claim 1, wherein: The first latch circuit is further arranged to generate a second test signal according to the first input signal, and the plurality of flip-flops further include a second flip-flop arranged to output a second data output signal at a second data output terminal of the multi-bit flip-flop, the second flip-flop comprising: a second selection circuit arranged to transmit a second data signal at a second data input terminal of the multi-bit flip-flop or the second test signal obtained from the first latch circuit to an output node of the second selection circuit for use as a second input signal; a second latch circuit coupled to the output node of the second selection circuit and generating a second signal according to the second input signal; and The second data output stage circuit is arranged to receive the second signal and generate the second data output signal according to the second signal.

9. The multi-bit flip-flop according to claim 1, wherein: The first flip-flop is further arranged to output a scan-out signal at a scan-out terminal of the multi-bit flip-flop, and further comprising: A scan output stage circuit is arranged to receive the first signal and generate a scan output signal based on the first signal, wherein when the multi-bit flip-flop operates in the test mode, the scan output stage circuit is arranged to generate the scan output signal, and the voltage level of the scan output signal changes in response to the voltage level of the first test signal.

10. The multi-bit flip-flop according to claim 9, wherein: When the multi-bit flip-flop operates in normal mode, the first selection circuit is arranged to send the first data signal to the output node of the first selection circuit for use as the first input signal, and the scan output stage circuit is arranged to maintain the scan output signal at a fixed voltage level regardless of the voltage level of the first data signal.

11. The multi-bit flip-flop according to claim 10, wherein: The scan output stage circuit is further arranged to receive the first test enable signal and to be controlled by the first test enable signal to generate the scan output signal according to the first signal.

12. The multi-bit flip-flop according to claim 10, wherein: The scan output stage circuit is further arranged to receive the second test enable signal and to be controlled by the second test enable signal to generate the scan output signal according to the first signal.

13. The multi-bit flip-flop according to claim 10, wherein: The scan output stage circuit is further arranged to receive the first test enable signal and the second test enable signal which is inverted from the first test enable signal, and is controlled by the first test enable signal and the second test enable signal to generate the scan output signal according to the first signal.

14. A control method, characterized in that: Applied to a multi-bit flip-flop having N flip-flops connected to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, N data input terminals respectively coupled to the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, wherein N is a positive integer not less than 1, the control method comprising: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, passing the external test signal through the internal scan chain; generating a scan output signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; receiving a first test enable signal at a test enable terminal of the multi-bit flip-flop to generate a second test enable signal inverted from the first test enable signal; and maintaining each of (N-1) data output signals at a fixed voltage level regardless of the voltage level of the external test signal, wherein the (N-1) data output signals are respectively output from the remaining (N-1) flip-flops other than the scan output signal among the N flip-flops to the remaining (N-1) output terminals among the N data output terminals; Wherein, regardless of the voltage level of the external test signal, each of the (N-1) data output signals is maintained at a fixed voltage level, further comprising: Each of the (N-1) data output signals is maintained at the fixed voltage level under the control of the first test enable signal and the second test enable signal.

15. A control method, characterized in that: Applicable to a multi-bit flip-flop having N flip-flops connected to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, a scan output terminal coupled to another of the N flip-flops, N data input terminals respectively coupled to the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, wherein N is a positive integer not less than 1; the control method comprising: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, passing the external test signal through the internal scan chain; generating a scan-out signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan-out signal is output from the other flip-flop among the N flip-flops to the scan-out terminal; and receiving a first test enable signal at a test enable terminal of the multi-bit flip-flop to generate a second test enable signal inverted from the first test enable signal; and maintaining the N data output signals at a fixed voltage level regardless of the voltage level of the external test signal, wherein the N data output signals are respectively output from the N flip-flops to the N data output terminals of the multi-bit flip-flop; Wherein, the method of maintaining the N data output signals at a fixed voltage level regardless of the voltage level of the external test signal further comprises: The N data output signals are maintained at the fixed voltage level under the control of the first test enable signal and the second test enable signal.

16. The control method according to claim 15, characterized in that: The control method further includes: In response to receiving a data signal at a data input terminal coupled to the other flip-flop among the N flip-flops, the scan-out signal is maintained at a fixed voltage level regardless of a voltage level of the data signal.

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