Low-power-consumption programmable frequency divider based on improved D flip-flop

Abstract

The invention discloses a low-power-consumption programmable frequency divider based on an improved D flip-flop, and relates to the technical field of radio frequency integrated circuit design. The circuit comprises an input buffer circuit, a low-power-consumption 4 / 5 pre-frequency dividing circuit (DIV45), a low-power-consumption P frequency dividing circuit (DIVP) and a low-power-consumption S frequency dividing circuit (DIVS). In order to solve the problem that a traditional programmable frequency divider is large in power consumption, the DFFI type structure D flip-flop provided by the invention is adopted in a low-power-consumption 4 / 5 pre-frequency-dividing circuit (DIV45), and the DFFPS type structure D flip-flop provided by the invention is adopted in a low-power-consumption P frequency-dividing circuit (DIVP) and a low-power-consumption S frequency-dividing circuit (DIVS), so that the number of logic gates is reduced, and the power consumption of the frequency divider is optimized. Meanwhile, due to the reduction of the number of the logic gates, the frequency divider also has the advantages of small area, low cost and high practicability.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuit design, and in particular to a low-power programmable frequency divider based on an improved D flip-flop. Background Art

[0002] As a key module in RFIC frequency synthesizers, the performance of the frequency divider directly affects the accuracy and power consumption of the communication system. For example, in the Global Navigation Satellite System (GNSS) scenario, the frequency divider must meet the dual stringent requirements of wideband operation (1164MHz to 1610MHz) and low power consumption.

[0003] Patent application CN 112713896 A discloses an improved pulse-swallowing divider and method for use in a fractional-number phase-locked loop (PLL). The structure includes a 4 / 5 prescaler, a programmable counter, and a swallow counter. A load signal is used to synchronize the programmable counter and swallow counter. The internal 4 / 5 prescaler TSPC structure reduces power consumption. However, the circuitry of other key modules of the divider is not fully optimized, leaving room for further power consumption optimization.

[0004] As the demand for frequency synthesizers in low-power areas such as IoT sensors and portable devices expands, traditional frequency dividers face significant challenges in power consumption control. Summary of the Invention

[0005] In response to the above defects or improvement needs of the prior art, the present application provides a low-power programmable frequency divider based on an improved D flip-flop.

[0006] A low-power programmable frequency divider based on an improved D flip-flop, comprising an input buffer circuit, a low-power 4 / 5 pre-dividing circuit (DIV_45), a low-power P frequency dividing circuit (DIV_P), and a low-power S frequency dividing circuit (DIV_S);

[0007] The output end of the input buffer circuit is connected to the input end CLK of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45), the output end OUT_45 of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is respectively connected to the input end CLK of the low-power P frequency dividing circuit (DIV_P) and the input end CLK of the low-power S frequency dividing circuit (DIV_S), the output end RELOAD of the low-power P frequency dividing circuit (DIV_P) is connected to the input end RELOAD of the low-power S frequency dividing circuit (DIV_S), and the output end S_OUT of the low-power S frequency dividing circuit (DIV_S) is connected to the input end MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45);

[0008] When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is at a low level, the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) realizes a 5-frequency dividing function;

[0009] When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is at a high level, the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) realizes a 4-frequency dividing function.

[0010] Preferably, the input buffer circuit includes: 3 inverters (INV1 to INV3);

[0011] The output end of the first inverter (INV1) is connected to the input end of the second inverter (INV2), and the input end of the third inverter (INV3) is connected to the output end of the second inverter (INV2).

[0012] Preferably, the low-power 4 / 5 pre-scaling circuit (DIV_45) includes: 3 D flip-flops (DFF1 to DFF3), 2 inverters (INV5, INV6);

[0013] The second D flip-flop (DFF2) adopts a DFF_I type structure, and the first D flip-flop (DFF1) and the third D flip-flop (DFF3) adopt a DFF type structure;

[0014] An input terminal CLK of the first D flip-flop (DFF1) is connected to an input terminal CLK of the low-power 4 / 5 pre-scaling circuit (DIV_45), an input terminal CLK of the second D flip-flop (DFF2) is connected to an input terminal CLK of the low-power 4 / 5 pre-scaling circuit (DIV_45), and an input terminal MC of the second D flip-flop (DFF2) is connected to an input terminal MC of the low-power 4 / 5 pre-scaling circuit (DIV_45);

[0015] The input end of the sixth inverter (INV6) is connected to the output end of the fifth inverter (INV5), and the output end of the sixth inverter (INV6) is connected to the output end OUT_45 of the low-power 4 / 5 pre-scaling circuit (DIV_45);

[0016] An input terminal D of the first D flip-flop (DFF1) is connected to an input terminal D1 of the second D flip-flop (DFF2) and an output terminal QN of the second D flip-flop (DFF2); an output terminal Q of the first D flip-flop (DFF1) is connected to an input terminal D3 of the second D flip-flop (DFF2); an input terminal D2 of the second D flip-flop (DFF2) is connected to an output terminal Q of the third D flip-flop (DFF3); an output terminal Q of the second D flip-flop (DFF2) is connected to an input terminal CLK of the third D flip-flop (DFF3); an input terminal D of the third D flip-flop (DFF3) is connected to an output terminal QN of the third D flip-flop (DFF3); and an output terminal Q of the third D flip-flop (DFF3) is connected to an input terminal of the fifth inverter (INV5).

[0017] Preferably, the DFF structure includes: 4 PMOS transistors (MP1-MP4), 5 NMOS transistors (MN1-MN5), and 1 inverter (INV4);

[0018] The gate of the first PMOS transistor (MP1) is connected to the gate of the first NMOS transistor (MN1), and the connection point is coupled to the input terminal D of the DFF structure;

[0019] The gate of the second PMOS transistor (MP2) is respectively connected to the gate of the third PMOS transistor (MP3), the gate of the third NMOS transistor (MN3), and the gate of the fourth NMOS transistor (MN4), and the connection point is coupled to the input terminal CLK of the DFF structure;

[0020] The drain of the fourth PMOS transistor (MP4) is respectively connected to the drain of the fourth NMOS transistor (MN4) and the input end of the fourth inverter (INV4), and the connection point is coupled to the output end QN of the DFF structure;

[0021] The output terminal of the fourth inverter (INV4) is connected to the output terminal Q of the DFF structure;

[0022] The source of the first PMOS tube (MP1) is respectively connected to the source of the third PMOS tube (MP3), the source of the fourth PMOS tube (MP4), and the power supply VDD; the drain of the first PMOS tube (MP1) is respectively connected to the source of the second PMOS tube (MP2); the drain of the second PMOS tube (MP2) is respectively connected to the drain of the first NMOS tube (MN1) and the gate of the second NMOS tube (MN2); the source of the first NMOS tube (MN1) is respectively connected to the source of the third NMOS tube (MP3), the source of the fourth PMOS tube (MP4), and the power supply VDD; the drain of the first PMOS tube (MP1) is respectively connected to the source of the second PMOS tube (MP2); the drain of the second PMOS tube (MP2) is respectively connected to the drain of the first NMOS tube (MN1) and the gate of the second NMOS tube (MN2); The source of the S transistor (MN3), the source of the fifth NMOS transistor (MN5), and the ground GND are connected; the drain of the third PMOS transistor (MP3) is respectively connected to the drain of the second NMOS transistor (MN2), the gate of the fourth PMOS transistor (MP4), and the gate of the fifth NMOS transistor (MN5); the source of the second NMOS transistor (MN2) is connected to the drain of the third NMOS transistor (MN3); and the source of the fourth NMOS transistor (MN4) is connected to the drain of the fifth NMOS transistor (MN5).

[0023] Preferably, the DFF_I type structure includes: 7 PMOS transistors (MP5-MP11), 8 NMOS transistors (MN6-MN13), and 1 inverter (INV7);

[0024] The gate of the fifth PMOS transistor (MP5) is connected to the gate of the ninth NMOS transistor (MN9), and the connection point is coupled to the input terminal D1 of the DFF_I type structure;

[0025] The gate of the seventh PMOS transistor (MP7) is connected to the gate of the eighth NMOS transistor (MN8), and the connection point is coupled to the input terminal D2 of the DFF_I type structure;

[0026] The gate of the sixth PMOS transistor (MP6) is connected to the gate of the seventh NMOS transistor (MN7), and the connection point is coupled to the input terminal D3 of the DFF_I type structure;

[0027] The gate of the eighth PMOS transistor (MP8) is connected to the gate of the sixth NMOS transistor (MN6), and the connection point is coupled to the input terminal MC of the DFF_I type structure;

[0028] The gate of the ninth PMOS transistor (MP9) is respectively connected to the gate of the tenth PMOS transistor (MP10), the gate of the eleventh NMOS transistor (MN11), and the gate of the twelfth NMOS transistor (MN12), and the connection point is coupled to the input terminal CLK of the DFF_I type structure;

[0029] The drain of the twelfth NMOS transistor (MN12) is respectively connected to the drain of the eleventh PMOS transistor (MP11) and the input end of the seventh inverter (INV7), and the connection point is coupled to the input end QN of the DFF_I type structure;

[0030] The output terminal of the seventh inverter (INV7) is connected to the output terminal Q of the DFF_I type structure;

[0031] The source of the fifth PMOS tube (MP5) is respectively connected to the source of the sixth PMOS tube (MP6), the source of the tenth PMOS tube (MP10), the source of the eleventh PMOS tube (MP11), and the power supply VDD; the drain of the fifth PMOS tube (MP5) is respectively connected to the drain of the eighth PMOS tube (MP8) and the source of the ninth PMOS tube (MP9); the drain of the sixth PMOS tube (MP6) is connected to the source of the seventh PMOS tube (MP7); the drain of the seventh PMOS tube (MP7) is connected to the source of the eighth PMOS tube (MP8); the drain of the ninth PMOS tube (MP9) is respectively connected to the gate of the tenth NMOS tube (MN10), the drain of the sixth NMOS tube (MN6), the drain of the seventh NMOS tube (MN7), the drain of the eighth NMOS tube (MN8), and the drain of the ninth PMOS tube (MP9). The drain of the ninth NMOS transistor (MN9) is connected to the source of the sixth NMOS transistor (MN6), the source of the seventh NMOS transistor (MN7), and the source of the eighth NMOS transistor (MN8), respectively; the source of the ninth NMOS transistor (MN9) is connected to the source of the eleventh NMOS transistor (MN11), the source of the thirteenth NMOS transistor (MN11), and the ground GND, respectively; the drain of the tenth PMOS transistor (MP10) is connected to the drain of the tenth NMOS transistor (MN10), the gate of the eleventh PMOS transistor (MP11), and the gate of the thirteenth NMOS transistor (MN13), respectively; the source of the tenth NMOS transistor (MN10) is connected to the drain of the eleventh NMOS transistor (MN11), and the source of the twelfth NMOS transistor (MN12) is connected to the drain of the thirteenth NMOS transistor (MN13).

[0032] Preferably, the low-power P frequency divider circuit (DIV_P) includes: 6 D flip-flops (DFF4-DFF9), 3 inverters (INV8-INV10), 2 three-input NOR gates (NOR3_1, NOR3_2), and 1 two-input NAND gate (NAND2_1);

[0033] The input terminal P_DIV<4:0> of the low power consumption P frequency dividing circuit (DIV_P) includes: P_DIV <4> 、P_DIV <3> 、P_DIV <2> 、P_DIV <1> 、P_DIV <0> ;

[0034] The six D flip-flops (DFF4 to DFF9) all adopt a DFF_PS structure;

[0035] The input terminal CLK of the fifth D flip-flop (DFF5) is connected to the input terminal CLK of the fourth D flip-flop (DFF4), and the connection point is coupled to the input terminal CLK of the low-power P frequency dividing circuit (DIV_P);

[0036] The input terminal D of the fifth D flip-flop (DFF5) is connected to the output terminal QN of the fifth D flip-flop (DFF5), and the input terminal A of the fifth D flip-flop (DFF5) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <0> connect;

[0037] An input terminal S of the fifth D flip-flop (DFF5) is respectively connected to an input terminal S of the sixth D flip-flop (DFF6), an input terminal S of the seventh D flip-flop (DFF7), an input terminal S of the eighth D flip-flop (DFF8), an input terminal S of the ninth D flip-flop (DFF9), and an output terminal of a ninth inverter (INV9), and the connection point is coupled to an output terminal RELOAD of the low-power P frequency divider circuit (DIV_P);

[0038] The output terminal Q of the fifth D flip-flop (DFF5) is connected to the input terminal CLK of the sixth D flip-flop (DFF6), and the connection line is P_Q <0> ;

[0039] The input terminal D of the sixth D flip-flop (DFF6) is connected to the output terminal QN of the sixth D flip-flop (DFF6), and the input terminal A of the sixth D flip-flop (DFF6) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <1> connect;

[0040] The output terminal Q of the sixth D flip-flop (DFF6) is connected to the input terminal CLK of the seventh D flip-flop (DFF7), and the connection line is P_Q <1> ;

[0041] The input terminal D of the seventh D flip-flop (DFF7) is connected to the output terminal QN of the seventh D flip-flop (DFF7), and the input terminal A of the seventh D flip-flop (DFF7) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <2> connect;

[0042] The output terminal Q of the seventh D flip-flop (DFF7) is connected to the input terminal CLK of the eighth D flip-flop (DFF8), and the connection line is P_Q <2> ;

[0043] The input terminal D of the eighth D flip-flop (DFF8) is connected to the output terminal QN of the eighth D flip-flop (DFF8), and the input terminal A of the eighth D flip-flop (DFF8) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <3> connect;

[0044] The output terminal Q of the eighth D flip-flop (DFF8) is connected to the input terminal CLK of the ninth D flip-flop (DFF9), and the connection line is P_Q <3> ;

[0045] The input terminal D of the ninth D flip-flop (DFF9) is connected to the output terminal QN of the ninth D flip-flop (DFF9), and the input terminal A of the ninth D flip-flop (DFF9) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <4> The output terminal Q of the ninth D flip-flop (DFF9) is connected to P_Q <4> ;

[0046] The input terminal of the eighth inverter (INV8) is connected to the connection P_Q <1> connect;

[0047] The three input terminals of the first three-input NOR gate (NOR3_1) are connected to the wiring P_Q <0> , the output terminal of the eighth inverter (INV8), the connection P_Q <2> connect;

[0048] The three input terminals of the second three-input NOR gate (NOR3_2) are connected to the wiring P_Q <3> , the wiring P_Q <4> , ground GND connection;

[0049] Two input terminals of the first two-input NAND gate (NAND2_1) are respectively connected to the output terminal of the first three-input NOR gate (NOR3_1) and the output terminal of the second three-input NOR gate (NOR3_2);

[0050] An input terminal D of the fourth D flip-flop (DFF4) is connected to the output terminal of the first two-input NAND gate (NAND2_1), an input terminal A of the fourth D flip-flop (DFF4) is connected to the ground GND, an input terminal S of the fourth D flip-flop (DFF4) is connected to the ground GND, and an output terminal Q of the fourth D flip-flop (DFF4) is connected to the input terminal of the ninth inverter (INV9) and the input terminal of the tenth inverter (INV10), respectively;

[0051] The output end of the tenth inverter (INV10) is connected to the output end P_OUT of the low-power consumption P frequency dividing circuit (DIV_P).

[0052] Preferably, the low-power S-dividing circuit (DIV_S) includes: 7 D flip-flops (DFF10-DFF16), 4 inverters (INV11-INV14), 2 three-input NOR gates (NOR3_3, NOR3_4), and 1 two-input NAND gate (NAND2_2);

[0053] The input terminal S_DIV<3:0> of the low power consumption S frequency dividing circuit (DIV_S) includes: S_DIV <3> 、S_DIV <2> 、S_DIV <1> 、S_DIV <0> ;

[0054] The seven D flip-flops (DFF10 to DFF16) all adopt a DFF_PS structure;

[0055] The input terminal CLK of the twelfth D flip-flop (DFF12) is connected to the input terminal CLK of the tenth D flip-flop (DFF10), and the connection point is coupled to the input terminal CLK of the low-power S frequency dividing circuit (DIV_S);

[0056] The input terminal D of the twelfth D flip-flop (DFF12) is connected to the output terminal QN of the twelfth D flip-flop (DFF12), and the input terminal A of the twelfth D flip-flop (DFF12) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <0> connect;

[0057] An input terminal S of the twelfth D flip-flop (DFF12) is respectively connected to an input terminal S of the thirteenth D flip-flop (DFF13), an input terminal S of the fourteenth D flip-flop (DFF14), an input terminal S of the fifteenth D flip-flop (DFF15), and an input terminal S of the sixteenth D flip-flop (DFF16), and the connection lines are RELOAD_P;

[0058] The output terminal Q of the twelfth D flip-flop (DFF12) is connected to the input terminal CLK of the thirteenth D flip-flop (DFF13), and the connection line is S_Q <0> ;

[0059] The input terminal D of the thirteenth D flip-flop (DFF13) is connected to the output terminal QN of the thirteenth D flip-flop (DFF13), and the input terminal A of the thirteenth D flip-flop (DFF13) is connected to the input terminal S_DIV of the low-power S frequency dividing circuit (DIV_S). <1> connect;

[0060] The output terminal Q of the thirteenth D flip-flop (DFF13) is connected to the input terminal CLK of the fourteenth D flip-flop (DFF14), and the connection line is S_Q <1> ;

[0061] The input terminal D of the fourteenth D flip-flop (DFF14) is connected to the output terminal QN of the fourteenth D flip-flop (DFF14), and the input terminal A of the fourteenth D flip-flop (DFF14) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <2> connect;

[0062] The output terminal Q of the fourteenth D flip-flop (DFF14) is connected to the input terminal CLK of the fifteenth D flip-flop (DFF15), and the connection line is S_Q <2> ;

[0063] The input terminal D of the fifteenth D flip-flop (DFF15) is connected to the output terminal QN of the fifteenth D flip-flop (DFF15), and the input terminal A of the fifteenth D flip-flop (DFF15) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <3> connect;

[0064] The output terminal Q of the fifteenth D flip-flop (DFF15) is connected to the input terminal CLK of the sixteenth D flip-flop (DFF16), and the connection line is S_Q <3> ;

[0065] The input terminal D of the sixteenth D flip-flop (DFF16) is connected to the output terminal QN of the sixteenth D flip-flop (DFF16), the input terminal A of the sixteenth D flip-flop (DFF16) is connected to the ground GND, and the wiring of the output terminal Q of the sixteenth D flip-flop (DFF16) is S_Q <4> ;

[0066] The input end of the eleventh inverter (INV11) is connected to the input end RELOAD of the low-power S-frequency dividing circuit (DIV_S), and the output end of the eleventh inverter (INV11) is connected to the input end of the twelfth inverter (INV12);

[0067] The output terminal of the twelfth inverter (INV12) is connected to RELOAD_P;

[0068] The input terminal of the thirteenth inverter (INV13) is connected to the connection S_Q <1> connect;

[0069] The three input terminals of the third three-input NOR gate (NOR3_3) are connected to the wiring S_Q <0> , the output terminal of the thirteenth inverter (INV13), the connection S_Q <2> connect;

[0070] The three input terminals of the fourth three-input NOR gate (NOR3_4) are connected to the wiring S_Q <3> 、The connection S_Q <4> , ground GND connection;

[0071] Two input terminals of the second two-input NAND gate (NAND2_2) are respectively connected to the output terminal of the third three-input NOR gate (NOR3_3) and the output terminal of the fourth three-input NOR gate (NOR3_4);

[0072] an input terminal D of the tenth D flip-flop (DFF10) connected to the output terminal of the second two-input NAND gate (NAND2_2), an input terminal A of the tenth D flip-flop (DFF10) connected to ground GND, an input terminal S of the tenth D flip-flop (DFF10) connected to ground GND, and an output terminal Q of the tenth D flip-flop (DFF4) connected to the input terminal of the fourteenth inverter (INV14);

[0073] An input terminal D of the eleventh D flip-flop (DFF11) is connected to an output terminal QN of the eleventh D flip-flop (DFF11), an input terminal CLK of the eleventh D flip-flop (DFF11) is connected to the output terminal of the fourteenth inverter (INV14), an input terminal A of the eleventh D flip-flop (DFF11) is connected to the ground GND, an input terminal S of the eleventh D flip-flop (DFF11) is connected to the wiring RELOAD_P, and an output terminal Q of the eleventh D flip-flop (DFF11) is connected to an output terminal S_OUT of the low-power S-dividing circuit (DIV_S).

[0074] Preferably, the DFF_PS type structure includes: 8 PMOS transistors (MP12 to MP19), 11 NMOS transistors (MN6 to MN13), and 3 inverters (INV15 to INV17);

[0075] The input end of the fifteenth inverter (INV15) is respectively connected to the gate of the twelfth PMOS transistor (MP12), the gate of the sixteenth NMOS transistor (MN16), the gate of the fifteenth PMOS transistor (MP15), the gate of the twenty-first NMOS transistor (MN21), and the gate of the twenty-third NMOS transistor (MN23), and the connection point is coupled to the input end S of the DFF_PS structure;

[0076] The gate of the thirteenth PMOS transistor (MP13) is connected to the gate of the fourteenth NMOS transistor (MN14), and the connection point is coupled to the input terminal D of the DFF_PS structure;

[0077] The gate of the fourteenth PMOS transistor (MP14) is respectively connected to the gate of the sixteenth PMOS transistor (MP16), the gate of the eighteenth NMOS transistor (MN18), and the gate of the twenty-second NMOS transistor (MN22), and the connection point is coupled to the input terminal CLK of the DFF_PS structure;

[0078] The output end of the fifteenth inverter (INV15) is respectively connected to the gate of the fifteenth NMOS transistor (MN15), the gate of the nineteenth NMOS transistor (MN19), and the gate of the seventeenth PMOS transistor (MP17); the source of the twelfth PMOS transistor (MP12) is respectively connected to the source of the fifteenth PMOS transistor (MP15), the source of the seventeenth PMOS transistor (MP17), and the source of the nineteenth PMOS transistor (MP19); the drain of the twelfth PMOS transistor (MP12) is connected to the source of the thirteenth PMOS transistor (MP13); and the drain of the fourteenth PMOS transistor (MP14) is connected to the source of the thirteenth PMOS transistor (MP13). The source of the 13th PMOS tube (MP13) is connected to the drain of the 14th PMOS tube (MP14), the drain of the 14th NMOS tube (MN14), the drain of the 16th NMOS tube (MN16), and the gate of the 17th NMOS tube (MN17), the drain of the 15th NMOS tube (MN15) is connected to the source of the 14th NMOS tube (NM14), the source of the 15th NMOS tube (MN15) is connected to the source of the 16th NMOS tube (MN16), the source of the 19th NMOS tube (MN19), and the gate of the 21st NMOS tube (MN17), respectively. The source of the NMOS transistor (MN21), the source of the twenty-fourth NMOS transistor (MN24), and the ground GND are connected; the source of the sixteenth PMOS transistor (MP16) is connected to the drain of the fifteenth PMOS transistor (MP15); the drain of the sixteenth PMOS transistor (MP16) is respectively connected to the drain of the eighteenth PMOS transistor (MP18), the drain of the seventeenth NMOS transistor (MN17), the drain of the twentieth NMOS transistor (MN20), the gate of the nineteenth PMOS transistor (MP19), and the gate of the twenty-fourth NMOS transistor (MN24); the eighteenth NMOS transistor (MN The drain of the 20th NMOS transistor (MN20) is connected to the drain of the 21st NMOS transistor (MN21), and the drain of the 24th NMOS transistor (MN24) is connected to the source of the 22nd NMOS transistor (MN22) and the source of the 23rd NMOS transistor (MN23);

[0079] The drain of the nineteenth PMOS transistor (MP19) is respectively connected to the drain of the twenty-second NMOS transistor (MN22), the drain of the twenty-third NMOS transistor (MN23), and the input end of the seventeenth inverter (INV17), and the connection point is coupled to the output end QN of the DFF_PS structure;

[0080] The output terminal of the seventeenth inverter (INV17) is connected to the output terminal Q of the DFF_PS structure.

[0081] In general, the above technical solutions conceived by the present application have the following beneficial effects compared with the existing technology: 1) The DFF_I type structure D flip-flop proposed in the present application is used in the low-power 4 / 5 pre-dividing circuit (DIV_45), thereby reducing the number of combinational logic gates and thus optimizing power consumption; 2) The DFF_PS type structure D flip-flop proposed in the present application is used in the low-power P dividing circuit (DIV_P) and the low-power S dividing circuit (DIV_S), thereby reducing the number of combinational logic gates and thus optimizing power consumption; 3) Thanks to the reduction in the number of logic gates, the low-power programmable divider based on the improved D flip-flop provided by the present application also has the advantages of small area, low cost and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0083] Figure 1 This is a structural diagram of a low-power programmable frequency divider based on an improved D flip-flop provided in this application.

[0084] Figure 2 This is a specific circuit diagram of a low-power 4 / 5 pre-dividing circuit (DIV_45) of a low-power programmable divider based on an improved D flip-flop provided in this application.

[0085] Figure 3 This is a specific circuit diagram of a low-power P-divider circuit (DIV_P) based on a low-power programmable divider of an improved D flip-flop provided in this application.

[0086] Figure 4 This is a specific circuit diagram of a low-power S-divider circuit (DIV_S) based on a low-power programmable divider of an improved D flip-flop provided in this application.

[0087] Figure 5This is a specific circuit diagram of a DFF_PS type structure of a low-power programmable frequency divider based on an improved D flip-flop provided in this application.

[0088] Figure 6 This is a specific circuit diagram of the traditional 4 / 5 pre-scaling circuit provided in this application.

[0089] Figure 7 This is a specific circuit diagram of the traditional P frequency division circuit provided in this application.

[0090] Figure 8 This is a specific circuit diagram of the traditional S-frequency dividing circuit provided in this application.

[0091] Figure 9 This is a specific circuit diagram of a traditional counting unit provided in this application.

[0092] Figure 10 This application provides a power consumption comparison chart of a low-power programmable frequency divider based on an improved D flip-flop and a traditional programmable frequency divider within the GNSS frequency range when the total division ratio M is 71. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0095] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0096] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connect," "fixed," "coupled," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified or limited. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0097] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0098] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the terms used in this specification include any and all combinations of the relevant listed items.

[0099] This application proposes two improved D flip-flop structures, namely DFF_I structure and DFF_PS structure. Among them, the DFF_I structure is defined as follows:

[0100] Figure 2 This is a specific circuit diagram of a low-power 4 / 5 pre-scaling circuit DIV_45 of a low-power programmable frequency divider based on an improved D flip-flop provided by this application. Figure 2 As shown, the DFF_I type structure includes: 7 PMOS transistors MP5 to MP11, 8 NMOS transistors MN6 to MN13, and 1 inverter INV7;

[0101] The gate of the fifth PMOS transistor MP5 is connected to the gate of the ninth NMOS transistor MN9, and the connection point is coupled to the input terminal D1 of the DFF_I type structure;

[0102] The gate of the seventh PMOS transistor MP7 is connected to the gate of the eighth NMOS transistor MN8, and the connection point is coupled to the input terminal D2 of the DFF_I type structure;

[0103] The gate of the sixth PMOS transistor MP6 is connected to the gate of the seventh NMOS transistor MN7, and the connection point is coupled to the input terminal D3 of the DFF_I type structure;

[0104] The gate of the eighth PMOS transistor MP8 is connected to the gate of the sixth NMOS transistor MN6, and the connection point is coupled to the input terminal MC of the DFF_I type structure;

[0105] The gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10, the gate of the eleventh NMOS transistor MN11, and the gate of the twelfth NMOS transistor MN12, respectively, and the connection points are coupled to the input terminal CLK of the DFF_I type structure;

[0106] The drain of the twelfth NMOS transistor MN12 is connected to the drain of the eleventh PMOS transistor MP11 and the input terminal of the seventh inverter INV7, respectively, and the connection point is coupled to the input terminal QN of the DFF_I type structure;

[0107] The output end of the seventh inverter INV7 is connected to the output end Q of the DFF_I type structure;

[0108] The source of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, the source of the tenth PMOS transistor MP10, the source of the eleventh PMOS transistor MP11, and the power supply VDD, respectively. The drain of the fifth PMOS transistor MP5 is connected to the drain of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9, respectively. The drain of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP7, the drain of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8, and the drain of the ninth PMOS transistor MP9 is connected to the gate of the tenth NMOS transistor MN10, the drain of the sixth NMOS transistor MN6, the drain of the seventh NMOS transistor MN7, and the drain of the eighth NMOS transistor MN8, respectively. The drain of the ninth NMOS transistor MN9 is connected to the source of the sixth NMOS transistor MN6, the source of the seventh NMOS transistor MN7, and the source of the eighth NMOS transistor MN8, respectively. The source of the ninth NMOS transistor MN9 is connected to the source of the eleventh NMOS transistor MN11, the source of the thirteenth NMOS transistor MN11, and the ground GND, respectively. The drain of the tenth PMOS transistor MP10 is connected to the drain of the tenth NMOS transistor MN10, the gate of the eleventh PMOS transistor MP11, and the gate of the thirteenth NMOS transistor MN13, respectively. The source of the tenth NMOS transistor MN10 is connected to the drain of the eleventh NMOS transistor MN11, and the source of the twelfth NMOS transistor MN12 is connected to the drain of the thirteenth NMOS transistor MN13.

[0109] Figure 5 This is a specific circuit diagram of a DFF_PS type structure of a low-power programmable frequency divider based on an improved D flip-flop provided by this application. Figure 5 As shown, the DFF_PS type structure includes: 8 PMOS transistors MP12 to MP19, 11 NMOS transistors MN6 to MN13, and 3 inverters INV15 to INV17;

[0110] An input terminal of the fifteenth inverter INV15 is respectively connected to the gate of the twelfth PMOS transistor MP12, the gate of the sixteenth NMOS transistor MN16, the gate of the fifteenth PMOS transistor MP15, the gate of the twenty-first NMOS transistor MN21, and the gate of the twenty-third NMOS transistor MN23, and the connection point is coupled to the input terminal S of the DFF_PS structure;

[0111] The gate of the thirteenth PMOS transistor MP13 is connected to the gate of the fourteenth NMOS transistor MN14, and the connection point is coupled to the input terminal D of the DFF_PS structure;

[0112] The gate of the fourteenth PMOS transistor MP14 is connected to the gate of the sixteenth PMOS transistor MP16, the gate of the eighteenth NMOS transistor MN18, and the gate of the twenty-second NMOS transistor MN22, respectively, and the connection points are coupled to the input terminal CLK of the DFF_PS structure;

[0113] The output end of the fifteenth inverter INV15 is respectively connected to the gate of the fifteenth NMOS transistor MN15, the gate of the nineteenth NMOS transistor MN19, and the gate of the seventeenth PMOS transistor MP17; the source of the twelfth PMOS transistor MP12 is respectively connected to the source of the fifteenth PMOS transistor MP15, the source of the seventeenth PMOS transistor MP17, and the source of the nineteenth PMOS transistor MP19; the drain of the twelfth PMOS transistor MP12 is connected to the source of the thirteenth PMOS transistor MP13; and the fourteenth PMOS transistor MP The source of the PMOS transistor MP14 is connected to the drain of the thirteenth PMOS transistor MP13, the drain of the fourteenth PMOS transistor MP14 is respectively connected to the drain of the fourteenth NMOS transistor MN14, the drain of the sixteenth NMOS transistor MN16, and the gate of the seventeenth NMOS transistor MN17, the drain of the fifteenth NMOS transistor MN15 is respectively connected to the source of the fourteenth NMOS transistor NM14, the source of the fifteenth NMOS transistor MN15 is respectively connected to the source of the sixteenth NMOS transistor MN16, the source of the nineteenth NMOS transistor MN19, and the gate of the twenty-first NMOS transistor MN17. The source of the NMOS transistor MN21, the source of the twenty-fourth NMOS transistor MN24, and the ground GND are connected; the source of the sixteenth PMOS transistor MP16 is connected to the drain of the fifteenth PMOS transistor MP15; the drain of the sixteenth PMOS transistor MP16 is respectively connected to the drain of the eighteenth PMOS transistor MP18, the drain of the seventeenth NMOS transistor MN17, the drain of the twentieth NMOS transistor MN20, the gate of the nineteenth PMOS transistor MP19, and the gate of the twenty-fourth NMOS transistor MN24; the eighteenth NMOS transistor MN The drain of the NMOS transistor MN18 is connected to the source of the seventeenth NMOS transistor MN17, the source of the eighteenth NMOS transistor MN18 is connected to the drain of the nineteenth NMOS transistor MN19, the source of the eighteenth PMOS transistor MP18 is connected to the drain of the seventeenth PMOS transistor MP17, the source of the twentieth NMOS transistor MN20 is connected to the drain of the twenty-first NMOS transistor MN21, and the drain of the twenty-fourth NMOS transistor MN24 is connected to the source of the twenty-second NMOS transistor MN22 and the source of the twenty-third NMOS transistor MN23 respectively;

[0114] The drain of the nineteenth PMOS transistor MP19 is respectively connected to the drain of the twenty-second NMOS transistor MN22, the drain of the twenty-third NMOS transistor MN23, and the input end of the seventeenth inverter INV17, and the connection point is coupled to the output end QN of the DFF_PS structure;

[0115] The output end of the seventeenth inverter INV17 is connected to the output end Q of the DFF_PS structure.

[0116] The DFF structure mentioned in this application is a common TSPC D flip-flop structure, which is defined as follows:

[0117] like Figure 2 As shown, the DFF structure includes: 4 PMOS transistors MP1 to MP4, 5 NMOS transistors MN1 to MN5, and 1 inverter INV4;

[0118] The gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the connection point is coupled to the input terminal D of the DFF structure;

[0119] The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3, the gate of the third NMOS transistor MN3, and the gate of the fourth NMOS transistor MN4 respectively, and the connection points are coupled to the input terminal CLK of the DFF structure;

[0120] The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4 and the input terminal of the fourth inverter INV4 respectively, and the connection point is coupled to the output terminal QN of the DFF structure;

[0121] The output end of the fourth inverter INV4 is connected to the output end Q of the DFF structure;

[0122] The source of the first PMOS transistor MP1 is respectively connected to the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, and the power supply VDD; the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2; the drain of the second PMOS transistor MP2 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is respectively connected to the source of the third NMOS transistor MN3, the source of the fifth NMOS transistor MN5, and the ground GND; the drain of the third PMOS transistor MP3 is respectively connected to the drain of the second NMOS transistor MN2, the gate of the fourth PMOS transistor MP4, and the gate of the fifth NMOS transistor MN5; the source of the second NMOS transistor MN2 is connected to the drain of the third NMOS transistor MN3; and the source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5.

[0123] The present application provides a detailed description of an embodiment of a low-power programmable frequency divider based on an improved D flip-flop, as follows:

[0124] Figure 1 This is a schematic diagram of the structure of a low-power programmable frequency divider based on an improved D flip-flop provided in this application, as shown in FIG. Figure 1 As shown, a low-power programmable frequency divider based on an improved D flip-flop includes an input buffer circuit, a low-power 4 / 5 pre-dividing circuit DIV_45, a low-power P frequency dividing circuit DIV_P, and a low-power S frequency dividing circuit DIV_S;

[0125] The output end of the input buffer circuit is connected to the input end CLK of the low-power 4 / 5 pre-frequency dividing circuit DIV_45, the output end OUT_45 of the low-power 4 / 5 pre-frequency dividing circuit DIV_45 is respectively connected to the input end CLK of the low-power P frequency dividing circuit DIV_P and the input end CLK of the low-power S frequency dividing circuit DIV_S, the output end RELOAD of the low-power P frequency dividing circuit DIV_P is connected to the input end RELOAD of the low-power S frequency dividing circuit DIV_S, and the output end S_OUT of the low-power S frequency dividing circuit DIV_S is connected to the input end MC of the low-power 4 / 5 pre-frequency dividing circuit DIV_45;

[0126] When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit DIV_45 is at a low level, the low-power 4 / 5 pre-frequency dividing circuit DIV_45 realizes a 5-frequency dividing function;

[0127] When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit DIV_45 is at a high level, the low-power 4 / 5 pre-frequency dividing circuit DIV_45 realizes a 4-frequency dividing function.

[0128] Preferably, if Figure 1 As shown, the input buffer circuit includes: three inverters INV1 to INV3;

[0129] The output end of the first inverter INV1 is connected to the input end of the second inverter INV2 , and the input end of the third inverter INV3 is connected to the output end of the second inverter INV2 .

[0130] Preferably, if Figure 2 As shown, the low-power 4 / 5 pre-scaling circuit DIV_45 includes: 3 D flip-flops DFF1 to DFF3, and 2 inverters INV5 to INV6;

[0131] The second D flip-flop DFF2 adopts a DFF_I type structure, and the first D flip-flop DFF1 and the third D flip-flop DFF3 adopt a DFF type structure;

[0132] The input terminal CLK of the first D flip-flop DFF1 is connected to the input terminal CLK of the low-power 4 / 5 pre-scaling circuit DIV_45, the input terminal CLK of the second D flip-flop DFF2 is connected to the input terminal CLK of the low-power 4 / 5 pre-scaling circuit DIV_45, and the input terminal MC of the second D flip-flop DFF2 is connected to the input terminal MC of the low-power 4 / 5 pre-scaling circuit DIV_45;

[0133] The input end of the sixth inverter INV6 is connected to the output end of the fifth inverter INV5, and the output end of the sixth inverter INV6 is connected to the output end OUT_45 of the low-power 4 / 5 pre-scaling circuit DIV_45;

[0134] An input terminal D of the first D flip-flop DFF1 is connected to an input terminal D1 of the second D flip-flop DFF2 and an output terminal QN of the second D flip-flop DFF2, an output terminal Q of the first D flip-flop DFF1 is connected to an input terminal D3 of the second D flip-flop DFF2, an input terminal D2 of the second D flip-flop DFF2 is connected to an output terminal Q of the third D flip-flop DFF3, an output terminal Q of the second D flip-flop DFF2 is connected to an input terminal CLK of the third D flip-flop DFF3, an input terminal D of the third D flip-flop DFF3 is connected to an output terminal QN of the third D flip-flop DFF3, and an output terminal Q of the third D flip-flop DFF3 is connected to an input terminal of the fifth inverter INV5.

[0135] Preferably, if Figure 2As shown, the DFF structure includes: 4 PMOS transistors MP1 to MP4, 5 NMOS transistors MN1 to MN5, and 1 inverter INV4;

[0136] The gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1, and the connection point is coupled to the input terminal D of the DFF structure;

[0137] The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3, the gate of the third NMOS transistor MN3, and the gate of the fourth NMOS transistor MN4 respectively, and the connection points are coupled to the input terminal CLK of the DFF structure;

[0138] The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4 and the input terminal of the fourth inverter INV4 respectively, and the connection point is coupled to the output terminal QN of the DFF structure;

[0139] The output end of the fourth inverter INV4 is connected to the output end Q of the DFF structure;

[0140] The source of the first PMOS transistor MP1 is respectively connected to the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, and the power supply VDD; the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2; the drain of the second PMOS transistor MP2 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is respectively connected to the source of the third NMOS transistor MN3, the source of the fifth NMOS transistor MN5, and the ground GND; the drain of the third PMOS transistor MP3 is respectively connected to the drain of the second NMOS transistor MN2, the gate of the fourth PMOS transistor MP4, and the gate of the fifth NMOS transistor MN5; the source of the second NMOS transistor MN2 is connected to the drain of the third NMOS transistor MN3; and the source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5.

[0141] Preferably, if Figure 2 As shown, the DFF_I type structure includes: 7 PMOS transistors MP5 to MP11, 8 NMOS transistors MN6 to MN13, and 1 inverter INV7;

[0142] The gate of the fifth PMOS transistor MP5 is connected to the gate of the ninth NMOS transistor MN9, and the connection point is coupled to the input terminal D1 of the DFF_I type structure;

[0143] The gate of the seventh PMOS transistor MP7 is connected to the gate of the eighth NMOS transistor MN8, and the connection point is coupled to the input terminal D2 of the DFF_I type structure;

[0144] The gate of the sixth PMOS transistor MP6 is connected to the gate of the seventh NMOS transistor MN7, and the connection point is coupled to the input terminal D3 of the DFF_I type structure;

[0145] The gate of the eighth PMOS transistor MP8 is connected to the gate of the sixth NMOS transistor MN6, and the connection point is coupled to the input terminal MC of the DFF_I type structure;

[0146] The gate of the ninth PMOS transistor MP9 is connected to the gate of the tenth PMOS transistor MP10, the gate of the eleventh NMOS transistor MN11, and the gate of the twelfth NMOS transistor MN12, respectively, and the connection points are coupled to the input terminal CLK of the DFF_I type structure;

[0147] The drain of the twelfth NMOS transistor MN12 is connected to the drain of the eleventh PMOS transistor MP11 and the input terminal of the seventh inverter INV7, respectively, and the connection point is coupled to the input terminal QN of the DFF_I type structure;

[0148] The output end of the seventh inverter INV7 is connected to the output end Q of the DFF_I type structure;

[0149] The source of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, the source of the tenth PMOS transistor MP10, the source of the eleventh PMOS transistor MP11, and the power supply VDD, respectively. The drain of the fifth PMOS transistor MP5 is connected to the drain of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9, respectively. The drain of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP7, the drain of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8, and the drain of the ninth PMOS transistor MP9 is connected to the gate of the tenth NMOS transistor MN10, the drain of the sixth NMOS transistor MN6, the drain of the seventh NMOS transistor MN7, and the drain of the eighth NMOS transistor MN8, respectively. The drain of the ninth NMOS transistor MN9 is connected to the source of the sixth NMOS transistor MN6, the source of the seventh NMOS transistor MN7, and the source of the eighth NMOS transistor MN8, respectively. The source of the ninth NMOS transistor MN9 is connected to the source of the eleventh NMOS transistor MN11, the source of the thirteenth NMOS transistor MN11, and the ground GND, respectively. The drain of the tenth PMOS transistor MP10 is connected to the drain of the tenth NMOS transistor MN10, the gate of the eleventh PMOS transistor MP11, and the gate of the thirteenth NMOS transistor MN13, respectively. The source of the tenth NMOS transistor MN10 is connected to the drain of the eleventh NMOS transistor MN11, and the source of the twelfth NMOS transistor MN12 is connected to the drain of the thirteenth NMOS transistor MN13.

[0150] Preferably, if Figure 3 As shown, the low-power P frequency dividing circuit DIV_P includes: 6 D flip-flops DFF4-DFF9, 3 inverters INV8-INV10, 2 three-input NOR gates NOR3_1-NOR3_2, and 1 two-input NAND gate NAND2_1;

[0151] The input terminal P_DIV<4:0> of the low power consumption P frequency dividing circuit DIV_P includes: P_DIV <4> 、P_DIV <3> 、P_DIV <2> 、P_DIV <1> 、P_DIV <0> ;

[0152] The six D flip-flops DFF4 to DFF9 all adopt a DFF_PS structure;

[0153] The input terminal CLK of the fifth D flip-flop DFF5 is connected to the input terminal CLK of the fourth D flip-flop DFF4, and the connection point is coupled to the input terminal CLK of the low-power P frequency dividing circuit DIV_P;

[0154] The input terminal D of the fifth D flip-flop DFF5 is connected to the output terminal QN of the fifth D flip-flop DFF5, and the input terminal A of the fifth D flip-flop DFF5 is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit DIV_P. <0> connect;

[0155] An input terminal S of the fifth D flip-flop DFF5 is respectively connected to an input terminal S of the sixth D flip-flop DFF6, an input terminal S of the seventh D flip-flop DFF7, an input terminal S of the eighth D flip-flop DFF8, an input terminal S of the ninth D flip-flop DFF9, and an output terminal of a ninth inverter INV9, and the connection points are coupled to an output terminal RELOAD of the low-power P frequency divider circuit DIV_P;

[0156] The output terminal Q of the fifth D flip-flop DFF5 is connected to the input terminal CLK of the sixth D flip-flop DFF6, and the connection line is P_Q <0> ;

[0157] The input terminal D of the sixth D flip-flop DFF6 is connected to the output terminal QN of the sixth D flip-flop DFF6, and the input terminal A of the sixth D flip-flop DFF6 is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit DIV_P. <1> connect;

[0158] The output terminal Q of the sixth D flip-flop DFF6 is connected to the input terminal CLK of the seventh D flip-flop DFF7, and the connection line is P_Q <1> ;

[0159] The input terminal D of the seventh D flip-flop DFF7 is connected to the output terminal QN of the seventh D flip-flop DFF7, and the input terminal A of the seventh D flip-flop DFF7 is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit DIV_P. <2> connect;

[0160] The output terminal Q of the seventh D flip-flop DFF7 is connected to the input terminal CLK of the eighth D flip-flop DFF8, and the connection line is P_Q <2> ;

[0161] The input terminal D of the eighth D flip-flop DFF8 is connected to the output terminal QN of the eighth D flip-flop DFF8, and the input terminal A of the eighth D flip-flop DFF8 is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit DIV_P. <3> connect;

[0162] The output terminal Q of the eighth D flip-flop DFF8 is connected to the input terminal CLK of the ninth D flip-flop DFF9, and the connection line is P_Q <3> ;

[0163] The input terminal D of the ninth D flip-flop DFF9 is connected to the output terminal QN of the ninth D flip-flop DFF9, and the input terminal A of the ninth D flip-flop DFF9 is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit DIV_P. <4> The output terminal Q of the ninth D flip-flop DFF9 is connected to P_Q <4> ;

[0164] The input terminal of the eighth inverter INV8 is connected to the connection P_Q <1> connect;

[0165] The three input terminals of the first three-input NOR gate NOR3_1 are connected to the connection P_Q <0> , the output end of the eighth inverter INV8, the connection P_Q <2> connect;

[0166] The three input terminals of the second three-input NOR gate NOR3_2 are connected to the connection P_Q <3> , the wiring P_Q <4> , ground GND connection;

[0167] Two input terminals of the first two-input NAND gate NAND2_1 are respectively connected to the output terminal of the first three-input NOR gate NOR3_1 and the output terminal of the second three-input NOR gate NOR3_2;

[0168] An input terminal D of the fourth D flip-flop DFF4 is connected to the output terminal of the first two-input NAND gate NAND2_1, an input terminal A of the fourth D flip-flop DFF4 is connected to the ground GND, an input terminal S of the fourth D flip-flop DFF4 is connected to the ground GND, and an output terminal Q of the fourth D flip-flop DFF4 is connected to the input terminal of the ninth inverter INV9 and the input terminal of the tenth inverter INV10 respectively;

[0169] The output end of the tenth inverter INV10 is connected to the output end P_OUT of the low power consumption P frequency dividing circuit DIV_P.

[0170] Preferably, if Figure 4 As shown, the low-power S-dividing circuit DIV_S includes: 7 D flip-flops DFF10 to DFF16, 4 inverters INV11 to INV14, 2 three-input NOR gates NOR3_3 to NOR3_4, and 1 two-input NAND gate NAND2_2;

[0171] The input terminal S_DIV<3:0> of the low power consumption S frequency dividing circuit DIV_S includes: S_DIV <3> 、S_DIV <2> 、S_DIV <1> 、S_DIV <0> ;

[0172] The seven D flip-flops DFF10 to DFF16 all adopt a DFF_PS structure;

[0173] The input terminal CLK of the twelfth D flip-flop DFF12 is connected to the input terminal CLK of the tenth D flip-flop DFF10, and the connection point is coupled to the input terminal CLK of the low-power S frequency divider circuit DIV_S;

[0174] The input terminal D of the twelfth D flip-flop DFF12 is connected to the output terminal QN of the twelfth D flip-flop DFF12, and the input terminal A of the twelfth D flip-flop DFF12 is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit DIV_S. <0> connect;

[0175] The input terminal S of the twelfth D flip-flop DFF12 is respectively connected to the input terminal S of the thirteenth D flip-flop DFF13, the input terminal S of the fourteenth D flip-flop DFF14, the input terminal S of the fifteenth D flip-flop DFF15, and the input terminal S of the sixteenth D flip-flop DFF16, and the connection lines are RELOAD_P;

[0176] The output terminal Q of the twelfth D flip-flop DFF12 is connected to the input terminal CLK of the thirteenth D flip-flop DFF13, and the connection line is S_Q <0> ;

[0177] The input terminal D of the thirteenth D flip-flop DFF13 is connected to the output terminal QN of the thirteenth D flip-flop DFF13, and the input terminal A of the thirteenth D flip-flop DFF13 is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit DIV_S. <1> connect;

[0178] The output terminal Q of the thirteenth D flip-flop DFF13 is connected to the input terminal CLK of the fourteenth D flip-flop DFF14, and the connection line is S_Q <1> ;

[0179] The input terminal D of the fourteenth D flip-flop DFF14 is connected to the output terminal QN of the fourteenth D flip-flop DFF14, and the input terminal A of the fourteenth D flip-flop DFF14 is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit DIV_S. <2> connect;

[0180] The output terminal Q of the fourteenth D flip-flop DFF14 is connected to the input terminal CLK of the fifteenth D flip-flop DFF15, and the connection line is S_Q <2> ;

[0181] The input terminal D of the fifteenth D flip-flop DFF15 is connected to the output terminal QN of the fifteenth D flip-flop DFF15, and the input terminal A of the fifteenth D flip-flop DFF15 is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit DIV_S. <3> connect;

[0182] The output terminal Q of the fifteenth D flip-flop DFF15 is connected to the input terminal CLK of the sixteenth D flip-flop DFF16, and the connection line is S_Q <3> ;

[0183] The input terminal D of the sixteenth D flip-flop DFF16 is connected to the output terminal QN of the sixteenth D flip-flop DFF16, the input terminal A of the sixteenth D flip-flop DFF16 is connected to the ground GND, and the wiring of the output terminal Q of the sixteenth D flip-flop DFF16 is S_Q <4> ;

[0184] The input end of the eleventh inverter INV11 is connected to the input end RELOAD of the low-power S-frequency dividing circuit DIV_S, and the output end of the eleventh inverter INV11 is connected to the input end of the twelfth inverter INV12;

[0185] The output terminal of the twelfth inverter INV12 is connected to RELOAD_P;

[0186] The input terminal of the thirteenth inverter INV13 is connected to the connection S_Q <1> connect;

[0187] The three input terminals of the third three-input NOR gate NOR3_3 are connected to the connection S_Q <0> , the output end of the thirteenth inverter INV13, the connection S_Q <2> connect;

[0188] The three input terminals of the fourth three-input NOR gate NOR3_4 are respectively connected to the connection S_Q <3> 、The wiring S_Q <4> , ground GND connection;

[0189] Two input terminals of the second two-input NAND gate NAND2_2 are respectively connected to the output terminal of the third three-input NOR gate NOR3_3 and the output terminal of the fourth three-input NOR gate NOR3_4;

[0190] An input terminal D of the tenth D flip-flop DFF10 is connected to the output terminal of the second two-input NAND gate NAND2_2, an input terminal A of the tenth D flip-flop DFF10 is connected to the ground GND, an input terminal S of the tenth D flip-flop DFF10 is connected to the ground GND, and an output terminal Q of the tenth D flip-flop DFF4 is connected to the input terminal of the fourteenth inverter INV14;

[0191] An input terminal D of the eleventh D flip-flop DFF11 is connected to an output terminal QN of the eleventh D flip-flop DFF11, an input terminal CLK of the eleventh D flip-flop DFF11 is connected to the output terminal of the fourteenth inverter INV14, an input terminal A of the eleventh D flip-flop DFF11 is connected to the ground GND, an input terminal S of the eleventh D flip-flop DFF11 is connected to the wiring RELOAD_P, and an output terminal Q of the eleventh D flip-flop DFF11 is connected to an output terminal S_OUT of the low-power S frequency divider circuit DIV_S.

[0192] Preferably, if Figure 5 As shown, the DFF_PS type structure includes: 8 PMOS transistors MP12 to MP19, 11 NMOS transistors MN6 to MN13, and 3 inverters INV15 to INV17;

[0193] An input terminal of the fifteenth inverter INV15 is respectively connected to the gate of the twelfth PMOS transistor MP12, the gate of the sixteenth NMOS transistor MN16, the gate of the fifteenth PMOS transistor MP15, the gate of the twenty-first NMOS transistor MN21, and the gate of the twenty-third NMOS transistor MN23, and the connection point is coupled to the input terminal S of the DFF_PS structure;

[0194] The gate of the thirteenth PMOS transistor MP13 is connected to the gate of the fourteenth NMOS transistor MN14, and the connection point is coupled to the input terminal D of the DFF_PS structure;

[0195] The gate of the fourteenth PMOS transistor MP14 is connected to the gate of the sixteenth PMOS transistor MP16, the gate of the eighteenth NMOS transistor MN18, and the gate of the twenty-second NMOS transistor MN22, respectively, and the connection points are coupled to the input terminal CLK of the DFF_PS structure;

[0196] The output end of the fifteenth inverter INV15 is respectively connected to the gate of the fifteenth NMOS transistor MN15, the gate of the nineteenth NMOS transistor MN19, and the gate of the seventeenth PMOS transistor MP17; the source of the twelfth PMOS transistor MP12 is respectively connected to the source of the fifteenth PMOS transistor MP15, the source of the seventeenth PMOS transistor MP17, and the source of the nineteenth PMOS transistor MP19; the drain of the twelfth PMOS transistor MP12 is connected to the source of the thirteenth PMOS transistor MP13; and the fourteenth PMOS transistor MP The source of the PMOS transistor MP14 is connected to the drain of the thirteenth PMOS transistor MP13, the drain of the fourteenth PMOS transistor MP14 is respectively connected to the drain of the fourteenth NMOS transistor MN14, the drain of the sixteenth NMOS transistor MN16, and the gate of the seventeenth NMOS transistor MN17, the drain of the fifteenth NMOS transistor MN15 is respectively connected to the source of the fourteenth NMOS transistor NM14, the source of the fifteenth NMOS transistor MN15 is respectively connected to the source of the sixteenth NMOS transistor MN16, the source of the nineteenth NMOS transistor MN19, and the gate of the twenty-first NMOS transistor MN17. The source of the NMOS transistor MN21, the source of the twenty-fourth NMOS transistor MN24, and the ground GND are connected; the source of the sixteenth PMOS transistor MP16 is connected to the drain of the fifteenth PMOS transistor MP15; the drain of the sixteenth PMOS transistor MP16 is respectively connected to the drain of the eighteenth PMOS transistor MP18, the drain of the seventeenth NMOS transistor MN17, the drain of the twentieth NMOS transistor MN20, the gate of the nineteenth PMOS transistor MP19, and the gate of the twenty-fourth NMOS transistor MN24; the eighteenth NMOS transistor MN The drain of the NMOS transistor MN18 is connected to the source of the seventeenth NMOS transistor MN17, the source of the eighteenth NMOS transistor MN18 is connected to the drain of the nineteenth NMOS transistor MN19, the source of the eighteenth PMOS transistor MP18 is connected to the drain of the seventeenth PMOS transistor MP17, the source of the twentieth NMOS transistor MN20 is connected to the drain of the twenty-first NMOS transistor MN21, and the drain of the twenty-fourth NMOS transistor MN24 is connected to the source of the twenty-second NMOS transistor MN22 and the source of the twenty-third NMOS transistor MN23 respectively;

[0197] The drain of the nineteenth PMOS transistor MP19 is respectively connected to the drain of the twenty-second NMOS transistor MN22, the drain of the twenty-third NMOS transistor MN23, and the input end of the seventeenth inverter INV17, and the connection point is coupled to the output end QN of the DFF_PS structure;

[0198] The output end of the seventeenth inverter INV17 is connected to the output end Q of the DFF_PS structure.

[0199] Among them, Figure 1 As shown, in the low-power programmable frequency divider based on the improved D flip-flop, the input buffer circuit is used to buffer the input signal of the input terminal CLK of the low-power programmable frequency divider based on the improved D flip-flop, so that the signal amplitude can be amplified.

[0200] like Figure 3 As shown, in the low-power P frequency divider circuit DIV_P, the eighth inverter INV8, the first three-input NOR gate NOR3_1, the second three-input NOR gate NOR3_2, the first two-input NAND gate NAND2_1, the fourth D flip-flop DFF4, the ninth inverter INV9, and the tenth inverter INV10 constitute a P cycle end detection circuit 1031, and the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, the seventh D flip-flop DFF7, the eighth D flip-flop DFF8, and the ninth D flip-flop DFF9 constitute a P counting circuit 1032. The P counting circuit 1032 counts the input signal at the input terminal CLK of the low-power P frequency divider circuit DIV_P and transmits the counting information to the P cycle end detection circuit 1031. The P cycle end detection circuit 1031 determines whether the frequency division cycle of the low-power programmable frequency divider based on the improved D flip-flop has ended based on the counting information of the P counting circuit 1032. If the division cycle of the low-power programmable divider based on the improved D flip-flop ends, the P cycle end detection circuit 1031 will generate a RELOAD signal to cause the low-power P division circuit DIV_P and the low-power S division circuit DIV_S to reload the division values ​​P_DIV<4:0> and S_DIV<3:0> respectively.

[0201] like Figure 3As shown, in the low-power S-dividing circuit DIV_S, the eleventh inverter INV11, the twelfth inverter INV12, the thirteenth inverter INV13, the fourteenth inverter INV14, the third three-input NOR gate NOR3_3, the fourth three-input NOR gate NOR3_4, the second two-input NAND gate NAND2_2, the tenth D flip-flop DFF10, and the eleventh D flip-flop DFF11 constitute an S-cycle end detection circuit 1041, and the twelfth D flip-flop DFF12, the thirteenth D flip-flop DFF13, the fourteenth D flip-flop DFF14, the fifteenth D flip-flop DFF15, and the sixteenth D flip-flop DFF16 constitute an S counting circuit 1042. The S counting circuit 1042 counts the input signal at the input terminal CLK of the low-power S-dividing circuit DIV_S and transmits the counting information to the S-cycle end detection circuit 1041. The S cycle end detection circuit 1041 determines whether the counting cycle of the low-power S frequency divider circuit DIV_S has ended based on the counting information of the S counting circuit 1042. If the counting cycle of the low-power S frequency divider circuit DIV_S has ended, the S cycle end detection circuit 1041 generates an S_OUT signal, which causes the input terminal MC of the low-power 4 / 5 pre-scaling circuit DIV_45 to be high, and the low-power 4 / 5 pre-scaling circuit DIV_45 implements a divide-by-4 function.

[0202] At the beginning of a division cycle of the low-power programmable divider based on the improved D flip-flop, the low-power 4 / 5 pre-division circuit DIV_45 realizes a 5-division function and transmits the divided signal to the input terminal CLK of the low-power P division circuit DIV_P and the input terminal CLK of the low-power S division circuit DIV_S. The low-power S frequency dividing circuit DIV_S counts the output signal of the low-power 4 / 5 pre-frequency dividing circuit DIV_45. When the count reaches S_DIV<3:0>, the S cycle end detection circuit 1041 generates an S_OUT signal, so that the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit DIV_45 is high. The low-power 4 / 5 pre-frequency dividing circuit DIV_45 implements a 4-frequency dividing function. At this time, 5*S_DIV<3:0> of the input signal of the input terminal CLK of the low-power programmable frequency divider based on the improved D flip-flop is counted. At this time, the low-power P frequency dividing circuit DIV_P has completed the S_DIV<3:0> count. After that, the low-power P frequency dividing circuit DIV_P will continue to count P_DIV<4:0>-S_DIV<3:0> on the output signal of the low-power 4 / 5 pre-dividing circuit DIV_45, that is, the low-power P frequency dividing circuit DIV_P will continue to count 4*(P_DIV<4:0>-S_DIV<3:0>) on the input signal of the input terminal CLK of the low-power programmable frequency divider based on the improved D flip-flop. When the count is full, the low-power programmable frequency divider based on the improved D flip-flop completes one frequency division of the input signal of the input terminal CLK of the low-power programmable frequency divider based on the improved D flip-flop. The total division ratio M of the low-power programmable frequency divider based on the improved D flip-flop is 5*S_DIV<3:0>+4*(P_DIV<4:0>-S_DIV<3:0>), that is, M=4*P_DIV<4:0>+S_DIV<3:0>, wherein P_DIV<4:0> needs to be greater than S_DIV<3:0>.

[0203] Taking the output signal frequency of the low-power programmable frequency divider based on the improved D flip-flop as 16.368MHz after frequency division as an example, it can be seen that if the input signal frequency range of the low-power programmable frequency divider based on the improved D flip-flop needs to cover the GNSS frequency range (1164MHz~1610MHz), then the total division ratio M of the low-power programmable frequency divider based on the improved D flip-flop needs to be 71~99 (corresponding to an input frequency range of 16.368MHz*71~16.368MHz*99, which is approximately 1162MHz~1620MHz). If the total division ratio M needs to be 71, P_DIV<4:0> can be set to 16 and S_DIV<3:0> can be set to 7, that is, P_DIV <4> 、P_DIV <3> 、P_DIV <2> 、P_DIV <1> 、P_DIV <0> 1, 0, 0, 0, 0, S_DIV <3> 、S_DIV <2> 、S_DIV <1> 、S_DIV <0> They are 0, 1, 1, and 1 respectively. If you want to achieve a total frequency division ratio of 99, you can set P_DIV<4:0> to 23 and S_DIV<3:0> to 7, that is, P_DIV <4> 、P_DIV <3> 、P_DIV <2> 、P_DIV <1> 、P_DIV <0> 1, 0, 1, 1, 1, S_DIV <3> 、S_DIV <2> 、S_DIV <1> 、S_DIV <0> They are 0, 1, 1, and 1 respectively.

[0204] Figure 6 This is a specific circuit diagram of the traditional 4 / 5 pre-scaling circuit provided by this application. Figure 6 As shown, the conventional 4 / 5 pre-scaling circuit uses more combinational logic to achieve the 4-divide or 5-divide function, including: 5 inverters INV18-INV22, 2 two-input NOR gates NOR2_1, NOR2_2, and 1 two-input NAND gate NAND2_3.

[0205] contrast Figure 6 The traditional 4 / 5 pre-scaling circuit described in Figure 2 As shown, the D flip-flop in the low-power 4 / 5 pre-dividing circuit DIV_45 provided in the present application adopts the improved D flip-flop structure (DFF_I type structure) proposed in the present application, which reduces the number of logic gates and thus optimizes power consumption.

[0206] Figure 7 This is a specific circuit diagram of the traditional P frequency division circuit provided in this application. Figure 8 This is a specific circuit diagram of the traditional S-type frequency divider circuit provided in this application. Figure 9 This is a specific circuit diagram of a traditional counting unit provided in this application. Figure 7 、 Figure 8 、 Figure 9As shown, the conventional counting unit uses a large number of combinational logic gates. Taking the conventional counting unit 20221 as an example, the conventional counting unit includes: an inverter INV26, two two-input NAND gates NAND2_5 to NAND2_6, and a D flip-flop DFF21, wherein the twenty-first D flip-flop DFF21 adopts a DFF_TG structure.

[0207] contrast Figure 7 The traditional P frequency dividing circuit described in Figure 8 In the traditional S-frequency divider circuit, such as Figure 3 、 Figure 4 As shown, the D flip-flops in the low-power P frequency dividing circuit DIV_P and the low-power S frequency dividing circuit DIV_S provided by the present application adopt the improved D flip-flop structure (DFF_PS type structure) proposed in the present application, which reduces the number of logic gates and thus optimizes power consumption.

[0208] Table 1 Comparison of power consumption between the frequency divider of this application and the traditional frequency divider

[0209]

[0210] Table 1 is a table comparing the power consumption of the frequency divider of the present application and traditional frequency dividers. Table 1 provides power consumption comparison data of the frequency divider of the present application and traditional frequency dividers under the total frequency division ratio M of 71 and the total frequency division ratio M of 99, corresponding to the input frequencies of 1160MHz, 1390MHz, and 1620MHz.

[0211] Taking the total frequency division ratio M as 71 as an example, Figure 10 The power consumption comparison chart of a low-power programmable frequency divider based on an improved D flip-flop and a traditional programmable frequency divider within the GNSS frequency range is shown in Table 1 when the total frequency division ratio M is 71. Figure 10 As shown, within the GNSS frequency range, the power consumption of the low-power programmable frequency divider based on the improved D flip-flop provided by the present application is better than that of the traditional programmable frequency divider.

[0212] In general, the above technical solutions conceived by the present application have the following beneficial effects compared with the existing technology: 1) The DFF_I type structure D flip-flop proposed in the present application is adopted in the low-power 4 / 5 pre-dividing circuit DIV_45, thereby reducing the number of combinational logic gates and thus optimizing power consumption; 2) The DFF_PS type structure D flip-flop proposed in the present application is adopted in the low-power P dividing circuit DIV_P and the low-power S dividing circuit DIV_S, thereby reducing the number of combinational logic gates and thus optimizing power consumption; 3) Thanks to the reduction in the number of logic gates, the low-power programmable divider based on the improved D flip-flop provided by the present application also has the advantages of small area, low cost and strong practicality.

[0213] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A low-power programmable frequency divider based on an improved D flip-flop, characterized in that: Includes input buffer circuit, low-power 4 / 5 pre-dividing circuit (DIV_45), low-power P dividing circuit (DIV_P) and low-power S dividing circuit (DIV_S); The output end of the input buffer circuit is connected to the input end CLK of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45), the output end OUT_45 of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is respectively connected to the input end CLK of the low-power P frequency dividing circuit (DIV_P) and the input end CLK of the low-power S frequency dividing circuit (DIV_S), the output end RELOAD of the low-power P frequency dividing circuit (DIV_P) is connected to the input end RELOAD of the low-power S frequency dividing circuit (DIV_S), and the output end S_OUT of the low-power S frequency dividing circuit (DIV_S) is connected to the input end MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45); When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is at a low level, the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) realizes a 5-frequency dividing function; When the input terminal MC of the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) is at a high level, the low-power 4 / 5 pre-frequency dividing circuit (DIV_45) realizes a 4-frequency dividing function.

2. A low-power programmable frequency divider based on an improved D flip-flop according to claim 1, characterized in that: The input buffer circuit includes: 3 inverters (INV1 to INV3); The output end of the first inverter (INV1) is connected to the input end of the second inverter (INV2), and the input end of the third inverter (INV3) is connected to the output end of the second inverter (INV2).

3. The low-power programmable frequency divider based on the improved D flip-flop according to claim 1, characterized in that: The low-power 4 / 5 pre-dividing circuit (DIV_45) includes: 3 D flip-flops (DFF1 to DFF3) and 2 inverters (INV5 and INV6); The second D flip-flop (DFF2) adopts a DFF_I type structure, and the first D flip-flop (DFF1) and the third D flip-flop (DFF3) adopt a DFF type structure; An input terminal CLK of the first D flip-flop (DFF1) is connected to an input terminal CLK of the low-power 4 / 5 pre-scaling circuit (DIV_45), an input terminal CLK of the second D flip-flop (DFF2) is connected to an input terminal CLK of the low-power 4 / 5 pre-scaling circuit (DIV_45), and an input terminal MC of the second D flip-flop (DFF2) is connected to an input terminal MC of the low-power 4 / 5 pre-scaling circuit (DIV_45); The input end of the sixth inverter (INV6) is connected to the output end of the fifth inverter (INV5), and the output end of the sixth inverter (INV6) is connected to the output end OUT_45 of the low-power 4 / 5 pre-scaling circuit (DIV_45); An input terminal D of the first D flip-flop (DFF1) is connected to an input terminal D1 of the second D flip-flop (DFF2) and an output terminal QN of the second D flip-flop (DFF2); an output terminal Q of the first D flip-flop (DFF1) is connected to an input terminal D3 of the second D flip-flop (DFF2); an input terminal D2 of the second D flip-flop (DFF2) is connected to an output terminal Q of the third D flip-flop (DFF3); an output terminal Q of the second D flip-flop (DFF2) is connected to an input terminal CLK of the third D flip-flop (DFF3); an input terminal D of the third D flip-flop (DFF3) is connected to an output terminal QN of the third D flip-flop (DFF3); and an output terminal Q of the third D flip-flop (DFF3) is connected to an input terminal of the fifth inverter (INV5).

4. A low-power programmable frequency divider based on an improved D flip-flop according to claim 3, characterized in that: The DFF structure includes: 4 PMOS transistors (MP1-MP4), 5 NMOS transistors (MN1-MN5), and 1 inverter (INV4); The gate of the first PMOS transistor (MP1) is connected to the gate of the first NMOS transistor (MN1), and the connection point is coupled to the input terminal D of the DFF structure; The gate of the second PMOS transistor (MP2) is respectively connected to the gate of the third PMOS transistor (MP3), the gate of the third NMOS transistor (MN3), and the gate of the fourth NMOS transistor (MN4), and the connection point is coupled to the input terminal CLK of the DFF structure; The drain of the fourth PMOS transistor (MP4) is respectively connected to the drain of the fourth NMOS transistor (MN4) and the input end of the fourth inverter (INV4), and the connection point is coupled to the output end QN of the DFF structure; The output terminal of the fourth inverter (INV4) is connected to the output terminal Q of the DFF structure; The source of the first PMOS tube (MP1) is respectively connected to the source of the third PMOS tube (MP3), the source of the fourth PMOS tube (MP4), and the power supply VDD; the drain of the first PMOS tube (MP1) is respectively connected to the source of the second PMOS tube (MP2); the drain of the second PMOS tube (MP2) is respectively connected to the drain of the first NMOS tube (MN1) and the gate of the second NMOS tube (MN2); the source of the first NMOS tube (MN1) is respectively connected to the source of the third NMOS tube (MP3), the source of the fourth PMOS tube (MP4), and the power supply VDD; the drain of the first PMOS tube (MP1) is respectively connected to the source of the second PMOS tube (MP2); the drain of the second PMOS tube (MP2) is respectively connected to the drain of the first NMOS tube (MN1) and the gate of the second NMOS tube (MN2); The source of the S transistor (MN3), the source of the fifth NMOS transistor (MN5), and the ground GND are connected; the drain of the third PMOS transistor (MP3) is respectively connected to the drain of the second NMOS transistor (MN2), the gate of the fourth PMOS transistor (MP4), and the gate of the fifth NMOS transistor (MN5); the source of the second NMOS transistor (MN2) is connected to the drain of the third NMOS transistor (MN3); and the source of the fourth NMOS transistor (MN4) is connected to the drain of the fifth NMOS transistor (MN5).

5. The low-power programmable frequency divider based on the improved D flip-flop according to claim 3, characterized in that: The DFF_I type structure includes: 7 PMOS transistors (MP5-MP11), 8 NMOS transistors (MN6-MN13), and 1 inverter (INV7); The gate of the fifth PMOS transistor (MP5) is connected to the gate of the ninth NMOS transistor (MN9), and the connection point is coupled to the input terminal D1 of the DFF_I type structure; The gate of the seventh PMOS transistor (MP7) is connected to the gate of the eighth NMOS transistor (MN8), and the connection point is coupled to the input terminal D2 of the DFF_I type structure; The gate of the sixth PMOS transistor (MP6) is connected to the gate of the seventh NMOS transistor (MN7), and the connection point is coupled to the input terminal D3 of the DFF_I type structure; The gate of the eighth PMOS transistor (MP8) is connected to the gate of the sixth NMOS transistor (MN6), and the connection point is coupled to the input terminal MC of the DFF_I type structure; The gate of the ninth PMOS transistor (MP9) is respectively connected to the gate of the tenth PMOS transistor (MP10), the gate of the eleventh NMOS transistor (MN11), and the gate of the twelfth NMOS transistor (MN12), and the connection point is coupled to the input terminal CLK of the DFF_I type structure; The drain of the twelfth NMOS transistor (MN12) is respectively connected to the drain of the eleventh PMOS transistor (MP11) and the input end of the seventh inverter (INV7), and the connection point is coupled to the input end QN of the DFF_I type structure; The output terminal of the seventh inverter (INV7) is connected to the output terminal Q of the DFF_I type structure; The source of the fifth PMOS tube (MP5) is respectively connected to the source of the sixth PMOS tube (MP6), the source of the tenth PMOS tube (MP10), the source of the eleventh PMOS tube (MP11), and the power supply VDD; the drain of the fifth PMOS tube (MP5) is respectively connected to the drain of the eighth PMOS tube (MP8) and the source of the ninth PMOS tube (MP9); the drain of the sixth PMOS tube (MP6) is connected to the source of the seventh PMOS tube (MP7); the drain of the seventh PMOS tube (MP7) is connected to the source of the eighth PMOS tube (MP8); the drain of the ninth PMOS tube (MP9) is respectively connected to the gate of the tenth NMOS tube (MN10), the drain of the sixth NMOS tube (MN6), the drain of the seventh NMOS tube (MN7), the drain of the eighth NMOS tube (MN8), and the drain of the ninth PMOS tube (MP9). The drain of the ninth NMOS transistor (MN9) is connected to the source of the sixth NMOS transistor (MN6), the source of the seventh NMOS transistor (MN7), and the source of the eighth NMOS transistor (MN8), respectively; the source of the ninth NMOS transistor (MN9) is connected to the source of the eleventh NMOS transistor (MN11), the source of the thirteenth NMOS transistor (MN11), and the ground GND, respectively; the drain of the tenth PMOS transistor (MP10) is connected to the drain of the tenth NMOS transistor (MN10), the gate of the eleventh PMOS transistor (MP11), and the gate of the thirteenth NMOS transistor (MN13), respectively; the source of the tenth NMOS transistor (MN10) is connected to the drain of the eleventh NMOS transistor (MN11), and the source of the twelfth NMOS transistor (MN12) is connected to the drain of the thirteenth NMOS transistor (MN13).

6. The low-power programmable frequency divider based on the improved D flip-flop according to claim 1, characterized in that: The low-power P frequency divider circuit (DIV_P) includes: 6 D flip-flops (DFF4-DFF9), 3 inverters (INV8-INV10), 2 three-input NOR gates (NOR3_1, NOR3_2), and 1 two-input NAND gate (NAND2_1); The input terminal P_DIV<4:0> of the low power consumption P frequency dividing circuit (DIV_P) includes: P_DIV <4> 、P_DIV <3> 、P_DIV <2> 、P_DIV <1> 、P_DIV <0> ; The six D flip-flops (DFF4 to DFF9) all adopt a DFF_PS structure; The input terminal CLK of the fifth D flip-flop (DFF5) is connected to the input terminal CLK of the fourth D flip-flop (DFF4), and the connection point is coupled to the input terminal CLK of the low-power P frequency dividing circuit (DIV_P); The input terminal D of the fifth D flip-flop (DFF5) is connected to the output terminal QN of the fifth D flip-flop (DFF5), and the input terminal A of the fifth D flip-flop (DFF5) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <0> connect; An input terminal S of the fifth D flip-flop (DFF5) is respectively connected to an input terminal S of the sixth D flip-flop (DFF6), an input terminal S of the seventh D flip-flop (DFF7), an input terminal S of the eighth D flip-flop (DFF8), an input terminal S of the ninth D flip-flop (DFF9), and an output terminal of a ninth inverter (INV9), and the connection point is coupled to an output terminal RELOAD of the low-power P frequency divider circuit (DIV_P); The output terminal Q of the fifth D flip-flop (DFF5) is connected to the input terminal CLK of the sixth D flip-flop (DFF6), and the connection line is P_Q <0> ; The input terminal D of the sixth D flip-flop (DFF6) is connected to the output terminal QN of the sixth D flip-flop (DFF6), and the input terminal A of the sixth D flip-flop (DFF6) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <1> connect; The output terminal Q of the sixth D flip-flop (DFF6) is connected to the input terminal CLK of the seventh D flip-flop (DFF7), and the connection line is P_Q <1> ; The input terminal D of the seventh D flip-flop (DFF7) is connected to the output terminal QN of the seventh D flip-flop (DFF7), and the input terminal A of the seventh D flip-flop (DFF7) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <2> connect; The output terminal Q of the seventh D flip-flop (DFF7) is connected to the input terminal CLK of the eighth D flip-flop (DFF8), and the connection line is P_Q <2> ; The input terminal D of the eighth D flip-flop (DFF8) is connected to the output terminal QN of the eighth D flip-flop (DFF8), and the input terminal A of the eighth D flip-flop (DFF8) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <3> connect; The output terminal Q of the eighth D flip-flop (DFF8) is connected to the input terminal CLK of the ninth D flip-flop (DFF9), and the connection line is P_Q <3> ; The input terminal D of the ninth D flip-flop (DFF9) is connected to the output terminal QN of the ninth D flip-flop (DFF9), and the input terminal A of the ninth D flip-flop (DFF9) is connected to the input terminal P_DIV of the low power consumption P frequency dividing circuit (DIV_P). <4> The output terminal Q of the ninth D flip-flop (DFF9) is connected to P_Q <4> ; The input terminal of the eighth inverter (INV8) is connected to the connection P_Q <1> connect; The three input terminals of the first three-input NOR gate (NOR3_1) are connected to the wiring P_Q <0> , the output terminal of the eighth inverter (INV8), the connection P_Q <2> connect; The three input terminals of the second three-input NOR gate (NOR3_2) are connected to the wiring P_Q <3> , the wiring P_Q <4> , ground GND connection; Two input terminals of the first two-input NAND gate (NAND2_1) are respectively connected to the output terminal of the first three-input NOR gate (NOR3_1) and the output terminal of the second three-input NOR gate (NOR3_2); An input terminal D of the fourth D flip-flop (DFF4) is connected to the output terminal of the first two-input NAND gate (NAND2_1), an input terminal A of the fourth D flip-flop (DFF4) is connected to the ground GND, an input terminal S of the fourth D flip-flop (DFF4) is connected to the ground GND, and an output terminal Q of the fourth D flip-flop (DFF4) is connected to the input terminal of the ninth inverter (INV9) and the input terminal of the tenth inverter (INV10), respectively; The output end of the tenth inverter (INV10) is connected to the output end P_OUT of the low-power consumption P frequency dividing circuit (DIV_P).

7. The low-power programmable frequency divider based on the improved D flip-flop according to claim 1, characterized in that: The low-power S-frequency divider circuit (DIV_S) includes: 7 D flip-flops (DFF10-DFF16), 4 inverters (INV11-INV14), 2 three-input NOR gates (NOR3_3, NOR3_4), and 1 two-input NAND gate (NAND2_2); The input terminal S_DIV<3:0> of the low power consumption S frequency dividing circuit (DIV_S) includes: S_DIV <3> 、S_DIV <2> 、S_DIV <1> 、S_DIV <0> ; The seven D flip-flops (DFF10 to DFF16) all adopt a DFF_PS structure; The input terminal CLK of the twelfth D flip-flop (DFF12) is connected to the input terminal CLK of the tenth D flip-flop (DFF10), and the connection point is coupled to the input terminal CLK of the low-power S frequency dividing circuit (DIV_S); The input terminal D of the twelfth D flip-flop (DFF12) is connected to the output terminal QN of the twelfth D flip-flop (DFF12), and the input terminal A of the twelfth D flip-flop (DFF12) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <0> connect; An input terminal S of the twelfth D flip-flop (DFF12) is respectively connected to an input terminal S of the thirteenth D flip-flop (DFF13), an input terminal S of the fourteenth D flip-flop (DFF14), an input terminal S of the fifteenth D flip-flop (DFF15), and an input terminal S of the sixteenth D flip-flop (DFF16), and the connection lines are RELOAD_P; The output terminal Q of the twelfth D flip-flop (DFF12) is connected to the input terminal CLK of the thirteenth D flip-flop (DFF13), and the connection line is S_Q <0> ; The input terminal D of the thirteenth D flip-flop (DFF13) is connected to the output terminal QN of the thirteenth D flip-flop (DFF13), and the input terminal A of the thirteenth D flip-flop (DFF13) is connected to the input terminal S_DIV of the low-power S frequency dividing circuit (DIV_S). <1> connect; The output terminal Q of the thirteenth D flip-flop (DFF13) is connected to the input terminal CLK of the fourteenth D flip-flop (DFF14), and the connection line is S_Q <1> ; The input terminal D of the fourteenth D flip-flop (DFF14) is connected to the output terminal QN of the fourteenth D flip-flop (DFF14), and the input terminal A of the fourteenth D flip-flop (DFF14) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <2> connect; The output terminal Q of the fourteenth D flip-flop (DFF14) is connected to the input terminal CLK of the fifteenth D flip-flop (DFF15), and the connection line is S_Q <2> ; The input terminal D of the fifteenth D flip-flop (DFF15) is connected to the output terminal QN of the fifteenth D flip-flop (DFF15), and the input terminal A of the fifteenth D flip-flop (DFF15) is connected to the input terminal S_DIV of the low power consumption S frequency dividing circuit (DIV_S). <3> connect; The output terminal Q of the fifteenth D flip-flop (DFF15) is connected to the input terminal CLK of the sixteenth D flip-flop (DFF16), and the connection line is S_Q <3> ; The input terminal D of the sixteenth D flip-flop (DFF16) is connected to the output terminal QN of the sixteenth D flip-flop (DFF16), the input terminal A of the sixteenth D flip-flop (DFF16) is connected to the ground GND, and the wiring of the output terminal Q of the sixteenth D flip-flop (DFF16) is S_Q <4> ; The input end of the eleventh inverter (INV11) is connected to the input end RELOAD of the low-power S-frequency dividing circuit (DIV_S), and the output end of the eleventh inverter (INV11) is connected to the input end of the twelfth inverter (INV12); The output terminal of the twelfth inverter (INV12) is connected to RELOAD_P; The input terminal of the thirteenth inverter (INV13) is connected to the connection S_Q <1> connect; The three input terminals of the third three-input NOR gate (NOR3_3) are connected to the wiring S_Q <0> , the output terminal of the thirteenth inverter (INV13), the connection S_Q <2> connect; The three input terminals of the fourth three-input NOR gate (NOR3_4) are connected to the wiring S_Q <3> 、The connection S_Q <4> , ground GND connection; Two input terminals of the second two-input NAND gate (NAND2_2) are respectively connected to the output terminal of the third three-input NOR gate (NOR3_3) and the output terminal of the fourth three-input NOR gate (NOR3_4); an input terminal D of the tenth D flip-flop (DFF10) connected to the output terminal of the second two-input NAND gate (NAND2_2), an input terminal A of the tenth D flip-flop (DFF10) connected to ground GND, an input terminal S of the tenth D flip-flop (DFF10) connected to ground GND, and an output terminal Q of the tenth D flip-flop (DFF4) connected to the input terminal of the fourteenth inverter (INV14); An input terminal D of the eleventh D flip-flop (DFF11) is connected to an output terminal QN of the eleventh D flip-flop (DFF11), an input terminal CLK of the eleventh D flip-flop (DFF11) is connected to the output terminal of the fourteenth inverter (INV14), an input terminal A of the eleventh D flip-flop (DFF11) is connected to the ground GND, an input terminal S of the eleventh D flip-flop (DFF11) is connected to the wiring RELOAD_P, and an output terminal Q of the eleventh D flip-flop (DFF11) is connected to an output terminal S_OUT of the low-power S-dividing circuit (DIV_S).

8. A low-power programmable frequency divider based on an improved D flip-flop according to any one of claims 6 or 7, characterized in that: The DFF_PS type structure includes: 8 PMOS transistors (MP12 to MP19), 11 NMOS transistors (MN6 to MN13), and 3 inverters (INV15 to INV17); The input end of the fifteenth inverter (INV15) is respectively connected to the gate of the twelfth PMOS transistor (MP12), the gate of the sixteenth NMOS transistor (MN16), the gate of the fifteenth PMOS transistor (MP15), the gate of the twenty-first NMOS transistor (MN21), and the gate of the twenty-third NMOS transistor (MN23), and the connection point is coupled to the input end S of the DFF_PS structure; The gate of the thirteenth PMOS transistor (MP13) is connected to the gate of the fourteenth NMOS transistor (MN14), and the connection point is coupled to the input terminal D of the DFF_PS structure; The gate of the fourteenth PMOS transistor (MP14) is respectively connected to the gate of the sixteenth PMOS transistor (MP16), the gate of the eighteenth NMOS transistor (MN18), and the gate of the twenty-second NMOS transistor (MN22), and the connection point is coupled to the input terminal CLK of the DFF_PS structure; The output end of the fifteenth inverter (INV15) is respectively connected to the gate of the fifteenth NMOS transistor (MN15), the gate of the nineteenth NMOS transistor (MN19), and the gate of the seventeenth PMOS transistor (MP17); the source of the twelfth PMOS transistor (MP12) is respectively connected to the source of the fifteenth PMOS transistor (MP15), the source of the seventeenth PMOS transistor (MP17), and the source of the nineteenth PMOS transistor (MP19); the drain of the twelfth PMOS transistor (MP12) is connected to the source of the thirteenth PMOS transistor (MP13); and the drain of the fourteenth PMOS transistor (MP14) is connected to the source of the thirteenth PMOS transistor (MP13). The source of the 13th PMOS tube (MP13) is connected to the drain of the 14th PMOS tube (MP14), the drain of the 14th NMOS tube (MN14), the drain of the 16th NMOS tube (MN16), and the gate of the 17th NMOS tube (MN17), the drain of the 15th NMOS tube (MN15) is connected to the source of the 14th NMOS tube (NM14), the source of the 15th NMOS tube (MN15) is connected to the source of the 16th NMOS tube (MN16), the source of the 19th NMOS tube (MN19), and the gate of the 21st NMOS tube (MN17), respectively. The source of the NMOS transistor (MN21), the source of the twenty-fourth NMOS transistor (MN24), and the ground GND are connected; the source of the sixteenth PMOS transistor (MP16) is connected to the drain of the fifteenth PMOS transistor (MP15); the drain of the sixteenth PMOS transistor (MP16) is respectively connected to the drain of the eighteenth PMOS transistor (MP18), the drain of the seventeenth NMOS transistor (MN17), the drain of the twentieth NMOS transistor (MN20), the gate of the nineteenth PMOS transistor (MP19), and the gate of the twenty-fourth NMOS transistor (MN24); the eighteenth NMOS transistor (MN The drain of the 20th NMOS transistor (MN20) is connected to the drain of the 21st NMOS transistor (MN21), and the drain of the 24th NMOS transistor (MN24) is connected to the source of the 22nd NMOS transistor (MN22) and the source of the 23rd NMOS transistor (MN23); The drain of the nineteenth PMOS transistor (MP19) is respectively connected to the drain of the twenty-second NMOS transistor (MN22), the drain of the twenty-third NMOS transistor (MN23), and the input end of the seventeenth inverter (INV17), and the connection point is coupled to the output end QN of the DFF_PS structure; The output terminal of the seventeenth inverter (INV17) is connected to the output terminal Q of the DFF_PS structure.

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