Clock source and electronic equipment

Abstract

The embodiment of the invention discloses a clock source and electronic equipment, and belongs to the technical field of integrated circuits. The clock source comprises a plurality of inverter chain loops, the plurality of inverter chain loops comprise a main loop and at least two auxiliary loops, and the main loop is respectively coupled with the at least two auxiliary loops to construct at least two coupling relations. According to the embodiment of the invention, the problem of oscillation mode ambiguity of a clock source design scheme capable of improving the oscillation frequency in the related technology is at least solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to clock sources and electronic devices. Background Art

[0002] With the increasing demand for communication rates, traditional multi-phase clock sources face challenges in both oscillation frequency and pattern stability.

[0003] To increase the oscillation frequency of the clock source, the solution adopted in related technologies is to add feedforward coupling technology, which effectively reduces the delay of a single inverter stage and thus increases the oscillation frequency of the clock source. However, as the number of output phases increases, this solution will lead to uncertainty in the oscillation mode of the clock source. That is, the relationship between its output phase and oscillation frequency will change dramatically under process-voltage-temperature (PVT) changes, causing oscillation mode ambiguity and affecting the stability of the entire communication system. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a clock source and an electronic device, aiming to at least solve the problem of how to increase the oscillation frequency of the clock source and avoid ambiguity in the oscillation mode.

[0005] To achieve the above objectives, an embodiment of the present application provides a clock source, comprising: a plurality of inverter chain loops, wherein the plurality of inverter chain loops include a main loop and at least two secondary loops, wherein the main loop is coupled with at least two of the secondary loops to establish at least two coupling relationships.

[0006] In addition, to achieve the above-mentioned purpose, an embodiment of the present application further provides an electronic device, which includes the clock source as described above.

[0007] The embodiment of the present application proposes a clock source and electronic device, the clock source comprising: a plurality of inverter chain loops, the plurality of inverter chain loops comprising a main loop and at least two sub-loops, the main loop being coupled with the at least two sub-loops respectively to establish at least two coupling relationships. The clock source provided by the embodiment of the present application is based on the main loop in the inverter chain loop, and by introducing at least two sub-loops that form at least two coupling relationships with the main loop, the oscillation frequency of the main loop can be greatly increased, solving the problem in the related art that the oscillation frequency is too low to meet the communication rate requirements, and also enabling the clock source to stably complete the start-up and continuous oscillation in a specified oscillation mode, overcoming the problem in the related art that the oscillation mode may be ambiguous due to the increase in the number of output phases. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0009] Figure 1 A schematic diagram of the structure of a clock source provided in an embodiment of the present application;

[0010] Figure 2 A schematic diagram of a specific implementation of a clock source provided in an embodiment of the present application;

[0011] Figure 3 A schematic diagram of the relationship between the output phases of a clock source oscillator in oscillation mode 9 provided in an embodiment of the present application;

[0012] Figure 4 A schematic diagram of the relationship between the output phases of a clock source oscillator in oscillation mode 11 provided in an embodiment of the present application;

[0013] Figure 5 A schematic diagram of loop gains of various potential oscillation modes of a clock source provided in an embodiment of the present application without introducing the second sub-loop AL2;

[0014] Figure 6 A schematic diagram of loop gains of various potential oscillation modes of a clock source provided by an embodiment of the present application when a second sub-loop AL2 is introduced;

[0015] Figure 7 A schematic diagram of the distribution of oscillation modes of a clock source provided in an embodiment of the present application when performing a transient Monte Carlo simulation without introducing the second sub-loop AL2;

[0016] Figure 8 A schematic diagram of the distribution of oscillation modes of a clock source provided in an embodiment of the present application when a second sub-loop AL2 is introduced and transient Monte Carlo simulation is performed.

[0017] The realization of the objectives, functional features and advantages of the embodiments of the present application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0018] Description of Figure Numbers:

[0019] 10, main loop; 20, secondary loop; ML, main loop; AL, secondary loop; AL1, first secondary loop; AL2, second secondary loop; D, main loop inverter; A1, first secondary loop inverter; A2, second secondary loop inverter. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0021] In any modern communication system, a clock source is an essential component. Taking optical communication systems as an example, the clock source's oscillation frequency determines the sampling rate of the system's sampling circuits, while the number of phases in the clock source's output signal determines the number of parallel sampling channels in the sampling circuits. Together, these two factors determine the system's data transmission rate.

[0022] With the increasing demand for communication speeds, traditional multi-phase clock sources face challenges in both oscillation frequency and pattern stability. In related clock source designs, a multi-stage cascaded inverter structure is typically used to generate multi-phase oscillation signals. However, as the number of output phases increases, the number of cascaded inverters also increases, resulting in a lower frequency of the oscillation signal generated by the clock source, which cannot meet the communication speed requirements.

[0023] To increase the oscillation frequency of the clock source, the solution adopted in related technologies is to add feed-forward coupling (FFC) technology, which effectively reduces the delay of the single inverter stage and thus increases the oscillation frequency of the clock source. However, as the number of output phases increases, this solution will lead to uncertainty in the oscillation mode of the clock source. That is, the relationship between its output phase and oscillation frequency will change dramatically under process-voltage-temperature (PVT) changes, causing oscillation mode ambiguity and affecting the stability of the entire communication system.

[0024] Based on this, an embodiment of the present application provides a clock source and an electronic device, the clock source comprising: a plurality of inverter chain loops, the plurality of inverter chain loops comprising a main loop and at least two sub-loops, the main loop being coupled with the at least two sub-loops respectively to establish at least two coupling relationships. The clock source provided by the embodiment of the present application is based on the main loop in the inverter chain loop, and by introducing at least two sub-loops that form at least two coupling relationships with the main loop, the oscillation frequency of the main loop can be greatly improved, solving the problem in the related art that the oscillation frequency is too low to meet the communication rate requirements, and also enabling the clock source to stably complete the start-up and continuous oscillation in the specified oscillation mode, overcoming the problem in the related art that the oscillation mode may be ambiguous due to the increase in the number of output phases.

[0025] The clock source and electronic device provided in the embodiments of the present application are specifically described through the following embodiments. First, the clock source in the embodiments of the present application is described.

[0026] The present application embodiment provides a clock source, referring to Figure 1 , Figure 1 A schematic structural diagram of a clock source provided in an embodiment of the present application, wherein the clock source includes: multiple inverter chain loops, wherein the multiple inverter chain loops include a main loop 10 and at least two secondary loops 20, and the main loop 10 is coupled with the at least two secondary loops 20 respectively to establish at least two coupling relationships.

[0027] The clock source provided in this embodiment can be applied to scenarios requiring multi-phase clocks, such as DACs / ADCs based on time-interleaved topologies. Furthermore, the clock source proposed in this embodiment can be a multi-phase clock source based on an inverter chain.

[0028] In this embodiment, both the main loop 10 and the secondary loop 20 are implemented based on an inverter chain. The main loop 10 is connected to different secondary loops 20 in different ways, thereby establishing different coupling relationships.

[0029] In this embodiment, based on the clock source including an inverter chain main loop (Main Loop, ML), at least two inverter chain auxiliary loops (Auxilliary Loop, AL) are introduced to achieve the purpose of both increasing the oscillation frequency of the clock source and avoiding oscillation mode ambiguity.

[0030] As an example, see Figure 2 This embodiment introduces a first inverter chain sub-loop AL1, which forms a first coupling relationship with the inverter chain main loop ML, to significantly increase the oscillation frequency of the inverter chain main loop ML. However, when the number of output phases is too high, several potential oscillation modes may exist, resulting in mode ambiguity. Therefore, in addition to the introduction of the first inverter chain sub-loop AL1, a second inverter chain sub-loop AL2, which forms a second coupling relationship with the inverter chain main loop ML, can be introduced to increase the starting gain of a specific oscillation mode among the several potential oscillation modes. This ensures that the multi-phase clock source can stably start and sustain oscillation in this specific oscillation mode despite PVT fluctuations, thereby resolving the mode ambiguity issue. Furthermore, by adjusting the coupling between AL1, AL2, and ML and the transconductance (gm) ratios of the inverter units in these three loops, the oscillation mode and oscillation frequency of the multi-phase clock source can be adjusted, thereby significantly increasing the flexibility of the oscillation frequency and oscillation mode of the multi-phase oscillator.

[0031] It is understandable that in Figure 2 On the basis of the corresponding examples, it is possible to further introduce a third inverter chain sub-loop AL3 that forms a third coupling relationship with the main loop, a fourth inverter chain sub-loop AL4 that forms a fourth coupling relationship with the main loop, a third inverter chain sub-loop ALn that forms an nth coupling relationship with the main loop, etc., to further enhance the flexibility of the oscillation mode. All of these improvements should fall within the protection scope of this embodiment, and this embodiment does not impose any restrictions on this.

[0032] In some feasible embodiments, the main loop 10 includes a plurality of main loop inverters, and each sub-loop 20 includes a plurality of sub-loop inverters. The number of the main loop inverters is equal to the number of the sub-loop inverters in each sub-loop 20 .

[0033] In this embodiment, the number of inverters included in the main loop 10 and each sub-loop 20 is the same. Although the total number of sub-loop inverters included in different sub-loops 20 is the same, the specific structures of different sub-loops 20 are different due to the different connection relationships between the main loop 10 and different sub-loops 20. That is, different sub-loops 20 may include 2, 3 or more sub-loops respectively. Therefore, the number of inverters included in a single sub-loop in different sub-loops 20 will vary.

[0034] In some feasible embodiments, the number of main-loop inverters and the number of sub-loop inverters in each sub-loop 20 are equal to the number of phases of the clock source.

[0035] In this embodiment, the number of each type of inverter is the same as the number of output phases of the clock source. As an example, when the clock source provided in this embodiment is a 32-phase clock source, the number of main-ring inverters is 32, and the number of sub-ring inverters in each loop 20 is also 32; similarly, when the clock source provided in this embodiment is a 64-phase clock source, the number of main-ring inverters is 64, and the number of sub-ring inverters in each loop 20 is also 64; it should be understood that the number of phases of the clock source provided in this embodiment can be flexibly adjusted according to actual conditions, and this embodiment does not limit this.

[0036] In some feasible embodiments, multiple main-ring inverters are connected end to end in sequence to form a main loop. There is an output node between adjacent main-ring inverters, and each output node is connected to at least two sub-ring inverters.

[0037] In this embodiment, Figure 2 Taking the clock source shown in the figure as an example, multiple main ring inverters D are connected end to end to form the inverter chain main loop ML. There is an output node CLK between each adjacent main ring inverter D. , each output node CLK At least two sub-ring inverters are connected.

[0038] In some feasible embodiments, the secondary loop 20 includes a first secondary loop and a second secondary loop, and the secondary loop inverter includes a first secondary loop inverter for constituting the first secondary loop, and a second secondary loop inverter for constituting the second secondary loop;

[0039] Each output node is connected to at least one first sub-ring inverter and at least one second sub-ring inverter respectively.

[0040] In this embodiment, if Figure 2 As shown, the clock source is a three-ring coupled output 32-phase clock source based on an inverter chain, including an inverter chain main loop ML composed of 32 main-ring inverters D, a first sub-loop AL1 composed of 32 first sub-loop inverters A1, and a second sub-loop AL2 composed of 32 second sub-loop inverters A2. Figure 2 It can be seen that the output node CLK <0> For example, the node is connected to at least one first sub-ring inverter A1 and at least one second sub-ring inverter A2.

[0041] In some feasible embodiments, the above coupling relationship includes a first coupling relationship;

[0042] The first secondary loop is composed of at least two first sub-loops, each of which is composed of a plurality of first secondary loop inverters. The at least two first sub-loops are respectively coupled to the main loop to establish a first coupling relationship.

[0043] In this embodiment, Figure 2 It can be seen that the two ends of the first sub-ring inverter A1 are connected to the output node CLK and output node CLK<i+2> (This is because if the two ends of the secondary ring inverter are connected to the output node CLK and output node CLK<i+1> , it is equivalent to each secondary ring inverter being connected in parallel with each main ring inverter. The first secondary loop is equivalent to a parallel loop of the main loop and cannot play a role in improving the oscillation efficiency of the main loop). By gradually increasing i from 0 to 29, two first sub-loops consisting of 16 first secondary ring inverters A1 can be formed. The two first sub-loops are coupled to the main loop through odd-numbered output nodes and even-numbered output nodes respectively.

[0044] In some feasible embodiments, the first coupling relationship includes: at least two main-ring inverters are included between two output nodes connected to two ends of each first sub-ring inverter.

[0045] In this embodiment, the number of the first sub-loops is determined by the number of main-loop inverters spaced between the two ends of each first sub-loop inverter in the first coupling relationship, such as Figure 2 Taking the 32-phase clock source shown in the figure as an example, the two ends of the first sub-ring inverter A1 are connected to the output node CLK and output node CLK<i+2> , that is, if there are two main-ring inverters D between the two ends of the first sub-ring inverter A1, then the number of the first sub-ring is also two, and the number of the first sub-ring inverters A1 constituting one first sub-ring is 32 / 2=16; if the two ends of the first sub-ring inverter A1 are connected to the output node CLK and output node CLK<i+4> That is, when there are four main-ring inverters D between the two ends of the first auxiliary-ring inverter A1, the number of the first sub-loops is also four, and the number of first auxiliary-ring inverters A1 constituting one first sub-loop is 32 / 4=8. It should be understood that the number of main-ring inverters between the two ends of the first auxiliary-ring inverter can be flexibly adjusted according to actual conditions, and this embodiment does not impose any limitation thereto.

[0046] In some feasible embodiments, the above coupling relationship includes a second coupling relationship;

[0047] The second secondary loop is composed of at least three second sub-loops, each of which is composed of a plurality of second secondary loop inverters. The at least three second sub-loops are respectively coupled with the main loop to establish a second coupling relationship.

[0048] In this embodiment, the interval between the output nodes connected to the two ends of the second sub-ring inverter should be different from the interval between the output nodes connected to the two ends of the first sub-ring inverter in the aforementioned embodiment. In the aforementioned embodiment, the two ends of the first sub-ring inverter A1 are respectively connected to the output nodes CLK and output node CLK<i+2> In this embodiment, both ends of the second sub-ring inverter A2 are connected to the output node CLK and output node CLK<i+3> , where the output node CLK<i+3> It can also be the output node CLK<i+4> , output node CLK<i+5> , or Figure 2 The output node CLK is shown in<i+9> The two ends of the second sub-ring inverter A2 are connected to the output node CLK and output node CLK<i+3> For example, the second sub-loop includes three second sub-loops.

[0049] In some feasible embodiments, the second coupling relationship includes: at least three main-ring inverters are included between two output nodes connected to two ends of each second sub-ring inverter.

[0050] In this embodiment, the number of second sub-loops is determined by the number of main-loop inverters spaced between the two ends of each second sub-loop inverter in the second coupling relationship. At the same time, the second coupling relationship needs to be different from the first coupling relationship.

[0051] As Figure 2 Taking the 32-phase clock source shown in FIG as an example, the two ends of the second sub-ring inverter A2 are connected to the output node CLK and output node CLK<i+9> , that is, when there are 9 main-ring inverters D between the two ends of the second auxiliary-ring inverter A2, the number of the second sub-loop is at least 9; it should be understood that the number of main-ring inverters between the two ends of the second auxiliary-ring inverter can be flexibly adjusted according to actual conditions, and this embodiment does not limit this.

[0052] It should be understood that the above Figure 2 In the various embodiments described, the number of stages N of the main loop ML, the first sub-loop AL1, and the second sub-loop AL2 is equal, and the specific number of stages is not limited to Figure 2 N = 32 levels shown, Figure 2 Just as a demonstration of a specific embodiment, N can be equal to any integer greater than 2. Correspondingly, when the value of N is different and the required oscillation mode is different, the connection mode of AL1 and AL2 will also change accordingly, for example Figure 2 AL1 is used to connect CLK and CLK<i+2> AL2 is used to connect CLK and CLK<i+9> , where i+2 and i+9 are only used as Figure 2 The specific embodiment shown is an example of the use of AL1 and AL2, which does not mean that the clock source proposed in the embodiment of the present application can only be applied to N=32, AL1 connected to CLK and CLK<i+2> AL2 connects to CLK and CLK<i+9> Under other feasible correct connection modes, the multi-phase clock source based on multi-ring coupling proposed in this embodiment still has the effect of increasing the oscillation frequency and eliminating mode ambiguity, and therefore should be included in the protection scope of this embodiment.

[0053] Based on the above embodiments, this embodiment uses a 32-phase clock source to perform simulation tests and obtains the following results: Figure 3 and Figure 4 The diagram of the relationship between the output phases of the 32-phase clock source oscillation in different modes is shown in FIG. Figure 5 and Figure 6 The loop gain diagram of each potential oscillation mode is shown in FIG. Figure 7 and Figure 8 Schematic diagram of transient Monte Carlo simulation results for mode ambiguity elimination.

[0054] in, Figure 3 and Figure 4 It shows that when the main loop ML and the first sub-loop AL1 are coupled to each other, the oscillation gains of oscillation mode 9 (mode-9) and oscillation mode 11 (mode-11) are similar, which leads to the problem of mode ambiguity. Figure 3 It can be seen that when the clock source oscillates in mode-9, if the output signal CLK <9> Coupled to CLK through the second sub-loop inverter A2 <0> The second sub-loop AL2 is formed, which can increase CLK <0> The vector amplitude of the mode-9 oscillation gain is increased; at the same time, when the clock source oscillates in mode-11, if the output signal CLK <9> Coupled to CLK through the second sub-loop inverter A2 <0> The second sub-loop AL2 is formed, which can reduce CLK <0> The vector amplitude of mode-11 is reduced, that is, the oscillation gain of mode-9 is reduced. Through the above means, the oscillation gain of mode-9 can be greatly improved, and the oscillation gain of mode-11 can be greatly improved, thereby significantly improving the oscillation stability of mode-9 during the oscillation start-up phase of the 32-phase clock source shown in this embodiment.

[0055] In order to more intuitively illustrate the technical effects of this embodiment, Figure 5 and Figure 6 The influence of the second sub-loop AL2 on various potential oscillation modes is shown. Figure 5 is the loop gain of each potential oscillation mode when only the main loop ML and the first sub-loop AL1 are coupled to each other. Figure 5 It can be seen that no matter the injection intensity of the first secondary loop AL1 ( Figure 5 However, once the second sub-loop AL2 is introduced to couple with the main loop ML, the loop gain of the mdoe-9 oscillation mode can be greatly improved, thereby widening the gap with the loop gain of other oscillation modes, ensuring that mode-9 can quickly form oscillations during the start-up phase and eventually form a stable oscillation mode. Figure 6 The situation shown.

[0056] Further, Figure 7 and Figure 8 From the perspective of transient Monte Carlo simulation, the effectiveness of the second sub-loop AL2 in eliminating mode ambiguity is further demonstrated. Figure 7 It shows that in the absence of the second secondary loop AL2, the final oscillation mode has four potential states, namely mode-8, mode-9, mode-10 and mode-11, which is consistent with the above Figure 5 The expected results are shown in Figure 2. In contrast, when the second sub-loop AL2 is added, the 200 transient Monte Carlo simulation results show that the oscillation is stable in mode-9, which is consistent with the above Figure 6 Expected results shown.

[0057] In addition, an embodiment of the present application also provides an electronic device, which includes the clock source provided by the above embodiment.

[0058] The electronic device proposed in this embodiment and the clock source proposed in the above embodiments belong to the same technical concept. For technical details not fully described in this embodiment, please refer to any of the above embodiments, and this embodiment has the same beneficial effects as the above clock source embodiments.

[0059] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0060] In addition, in the embodiments of the present application, descriptions involving "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, "multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the meaning of "and / or" appearing throughout the text is to include three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme in which both A and B are satisfied.

[0061] In the embodiments of the present application, unless otherwise expressly specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean internal communication between two elements or an interaction relationship between two elements, unless otherwise expressly limited. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0062] It should also be understood that references to "one embodiment" or "some embodiments" in the description of the embodiments of this application mean that one or more embodiments of the embodiments of this application include the specific features, structures, or characteristics described in conjunction with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" that appear in different places in this description do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0063] It should be noted that the technical solutions of the various embodiments of the present application can be combined with each other, but it must be based on the fact that technical personnel in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.

[0064] The above are only optional embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.

Claims

1. A clock source, characterized in that: The clock source includes: a plurality of inverter chain loops, the plurality of inverter chain loops include a main loop and at least two sub-loops, the main loop is coupled with the at least two sub-loops respectively, and at least two coupling relationships are established.

2. The clock source according to claim 1, wherein: The main loop includes a plurality of main loop inverters, and each of the secondary loops includes a plurality of secondary loop inverters. The number of the main loop inverters is equal to the number of the secondary loop inverters in each of the secondary loops.

3. The clock source according to claim 2, wherein: A plurality of the main-ring inverters are connected end to end in sequence to form the main loop. There is an output node between adjacent main-ring inverters, and each output node is connected to at least two of the sub-ring inverters.

4. The clock source according to claim 3, wherein: The secondary loop includes a first secondary loop and a second secondary loop, and the secondary loop inverter includes a first secondary loop inverter for constituting the first secondary loop and a second secondary loop inverter for constituting the second secondary loop; Each of the output nodes is respectively connected to at least one of the first sub-ring inverters and at least one of the second sub-ring inverters.

5. The clock source according to claim 4, wherein: The coupling relationship includes a first coupling relationship; The first secondary loop is composed of at least two first sub-loops, each of which is composed of a plurality of first secondary loop inverters. The at least two first sub-loops are respectively coupled with the main loop to establish the first coupling relationship.

6. The clock source according to claim 5, wherein: The first coupling relationship includes: at least two main-ring inverters are included between the two output nodes connected at both ends of each first sub-ring inverter.

7. The clock source according to claim 4, wherein: The coupling relationship includes a second coupling relationship; The second secondary loop is composed of at least three second sub-loops, each of which is composed of a plurality of second secondary loop inverters. The at least three second sub-loops are respectively coupled with the main loop to establish the second coupling relationship.

8. The clock source according to claim 7, wherein: The second coupling relationship includes: at least three main-ring inverters are included between the two output nodes connected at both ends of each second sub-ring inverter.

9. The clock source according to any one of claims 2 to 8, wherein: The number of the main loop inverters and the number of the secondary loop inverters in each of the secondary loops are equal to the number of phases of the clock source.

10. An electronic device, characterized in that: The electronic device comprises the clock source according to any one of claims 1 to 9.

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