High speed receiver for multi-gigahertz operation

Abstract

The invention relates to a high speed receiver for multi-gigahertz operation. Methods, systems, and apparatus provide techniques for an input receiver of an input / output (I / O) circuit operable to communicate data. An input receiver includes an analog front end configured to receive an analog differential input signal from outside the I / O circuit. The analog front-end includes a cascode circuit having a differential input configured to receive the analog differential input signal and to provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range. The input receiver further includes a bias circuit configured to control a bias voltage of the cascode circuit; and cascaded inverter-based stages electrically coupled to the analog front end to receive the front end differential output signal and output an equalized differential signal representative of received data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 564,958, filed on March 13, 2024, entitled “HIGH SPEED RECEIVER FOR MULTI-GIGA HERTZ OPERATIONS,” the contents of which are incorporated by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure relates to one or more systems and circuits for memory, including input / output (I / O) circuit technology for input receivers used in high-speed data communication operations. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. Information can also be erased from a memory cell and new information can be stored in the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and the like. Memory cells can be described as being in a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for an extended period of time, even in the absence of an external power source. Memory cells configured in a volatile configuration can lose their stored state when disconnected from an external power source. Summary of the Invention

[0006] In one aspect, the present disclosure provides an input receiver of an I / O circuit operable to communicate data, the input receiver comprising: an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end comprises: a cascode circuit having a differential input configured to receive the analog differential input signal and provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable within a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and cascaded inverter-based stages electrically coupled to the analog front end to receive the front-end differential output signal and output a balanced differential signal representing the data.

[0007] On the other hand, the present disclosure provides an input receiver of an I / O circuit operable to communicate data, the input receiver comprising: an analog front end configured to receive an analog differential input signal from outside the I / O circuit and provide a front-end differential output signal based on the received analog differential input signal, the analog front end being operable within a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the analog front end; and cascaded inverter-based stages electrically coupled to the analog front end to receive the front-end differential output signal and output a balanced differential signal representing the data, wherein at least two of the cascaded inverter-based stages include resistive feedback.

[0008] On the other hand, the present disclosure provides a memory device comprising: an I / O circuit having an input receiver, the input receiver including an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end includes: a cascode circuit having a differential input configured to receive the analog differential input signal and provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and cascaded inverter-based stages electrically coupled to the analog front end to receive the front-end differential output signal and output a balanced differential signal representing the data; a memory array coupled to the I / O circuit to receive and transmit data; and a memory controller configured to control the memory array and the I / O circuit.

[0009] On the other hand, the present disclosure provides a system comprising: a processor; a first memory controller; and a memory device coupled to at least one of the processor and the first memory controller, wherein the memory device comprises: an I / O circuit having an input receiver, the input receiver comprising an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end comprises: a cascode circuit having a differential input configured to receive the analog differential input signal and provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and cascaded inverter-based stages electrically coupled to the analog front end to receive the front-end differential output signal and output a balanced differential signal representing the data; a memory array coupled to the I / O circuit to receive and transmit data; and a second memory controller configured to control the memory array and the I / O circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and 1B Examples of host systems and memory systems supporting techniques for high-speed data operations according to examples as disclosed herein are described.

[0011] Figure 1C is a block diagram of a memory device in communication with a memory system controller of a memory system according to examples as disclosed herein.

[0012] Figures 2A to 2C is an illustrative schematic diagram of a portion of a memory cell array in a memory device according to examples as disclosed herein.

[0013] Figure 2D Examples of memory devices including multiple blocks of memory cells according to examples as disclosed herein are described.

[0014] Figure 3 is a block diagram of an example device for implementing one or more systems and for performing one or more methods described herein according to examples as disclosed herein.

[0015] Figure 4 is a block diagram of an example memory device with an input receiver according to examples as disclosed herein.

[0016] Figure 5A is a circuit diagram illustrating a common-source circuit and a cascode circuit according to examples as disclosed herein.

[0017] Figure 5Bis a circuit diagram of an analog front end with a folded cascode circuit according to examples as disclosed herein.

[0018] Figure 6 A circuit diagram illustrating a bias circuit configured to control a bias voltage of an analog front end circuit according to examples as disclosed herein.

[0019] Figure 7A is a block diagram of an inverter-based stage and associated gain profiles according to examples as disclosed herein.

[0020] Figure 7B is a block diagram of an inverter-based stage with a pair of cross-coupled inverters according to examples as disclosed herein.

[0021] Figure 7C The gain profile of an inverter-based stage having a pair of cross-coupled inverters according to examples as disclosed herein is illustrated.

[0022] Figure 8A is a block diagram of an inverter-based stage with a cascade of cross-coupled inverter pairs according to examples as disclosed herein.

[0023] Figure 8B Gain profiles of inverter-based stages having cascades of cross-coupled inverter pairs according to examples as disclosed herein are illustrated.

[0024] Figure 8C are illustrative signal waveforms for an analog front end with and without a cascode circuit according to examples as disclosed herein. DETAILED DESCRIPTION

[0025] Memory devices typically include input / output (I / O) circuitry for receiving and / or transmitting data at high speeds, such as in the multi-gigahertz frequency range. For example, data may be communicated between the memory device and a host system at speeds of 3.6 gigatransfers per second (GT / s) or higher. Transmitting data at such high speeds places significant demands on the memory device's input receivers. The input receivers receive high-speed analog differential signals representing the data. The input receivers include analog front ends for receiving such high-speed analog differential signals. The input receivers may amplify, filter, and / or perform other processing on the received analog differential signals. The input receivers then provide output differential or single-ended signals for downstream processing, such as digitization and clock recovery.

[0026] Existing input receivers can be bandwidth-limited due to the high gate resistance caused by the Miller effect and its pole. The pole frequency is the frequency at which the system's transfer function approaches infinity. The location of the input receiver's pole determines how quickly the input receiver can respond to an input signal and whether it remains stable. Under high-speed operation, existing input receivers may not respond quickly enough to the input signal and may become unstable. Furthermore, when the input receiver's power supply varies (which is sometimes unavoidable), the common-mode shift and trip point shift of the front-end output signal may not be equal, resulting in duty cycle distortion.

[0027] The techniques and circuits described herein provide an input receiver that uses a cascode circuit to receive high-speed differential input signals. The cascode circuit can be configured to reduce the Miller effect of existing input receivers, thereby reducing gate resistance effects and increasing the bandwidth of the input receiver. The cascode circuit used in the analog front end further implements continuous time linear equalization (CTLE) to provide a balanced differential output signal representing the data. As a result, the differential output signal can have a better eye opening, thereby improving signal quality and integrity within the multi-gigahertz transmission operating range. The cascode circuit can enable the input receiver to have higher bandwidth and higher transmission speeds without increasing the layout area and power of the input receiver, or at least without increasing the layout area and power of the input receiver.

[0028] The techniques and circuits described herein further provide an input receiver using cascaded inverter-based stages. The inverter-based stage (also known as an active inductor stage) can be coupled to receive a differential output signal from an analog front end. The inverter-based stage can further amplify the front-end differential output signal. The cascaded inverter-based stage includes multiple inverter-based stages cascaded in series. The cascaded inverter-based stage can provide higher amplification gain than a single inverter-based stage. By using cascaded inverter-based stages, the zero and pole frequencies of the input receiver can be extended without increasing or significantly increasing power consumption. As described above, the pole frequency is the frequency at which the system's transfer function approaches infinity. And the zero frequency is the frequency at which the system's transfer function approaches zero. Therefore, extending the zero and / or pole frequencies of the input receiver effectively extends the input receiver's passband, thereby increasing the bandwidth. The techniques and circuits are further described in more detail below.

[0029] Figure 1AAn example of a system 100 supporting techniques for high-speed data operations according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0030] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0031] System 100 may include a host system 105, which may be coupled to memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause host system 105 to perform various operations according to examples as described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. Host system 105 may be comprised of, for example, Figure 3 10. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1A One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0032] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of a physical host interface can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a Graphics Double Data Rate (GDDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled with the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled with the memory system controller 115).

[0033] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1A , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0034] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130—as well as other such operations—which can generally be referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0035] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background flushing, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0036] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0037] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115.

[0038] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetically controlled RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0039] In some examples, the memory devices 130 may include a local controller 135 (e.g., on the same semiconductor die or within the same package) that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1A As described in the examples described in this disclosure (e.g., Figure 1CIn the example shown in FIG, local controller 135 is disposed on the same semiconductor die as the memory array (e.g., array 104), and separate memory system controller 115 is disposed on a different die. In other examples, some portions of memory device 130 may be disposed on a first die, and other portions of memory device 130 may be disposed on a second die different from the first die. For example, the first die may include memory cell array 104 and its associated circuitry, such as column decoder 111 and row decoder 108. The second die may include the logic circuitry, power circuitry, or other circuitry of device 130. Thus, the second die may include system controller 115, I / O control 112, etc. In this example, the first die does not have a local controller, and the second die includes system controller 115. The first and second dies may be hybrid-bonded together using, for example, through-hole vias (TSVs) to electrically connect them. The first and second dies may also be wafer-bonded using flip-chip bonding techniques. In this disclosure, for simplicity, the memory system controller 115 and the local controller 135 may be referred to as memory controllers, or as the first memory controller and the second memory controller. It should be understood that although they may be different controllers, certain operations disclosed herein may be initiated or performed by either or both memory controllers unless otherwise specified.

[0040] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a semiconductor die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more dies 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding memory blocks 170, where each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0041] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLCs) if configured to store two bits of information each, three-level cells (TLCs) if configured to store three bits of information each, quad-level cells (QLCs) if configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0042] In some cases, a plane 165 may refer to a group of memory blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual memory blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0043] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled to a common word line), and memory cells in the same string can share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line). Example memory cell structures are shown in more detail below using illustrative schematics.

[0044] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof), but can be erased at a second granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single program or read operation), while a memory block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they are overwritten with new data. Thus, for example, in some cases, a used page 175 is not updated until the entire block 170 containing the page 175 has been erased.

[0045] In some cases, an L2P (logical to physical) mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data, which may be due to a more recent or updated version of the data being stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address (e.g., a logical address referenced by the host system 105). Valid data may be the most recent version of this data stored on the memory device 130. A page 175 containing no data may be a page 175 that has never been written to or has been erased.

[0046] In some cases, the memory system 110 may utilize a memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller, such as a local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0047] The system 100 may include any number of non-transitory computer-readable media that support techniques for logical-to-physical table compression. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0048] In some cases, the memory system 110 may compress the L2P map to expand the number of physical addresses mapped by the L2P map. For example, if a set of consecutive entries of an uncompressed L2P map includes consecutive physical addresses, the memory system 110 may compress the consecutive entries into a single entry that includes a starting physical address from among the consecutive physical addresses. Additionally, the memory system 110 may include an indication of a starting logical address corresponding to the starting physical address in the compressed entry. To identify a physical address within the compressed entry, the memory system 110 may use the indication to determine an offset between a logical address corresponding to the physical address (e.g., a logical address included in a read command for data stored at the physical address) and the starting physical address, and may apply the offset to the starting physical address to determine the physical address. Compressing the L2P map may allow the L2P map to cover an expanded range of the physical address space without increasing the size of the L2P map.

[0049] Figure 1B The illustration shows an example of a system diagram 101 for communicating between a host system 105 and a memory system 110 through the use of a kernel and firmware according to examples as disclosed herein. The system diagram 101 may include the memory system 110, the kernel 107, and the application 109. The memory system 110 may include firmware 119. The firmware 119 may be implemented by a controller and / or other circuitry of the memory system (e.g., Figure 1A 10 and / or local controller 135). In some examples, system 123 as described herein may include memory system 110 and kernel 107. Additionally, host system 105 may include kernel 107 and application 109.

[0050] As described above, the memory system 110 may include multiple memory devices configured to store and retrieve data, including non-volatile memory devices and volatile memory devices (e.g., local memory 120). Firmware 119 may refer to software stored in a memory array within the memory system 110 (e.g., a non-volatile memory device within the memory system 110) and / or within the local memory 120, such as Figure 1A . The firmware 119 may provide low-level control functions for the memory system 110. For example, the firmware 119 may serve as an interface between the memory system 110 and other components of the system 123, and the host system 105 may issue access operations to the memory system 110 by interfacing with the firmware 119. In some examples, the firmware 119 may be included within or implemented by the memory system controller 115, as described herein with reference to Figure 1A In some examples, the memory system 110 may store a logical-to-physical (L2P) mapping within the non-volatile memory device (e.g., in a logical-to-physical table), which maps logical addresses to physical addresses. To perform a memory access operation, the memory system 110 may move a portion of the logical-to-physical mapping corresponding to one or more logical addresses (e.g., as indicated by the kernel 107) from the non-volatile memory device to the volatile memory device.

[0051] The kernel 107 may serve as an interface between the host system 105 and components associated with the host system 105 (e.g., the operating system of the host system 105). Furthermore, the kernel 107 may perform resource allocation and file management, among other operations, for the host system 105. For example, an application 109 running within the host system 105 may access information stored in the memory system 110 by issuing commands to the kernel 107. The information may indicate a file to be accessed. The kernel 107 may store mapping information associated with the file. For example, a file may be associated with a file name and may correspond to a range of logical block addresses. The kernel 107 may store mapping information (e.g., a mapping table) that tracks the logical block addresses corresponding to the files of the host system 105. In some examples, the application 109 may issue an access command to the kernel 107 indicating the file name, offset, and length associated with the file to be accessed, and the kernel 107 may retrieve one or more logical block addresses corresponding to the file to be accessed. The kernel 107 may then communicate with the firmware 119 to indicate the one or more logical block addresses to the memory system 110, and the memory system 110 may perform access operations based on the one or more logical block addresses.The memory system 110 may communicate the accessed information to the kernel 107 (eg, via the firmware 119).

[0052] In some examples, the kernel 107 may communicate with the firmware 119 using information units (e.g., UFS protocol information units (UPIUs)). For example, the kernel 107 may issue or receive commands, responses, data, or other information via information units exchanged with the firmware 119. An information unit may refer to a data packet that may contain a header segment and one or more transaction-specific fields. In some examples, an information unit may additionally include one or more extended header segments, one or more data segments, or a combination thereof. The header segment of an information unit may indicate information associated with the destination of the information unit, the source of the information unit, a function request, whether additional data or parameters are to be transmitted, whether the additional data or parameters are to be included in the information unit or to be sent in a subsequent information unit, or any combination thereof. Depending on the operation associated with the information unit, transaction-specific fields may be used for the additional fields. The data segment may be used to include data to be transferred from one device to another.

[0053] In some examples, a command information unit (e.g., a command UPIU) may be an example of an information unit associated with the transmission of a command (e.g., a SCSI command) and may instruct a device to perform some operation indicated by the command information unit. For example, the command information unit may include a block descriptor (e.g., a command descriptor block) that may indicate information related to the operation indicated by the command information unit. In some examples, the kernel 107 may transmit the command information unit to the memory system 110 to indicate to the memory system 110 the operation to be performed by the memory system 110.

[0054] In some examples, to perform an access operation, the memory system 110 may load an L2P map associated with the information to be accessed. For example, the memory system 110 may transfer a portion of a logical-to-physical map associated with the information to be accessed from a non-volatile memory device (e.g., NAND memory) of the memory system 110 to a volatile memory device (e.g., SRAM) of the memory system 110. In another example, the host system 105 may notify the memory system 110 of a logical block address range corresponding to an upcoming access operation (e.g., before issuing an access command). Before receiving an access command instructing the memory system 110 to perform the access operation, the memory system 110 may use the logical block address range to load (e.g., preload, prefetch) the associated portion of the L2P map (e.g., from the non-volatile memory device to the volatile memory device). As a result, after the host system 105 issues an access command, the memory system 110 may issue a response to the host system 105 more quickly because the memory system 110 has already loaded the relevant portion of the L2P map associated with the access operation.

[0055] The above description of system diagram 101 is an illustrative example of communication between host system 105 and memory system 110 using kernel 107, application 109, and firmware 119. It should be understood that additional communication means (including function calls, commands, responses, messages, etc.) can be implemented using host system 105 and memory system 110 and / or additional systems or components.

[0056] Figure 1C is in accordance with an embodiment with a memory system (e.g., Figure 1A and 1B A simplified block diagram of a memory device 130 communicating with a memory system controller 115 of a memory system 110. Figure 1C As shown in FIG and described in more detail below, the memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. The memory cells of a logical row are typically connected to the same access line (e.g., a word line), while the memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the memory cell array 104 ( Figure 1C ) can be programmed into one of at least two target data states for storing any number of bits of information.

[0057] Continue to refer Figure 1C , row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from memory device 130. Address registers 114 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 111 to latch address signals prior to decoding. Row decoding circuitry 108 and column decoding circuitry 111 may be referred to simply as row decoder 108 and column decoder 111, respectively. Command register 124 communicates with I / O control circuitry 112 and local controller 135 to latch incoming commands.

[0058] A memory controller (e.g., a local controller 135 within the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory system controller 115. That is, the local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 111 to control the row decoding circuitry 108 and the column decoding circuitry 111 according to addresses.

[0059] Local controller 135 also communicates with cache registers 118 and data registers 121. In some embodiments, one or more cache registers 118 may collectively form at least a portion of a cache buffer. Cache registers 118 latch or buffer data (incoming or outgoing) as directed by local controller 135 to temporarily store data while memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; the new data from I / O control circuitry 112 may then be latched in cache register 118. During a read operation, data may be transferred from cache register 118 to I / O control circuitry 112 for output to memory system controller 115; the new data may then be transferred from data register 121 to cache register 118. In some embodiments, cache register 118 and / or data register 121 may form at least a portion of page buffer 152 of memory device 130. The page buffer 152 may further include a sensing device (e.g., a sense amplifier) ​​to sense the data state of a memory cell of the memory cell array 104, for example, by sensing the state of a data line connected to that memory cell. The status register 122 may communicate with the I / O control circuitry 112 and the local memory controller 135 to latch status information for output to the memory system controller 115.

[0060] like Figure 1C, memory device 130 receives various control signals from memory system controller 115 via local controller 135 over control link 132. For example, the control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protect signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received over control link 132. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory system controller 115 over a multiplexed input / output (I / O) bus 134, and outputs the data to memory system controller 115 over I / O bus 134.

[0061] For example, a command may be received at I / O control circuitry 112 over input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address may be received at I / O control circuitry 112 over input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data may be received at I / O control circuitry 112 over input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data may then be written to data register 121 for use in programming memory cell array 104.

[0062] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference may be made to I / O pins, they may include any conductive node, such as a commonly used conductive pad or conductive bump, that provides an electrical connection to memory device 130 by an external device (e.g., memory system controller 115). Although the above description uses a 16-bit I / O bus 134 as an example, it should be understood that bus 134 may be configured for any number of bits (e.g., 64 bits).

[0063] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1C It will be appreciated that the reference Figure 1CThe functionality of the various block components described may not necessarily be separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1C Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1C Additionally, while specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0064] Figures 2A to 2B FIG. 1 is an example diagram of a portion of a memory cell array 200A (eg, a NAND memory array). According to an embodiment, the memory cell array 200A may be as shown in FIG. Figure 1C An example of a memory array 104 of a memory device 130 is depicted. Memory array 200A includes access lines (e.g., word lines 2020 through 202 N ) and data lines (eg, bit lines 2040 to 204 M ). The word lines 202 may be connected to the Figure 2A For some embodiments, memory array 200A may be formed over a semiconductor that may be doped to have a conductivity type such as p-type conductivity, such as to form a p-well, or to have n-type conductivity, such as to form an n-well.

[0065] The memory array 200A can be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 may represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 may be connected in series at a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 2101). M (eg, it may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 ) (for example, it may be a drain select transistor, often referred to as a select gate drain). M2. Select gates 210 and 212 may be commonly connected to a select line 214 (e.g., a source select line (SGS)), and select gates 2120 through 212M may be commonly connected to a select line 215 (e.g., a drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 may utilize a structure similar to (e.g., the same as) memory cell 208. Select gates 210 and 212 may represent a plurality of select gates connected in series, with each select gate configured in series to receive the same or independent control signals.

[0066] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of a corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0067] The drain of each select gate 212 can be connected to the bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0068] Figure 2A The memory array 200A in can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204 (which can be substantially parallel to the plane including the common source 216).

[0069] The typical construction of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as Figure 2A. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cells 208 have their control gates 236 connected to (and in some cases forming) the word line 202.

[0070] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may generally be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 may be commonly connected to a word line 202. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be one physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 are commonly connected to the word line 202. N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of memory cells 208 (eg, odd memory cells).

[0071] although Figure 2A The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is apparent from the figure that the bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204. M . Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all of the memory cells commonly connected to a given word line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which in some embodiments may still be an entire row) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 202. NAll memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells. A logical page may or may not be the same as a physical page. Although discussed in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0072] Figure 2B As reference Figure 1B Another schematic diagram of a portion of a memory cell array 200B that may be used in the described memory device (eg, as part of memory cell array 104). Figure 2B The same numbered elements in the corresponding Figure 2A Description provided. Figure 2B Additional details are provided for one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as the channel region of the memory cells of the NAND string 206. The NAND strings 206 can each be selectively connected to bit lines 2040 through 204 through select transistors 212 (e.g., which can be drain select transistors, often referred to as select gate drains). M , and are selectively connected to a common source 216 through a select transistor 210 (e.g., which may be a source select transistor, often referred to as a select gate source). Multiple NAND strings 206 may be selectively connected to the same bit line 204. A subset of NAND strings 206 may be selectively connected to the same bit line 204 by biasing select lines 2150 to 215 K 2. The word lines 202 are connected to their respective bit lines 204 to selectively activate a particular select transistor 212 between the NAND string 206 and the bit line 204. The select transistors 210 can be activated by biasing the select line 214. In some embodiments, each sub-block or string of memory cells has a separate select line 214 from the other sub-blocks or strings. In some embodiments, a pair of sub-blocks share a select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells that are typically connected to each other by a particular word line 202 can be collectively referred to as a level.

[0073] The three-dimensional NAND memory array 200B may include multiple stacked layers of memory cell levels connected using vertical channels (e.g., semiconductor pillars). The number of layers in the three-dimensional NAND memory array 200B may be, for example, 32, 48, 64, 96, 112 layers, or any other number of layers. In some examples, groups of layers may be collectively referred to as a stack. The stacks in a three-dimensional NAND memory array may be processed together (e.g., etched together to form a portion of a semiconductor pillar). A memory device having a three-dimensional NAND memory array may provide more memory cells on a single chip than a memory device formed from a two-dimensional NAND array, and thus provide higher storage capacity. Furthermore, in a memory device having a three-dimensional NAND memory array, the transistors in the memory cells are isolated, thereby reducing interference and electron leakage.

[0074] As described above, memory cells can be grouped into memory blocks. Figure 2C Depicts grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500-250 L . A memory cell block 250 can be a grouping of memory cells 208 that can be erased together in a single erase operation. A group of memory cells that can be erased together is also referred to as an erase block. Each memory cell block 250 can represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The common source 216 of the memory cell block 250 can be the same as the common source 216 of the memory cell block 250. L For example, each memory cell block 2500 to 250 L The access line 202 and the select lines 214 and 215 of one memory cell block 250 may not be directly connected to the memory cell blocks 250 to 250, respectively. L The access line 202 and the select lines 214 and 215 of any other memory cell block in the memory cell block are connected.

[0075] Bit lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to the buffer portion 240, which may be part of the page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (eg, the group of memory cell blocks 2500 to 250 L Buffer portion 240 may include sensing circuitry (which may include a sense amplifier) ​​for sensing the data value indicated on the corresponding bit line 204 .

[0076] Figure 2D is a block diagram of a portion of an example memory cell array 260. The memory cell array 260 may be used as a reference Figure 1C Array 104 in the depicted memory device 130. Memory cell array 260 is depicted as having four memory planes 261 (eg, memory planes 261a through 261d). Each of the memory planes 261 may correspond to Figure 1A Each memory plane 261 can communicate with a corresponding buffer portion 240, which can collectively form a page buffer 262. The page buffer 262 can be used to implement Figure 1C . Although four memory planes 261 are depicted, other numbers of memory planes 261 may generally communicate with the page buffers 262. Each memory plane 261 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 through 2501). L ).

[0077] Continue to refer Figure 1C and 2A During a true erase operation (during which memory cells are actually erased), the local controller 135 (eg, using the erase operation manager 137) may select gates 2100 to 210C. M (SGS transistor) is turned on using an erase pulse causing the common source voltage line (e.g., SRC 216 ( Figure 2A )) ramps up to the erase voltage (Vera). Ramping up to this high bias erase voltage and then recovering from this voltage ramp may require a significant amount of time. Concurrently, the erase operation manager 137 may cause the select gates 2120 to 212 m ( Figure 2A ) is turned off so that the select gates 2120 to 212 m The drain of the bit line 2040 to 204 can float. M Also floated. In addition, the erase operation manager 137 can Figure 2A ) is coupled to ground (e.g., zero volts), or word line 202 is held at a low voltage. This set of voltage levels at memory array 200A can produce erase potentials that cause memory cells 2080-208 N is erased, for example, by forcing electrons to exit through the body of each memory cell and off the floating bit lines 2040 to 204 M In other embodiments, the reverse operation may be performed so that gates 2100 to 210 M is turned off, causing the SRC line 216 to float, while the voltage of the bit line is between select gates 2120 and 212 MWhen turned on, it is ramped to Vera. As mentioned earlier, in 3D NAND, one of the channel region, pillars, or bit lines can also be ramped in voltage to cause the erase of the attached memory cells. Therefore, for simplicity, references to "memory lines" herein should be understood as references to either the SRC line or the bit line in 2D NAND, or to either the channel, pillar, or bit line in 3D NAND. In some embodiments, one or more sub-blocks of memory cells are erased during the same true erase operation to comprise a physical block. A block of memory cells can generally be understood to comprise four or more sub-blocks, where each sub-block comprises a separate string of memory cells.

[0078] Figure 3 A high-level block diagram of an example device 300 that can be used to implement the systems, devices, and methods described herein is illustrated in FIG. It should be understood that the various systems, devices, and methods described herein can be implemented using analog and / or digital circuitry, or using one or more computers using well-known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory systems for storing instructions and data. A computer may also include or be coupled to one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, and the like.

[0079] The various systems, devices, and methods described herein can be implemented using computers operating in a client-server relationship. Typically, in such a system, a client computer is remotely located from a server computer and interacts via a network. The client-server relationship can be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers can include desktop computers, workstations, laptop computers, cellular smartphones, tablet computers, or other types of computing devices.

[0080] The various systems, devices, and methods described herein may be implemented using a computer program product tangibly embodied in an information carrier (e.g., in a non-transitory machine-readable storage device) for execution by a programmable processor; and the method processes and steps described herein (including one or more steps of at least some of Figures 1 to 8C) may be implemented using one or more computer programs executable by such a processor. A computer program is a set of computer program instructions that can be used directly or indirectly in a computer to perform a certain activity or cause a certain result. A computer program may be written in any form of programming language (including compiled or interpreted languages), and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0081] like Figure 3As shown in FIG. 1 , the apparatus 300 may be used to implement a host system (e.g., Figure 1A ), which includes, is coupled to, or utilizes a memory system (e.g., Figure 1A The device 300 may be used to execute the operations of the controller (eg, to execute an operating system to execute a program corresponding to the Figure 1A operation of the host system controller 106 and / or local controller 135).

[0082] In some embodiments, the apparatus 300 includes a processor 310 operatively coupled to a data storage device 320 and a main memory device 330. The processor 310 controls the overall operation of the apparatus 300 by executing computer program instructions 324 that define such operation. The instructions 324 include instructions for implementing the controller (e.g., Figure 1A The computer program instructions 324 may be stored in a data storage device 320 or other computer readable medium and loaded into the main memory device 330 when execution of the computer program instructions is desired. For example, the processor 310 may be used to implement one or more components and systems described herein, such as the host system controller 106 and / or the local controller 135 ( Figure 1A 1 to 8C ). Thus, at least some of the method steps of Figures 1 to 8C may be defined by computer program instructions 324 stored in the main memory device 330 and / or the data storage device 320, and controlled by the processor 310 executing the computer program instructions 324. For example, the computer program instructions 324 may be implemented as computer executable code programmed by one skilled in the art to perform the algorithms defined by the method steps discussed herein in conjunction with at least some of Figures 1 to 8C. Thus, by executing the computer program instructions, the processor 310 executes the algorithms defined by the method steps of these aforementioned figures to perform operations (e.g., reading, programming, erasing, etc.). The device 300 also includes one or more network interfaces 380 for communicating with other devices via a network. The device 300 may also include one or more input / output devices 390 (e.g., a display, keyboard, mouse, speaker, buttons, etc.) that enable a user to interact with the device 300.

[0083] The processor 310 may include both general-purpose and special-purpose microprocessors and may be the sole processor of the apparatus 300 or one of multiple processors. The processor 310 may include one or more central processing units (CPUs) and one or more graphics processing units (GPUs), which may, for example, operate separately from the one or more CPUs and / or perform multitasking with the one or more CPUs to accelerate processing, such as for the various image processing applications described herein. The processor 310, the data storage device 320, and / or the main memory device 330 may include, be supplemented by, or incorporate one or more application-specific integrated circuits (ASICs) and / or one or more field-programmable gate arrays (FPGAs).

[0084] The data storage device 320 and the main memory device 330 each include a tangible, non-transitory computer-readable storage medium. The data storage device 320 and the main memory device 330 may each include a high-speed random access memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), double data rate synchronous dynamic random access memory (DDR RAM), or other random access solid-state memory devices), and may include a non-volatile memory (e.g., one or more magnetic disk storage devices (e.g., internal hard disk and removable magnetic disk, magneto-optical disk storage device, optical disk storage device), flash memory device (NAND memory device, NOR memory device), semiconductor memory device (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM), digital versatile disk read-only memory (DVD-ROM)), or other non-volatile solid-state storage device). For example, the data storage device 320 may use the memory system 110 described herein ( Figure 1A ) implementation. In some examples, the data storage device 320 and the main memory device 330 may include one or more memory devices 130 ( Figure 1A ).

[0085] Input / output devices 390 may include peripheral devices such as printers, scanners, display screens, etc. For example, input / output devices 390 may include a display device (such as a cathode ray tube (CRT), plasma, or liquid crystal display (LCD) monitor) for displaying information to a user, a keyboard, and a pointing device (such as a mouse or trackball) through which a user can provide input to apparatus 300.

[0086] Any or all of the functionality of the systems and devices discussed herein may be performed by processor 310 and / or incorporated into a device or system (system 100). Additionally, system 100 and / or device 300 may utilize one or more neural networks or other deep learning techniques performed by processor 310 or other systems or devices discussed herein.

[0087] Those skilled in the art will recognize that actual computer or computer system implementations may have other structures and may contain other components as well, and for illustrative purposes, Figure 3 Is a high-level representation of some of the components of this computer.

[0088] Figure 4 is a block diagram of an example memory device 130 having an input receiver 402 according to examples as disclosed herein. The input receiver 402 may be, for example, as described above in conjunction with Figure 1C As described above, the I / O control circuitry 112 may be a portion of the I / O control circuitry 112, or another portion of the I / O circuitry of the memory device 130. Figure 4 As illustrated in FIG, in some examples, the memory device 130 includes an input receiver 402 and other circuitry 480. It should be understood that Figure 4 The memory device 130 shown in FIG. 1 is simplified and may include the above combined Figure 1C Other components described. For example, Figure 4 The other circuit systems 480 shown in the figure may include a memory cell array 104, a column decoder 111, a row decoder 108, one or more registers 114, 122 and 124, a local controller 135, etc., as described above in conjunction with Figure 1C Therefore, these circuit systems will not be described again and will be explained in detail. Figure 4 The other circuit systems may also include components not described above. For example, the other circuit systems 480 may include an analog-to-digital converter (ADC) for converting the analog signal provided by the input receiver 402 into a digital signal for further processing.

[0089] Continue to refer Figure 4 In some embodiments, the input receiver 402 receives a high-speed analog differential input signal 409. Typically, the signal 409 is a data signal and can be transmitted in the multi-gigahertz frequency range. In differential signaling, information is conveyed by the difference between two complementary signals. Differential signaling has the advantage of being able to reject common-mode noise, which is unwanted interference that affects both signal lines equally. Therefore, differential signaling has better noise immunity than single-ended signaling. Differential signaling can also increase the dynamic range of the input receiver 402. Differential signaling is typically used for high-speed data transmission and is less commonly used to transmit low-speed address or control signals. Thus, in Figure 4In FIG. 4 , the analog differential input signal 409 may include the data signal 405 , but does not necessarily include the address signal 403 and the control signal 407 .

[0090] exist Figure 4 In FIG, input receiver 402 includes an analog front end 410 configured to receive an analog differential input signal 409 from outside of input receiver 402 or outside of memory device 130. For example, analog differential input signal 409 may be part of a data signal 405 sent by an external memory controller (e.g., controller 115) or a host. Analog front end 410 processes the analog input differential signal and generates a front-end differential output signal 413. Analog signals represent information as continuously varying voltages, currents, or other physical quantities, while digital signals use discrete values ​​to represent data. In some examples, bias circuit 420 provides bias voltages and / or bias currents to analog front end 410 for setting the appropriate operating point. Analog front end 410 amplifies and / or equalizes analog differential input signal 409 and generates a front-end differential output signal 413, which is an amplified differential signal. Front-end differential output signal 413 is then provided to a cascaded inverter-based stage 430 for further amplification and bandwidth extension. Thus, the cascaded inverter-based stages 430 provide continuous time linear equalization (CTLE) for the input receiver 402. CTLE can be used to mitigate the effects of signal distortion and compensate for the frequency-dependent attenuation and phase distortion of the signal, thereby allowing the input receiver 402 to more accurately recover the original transmitted signal. Figure 4 , the cascaded inverter-based stage 430 thus outputs the balanced differential signal 415 to other circuitry 480 of the memory device 130 or another device for further processing (e.g., digitization, filtering, storage, or other processing). The analog front end 410, bias circuit 420, and cascaded inverter-based stage 430 are described in more detail below.

[0091] As described above, in one example, the analog front end 410 may include a cascode circuit. Figure 5A is a circuit diagram illustrating a common source circuit 510 and a common source common gate circuit 520 for comparison according to an example disclosed herein. Both circuits can be used in an input receiver to receive an input signal. However, the common source circuit 510 has a common source level Miller effect. Figure 5A As shown in FIG, circuit 510 includes a transistor 512, which may be a FET (field effect transistor) or another type of transistor. For illustrative purposes, transistor 512 is shown as an NMOS (n-type metal oxide semiconductor) transistor, but it may also be a PMOS (p-type MOS) transistor. The gate terminal of transistor 512 receives an input analog signal V in The source of transistor 512 is coupled to thess and the drain of transistor 512 is coupled to the electrical ground represented by V cc The circuit 510 also includes a power supply represented by C gd The parasitic gate-drain capacitance represented by C gs The parasitic gate-source capacitor represented by R int The gate resistor represented by R D These components are associated with transistor 512 and the wiring of circuit 510 and may be unintended or undesirable parasitic components (capacitance or resistance) present in circuit 510. The input capacitance of circuit 510 (i.e., the capacitance when looking at the gate terminal of transistor 512) may be as shown in FIG. Figure 5A is calculated as shown in equation [1] below.

[0092] C input1 =C gs +(1+g m R D )C gd [1]

[0093] In equation [1], C input1 represents the input capacitance of circuit 510, C gs represents the gate-source capacitance, C gd represents the gate-drain capacitance, g m represents the gain of transistor 512, and R D represents the gate resistance. Therefore, the input capacitance is the gain g of transistor 512 m The function of gain g m The higher the gate resistance R, the higher the input capacitance. This increase in the input capacitance of transistor 512 is due to the Miller effect, which refers to the increase in the equivalent input capacitance of an amplifier or transistor when there is a voltage gain between the input and output terminals. The Miller effect, in turn, increases the time constant of circuit 510 because the time constant is the gate resistance R. int With input capacitor C input1 The product of , as shown below in equation [2].

[0094] τ1=R int C input1 [2]

[0095] In the above equation [2], τ1 represents the time constant, C input1 represents the input capacitance of circuit 510, and R int represents the gate resistance. An increase in the time constant reduces the bandwidth of circuit 510 and, in turn, the bandwidth of the input receiver.

[0096] To mitigate the Miller effect of the common-source circuit 510, a cascode circuit 520 may be used. The cascode circuit 520 includes two transistors 522 and 524 connected in series. Figure 5A The cascode circuit 520 is illustrated using NMOS transistors, but PMOS or other types of transistors can also be used to form the cascode circuit. In the circuit 520, the source terminal of the transistor 522 is coupled to the V ss The drain terminal of transistor 522 is coupled to the source terminal of transistor 524; and the gate terminal of the transistor receives the input signal V in The gate terminal of transistor 524 is coupled to another bias circuit to receive a bias voltage V bias The drain terminal of transistor 524 is coupled to the V cc Also shown are the parasitic components of circuit 520, including the parasitic gate-drain capacitor C gd , parasitic gate-source capacitor C gs , gate resistor R int and drain resistor R D The input capacitance C of the cascode circuit 520 is input2 like Figure 5A is calculated as shown in equation [3] below.

[0097]

[0098] In the above equation [3], C input2 represents the input capacitance of the cascode circuit 520, C gs represents the gate-source capacitance, C gd represents the gate-drain capacitance, g m1 represents the gain of transistor 522, g m2 represents the gain of transistor 524, and R D The time constant τ2 of the cascode circuit 520 can be calculated using equation [4] as follows.

[0099] τ2=R int C input2 [4]

[0100] Based on equations [3] and [4] above, the Miller effect of the common source circuit 510 can be mitigated by using a cascode circuit 520. The input capacitance of the circuit 520 is the gain of the transistor 522 (given by g m1 ) and the gain of transistor 524 (denoted by g m2 Therefore, by properly configuring the gain ratio of the two transistors 522 and 524, the input capacitance C input2Can be set to be much smaller than C input1 Conversely, the time constant τ2 of the cascode circuit 520 can be greatly reduced compared to the time constant τ1 of the common-source circuit 510. Therefore, the cascode circuit 520 can enable the input receiver to have a higher bandwidth and improved high-frequency performance.

[0101] Figure 5B yes Figure 4 FIGURE 4 is a circuit diagram of an analog front end 410 that can be used in an input receiver 402 as shown in FIGURE 4. The analog front end 410 includes a folded cascode circuit having an input transistor pair 532a-532b (collectively, input transistor pair 532), cascode transistors 534a-534b (collectively, cascode transistors 534), and other bias and / or current source transistors (e.g., 536a-536b, 538, 542, 544, 546, 548, 552). The folded cascode circuit is an extension of the cascode circuit 520 described above and can include two or more cascode stages connected in a folded arrangement. Each cascode stage includes a series combination of transistors, typically consisting of a lower transistor (common emitter or common source transistor) that acts as an input device and an upper transistor (common base or common gate transistor) that acts as a cascode device. In a folded cascode arrangement, the output of the first cascode stage is folded back and connected to the input of the subsequent cascode stage. This creates a series connection of cascaded cascode stages, thereby achieving a reduced Miller effect and improved bandwidth of the input receiver. Figure 5B In the arrangement shown in , the input transistor pair 532a-532b is a first cascode stage, and the output signal 533a-533b of the first cascode stage is folded and connected to the input of a second cascode stage comprising cascode transistors 534a-534b.

[0102] exist Figure 5B In the example shown in FIG, the analog front end 410 has an input transistor pair 532a and 532b (collectively referred to as input transistor pair 532). The input transistor pair 532 is configured to receive an analog differential input signal V at its gate terminals from an input receiver or external I / O circuit (e.g., from a memory system controller). inp 531a and V inn 531b (e.g., corresponding to Figure 4 ). Figure 5BIn the example shown in , the input transistor pair 532 includes PMOS (p-type metal oxide semiconductor) transistors. The gate terminals of the input transistor pair 532 receive the analog differential input signal. The source terminals of the input transistor pair 532 are coupled to the power supply (represented by pn_Vcc) via transistors 538 and 542. The drain terminals of the input transistor pair 532 are folded and connected to the source terminal of the cascode transistor 534. It should be understood that with appropriate configuration changes of the cascode transistors, the input transistor pair 532 may also be NMOS transistors or other types of transistors. The use of PMOS or NMOS transistors of the input transistor pair 532 depends on the common mode voltage of the input signal and possible other factors. For example, when the common mode voltage of the input signal may have a range close to the ground voltage (represented by Figure 5B V in ss PMOS transistors can be used when the common mode voltage of the input signal can have a range close to the power supply voltage (represented by Figure 5B NMOS transistors can be used when (represented by pn_Vcc in ).

[0103] The differential output signal V from the input transistor pair 532 outn1 533a and V outp1 533b is folded and connected to the source terminals of cascode transistors 534a and 534b, respectively; and to the drain terminals of current source transistors 536a and 536b, respectively. Cascode transistors 534a and 534b have a common gate terminal. The drain terminal of cascode transistor 534 provides the output differential signal of analog front end 410 and is coupled to a power supply represented by pn_Vcc via bias and / or current source transistors 544, 546, 548, and 552, as shown. Figure 5B The source terminals of cascode transistors 534a and 534b are coupled to the drain terminals of current source transistors 536a and 536b, respectively, which in turn are coupled to the drain terminals of V ss The current source transistors 536a and 536b have a common gate terminal, which has a bias voltage V from the bias circuit. bn1 (described in more detail below). Bias voltage V bn1 The appropriate operating point of the cascode transistor is set and current is provided to the cascode transistor 534. The cascode transistor 534 can be appropriately sized and biased so that the ratio of the gain of the input transistor pair 532 and the cascode transistor 534 is configured to reduce or minimize the Miller effect, similar to the above description in conjunction with Figure 5ACascode transistor 534, along with bias / current source transistors 536, 544, 546, 548, and 552, may also be appropriately sized and biased to provide the desired common mode of the front-end differential output signal 413 (including signals 413a and 413b). For illustrative purposes, bias / current source transistors 544, 546, 548, and 552 are shown as PMOS transistors and current source transistor 536 is shown as an NMOS transistor. It should be understood that NMOS / PMOS or other transistors may be used depending on the overall configuration of the folded cascode circuit of the analog front end 410 and the common mode requirements of the input differential signal 531 and the differential output signal 413.

[0104] exist Figure 5B , the analog front end 410 generates a differential output signal 413 by using a folded cascode circuit configuration that can have a higher amplitude and improved eye opening compared to the input differential signal 531. In other words, by using and properly configuring the folded cascode circuit, the analog front end 410 can reduce or minimize the Miller effect to improve bandwidth (by reducing the time constant). Due to the cascode circuit, the analog front end 410 can achieve higher gain, thereby providing a higher output signal amplitude and improved eye opening. The analog front end 410 can also be configured to have a wider input signal range by, for example, using PMOS as the input transistor pair, and thus can operate with a low power supply (represented by pn_Vcc) of, for example, 1.6V. In the analog front end 410, one of the inputs can be a reference DC voltage (represented by V ref or V refbias denoted) and the other input can be a time-varying signal. This may introduce distortion if the tail current source is not ideal. Figure 5B 538 and 542) are used to reduce the voltage due to the reference voltage (V ref ) on the analog front end. A bias circuit is used to generate a bias for the cascode tail current source. The analog front end 410 can tolerate reference voltage variations and, therefore, makes the analog front end 410 more robust.

[0105] In addition, compared to a front end with multiple stages of a common source configuration, the folded cascode configuration of the analog front end 410 uses only a single stage. The common source configuration has limited bandwidth, higher gate resistance of the input transistors, high sensitivity to reference voltage variations, and a high probability of failure when operating at low power supply voltages. In contrast, the analog front end 410 avoids these limitations of the multi-stage common source configuration. The analog front end 410 further provides a high output impedance, which reduces the need for common mode feedback (CMFB). CMFB is used to adjust the common mode voltage of a differential amplifier, a differential transistor pair, or other differential circuit system. The common mode voltage is the average voltage between the two input terminals of a differential amplifier or a differential transistor pair. CMFB is used to ensure that the common mode voltage remains within a specified range, thereby providing better performance and stability in certain applications. As described above, the circuit configuration of the analog front end 410 has a greater ability to tolerate common mode offsets and therefore reduces the need for CMFB. In some instances, Figure 5B The common-mode voltage of the output signal 413 of the analog front end 410 shown in FIG can be set at the trip point of the subsequent inverter-based stages coupled to the analog front end 410, thereby reducing duty cycle variation or distortion. The inverter-based stages and duty cycle improvements are described in more detail below.

[0106] In some embodiments, the analog front end 410 with the folded cascode circuit can be adjusted to change its operating speed and / or power consumption. For example, fuses in a ROM (read-only memory) can be used to control the operation of the analog front end 410 to achieve the adjustment.

[0107] As described above, the analog front end 410 includes several bias / current source transistors that provide bias voltage and / or current to the input transistor pair and the cascode transistor. The gate terminals of these bias / current source transistors receive bias voltage from the bias circuit 420. Figure 6 is a circuit diagram of an example bias circuit 420 configured to control the bias voltage of the analog front end 410 according to examples as disclosed herein. By controlling the bias voltages of various transistors in the analog front end 410, the bias circuit 420 sets the operating point of the analog front end 410. For example, by providing appropriate bias voltages, the common-mode voltages of the input transistor pairs and cascode transistors in the analog front end 410 can be properly set for optimized operation (e.g., setting the common-mode voltage at the trip point of the inverter-based stages coupled to the analog front end 410). Thus, the two analog differential input signals 531 have the same common-mode voltage (also referred to as a DC signal voltage) and differential-mode voltages (also referred to as small-signal voltages or AC signal voltages) of opposite polarity. Similarly, the two front-end differential output signals have the same common-mode voltage and differential-mode voltages of opposite polarity.

[0108] Continue to refer Figure 6In some examples, the bias circuit 420 includes several branches. The first branch includes a transistor 602 (eg, a transistor 602 formed by M b2 PMOS represented by 604 (for example, by M b1 denoted by PMOS), 606 (eg, NMOS), and resistor 608 (denoted by R b denoted by ). In this example, the source terminal of transistor 602 is coupled to a power supply (denoted by pn_vcc), which may be the same power supply used for analog front end 410. The drain terminal of transistor 602 is coupled to the source terminal of transistor 604, and thus the two transistors are connected in series. The gate terminal of transistor 602 is coupled to the drain terminal of transistor 604. The gate terminal of transistor 606 is coupled to the output of operational amplifier 610 (op-amp 610). Op-amp 610 receives a reference voltage 601 (denoted by V at one input terminal (e.g., the positive input terminal) of op-amp 610. refbias ). Another input terminal (eg, negative input terminal) of op-amp 610 is coupled to the source terminal of transistor 606 and the first terminal of resistor 608. The source terminal of transistor 606 and the first terminal of resistor 608 are coupled together. A second terminal of transistor 606 is coupled to the V sslcl The op-amp 610 can be configured to have high input impedance and low output impedance, and have high gain. Figure 6 The closed-loop configuration shown in FIG. 1 makes the bias current in the first branch (given by I bias ) is the reference voltage divided by resistor 608 (ie, I bias =V refbias / R b ). Reference voltage V refbias Can be designed to have a value of k*V cclo , that is, the power supply voltage V cclo Therefore, the bias current I bias Can be calculated as I bias =k*V cclo / R b , where k is a positive number between 0 and 1.

[0109] Continue to refer Figure 6 The second branch of the bias circuit 420 includes a transistor 612 (eg, a transistor 612 formed by M b3 denoted by PMOS), 614 (eg, NMOS), and resistor 616 (denoted by R bdenoted by ). In this example, the source terminal of transistor 612 is coupled to a power supply (denoted by pn_vcc), which may be the same power supply used for analog front end 410. The drain terminal of transistor 612 is coupled to the drain terminal of transistor 614. Furthermore, the drain terminal and gate terminal of transistor 612 are coupled together, forming a diode connection. Thus, transistor 612 operates like a diode. The gate terminal of transistor 614 is coupled to the gate terminal of transistor 606 in the first branch and is also coupled to the output of op-amp 610. The source terminal of transistor 614 is coupled to a first terminal of resistor 616. A second terminal of resistor 616 is coupled to electrical ground (denoted by V sslcl express).

[0110] At least the first branch of the bias circuit 420 can be configured to function as a current generator configured to generate a bias current (given by I bias denoted by ) and operates to set a bias voltage for the PMOS transistor in the analog front end 410. As described above, based on the reference voltage V refbias and the value of resistor 608 sets the bias current I bias Based on the bias current, the bias voltages of PMOS transistors 602 and 604 can be set. The second branch of bias circuit 420 can be configured to act as a current mirror. Because the gate terminals of transistors 604 and 612 are coupled together, they have the same bias voltage. Similarly, the gate terminals of transistors 606 and 614 are coupled together, and therefore they have the same bias voltage. Therefore, the bias current I bias can be mirrored to the second branch. In addition, the gate terminal of transistor 602 of the first branch is coupled to the gate terminals of transistors 542, 546, and 552 of the analog front end 410; and the gate terminal of transistor 604 (and transistor 612) is coupled to the gate terminals of transistors 538, 544, and 548. The transistors whose gate terminals are coupled together are matched in size and therefore, the bias voltage is provided from the bias circuit 420 to the PMOS transistors of the analog front end 410 for setting the appropriate operating point. Figure 6 As shown in FIG. 1 , the bias voltage provided by the first branch can be obtained by pcascbias in the bias circuit 420 and V in the analog front end 410. bp2 and another bias voltage is represented by V in the analog front end 410 bp1 These bias voltages are used to bias the PMOS transistors in the analog front end 410 .

[0111] The third branch and the fourth branch of the bias circuit 420 are configured to function as a current mirror to provide a bias voltage to the NMOS transistor in the analog front end 410. Figure 6As shown in FIG. 1 , the third branch of bias circuit 420 includes transistor 622 (eg, transistor 622). b4 6 (e.g., PMOS) and 624 (e.g., NMOS). In this example, the source terminal of transistor 622 is coupled to a power supply (represented by pn_vcc), which can be the same power supply used for analog front end 410. The drain terminal of transistor 622 is coupled to the drain terminal of transistor 624. The gate terminal of transistor 622 is coupled to the gate terminals of transistors 604 and 612. The drain terminal and gate terminal of transistor 624 are coupled together to form a diode connection. Therefore, transistor 624 operates like a diode.

[0112] The fourth branch of the bias circuit 420 includes a transistor 632 (eg, a transistor 632 connected to a transistor 632). b6 PMOS represented by ), 634 (eg, by M b5 denoted by PMOS), 636 (e.g., NMOS), and 638 (e.g., NMOS). In this example, the source terminal of transistor 632 is coupled to a power supply (denoted by pn_vcc), which may be the same power supply used for analog front end 410. The drain terminal of transistor 632 is coupled to the source terminal of transistor 634. The gate terminal of transistor 632 is coupled to the gate terminal of transistor 602. The gate terminal of transistor 634 is coupled to the gate terminals of transistors 604, 612, and 622. The drain terminal of transistor 634 is coupled to the drain terminal of transistor 636. The gate terminal of transistor 636 is coupled to the gate terminal of transistor 624 in the third branch. The source terminal of transistor 636 is coupled to the drain terminal of transistor 638. The source terminal of transistor 638 is coupled to electrical ground (denoted by V sslcl denoted by ). The gate terminal of transistor 638 and the drain terminal of transistor 636 are coupled together.

[0113] The third branch and the fourth branch of the bias circuit 420 are configured to function as a current mirror and provide a bias voltage to the NMOS transistors of the analog front end 410. Figure 6 As shown in FIG, the sizes of transistors 622 and 634 match the sizes of transistors 604 and 612, and similarly, transistors 632 and 602 may be matched in size. Thus, the bias current generated by the first branch (by I bias ) can be mirrored to the third and fourth branches. Thus, the voltages of the gate terminals of transistors 636 and 638 can be set according to the mirrored bias current. In addition, the gate terminal of transistor 636 of the fourth branch is coupled to the gate terminals of transistors 534a and 534b of the analog front end 410, thereby converting the gate terminals of transistors 636 and 638 into the gate terminals of transistors 534a and 534b of the analog front end 410. bn1The bias voltage represented by V is provided to the cascode transistor 534. The gate terminal of the transistor 638 is coupled to the gate terminals of the transistors 536a and 536b, thereby bp1 The bias voltage represented by is provided to the current source transistor 536. The transistors having their gate terminals coupled together are matched in size and therefore, the bias voltage is provided from the bias circuit 420 to the PMOS transistors of the analog front end 410 for setting the proper operating point. Figure 6 As shown in FIG. 1 , the bias voltage provided by the fourth branch of the bias circuit 420 can be determined by ncascbias in the bias circuit 420 and V in the analog front end 410. bn1 and another bias voltage is represented by V in the analog front end 410 bn2 These bias voltages are used to bias the NMOS transistors in the analog front end 410 .

[0114] Figure 6 The configuration shown in FIG4 has a bias circuit 420 configured to bias the common mode of the folded cascode circuit of the analog front end 410 based on a termination relative to ground. Termination in high-speed signal communication refers to the use of electronic components (e.g., resistors, capacitors, and / or inductors) to properly terminate a transmission line and minimize signal reflections. The termination can be configured to terminate relative to electrical ground or a power supply. If the termination is configured relative to electrical ground, the circuit needs to be biased at an operating point close to ground (e.g., a common-mode voltage). For example, the termination may require an operating point of approximately 1 / 6 of the power supply voltage. In some examples, the operating point can be set to approximately 1 / 2 of the power supply voltage. The folded cascode circuit described above can be configured to have a common-mode voltage biased close to ground (e.g., 0V or 1 / 6 of the power supply voltage). Therefore, the bias circuit 420 can be configured accordingly. In some examples, in the first branch, the resistor 608 is a tunable resistor so that the resistance can be changed. Thus, the bias current can be varied, and the bias voltage can also be varied.Thus, the bias circuit 420 can be tuned based on the termination scheme and / or other requirements of the analog front end 410.

[0115] The bias circuit 420 described above can have a fast settling time (e.g., less than 5 ns), so that the analog front end 410 can be quickly provided with a bias voltage for proper operation. The bias circuit 420 can be designed to be tunable and thus configured according to different requirements of the input receiver (e.g., bandwidth, speed, input dynamic range, termination, etc.). The bias circuit 420 can also be designed to minimize power consumption.

[0116] Briefly refer again Figure 4The analog front end 410 generates a front end differential output signal 413, which is received by a cascaded inverter-based stage 430. The cascaded inverter-based stage 430 includes a plurality of inverter-based stages cascaded together. Figure 7A is a block diagram of a single inverter-based stage 700a according to examples as disclosed herein. Figure 7A and similarly Figure 7B and Figure 8A Two signal paths for differential signals are illustrated and the following description may refer to only one of the signal paths for the differential signal, it being understood that the other signal path operates in a similar manner. Figure 7A In FIG. 4 , the analog front end 410 receives analog differential input signals 701a and 701b. The difference between signals 701a and 701b is the differential input voltage and is represented by V 0d As described above, the analog front end 410 may include a folded cascode circuit and a bias circuit. The analog front end 410 amplifies the difference between the input signals 701a and 701b and provides front-end differential output signals 703a and 703b (collectively referred to as signals 703). The difference between signals 703a and 703b is the differential mode front-end output voltage and is represented by V 1d Therefore, the amplification gain or simply the gain (denoted by A1) of the analog front end 410 is the ratio between the differential mode front end output voltage and the differential mode input voltage. The gain is represented by A1 = V 1d / V 0d =-g m0 / g m1 .

[0117] The front-end differential output signal 703 is provided to the inverter-based stage 700a. The inverter-based stage 700a may include one or more inverter circuits 704a and 704b. The inverter circuit typically includes a PMOS transistor and an NMOS transistor connected in series. The drain terminal of the PMOS transistor may be connected to a power supply and the source terminal of the NMOS transistor may be connected to electrical ground. In some examples, each of the PMOS and NMOS transistors is diode-connected so that they operate like diodes. Thus, the gate terminal of the PMOS transistor is coupled to the source / drain terminals of the PMOS transistor; and similarly, the gate terminal of the NMOS transistor is coupled to the source / drain terminals of the NMOS transistor. The inverter-based stage 700a further includes feedback resistors 706a and 706b (represented by R1, collectively referred to as 706).

[0118] like Figure 7AAs shown in FIG, feedback resistor 706a forms a feedback path from the output of inverter-based stage 700a to the input of inverter-based stage 700a. This configuration is also known as an active inductor and can be used to smooth the overall system gain across the input signal voltage range. Figure 7A As shown in FIG. 7 , waveform 712 shows the waveform of gain A1 and the differential input voltage V 0d The differential input voltage V can be swept from low to high (e.g., from 0V to the power supply voltage). 0d , and the gain A1 can be measured to obtain the gain profile. Gain A1 is the differential mode front-end output voltage V 1d and the differential input voltage V 0d The ratio, that is, A1 = V 1d / V 0d .exist Figure 7A In the system shown in Figure 1, A1 = -g m0 / g m1 , where g m0 is the gain of the analog front end 410, and g m1 is the gain of the inverter-based stage 700a. Waveform 712 shows the gain A1 at the differential input voltage V 0d changes when V 0d There may be a peak in gain A1 at a specific value of . In other words, when the differential input voltage V 0d When changing, the gain A1 may not be smooth or flat and may vary significantly. This is generally undesirable because the eye opening of the front-end differential output signal 703 may be worse with a significant change in the gain A1.

[0119] Figure 7A Another waveform 722 is also shown, which is the gain A2 and the differential input voltage V 0d Similar to measuring gain A1, the differential input voltage V can be swept from low to high (e.g., from 0V to the power supply voltage). 0d , and the gain A2 can be measured. The amplification gain A2 is based on the differential mode output voltage V 2d Differential mode input voltage V 0d The ratio, that is, A2 = V 2d / V 0d .exist Figure 7A In the system shown in Figure 1, A2 = A1 + g m0 *R1, where g m0 is the gain of the analog front end 410, and R1 is the value of the feedback resistor in the inverter-based stage 700a. Waveform 722 shows that while the gain A2 is 0d Changes and still changes when V 0dThere may also be a peak in gain A2 at a particular value of , but the range of variation of gain A2 is smaller than the range of variation of gain A1. In other words, due to the configuration of inverter-based stage 700a with feedback resistor R1, the profile of gain A2 can be more linear or flat compared to the profile of gain A1. The peak value of gain A2 is also generally smaller than the peak value of gain A1. Across the differential input voltage V 0d Improved linearity over the voltage range of θ and a flatter gain profile are generally desirable because they reduce jitter and improve the eye opening of the output signal 707 .

[0120] Figure 7B is a block diagram of an inverter-based stage 700a having a pair of cross-coupled inverters 709a and 709b according to examples as disclosed herein. The inverter-based stage 700a and the front end 410 have been described above and are therefore not repeated. Figure 7B In FIG, after the inverter-based stage 700a, a pair of cross-coupled inverters 709a and 709b (collectively referred to as 709) are used. The cross-coupled inverter 709 is configured so that the output of the inverter 709a is coupled to the input of the inverter 709b, and vice versa. The cross-coupled inverters 709a and 709b are disposed between the two differential output signals 707a and 707b of the inverter-based stage 700a. The cross-coupled inverters 709a and 709b form a positive feedback loop between the differential output signals 707a and 707b. As discussed above, the differential signals have opposite polarities (e.g., one negative and one positive relative to the common mode voltage, or a high state or a low state). The cross-coupled inverters 709a and 709b create a bistability, thereby improving the stability of the differential output signals 707a and 707b so that they maintain their polarity (e.g., high or low) due to the feedback loop. In addition, the cross-coupled inverter 709 can also improve the Figure 7B The amplification gain of the system shown in .

[0121] Figure 7C The following description shows that when the differential input voltage V 0d The two waveforms 714 and 724 show the changes in gain A1 and gain A2 across the voltage range. Waveform 714 is the gain A1 versus differential input voltage V 0d To measure the gain A1, the differential input voltage V can be swept from low to high (for example, from 0V to the power supply voltage). 0d , and the gain A1 can be measured. The amplification gain A1 is the ratio of the front-end differential mode output voltage to the front-end differential mode input voltage, that is, A1 = V 1d / V 0d .

[0122] exist Figure 7B In the system shown in , A1 is calculated based on the following equation [5].

[0123]

[0124] In the above equation [5], g m0 is the gain of the analog front end 410, g m1 is the gain of inverter-based stage 700a, and g m1a is the gain of the cross-coupled inverter 709, and R1 is the value of the feedback resistor in the inverter-based stage 700a. In equation [5],

[0125] g m1a R1>>1 and g m1 >g m1a

[0126] Waveform 714 shows the gain A1 versus the differential input voltage V 0d Similarly, waveform 724 shows the relationship between gain A2 and differential input voltage V 0d When stage 700a has a cross-coupled inverter pair, the amplification gain A2 is based on the ratio of the differential mode output voltage of stage 700a to the front-end differential mode input voltage of the inverter (ie, A2 = V 2d / V 0d ).exist Figure 7B In the system shown in , A2 is calculated based on the following equation [6].

[0127]

[0128] Comparing waveforms 714 and 724, when the cross-coupled inverter pair 709 is added, although the two gains A1 and A2 are 0d changes when V 0d There may be a peak gain at a specific value of , but the gain A1 range is smaller than the gain A2 range. As described above, across the differential input voltage V 0d A smoother and flatter gain profile over a voltage range of 1 is generally desirable because it improves the eye opening of the output signal. Thus, by using multiple cascaded inverter-based stages with cross-coupled inverter pairs, a Figure 7B A further improvement of the configuration shown in is to make the gain profile of A2 smoother, as described below.

[0129] Figure 8Ais a block diagram of an input receiver 800 having cascaded inverter-based stages with multiple pairs of cross-coupled inverters according to examples as disclosed herein. Similar to the description above, the input receiver 800 has an analog front end 410 coupled to a first inverter-based stage 810a, which in turn is coupled to a first pair of cross-coupled inverters 809a and 809b (collectively 809). The input receiver 800 further includes a second inverter-based stage 810b and a second pair of cross-coupled inverter circuits 819a and 819b (collectively 819). The first inverter-based stage 810a includes a first pair of inverter circuits 804a and 804b coupled to the analog front end 410 to receive the front end differential output signals 803a and 803b (collectively referred to as 803), amplify the front end differential output signals 803, and output first amplified differential signals 807a and 807b (collectively referred to as 807). m1 denoted by a first amplification gain. Each of the inverter circuits 804a and 804b of the first inverter-based stage 810 has a feedback resistor 806a and 806b, respectively. Feedback resistors 806a and 806b connect the input and output of the respective inverter circuit 804a or 804b and provide a feedback path for the respective inverter circuit 804a or 804b. The inverter-based stage 810a may be the same or similar to the inverter-based stage 700a described above and will not be described again in detail.

[0130] Figure 8A Further shown are a first pair of cross-coupled inverter circuits 809a and 809b (collectively 809) coupled between the first amplified differential signals 807a and 807b. Each of the first pair of inverter circuits 809a and 809b has a first amplification gain (given by g m1a denoted by ). The first pair of cross-coupled inverter circuits 809 can be the same as or similar to the cross-coupled inverter circuits 709 described above and are therefore not described again. For example, the cross-coupled inverter circuits 809 can improve the amplification of the first inverter-based stage 810a at high frequencies. In some examples, the cross-coupled inverter circuits 809 are optional.

[0131] Figure 8AFurther illustrating that the second inverter-based stage 810b is coupled to the first inverter-based stage 810a and the optional cross-coupled inverter circuit 809. The second inverter-based stage 810a includes a second pair of inverter circuits 814a and 814b coupled to the first pair of inverter circuits 804a and 804b, respectively, to receive the first amplified differential signals 807a and 807b. The second pair of inverter circuits 814a and 814b further amplify the differential signals 807a and 807b and output second amplified differential signals 817a and 817b (collectively referred to as 817), respectively. Thus, the second inverter-based stage 810b has a phase shift of 0.01 s and 0.02 s. m2 The second amplification gain is represented by m2 May be equal to or not equal to the first amplification gain g m1 In some examples, the second amplification gain g m2 Can be less than the first amplification gain g m1 , so that the second inverter-based stage 810b does not add too much amplification gain to the overall input receiver 800.

[0132] like Figure 8A As shown in FIG, similar to the inverter circuit in the first inverter-based stage 810a, each of the inverter circuits 814a and 814b of the second inverter-based stage 810b has a feedback resistor 816a and 816b (represented by R2), respectively. The feedback resistor 816a or 816b connects the input and output of the corresponding inverter circuit 814a or 814b and provides a feedback path for the corresponding inverter circuit 814a or 814b. The second inverter-based stage 810b may be the same as or similar to the inverter-based stage 700a described above and is therefore not described again. The feedback resistor 816 used in the second inverter-based stage 810b may have the same or different value as the feedback resistor 806 used in the first inverter-based stage 810a (i.e., R1 may or may not be equal to R2).

[0133] Figure 8A A second pair of cross-coupled inverter circuits 819a and 819b (collectively 819) are further shown coupled between the second amplified differential signals 817a and 817b. Each of the second pair of inverter circuits 819a and 819b has a second amplification gain (given by g m2a denoted by ). The second pair of cross-coupled inverter circuits 819 can be the same as or similar to the cross-coupled inverter circuits 709 described above and are therefore not described again. For example, the cross-coupled inverter circuits 819 can boost the amplification of the second inverter-based stage 810b at high frequencies. In some examples, the cross-coupled inverter circuits 819 are optional.

[0134] It should be understood that each node of the input receiver 800 may have parasitic components associated with it. For example, Figure 8A It is shown that each of the differential outputs of the first inverter-based stage 810a can have a parasitic capacitance C1 relative to electrical ground; and each of the differential outputs of the second inverter-based stage 810b can have a parasitic capacitance C2 relative to electrical ground. In some cases, C1 may or may not be equal to C2. Figure 8A Not all parasitic components are shown.

[0135] The cascading of multiple inverter-based stages (e.g., stages 810a and 810b) improves the linearity of the overall gain profile of the input receiver 800, resulting in a flatter amplification of the input receiver 800. This means that the gain variation is reduced across the voltage variation range of the differential-mode input voltage of the input receiver 800. Figure 8B The following description shows that when the differential input voltage V 0d Three waveforms 812, 814, and 815 illustrate the variation of gains A1, A2, and A3 across the voltage range. Similar to the above, at the output of the analog front end 410 relative to the differential input voltage V 0d Gain A1 is measured at the output of the first inverter-based stage 810a relative to the differential input voltage V 0d Gain A2 is measured; and at the output of the second inverter-based stage 810b relative to the differential input voltage V 0d Measure the gain A3. To measure the gain A1, the input signal V can be swept from low to high (e.g., from 0V to the power supply voltage). 0d , and the gain A1 can be measured. The amplification gain A1 is the front-end differential output signal V 1d The ratio of the front-end differential input signal, that is, A1 = V 1d / V 0d .exist Figure 8A In the input receiver 800 shown in , A1 is calculated based on equation [7] below.

[0136]

[0137] In the above equation [7], g m0 is the gain of the analog front end 410, g m1 is the gain of the first inverter-based stage 810a, g m2 is the gain of the second inverter-based stage 810b, g m1a is the gain of the first cross-coupled inverter 809, g m2a is the gain of the second cross-coupled inverter circuit 819, and R1 is the value of the feedback resistor 806 in the first inverter-based stage 810a. In equation [7], k is calculated as follows in equation [8].

[0138]

[0139] In equation [8], R2 is the value of the feedback resistor 816 in the second inverter-based stage 810b. When the stage 810a has a cross-coupled inverter pair 809, the amplification gain A2 is the differential mode output voltage V of the first inverter-based stage 810a. 2d and the differential input voltage V 0d The ratio (ie, A2 = V 2d / V 0d ). Similarly, when the stage 810b has a cross-coupled inverter circuit 819, the amplification gain A3 is the differential mode output voltage V of the second inverter-based stage 810b. 3d Differential mode input voltage V 0d The ratio (ie, A3 = V 3d / V 0d ). Therefore, the gain A3 represents the overall gain of the input receiver 800.

[0140] refer to Figure 8B , waveform 812 shows the gain A1 versus the differential input voltage V 0d Waveform 814 shows the relationship between gain A2 and differential input voltage V 0d Waveform 815 shows the relationship between gain A3 and differential input voltage V 0d Comparing waveforms 812, 814, and 815, by cascading multiple inverter-based stages (e.g., stages 810a and 810b) and optionally including cross-coupled inverter circuits 809 and 819 at each stage, the gain A3 varies over at least the differential input voltage V 0d decreases within a certain voltage range. Figure 8B As shown in FIG. 8 , waveform 815 is at a differential input voltage V 0d This means that the gain of the input receiver 800 is more linear or balanced over the input voltage range. 0d A smoother and flatter gain profile over the voltage range of φ is generally desirable because it improves the eye opening of the high-speed output differential signal and reduces inter-symbol interference (ISI).

[0141] In the above equation [8], k is negative in the case of and positive in all other cases. 0d ) varies as shown above, the gain A1 varies from +ve to -ve values ​​(positive and negative values). It should be understood that R1, R2, g m0 、g m1 、g m2 、g m1a and gm2a to achieve a linear overall gain of the input receiver 800 with improved ISI. Figure 8A The example input receiver 800 shown above includes only two cascaded inverter-based stages, but it should be understood that more stages may be cascaded as needed, depending on the overall requirements for the input receiver (e.g., gain requirements, linearity requirements, ISI requirements, etc.). The number of inverter-based stages may be optimized taking into account performance requirements, power consumption, and layout area constraints.

[0142] Reference again Figure 8A , the feedback resistor 816 (represented by R2) can further improve the bandwidth of the input receiver 800. Without the feedback resistor 816, the zero frequency of this system (represented by W z1 denoted by W) and the pole frequency (denoted by W p1 ) is calculated below as Equations [9] and

[10] .

[0143]

[0144] In the above equations [9] and

[10] , W z1 is the zero frequency, R1 is the feedback resistor 806 of the first inverter-based stage 810a, g m1 is the gain of the first inverter-based stage 810a, and C1 is the capacitance at the output of the first inverter-based stage 810a with respect to ground. With the feedback resistor 816 (represented by R2) in the second inverter-based stage 810b, both the zero frequency and the pole frequency are extended as shown below in equations

[11] and

[12] , where R2 is the value of the feedback resistor 816 of the second inverter-based stage 810b and C2 is the capacitance at the output of the second inverter-based stage 810b. In some examples, C1 and C2 are the intended capacitors included in the input receiver 800. As Figure 8A As shown in , each capacitor C1 is coupled between a respective differential output of the first inverter-based stage 810a and ground. And each capacitor C2 is coupled between a respective differential output of the second inverter-based stage 810b and ground.

[0145] In other cases, they may be just parasitic capacitors or a mix of parasitic and intended capacitors.

[0146]

[0147] The pole frequency is the frequency at which the input receiver's transfer function approaches infinity. The zero frequency is the frequency at which the input receiver's transfer function approaches zero. Therefore, by extending one or both of the pole and zero frequencies, the bandwidth of the input receiver 800 is improved, allowing the input receiver to operate over a wider speed range.

[0148] An additional benefit of the input receiver 800 having cascaded inverter-based stages is that its analog front-end 410 does not require common-mode feedback (CMFB). CMFB is used to adjust the common-mode voltage of a differential amplifier, differential transistor pair, or other circuitry. The analog front-end 410 described herein has a high output impedance (i.e., the impedance when observing the output of the analog front-end 410), and therefore, this analog front-end may not require CMFB. Furthermore, due to resistor feedback (e.g., R1 in the first inverter-based stage 810a and / or R2 in the second inverter-based stage 810b), the output of the analog front-end 410 (e.g., the common mode of the front-end differential output signals 803a and 803b) can be biased at the trip point of the first inverter-based stage 810a. The trip point of an inverter-based stage is the voltage level at which the stage output switches from one polarity to another (e.g., from low to high, from high to low, from positive to negative, or from negative to positive).

[0149] Figure 8C 832 and 842 are illustrative front-end output signal waveforms of input receivers with and without cascode circuits in the analog front end according to examples as disclosed herein. Waveform 832 corresponds to, for example, the output signal from an analog front end that does not use a cascode circuit; and waveform 842 corresponds to, for example, the output signal from an analog front end that uses a cascode circuit (e.g., the folded cascode circuit in analog front end 410). Figure 8C As shown in FIG, for an input receiver that does not use a cascode circuit in an analog front end, the shift in the common-mode voltage of the front-end output differential signal and the shift in the trip point voltage of the subsequent inverter-based stage may differ. For example, waveform 832 shows that the shift in the common-mode voltage is smaller than the shift in the trip point. As a result, the duty cycle of the front-end output differential signal may be less than or greater than 50%. This causes undesirable duty cycle distortion.

[0150] When the analog front end uses a cascode circuit (e.g., the folded cascode circuit in the analog front end 410), duty cycle distortion is reduced. Figure 8C As shown in waveform 842 of FIG, when using a cascode circuit, the movement of the common mode voltage of the front-end output differential signal and the movement of the trip point voltage of the subsequent inverter-based stage are substantially equal. Figure 8A The duty cycle of the signals 803a and 803b in FIG. 8 remains approximately 50%. Thus, by using the cascode circuit described herein, the duty cycle of the signal at the input receiver can be improved.

[0151] It should be noted that the described techniques include possible implementations, and that operations and blocks may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more methods may be combined.

[0152] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0153] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can readily support signal flow between the components. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0154] The term "coupled" (e.g., "electrically coupled") may refer to a condition that moves from an open-circuit relationship between components (where signals cannot currently be communicated between the components via a conductive path) to a closed-circuit relationship between the components (where signals can be communicated between the components via a conductive path). If a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0155] The term "isolation" refers to a relationship between components where a signal cannot flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch located between the components is open, the two components separated by the switch are isolated from each other. If a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using the conductive path that previously allowed signal flow.

[0156] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a connection between conditional actions, conditional processes, or portions of processes.

[0157] The term "in response to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0158] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping means.

[0159] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material (e.g., metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "switched off" or "deactivated."

[0160] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0161] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0162] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Figure 3 If the functionality is implemented in software executed by a processor 310 of a computer, then the functionality may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functionality may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functionality may also be physically located at various locations, including portions distributed so that the functionality is implemented at different physical locations.

[0163] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0164] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An input receiver of an input / output (I / O) circuit operable to communicate data, the input receiver comprising: an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end comprises: a cascode circuit having a differential input configured to receive the analog differential input signal and to provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and A cascaded inverter-based stage is electrically coupled to the analog front end to receive the front end differential output signal and output a balanced differential signal representative of the data.

2. The input receiver of claim 1 , wherein the cascode circuit comprises: an input transistor pair configured to receive the analog differential input signal; a cascode transistor coupled to the input transistor pair, the cascode transistor configured to reduce input capacitance of the input transistor pair caused by a Miller capacitance effect; and A current source transistor is coupled to the input transistor pair, the current source transistor being controlled by the bias circuit to provide current to the cascode transistor. 3 . The input receiver of claim 2 , wherein the cascode circuit is a folded cascode circuit. 4 . The input receiver of claim 3 , wherein the bias circuit is configured such that a common mode of the folded cascode circuit is biased based on termination relative to ground.

5. The input receiver of claim 1 , wherein the bias circuit comprises: an operational amplifier configured to receive a reference bias voltage; one or more current generators configured to generate one or more bias currents; and One or more current mirrors configured to mirror the one or more bias currents and provide a bias voltage to the cascode circuit.

6. The input receiver of claim 1 , wherein the cascaded inverter-based stage comprises a first inverter-based stage and a second inverter-based stage, wherein at least one of the first inverter-based stage or the second inverter-based stage comprises one or more resistive feedbacks.

7. The input receiver of claim 6, wherein: The first inverter-based stage includes a first pair of inverter circuits coupled to the analog front end to receive the front end differential output signal and output a first amplified differential signal, each of the first pair of inverter circuits having a first amplification gain; and The second inverter-based stage includes a second pair of inverter circuits coupled to the first pair of inverter circuits to receive the first amplified differential signal and output a second amplified differential signal, each of the second pair of inverters having a second amplification gain.

8. The input receiver of claim 7, wherein the first inverter-based stage comprises a first pair of resistors, each resistor coupled to an input and an output of a first inverter of the first pair of inverters to form a feedback path associated with the first inverter-based stage.

9. The input receiver of claim 7, wherein the second inverter-based stage comprises a second pair of resistors, each resistor coupled to an input and an output of a second inverter of the second pair of inverters to form a feedback path associated with the second inverter-based stage.

10. The input receiver of claim 6, further comprising: a first pair of cross-coupled inverters coupled between differential outputs of the first inverter-based stage to boost the gain of the first inverter-based stage; and A second pair of cross-coupled inverters is coupled between the differential outputs of the second inverter-based stage to boost the gain of the second inverter-based stage.

11. The input receiver of claim 6, further comprising: a first pair of capacitors each coupled between a respective differential output of the first inverter-based stage and ground; and A second pair of capacitors is each coupled between a respective differential output of the second inverter-based stage and ground.

12. An input receiver of an input / output (I / O) circuit operable to communicate data, the input receiver comprising: an analog front end configured to receive an analog differential input signal from outside the I / O circuit and to provide a front-end differential output signal based on the received analog differential input signal, the analog front end being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the analog front end; and Cascaded inverter-based stages are electrically coupled to the analog front end to receive the front end differential output signal and output a balanced differential signal representative of the data, wherein at least two of the cascaded inverter-based stages include resistive feedback.

13. The input receiver of claim 12, wherein the analog front end comprises a cascode circuit.

14. The input receiver of claim 13 , wherein the cascode circuit comprises: an input transistor pair configured to receive the analog differential input signal; a cascode transistor coupled to the input transistor pair, the cascode transistor configured to reduce input capacitance of the input transistor pair caused by a Miller capacitance effect; and A current source transistor is coupled to the input transistor pair, the current source transistor being controlled by the bias circuit to provide current to the cascode transistor.

15. The input receiver of claim 13, wherein the cascode circuit is a folded cascode circuit.

16. The input receiver of claim 15, wherein the bias circuit is configured such that a common mode of the folded cascode circuit is biased based on termination relative to ground.

17. The input receiver of claim 12, wherein the bias circuit comprises: an operational amplifier configured to receive a reference bias voltage; one or more current generators configured to generate one or more bias currents; and One or more current mirrors configured to mirror the one or more bias currents and provide a bias voltage to the analog front end.

18. The input receiver of claim 12, wherein the cascaded inverter-based stages comprise: a first inverter-based stage coupled to the analog front end to receive the front end differential output signal; and A second inverter-based stage is coupled to the first inverter-based stage.

19. The input receiver of claim 18, wherein: The first inverter-based stage includes a first pair of inverters coupled to the analog front end to receive the front end differential output signal and output a first amplified differential signal, each of the first pair of inverters having a first amplification gain; and The second inverter-based stage includes a second pair of inverters coupled to the first pair of inverters to receive the first amplified differential signal and output a second amplified differential signal, each of the second pair of inverters having a second amplification gain.

20. The input receiver of claim 19, wherein the first inverter-based stage comprises a first pair of resistors, each resistor coupled to an input and an output of a first inverter of the first pair of inverters to form a feedback path associated with the first inverter-based stage.

21. The input receiver of claim 18, wherein the second inverter-based stage comprises a second pair of resistors, each resistor coupled to an input and an output of a second inverter of the second pair of inverters to form a feedback path associated with the second inverter-based stage.

22. The input receiver of claim 18, further comprising: a first pair of cross-coupled inverters coupled to the differential outputs of the first inverter-based stage to boost the gain of the first inverter-based stage; and A second pair of cross-coupled inverters is coupled to the differential outputs of the second inverter-based stage to boost the gain of the second inverter-based stage.

23. The input receiver of claim 18, further comprising: a first pair of capacitors each coupled between a respective differential output of the first inverter-based stage and ground; and A second pair of capacitors is each coupled between a respective differential output of the second inverter-based stage and ground.

24. A memory device comprising: An input / output (I / O) circuit having an input receiver, wherein the input receiver includes: an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end comprises: a cascode circuit having a differential input configured to receive the analog differential input signal and to provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and a cascaded inverter-based stage electrically coupled to the analog front end to receive the front end differential output signal and output a balanced differential signal representative of the data; a memory array coupled to the I / O circuitry to receive and transmit data; and A memory controller is configured to control the memory array and the I / O circuit.

25. A system comprising: processor; a first memory controller; and a memory device coupled to at least one of the processor and the first memory controller, wherein the memory device comprises: An input / output (I / O) circuit having an input receiver, wherein the input receiver includes: an analog front end configured to receive an analog differential input signal from outside the I / O circuit, wherein the analog front end comprises: a cascode circuit having a differential input configured to receive the analog differential input signal and to provide a front-end differential output signal based on the received analog differential input signal, the cascode circuit being operable in a multi-gigahertz frequency range; a bias circuit configured to control a bias voltage of the cascode circuit; and a cascaded inverter-based stage electrically coupled to the analog front end to receive the front end differential output signal and output a balanced differential signal representative of the data; a memory array coupled to the I / O circuitry to receive and transmit data; and A second memory controller is configured to control the memory array and the I / O circuit.

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