AIS multi-level time slot synchronization method

Abstract

The invention discloses an AIS (Automatic Identification System) multi-level time slot synchronization method, relates to the technical field of time slot synchronization, and aims to solve the problems of poor synchronization effect in a synchronization process and wrong verification after synchronization. By monitoring the communication process of the AIS equipment in each time slot in real time, the communication abnormal condition can be found in time, the time slot synchronization signal frequency is estimated, and the local clock frequency is adjusted accordingly, so that the system can adapt to the change of the signal frequency and is suitable for various different application scenes and signal environments, and in the feature information extraction process, the feature information extraction efficiency is improved. The initial timestamp is determined by detecting an amplitude abrupt change point or the initial position of a specific synchronous code pattern, the center frequency is determined through frequency domain analysis, and the initial phase value is combined with frequency information calculation, so that the accuracy of feature information extraction is improved, the local clock frequency is dynamically adjusted by using a phase-locked loop, and the accuracy of feature information extraction is improved. And the local clock frequency can be automatically adjusted to a state close to the time slot synchronization signal frequency according to the calculated frequency deviation.

Description

Technical Field

[0001] The present invention relates to the technical field of time slot synchronization, and in particular to an AIS multi-level time slot synchronization method. Background Art

[0002] Timeslot synchronization refers to the process of aligning the time slot start point of a device with that of a base station or other reference signal in a communication system.

[0003] Chinese patent publication number CN103986543B discloses a time slot synchronization method for a satellite-borne AIS signal receiving system. The method mainly involves extracting M signal segments of a certain length from the received continuous signal at intervals within an AIS time slot, performing a discrete Fourier transform on each signal segment, and converting the time domain signal into a frequency domain signal. The frequency domain signal is correlated with a local reference frequency domain signal to obtain M×N correlation values. The maximum value is taken from the obtained correlation values, and the start time of the received signal segment corresponding to the maximum value is used as the synchronization time. The corresponding frequency offset value of the local reference signal is used as the synchronization frequency point. Time slot synchronization is performed based on the obtained synchronization time and synchronization frequency point. Although the above patent solves the problem of time slot synchronization, the following problems still exist in actual operation:

[0004] 1. Failure to make targeted adjustments to AIS equipment allocation based on the final allocation data, and failure to effectively monitor the equipment allocation process, resulting in poor allocation results.

[0005] 2. The acquired signal data is not adequately synchronized, resulting in reduced signal data synchronization effect.

[0006] 3. After the signal data is acquired, no further signal processing and feature extraction are performed, resulting in inaccurate signal data acquisition. Summary of the Invention

[0007] The present invention aims to provide an AIS multi-level time slot synchronization method. By real-time monitoring of the communication process of AIS devices within their respective time slots, this method can promptly detect communication anomalies, estimate the time slot synchronization signal frequency, and adjust the local clock frequency accordingly, enabling the system to adapt to changes in signal frequency. The method is applicable to a variety of different application scenarios and signal environments. During feature information extraction, the start timestamp is determined by detecting the amplitude mutation point or the starting position of a specific synchronization pattern, the center frequency is determined through frequency domain analysis, and the initial phase value is calculated in combination with frequency information, all of which help improve the accuracy of feature information extraction. A phase-locked loop is used to dynamically adjust the local clock frequency, automatically adjusting the local clock frequency to a state close to the time slot synchronization signal frequency based on the calculated frequency deviation. This method can solve the problems of the prior art.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] An AIS multi-level time slot synchronization method, comprising:

[0010] First, the signal sent by the AIS base station is received, the received signal is identified as a time slot synchronization signal, and characteristic information is extracted. The extracted characteristic information is used for preliminary time slot synchronization. Based on the preliminary time slot synchronization, secondary time slot synchronization is performed. After the secondary time slot synchronization, multi-level verification is performed. The time slots in the AIS base station are allocated according to the multi-level verification results. Finally, synchronization execution is carried out according to the allocation results, and the execution process is monitored and adjusted.

[0011] Preferably, the signal sent by the AIS base station is first received, including:

[0012] Before receiving the signal sent by the AIS base station, first confirm the direction of the AIS frequency band and adjust the position and angle of the antenna;

[0013] The received signal is transmitted to a low-noise amplifier, which amplifies the signal while controlling the noise generated by the low-noise amplifier itself;

[0014] The low-noise amplifier introduces the amplified signal into the filter, which blocks and attenuates the interference signals outside the effective frequency band.

[0015] The filtered signal is transmitted to an analog-to-digital converter. The analog-to-digital converter discretely samples the signal according to the sampling frequency and quantization accuracy, converts the continuous signal amplitude value into the corresponding digital code, and converts the analog AIS signal into a digital signal.

[0016] Finally, the reception of AIS base station signal is completed.

[0017] Preferably, the received signal is subjected to time slot synchronization signal identification and feature information is extracted, including:

[0018] Comparing the received signal with a standard time slot synchronization signal template, wherein the standard time slot synchronization signal template is a digital signal sample of a standard time slot synchronization signal characteristic, and the standard time slot synchronization signal template is retrieved from a database;

[0019] The comparison process calculates the similarity between the received signal and the standard time slot synchronization signal template at different time points and frequency segments, and determines whether the time slot synchronization signal exists in the received signal based on the similarity between the received signal and the standard time slot synchronization signal template at different time points and frequency segments;

[0020] Compare and judge the comparison result threshold with the standard time slot synchronization threshold;

[0021] If the comparison result threshold exceeds the standard time slot synchronization threshold, the similarity between the received signal and the standard time slot synchronization signal template is high, and the time slot synchronization signal exists in the received signal;

[0022] If the comparison result threshold does not reach the standard time slot synchronization threshold, then there is no time slot synchronization signal in the received signal, and the subsequent received signal is detected;

[0023] Extract characteristic information of the time slot synchronization signal, including the starting timestamp, center frequency and initial phase value; the time slot synchronization implementation method flow

[0024] The extraction of the start timestamp is as follows: by detecting the amplitude mutation point of the timeslot synchronization signal or the starting position of a specific synchronization pattern, the precise start timestamp of the timeslot synchronization signal in the overall received signal is determined;

[0025] The center frequency is extracted by performing frequency domain analysis on the time slot synchronization signal to determine the center frequency and frequency offset of the time slot synchronization signal;

[0026] The initial phase value is extracted by detecting the phase value and phase variation law of the time slot synchronization signal at the start time, and calculating the phase noise level of the time slot synchronization signal in combination with the frequency information;

[0027] The extracted characteristic information is integrated into a data set, and after the integration is completed, a characteristic information data set of the time slot synchronization signal is obtained.

[0028] Preferably, judging whether a time slot synchronization signal exists in the received signal according to the similarity between different time points and frequency segments includes:

[0029] Determining the size of the sliding window for comparison based on the length of the standard time slot synchronization signal template as a reference sliding window;

[0030] Determine the sliding step size of the reference sliding window during the comparison of received signals based on the required accuracy of real-time time slot synchronization;

[0031] Comparing the sub-received signal within each reference sliding window with the standard time slot synchronization signal template to determine the signal correlation performance of each sub-received signal with the standard time slot synchronization signal template;

[0032] If the signal correlation performance is greater than a preset minimum correlation performance, taking the received signal corresponding to the sub-received signal as the first received signal;

[0033] If the signal correlation performance is not greater than the preset minimum correlation performance, it is determined that there is no time slot synchronization signal in the received signal corresponding to the current sub-received signal;

[0034] Determine the time synchronization threshold and frequency synchronization threshold for the real-time received signal based on the characteristics of the real-time received signal and the required accuracy of the real-time time slot synchronization;

[0035] If a signal peak value in the current first received signal exceeds the time synchronization threshold and the frequency synchronization threshold, the first received signal is used as the second received signal;

[0036] Otherwise, it is determined that there is no time slot synchronization signal in the first received signal;

[0037] Obtaining a signal peak position of the second received signal as a synchronization peak position, and obtaining delay-related parameters based on device transmission performance, thereby obtaining an initial delay range for current device transmission;

[0038] Obtain the real-time bandwidth of the transmission traffic, thereby optimizing the initial delay range and obtaining the comprehensive delay range of real-time signal transmission;

[0039] Determine whether the second received signal is within the comprehensive delay range by combining the signal peak position of the standard time slot synchronization signal template and the synchronization peak position of the second received signal;

[0040] Obtaining an average performance similarity of the second received signal within a plurality of consecutive reference sliding windows based on the signal correlation performance;

[0041] If the second received signal is within the comprehensive delay range and the average performance similarity is higher than a preset minimum similarity, determining that a time slot synchronization signal exists in the second received signal;

[0042] If the second received signal is not within the comprehensive delay range, or does not have an average performance similarity higher than a preset minimum similarity, it is determined that no time slot synchronization signal exists in the received signal.

[0043] Preferably, the extracted feature information is subjected to preliminary time slot synchronization, including:

[0044] First, retrieve the characteristic information, and then perform preliminary time slot synchronization after the retrieval is completed;

[0045] Time slot synchronization is as follows: confirming the absolute starting position of the time slot synchronization signal in the received signal stream based on the retrieved start timestamp;

[0046] At the same time, the phase of the local clock is adjusted so that the phase of the local clock is aligned with the start time of the time slot synchronization signal;

[0047] Based on the retrieved center frequency, the deviation between the local clock frequency and the timeslot synchronization signal frequency is calculated. The frequency of the local clock is adjusted using a phase-locked loop (PLL). The process is as follows: the PLL compares the local clock frequency with the timeslot synchronization signal frequency, generates an error signal after comparison, and dynamically adjusts the local clock frequency based on the error signal.

[0048] During the time slot synchronization process, the time difference and frequency difference between the local clock and the time slot synchronization signal are monitored in real time;

[0049] If the time difference is not within the standard monitoring range, the phase of the local clock is adjusted;

[0050] If the frequency difference is not within the standard monitoring range, adjust the parameters of the phase-locked loop;

[0051] Until the time difference and frequency difference meet the requirements of coarse synchronization, wherein the requirements of coarse synchronization are: time difference ≤ 50 μs, frequency difference ≤ 50 Hz;

[0052] When both the time difference and the frequency difference are lower than the requirements for coarse synchronization, it is determined that coarse synchronization is completed;

[0053] When the time difference and frequency difference do not meet the standards, time slot synchronization continues.

[0054] Preferably, a secondary time slot synchronization is performed on the basis of the initial time slot synchronization, including:

[0055] Acquire the data after coarse synchronization;

[0056] The time difference between the local clock and the synchronization signal is measured using a time interval counter;

[0057] Based on the measured time difference, the local clock is fine-tuned using a digital signal processing algorithm;

[0058] Among them, the digital signal processing algorithm adjusts the timing of the local clock according to the size and direction of the time difference;

[0059] Then, the frequency of the time slot synchronization signal is estimated, and the frequency of the local clock is adjusted according to the estimated frequency of the time slot synchronization signal;

[0060] After adjusting the time and frequency, measure the time and frequency differences between the local clock and the timeslot synchronization signal again to determine the synchronization performance index of the secondary timeslot synchronization, thereby checking the effectiveness of the secondary timeslot synchronization.

[0061] If the measurement results show that there is still an error and the error exceeds the expected high-precision synchronization standard, the time and frequency will be readjusted according to the new error data until the time difference and frequency difference meet the high-precision synchronization requirements;

[0062] When the time difference and frequency difference between the local clock and the time slot synchronization signal reach the set high-precision synchronization standard, the secondary time slot synchronization is completed.

[0063] Preferably, a multi-level check is performed after the secondary time slot synchronization, including:

[0064] After the secondary time slot synchronization is completed, data verification is performed, which includes time verification, frequency verification and phase verification;

[0065] Time verification involves using a time interval counter to measure the time difference between the local clock and the time slot synchronization signal. If the time difference is within the preset time threshold, the time verification is considered qualified. If the time difference is not within the preset time threshold, the data is marked as time synchronization abnormality.

[0066] Frequency verification involves observing the time slot synchronization signal for a long time and calculating the residual frequency deviation through spectrum analysis. If the frequency deviation is within the preset time threshold, the frequency verification is qualified; if the frequency deviation is not within the preset time threshold, it is marked as frequency synchronization abnormal data.

[0067] Phase verification is as follows: extract the phase change curve of the time slot synchronization signal and calculate the phase jump amplitude and phase noise power. If the phase noise power is within the preset time threshold range, the phase verification is qualified; if the phase noise power is not within the preset time threshold range, it is marked as phase synchronization abnormal data;

[0068] According to the data verification results, the data with verification abnormalities are processed abnormally;

[0069] Among them, the abnormal processing is to re-perform the initial time slot synchronization and the secondary time slot synchronization, and after the synchronization is completed, perform multi-level verification again until all the verifications are qualified.

[0070] Preferably, allocating time slots in the AIS base station according to the multi-level verification results includes:

[0071] Monitor the time slot resources currently occupied by each AIS device in the AIS base station in real time, and record the time slot number, occupancy time, and remaining available time slots of each device. Receive the communication demand information reported by each AIS device, including data transmission volume, communication priority, and expected communication duration, and finally obtain AIS device information.

[0072] The AIS equipment information uses a time division multiple access algorithm to divide time into a series of fixed-length time slots, each of which is allocated to a specific device;

[0073] The allocation strategy is formulated based on the communication needs and time slot usage of the devices. The allocation strategy is as follows: for devices with high priority and large data transmission volume, continuous and long time slots are preferentially allocated; for devices with low priority and small data transmission volume, scattered or shorter time slots are allocated.

[0074] Allocate each time slot to the corresponding AIS device one by one according to the allocation strategy, and generate a time slot allocation table;

[0075] The generated time slot allocation table is sent to each AIS device. After receiving the allocation result, the AIS device analyzes and confirms it.

[0076] Each AIS device communicates according to the allocated time slot, sending and receiving data within its own time slot.

[0077] Preferably, synchronous execution is performed according to the allocation results, and the execution process is monitored and adjusted, including:

[0078] When AIS devices send and receive data in their respective time slots, the communication process of each AIS device is monitored in real time;

[0079] The communication status information of the AIS device is collected, including the data transmission success rate, the integrity of the received data and the time slot occupancy;

[0080] Dynamically adjust the real-time monitoring results. Dynamic adjustment means: based on the monitoring results, if there is a communication anomaly or unreasonable time slot allocation, reallocate the time slot or adjust the communication parameters of the AIS equipment;

[0081] Adjusting the communication parameters of the AIS equipment includes: first analyzing and locating abnormal communication data based on monitoring results, and confirming the adjustment instructions of transmission parameters, time parameters or network parameters based on the abnormal causes of the abnormal communication data;

[0082] Parameter adjustments are executed according to the adjustment instructions, and the communication status of the AIS equipment after execution is verified and optimized.

[0083] Compared with the prior art, the present invention has the following beneficial effects:

[0084] 1. This invention provides an AIS multi-level time slot synchronization method. A low-noise amplifier (LNA) controls its own noise while amplifying the signal. This improves the signal-to-noise ratio (SNR) in weak signal conditions and prevents noise from overwhelming the signal. During feature extraction, the start timestamp is determined by detecting amplitude mutation points or the starting position of a specific synchronization pattern. The center frequency is determined through frequency domain analysis, and the initial phase value is calculated in conjunction with frequency information, helping to improve the accuracy of feature extraction.

[0085] 2. The present invention provides an AIS multi-level time slot synchronization method that utilizes a phase-locked loop to dynamically adjust the local clock frequency. Based on the calculated frequency deviation, the local clock frequency is automatically adjusted to a state close to the time slot synchronization signal frequency. This reduces manual intervention and the complexity of adjustment, improving the system's automation and stability. The method estimates the time slot synchronization signal frequency and adjusts the local clock frequency accordingly, enabling the system to adapt to changes in signal frequency. The method is applicable to a variety of different application scenarios and signal environments, and processes data with verification anomalies to prevent the impact of abnormal data on subsequent system operation, thereby ensuring data quality and normal system operation.

[0086] 3. The present invention provides an AIS multi-level time slot synchronization method that uses a time division multiple access algorithm to divide time into fixed-length time slots. These are allocated one by one based on device information and allocation strategies, generating a time slot allocation table. This achieves precise time slot allocation, enabling each device to communicate within its designated time slot, reducing the possibility of communication conflicts. By real-time monitoring of the communication process of AIS devices within their respective time slots, communication anomalies can be promptly detected and appropriate measures can be taken to address them. This helps ensure the stability and reliability of AIS device communications and reduces data transmission errors and losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Figure 1 Schematic diagram of the process of multi-level time slot synchronization of the present invention. DETAILED DESCRIPTION

[0088] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0089] Example 1:

[0090] In order to solve the problem in the prior art that signal data is not further processed and extracted after acquisition, which leads to inaccurate signal data acquisition, please refer to Figure 1 , this embodiment provides the following technical solutions:

[0091] An AIS multi-level time slot synchronization method, comprising:

[0092] First, the signal sent by the AIS base station is received, the received signal is identified as a time slot synchronization signal, and characteristic information is extracted. The extracted characteristic information is used for preliminary time slot synchronization. Based on the preliminary time slot synchronization, secondary time slot synchronization is performed. After the secondary time slot synchronization, multi-level verification is performed. The time slots in the AIS base station are allocated according to the multi-level verification results. Finally, synchronization execution is carried out according to the allocation results, and the execution process is monitored and adjusted.

[0093] Specifically, by first performing initial time slot synchronization and then performing secondary time slot synchronization based on this, this multi-level synchronization mechanism can gradually improve synchronization accuracy, reduce time slot errors, and make the time slot synchronization of the AIS system more accurate, helping to ensure the accuracy and timeliness of data transmission. After the secondary time slot synchronization, multi-level verification is performed, which can conduct multi-faceted and multi-level inspections of the synchronization results, and promptly detect errors or abnormalities that may occur during the synchronization process. When problems are found during the verification, timely measures can be taken to make adjustments, thereby improving the reliability of the entire synchronization process and reducing the risk of system failure or data loss due to synchronization errors. Monitoring and adjustment during the synchronization execution process can track the system's operating status in real time, promptly detect synchronization deviations caused by various factors (such as clock drift, external interference, etc.), and make timely adjustments to ensure that the system always maintains a good synchronization state and adapts to different working environments and operating conditions.

[0094] First, receive the signal sent by the AIS base station, including:

[0095] Before receiving the signal sent by the AIS base station, first confirm the direction of the AIS frequency band and adjust the position and angle of the antenna;

[0096] The received signal is transmitted to a low-noise amplifier, which amplifies the signal while controlling the noise generated by the low-noise amplifier itself;

[0097] The low-noise amplifier introduces the amplified signal into the filter, which blocks and attenuates the interference signals outside the effective frequency band.

[0098] The filtered signal is transmitted to an analog-to-digital converter. The analog-to-digital converter discretely samples the signal according to the sampling frequency and quantization accuracy, converts the continuous signal amplitude value into the corresponding digital code, and converts the analog AIS signal into a digital signal.

[0099] Finally, the reception of AIS base station signal is completed.

[0100] Specifically, prior to receiving a signal, the AIS frequency band is oriented and the antenna position and angle are adjusted. This allows the antenna to precisely align with the signal source, enhancing the target signal strength, reducing interference from other directions, and improving the accuracy and stability of the received signal. The filter blocks and attenuates interference signals outside the effective frequency band, further enhancing signal purity and ensuring that the subsequently processed signal more accurately reflects the original AIS signal, reducing bit error rates and improving data transmission accuracy. The low-noise amplifier controls its own noise while amplifying the signal. In weak signal conditions, it improves the signal-to-noise ratio, preventing noise from overwhelming the signal, and enhancing signal quality, facilitating subsequent signal analysis and processing. The analog-to-digital converter converts the analog signal into a digital signal, which has the advantages of strong anti-interference capabilities and ease of storage, transmission, and processing. After discrete sampling and quantization encoding, the signal can be easily processed, analyzed, and stored by digital circuits or computers, facilitating further optimization and feature extraction using various digital signal processing algorithms.

[0101] The received signal is identified as a time slot synchronization signal and feature information is extracted, including:

[0102] Comparing the received signal with a standard time slot synchronization signal template, wherein the standard time slot synchronization signal template is a digital signal sample of a standard time slot synchronization signal characteristic, and the standard time slot synchronization signal template is retrieved from a database;

[0103] The comparison process calculates the similarity between the received signal and the standard time slot synchronization signal template at different time points and frequency segments, and determines whether the time slot synchronization signal exists in the received signal based on the similarity between the received signal and the standard time slot synchronization signal template at different time points and frequency segments;

[0104] Compare and judge the comparison result threshold with the standard time slot synchronization threshold;

[0105] If the comparison result threshold exceeds the standard time slot synchronization threshold, the similarity between the received signal and the standard time slot synchronization signal template is high, and the time slot synchronization signal exists in the received signal;

[0106] If the comparison result threshold does not reach the standard time slot synchronization threshold, then there is no time slot synchronization signal in the received signal, and the subsequent received signal is detected;

[0107] Extract characteristic information of the time slot synchronization signal, including the starting timestamp, center frequency and initial phase value; the time slot synchronization implementation method flow

[0108] The extraction of the start timestamp is as follows: by detecting the amplitude mutation point of the timeslot synchronization signal or the starting position of a specific synchronization pattern, the precise start timestamp of the timeslot synchronization signal in the overall received signal is determined;

[0109] The center frequency is extracted by performing frequency domain analysis on the time slot synchronization signal to determine the center frequency and frequency offset of the time slot synchronization signal;

[0110] The initial phase value is extracted by detecting the phase value and phase variation law of the time slot synchronization signal at the start time, and calculating the phase noise level of the time slot synchronization signal in combination with the frequency information;

[0111] The extracted characteristic information is integrated into a data set, and after the integration is completed, a characteristic information data set of the time slot synchronization signal is obtained.

[0112] Determine whether the received signal contains a timeslot synchronization signal based on the similarity between different time points and frequency segments, including:

[0113] Determining the size of the sliding window for comparison based on the length of the standard time slot synchronization signal template as a reference sliding window;

[0114] Determine the sliding step size of the reference sliding window during the comparison of received signals based on the required accuracy of real-time time slot synchronization;

[0115] Comparing the sub-received signal within each reference sliding window with the standard time slot synchronization signal template to determine the signal correlation performance of each sub-received signal with the standard time slot synchronization signal template;

[0116] If the signal correlation performance is greater than a preset minimum correlation performance, taking the received signal corresponding to the sub-received signal as the first received signal;

[0117] If the signal correlation performance is not greater than the preset minimum correlation performance, it is determined that there is no time slot synchronization signal in the received signal corresponding to the current sub-received signal;

[0118] Determine the time synchronization threshold and frequency synchronization threshold for the real-time received signal based on the characteristics of the real-time received signal and the required accuracy of the real-time time slot synchronization;

[0119] If a signal peak value in the current first received signal exceeds the time synchronization threshold and the frequency synchronization threshold, the first received signal is used as the second received signal;

[0120] Otherwise, it is determined that there is no time slot synchronization signal in the first received signal;

[0121] Obtaining a signal peak position of the second received signal as a synchronization peak position, and obtaining delay-related parameters based on device transmission performance, thereby obtaining an initial delay range for current device transmission;

[0122] Obtain the real-time bandwidth of the transmission traffic, thereby optimizing the initial delay range and obtaining the comprehensive delay range of real-time signal transmission;

[0123] Determine whether the second received signal is within the comprehensive delay range by combining the signal peak position of the standard time slot synchronization signal template and the synchronization peak position of the second received signal;

[0124] Obtaining an average performance similarity of the second received signal within a plurality of consecutive reference sliding windows based on the signal correlation performance;

[0125] If the second received signal is within the comprehensive delay range and the average performance similarity is higher than a preset minimum similarity, determining that a time slot synchronization signal exists in the second received signal;

[0126] If the second received signal is not within the comprehensive delay range, or does not have an average performance similarity higher than a preset minimum similarity, it is determined that no time slot synchronization signal exists in the received signal.

[0127] In this embodiment, a sliding window is a technique used for signal processing and data stream analysis. It refers to a fixed-length window defined within a signal data stream. The window slides across the signal data stream, one step at a time, to process and analyze the data within the window. For example, if the received signal length is 50 sub-signals, the sliding window size is 10 signal samples, and the sliding step is 2 signal samples, the window will slide from the first signal sample to the 42nd signal sample (because the window length is 10, the final position is 50-10+2=42), sliding 2 signal samples at a time, for a total of 42 slides.

[0128] In this embodiment, the reference sliding window is a window used for comparison with the received signal, and its size is determined according to the length of the standard time slot synchronization signal template to ensure that the signal portion within the window can be fully compared with the template.

[0129] In this embodiment, the sliding step size is the distance that the sliding window moves each time it slides, and is determined based on the required accuracy of real-time time slot synchronization. The smaller the step size, the higher the detection accuracy.

[0130] In this embodiment, the signal correlation performance refers to the degree of similarity between the received signal and the standard time slot synchronization signal template. For example, it can be evaluated by calculating the cross-correlation function or other similarity metrics between the signals, and the higher the peak value of the cross-correlation function, the more similar the two signals are.

[0131] In this embodiment, the preset minimum correlation performance is a pre-set correlation threshold, which is used to determine whether the received signal is close enough to the standard time slot synchronization signal template. If the signal correlation performance is higher than the preset minimum correlation performance, it is considered that the signal may be a synchronization signal. For example, if the preset minimum correlation performance is 0.8, then only when the signal correlation performance is greater than 0.8, the sub-received signal is considered to match the standard time slot synchronization signal template.

[0132] In this embodiment, the time synchronization threshold and the frequency synchronization threshold are used to determine the synchronization of the signal in time and frequency. The time synchronization threshold is used to detect the degree of alignment of the signal in time, while the frequency synchronization threshold is used to detect the degree of alignment of the signal in frequency.

[0133] In this embodiment, the signal peak value refers to the maximum value of the signal at a specific time or frequency. In synchronous signal detection, the peak value is usually used to identify the starting or ending position of the signal.

[0134] In this embodiment, the synchronization peak position refers to the position in the received signal where the degree of match with the standard time slot synchronization signal template is the highest, that is, the position where the signal correlation performance is the highest. For example, in the calculation of the cross-correlation function, the synchronization peak position is the position where the cross-correlation function achieves its maximum value.

[0135] In this implementation, delay-related parameters refer to parameters related to the delay of a signal during transmission, such as propagation delay and processing delay. Propagation delay may be related to the distance and speed of signal propagation, while processing delay may be related to the signal processing speed within the device.

[0136] In this embodiment, the initial delay range is calculated based on delay-related parameters, indicating the delay range that a signal may experience during transmission. For example, if the calculated propagation delay is 10 ms and the processing delay is 2 ms, then the initial delay range may be 8 ms to 12 ms.

[0137] In this embodiment, the real-time bandwidth refers to the signal data transmission capacity available in the current network or communication link, and the bandwidth affects the speed and delay of signal transmission.

[0138] In this embodiment, the comprehensive delay range is a delay range obtained by optimizing the initial delay range according to the real-time bandwidth of the transmission traffic.

[0139] In this embodiment, the average performance similarity is the result of averaging the similarity between the second received signal and the standard template in multiple consecutive reference sliding windows, which is used to evaluate the stability and consistency of the signal. For example, the average value of the signal correlation performance of the second received signal in 5 consecutive reference sliding windows can be calculated as the average performance similarity.

[0140] In this embodiment, the preset minimum similarity is a pre-set similarity threshold used to determine signal stability within multiple windows. If the average performance similarity exceeds this threshold, the signal is considered stable and likely a synchronization signal. For example, if the preset minimum similarity is 0.75, then the second received signal is considered to consistently match the standard time slot synchronization signal template only when the average performance similarity is greater than 0.75.

[0141] The working principle of the above technical solution is: first, the reference sliding window size is determined according to the length of the standard time slot synchronization signal template, and the sliding step size is set based on the synchronization requirement accuracy; then, the sub-received signal in the window is compared with the template, and the signal correlation performance is calculated. If the performance meets the standard, the received signal is used as the first received signal, and the time and frequency synchronization thresholds are set according to the signal characteristics and the synchronization requirement accuracy, and the first received signal with peak values ​​exceeding the threshold is screened out as the second received signal. At the same time, by obtaining the synchronization peak position of the second received signal, the comprehensive delay range is determined in combination with the equipment transmission performance; thus, by comparing the peak position of the second received signal with that of the standard time slot synchronization signal template, it is determined whether the second received signal is within the comprehensive delay range, and combined with the average performance similarity in the continuous window, it is comprehensively determined whether there is a time slot synchronization signal in the second received signal.

[0142] The beneficial effects of the above technical solution are: by comparing the sliding window with the standard time slot synchronization signal template, it is possible to effectively screen out the received signals that may contain time slot synchronization signals, reduce the amount of data, improve the judgment efficiency, and set the threshold in combination with the real-time synchronization requirements to more accurately judge the signal synchronization situation. At the same time, by obtaining the synchronization peak position of the received signal and using the equipment performance and real-time bandwidth to optimize the delay range, position comparison is performed, and the accuracy of synchronization detection of the received signal is further improved. Therefore, by comprehensively judging whether the signal is within the delay range and the degree of performance similarity, the time slot synchronization signal can be accurately identified, communication synchronization can be guaranteed, and system stability and reliability can be improved.

[0143] Specifically, by comparing the received signal with the standard time slot synchronization signal template, calculating the similarity of different time points and frequency segments, and comparing it with the standard time slot synchronization threshold, it is possible to accurately determine whether there is a time slot synchronization signal in the received signal, reducing the possibility of misjudgment and missed judgment. In the feature information extraction process, the starting timestamp is determined by detecting the amplitude mutation point or the starting position of a specific synchronization code type, the center frequency is determined by frequency domain analysis, and the initial phase value is calculated in combination with the frequency information. These methods all help to improve the accuracy of feature information extraction. The standard time slot synchronization signal template is retrieved from the database, which ensures the standardization and stability of the comparison, so that the entire identification and feature extraction process has a reliable basis. Multiple feature information of the time slot synchronization signal is extracted and integrated to form a feature information data set, which describes the signal from multiple dimensions, improves the comprehensive grasp of the signal characteristics, enhances the reliability of the solution, and can adapt to different received signal conditions. Whether the amplitude, frequency or phase of the signal changes, the feature information can be extracted through corresponding detection and analysis methods. For example, when extracting the start timestamp, it can be determined by detecting either the amplitude mutation point or the starting position of a specific synchronization pattern, increasing the solution's adaptability to different signal characteristics. The extracted feature information can be integrated into a data set for further analysis, processing, and application, providing a foundation for system functionality expansion. For example, this feature information can be used for signal classification, identification of different types of time slot synchronization signals, and data sharing and collaboration with other related systems.

[0144] Example 2:

[0145] In order to solve the problem in the prior art that the acquired signal data is not fully synchronized, thereby reducing the signal data synchronization effect, please refer to Figure 1 , this embodiment provides the following technical solutions:

[0146] Perform preliminary time slot synchronization on the extracted feature information, including:

[0147] First, retrieve the characteristic information, and then perform preliminary time slot synchronization after the retrieval is completed;

[0148] Time slot synchronization is as follows: confirming the absolute starting position of the time slot synchronization signal in the received signal stream based on the retrieved start timestamp;

[0149] At the same time, the phase of the local clock is adjusted so that the phase of the local clock is aligned with the start time of the time slot synchronization signal;

[0150] Based on the retrieved center frequency, the deviation between the local clock frequency and the timeslot synchronization signal frequency is calculated. The frequency of the local clock is adjusted using a phase-locked loop (PLL). The process is as follows: the PLL compares the local clock frequency with the timeslot synchronization signal frequency, generates an error signal after comparison, and dynamically adjusts the local clock frequency based on the error signal.

[0151] During the time slot synchronization process, the time difference and frequency difference between the local clock and the time slot synchronization signal are monitored in real time;

[0152] If the time difference is not within the standard monitoring range, the phase of the local clock is adjusted;

[0153] If the frequency difference is not within the standard monitoring range, adjust the parameters of the phase-locked loop;

[0154] Until the time difference and frequency difference meet the requirements of coarse synchronization, wherein the requirements of coarse synchronization are: time difference ≤ 50 μs, frequency difference ≤ 50 Hz;

[0155] When both the time difference and the frequency difference are lower than the requirements for coarse synchronization, it is determined that coarse synchronization is completed;

[0156] When the time difference and frequency difference do not meet the standards, time slot synchronization continues.

[0157] Specifically, by confirming the absolute starting position of the time slot synchronization signal in the received signal stream based on the retrieved start timestamp and adjusting the local clock phase to align it with the start time, accurate time slot synchronization can be achieved, ensuring that the system processes signals at the correct time point, improving the accuracy of signal reception and processing. The local clock frequency is dynamically adjusted using a phase-locked loop (PLL), and can be automatically adjusted to a state close to the frequency of the time slot synchronization signal based on the calculated frequency deviation, reducing the complexity of manual intervention and adjustment, and improving the automation and stability of the system. During the time slot synchronization process, the time difference and frequency difference between the local clock and the time slot synchronization signal are monitored in real time, and the phase of the local clock and the parameters of the PLL are adjusted in a timely manner based on the monitoring results, enabling the system to adapt to different working environments and signal changes, with good adaptability and robustness. Clear coarse synchronization requirements are set, namely, time difference ≤ 50 μs and frequency difference ≤ 50 Hz, providing clear goals and judgment basis for the synchronization process, helping to ensure the quality and reliability of synchronization, and facilitating system design, debugging, and evaluation.

[0158] Based on the initial time slot synchronization, the secondary time slot synchronization is performed, including:

[0159] Acquire the data after coarse synchronization;

[0160] The time difference between the local clock and the synchronization signal is measured using a time interval counter;

[0161] Based on the measured time difference, the local clock is fine-tuned using a digital signal processing algorithm;

[0162] Among them, the digital signal processing algorithm adjusts the timing of the local clock according to the size and direction of the time difference;

[0163] Then, the frequency of the time slot synchronization signal is estimated, and the frequency of the local clock is adjusted according to the estimated frequency of the time slot synchronization signal;

[0164] After adjusting the time and frequency, measure the time and frequency differences between the local clock and the timeslot synchronization signal again to determine the synchronization performance index of the secondary timeslot synchronization, thereby checking the effectiveness of the secondary timeslot synchronization.

[0165] If the measurement results show that there is still an error and the error exceeds the expected high-precision synchronization standard, the time and frequency will be readjusted according to the new error data until the time difference and frequency difference meet the high-precision synchronization requirements;

[0166] When the time difference and frequency difference between the local clock and the time slot synchronization signal reach the set high-precision synchronization standard, the secondary time slot synchronization is completed.

[0167] In this embodiment, the synchronization performance index of the secondary time slot synchronization is T;

[0168]

[0169] Where T is the synchronization performance index of the secondary time slot synchronization, is the time performance index, is the frequency performance index, α1 is the time performance weight, α2 is the frequency performance weight, t is is the signal time representation value corresponding to the i-th signal in the local clock, t i is the signal time representation value of the i-th signal extracted from the time slot synchronization signal, p is is the signal frequency representation value corresponding to the i-th signal in the local clock, p i is the signal frequency representation value of the i-th signal extracted from the time slot synchronization signal, n is the number of signals randomly extracted from the time slot synchronization signal, where the value range of the time performance weight and the frequency performance weight is (0,1), and the sum of the time performance weight and the frequency performance weight is 1.

[0170] In this embodiment, the change in the value of n is related to the synchronization accuracy requirement. The higher the accuracy requirement, the larger the value of n, and the lower the accuracy requirement, the smaller the value of n.

[0171] In this embodiment, the time performance weight and the frequency performance weight are determined based on the degree of influence of the historical time difference and the historical frequency difference between the local clock and the time slot synchronization signal in the historical working process on the secondary time slot synchronization. The accuracy of the time performance weight and the frequency performance weight is related to the synchronization requirement accuracy. The higher the synchronization requirement accuracy, the higher the accuracy of the time performance weight and the frequency performance weight. For example, the time performance weight can be 0.6 and the frequency performance weight can be 0.4, or the time performance weight can be 0.506 and the frequency performance weight can be 0.494.

[0172] The beneficial effect of the above technical solution is: by determining the synchronization performance index of the secondary time slot synchronization, the secondary time slot synchronization effect can be clearly and accurately tested, which can make the secondary time slot synchronization effect test more accurate and effectively ensure the accuracy and stability of synchronization.

[0173] Specifically, by first measuring the time difference to fine-tune the local clock, then estimating the time slot synchronization signal frequency and adjusting the local clock frequency, and finally continuously measuring the error and readjusting it as needed, the time and frequency differences between the local clock and the time slot synchronization signal can reach the set high-precision synchronization standard, achieving precise time slot synchronization. The digital signal processing algorithm can flexibly adjust the local clock timing based on the size and direction of the time difference, adapting to different time difference situations. At the same time, the time slot synchronization signal frequency is estimated and the local clock frequency is adjusted accordingly, allowing the system to adapt to changes in signal frequency and be suitable for a variety of application scenarios and signal environments. After each adjustment, the time and frequency differences are measured again to check the synchronization effect. If the error exceeds the standard, the system is readjusted based on the new error data. This closed-loop feedback mechanism continuously optimizes the synchronization effect, ensuring that the system always adjusts towards the goal of high-precision synchronization, effectively ensuring the accuracy and stability of synchronization.

[0174] After the secondary time slot synchronization, multi-level verification is performed, including:

[0175] After the secondary time slot synchronization is completed, data verification is performed, which includes time verification, frequency verification and phase verification;

[0176] Time verification involves using a time interval counter to measure the time difference between the local clock and the time slot synchronization signal. If the time difference is within the preset time threshold, the time verification is considered qualified. If the time difference is not within the preset time threshold, the data is marked as time synchronization abnormality.

[0177] Frequency verification involves observing the time slot synchronization signal for a long time and calculating the residual frequency deviation through spectrum analysis. If the frequency deviation is within the preset time threshold, the frequency verification is qualified; if the frequency deviation is not within the preset time threshold, it is marked as frequency synchronization abnormal data.

[0178] Phase verification is as follows: extract the phase change curve of the time slot synchronization signal and calculate the phase jump amplitude and phase noise power. If the phase noise power is within the preset time threshold range, the phase verification is qualified; if the phase noise power is not within the preset time threshold range, it is marked as phase synchronization abnormal data;

[0179] According to the data verification results, the data with verification abnormalities are processed abnormally;

[0180] Among them, the abnormal processing is to re-perform the initial time slot synchronization and the secondary time slot synchronization, and after the synchronization is completed, perform multi-level verification again until all the verifications are qualified.

[0181] Specifically, through verification in the three dimensions of time, frequency and phase, the accuracy of time slot synchronization can be comprehensively and accurately evaluated, ensuring high-precision synchronization of the system in time and frequency, meeting application scenarios with high synchronization requirements, and being able to promptly detect synchronization abnormalities in time, frequency and phase, and correct errors by re-synchronizing the time slot and performing multi-level verification, thereby improving the reliability and stability of the system. By observing and analyzing the time slot synchronization signal for a long time, the synchronization state can be adaptively adjusted according to actual conditions, adapting to different working environments and signal changes, and enhancing the adaptability and robustness of the system. The data with verification abnormalities can be processed to avoid the impact of abnormal data on the subsequent operation of the system, thereby ensuring the quality of data and the normal operation of the system. The complete process from data verification to exception handling forms a systematic synchronization verification mechanism, which helps to improve the performance and reliability of the entire system.

[0182] Example 3:

[0183] In order to solve the problem in the existing technology that there is no targeted adjustment of AIS device allocation based on the final allocation data and no effective monitoring of the device allocation process, which leads to poor allocation results, please refer to Figure 1 , this embodiment provides the following technical solutions:

[0184] The time slots in the AIS base station are allocated based on the multi-level verification results, including:

[0185] Monitor the time slot resources currently occupied by each AIS device in the AIS base station in real time, and record the time slot number, occupancy time, and remaining available time slots of each device. Receive the communication demand information reported by each AIS device, including data transmission volume, communication priority, and expected communication duration, and finally obtain AIS device information.

[0186] The AIS equipment information uses a time division multiple access algorithm to divide time into a series of fixed-length time slots, each of which is allocated to a specific device;

[0187] The allocation strategy is formulated based on the communication needs and time slot usage of the devices. The allocation strategy is as follows: for devices with high priority and large data transmission volume, continuous and long time slots are preferentially allocated; for devices with low priority and small data transmission volume, scattered or shorter time slots are allocated.

[0188] Allocate each time slot to the corresponding AIS device one by one according to the allocation strategy, and generate a time slot allocation table;

[0189] The generated time slot allocation table is sent to each AIS device. After receiving the allocation result, the AIS device analyzes and confirms it.

[0190] Each AIS device communicates according to the allocated time slot, sending and receiving data within its own time slot.

[0191] Specifically, by real-time monitoring of the time slot resource occupancy and remaining available time slots of each AIS device in the AIS base station, time slots can be allocated according to the actual needs of the device, avoiding resource waste and improving the utilization rate of time slot resources. The allocation strategy gives priority to allocating continuous and longer time slots to devices with high priority and large data transmission volume, ensuring the communication quality and efficiency of important equipment and the smooth progress of key services. For devices with low priority and small data transmission volume, scattered or shorter time slots are allocated. It can flexibly respond to the diverse communication needs of different devices, so that the system can adapt to various complex communication scenarios. The time division multiple access algorithm is used to divide time into fixed-length time slots, and they are allocated one by one according to device information and allocation strategy to generate a time slot allocation table, realizing accurate allocation of time slots, so that each device can communicate within the specified time slot, reducing the possibility of communication conflicts. Each AIS device communicates according to the allocated time slot, sending and receiving data in its own time slot, making the entire communication process more orderly and improving the stability and reliability of the system.

[0192] Perform synchronous execution based on the allocation results, and monitor and adjust the execution process, including:

[0193] When AIS devices send and receive data in their respective time slots, the communication process of each AIS device is monitored in real time;

[0194] The communication status information of the AIS device is collected, including the data transmission success rate, the integrity of the received data and the time slot occupancy;

[0195] Dynamically adjust the real-time monitoring results. Dynamic adjustment means: based on the monitoring results, if there is a communication anomaly or unreasonable time slot allocation, reallocate the time slot or adjust the communication parameters of the AIS equipment;

[0196] Adjusting the communication parameters of the AIS equipment includes: first analyzing and locating abnormal communication data based on monitoring results, and confirming the adjustment instructions of transmission parameters, time parameters or network parameters based on the abnormal causes of the abnormal communication data;

[0197] Parameter adjustments are executed according to the adjustment instructions, and the communication status of the AIS equipment after execution is verified and optimized.

[0198] Specifically, by real-time monitoring of the communication process of AIS devices within their respective time slots, communication anomalies such as low data transmission success rates and incomplete received data can be promptly detected and adjusted accordingly. This helps ensure the stability and reliability of AIS device communications, reduce data transmission errors and losses, and ensure smooth communication. Monitoring time slot occupancy can promptly detect unreasonable time slot allocation and subsequently reallocate time slots, optimizing the utilization of time slot resources, avoiding time slot waste or conflicts, and improving the communication efficiency of the entire system. AIS devices can more effectively utilize limited communication resources for data transmission. Based on the monitoring results, the communication parameters of AIS devices can be adjusted. Transmission parameters, timing parameters, or network parameters can be precisely adjusted to address different anomaly causes, enabling the system to adapt to various complex communication environments and changes. This enhances the system's flexibility and adaptability and improves its ability to cope with various interferences and failures. The adjusted communication status of AIS devices is then verified and optimized, forming a closed-loop feedback system from monitoring, analysis, adjustment, to verification and optimization. This closed-loop mechanism helps continuously improve system performance, continuously enhance the communication quality and efficiency of AIS devices, and ensure that the system is always in optimal operation.

[0199] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0200] While the embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various changes, modifications, substitutions, and alterations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. An AIS multi-level time slot synchronization method, characterized in that: include: First, the signal sent by the AIS base station is received, the received signal is identified as a time slot synchronization signal, and characteristic information is extracted. The extracted characteristic information is used for preliminary time slot synchronization. Based on the preliminary time slot synchronization, secondary time slot synchronization is performed. After the secondary time slot synchronization, multi-level verification is performed. The time slots in the AIS base station are allocated according to the multi-level verification results. Finally, synchronization execution is carried out according to the allocation results, and the execution process is monitored and adjusted.

2. The AIS multi-level time slot synchronization method according to claim 1, characterized in that: First, receive the signal sent by the AIS base station, including: Before receiving the signal sent by the AIS base station, first confirm the direction of the AIS frequency band and adjust the position and angle of the antenna; The received signal is transmitted to a low-noise amplifier, which amplifies the signal while controlling the noise generated by the low-noise amplifier itself; The low-noise amplifier introduces the amplified signal into the filter, which blocks and attenuates the interference signals outside the effective frequency band. The filtered signal is transmitted to an analog-to-digital converter. The analog-to-digital converter discretely samples the signal according to the sampling frequency and quantization accuracy, converts the continuous signal amplitude value into the corresponding digital code, and converts the analog AIS signal into a digital signal. Finally, the reception of AIS base station signal is completed.

3. The AIS multi-level time slot synchronization method according to claim 1, characterized in that: The received signal is identified as a time slot synchronization signal and feature information is extracted, including: Comparing the received signal with a standard time slot synchronization signal template, wherein the standard time slot synchronization signal template is a digital signal sample of a standard time slot synchronization signal characteristic, and the standard time slot synchronization signal template is retrieved from a database; The comparison process calculates the similarity between the received signal and the standard time slot synchronization signal template at different time points and frequency segments, and determines whether the time slot synchronization signal exists in the received signal based on the similarity at different time points and frequency segments; the comparison result threshold is compared with the standard time slot synchronization threshold for judgment; If the comparison result threshold exceeds the standard time slot synchronization threshold, the similarity between the received signal and the standard time slot synchronization signal template is high, and the time slot synchronization signal exists in the received signal; If the comparison result threshold does not reach the standard time slot synchronization threshold, then there is no time slot synchronization signal in the received signal, and the subsequent received signal is detected; Extract characteristic information of the time slot synchronization signal, the characteristic information includes the start timestamp, center frequency and initial phase value; the time slot synchronization implementation method flow; The extraction of the start timestamp is as follows: by detecting the amplitude mutation point of the timeslot synchronization signal or the starting position of a specific synchronization pattern, the precise start timestamp of the timeslot synchronization signal in the overall received signal is determined; The center frequency is extracted by performing frequency domain analysis on the time slot synchronization signal to determine the center frequency and frequency offset of the time slot synchronization signal; The initial phase value is extracted by detecting the phase value and phase variation law of the time slot synchronization signal at the start time, and calculating the phase noise level of the time slot synchronization signal in combination with the frequency information; The extracted characteristic information is integrated into a data set, and after the integration is completed, a characteristic information data set of the time slot synchronization signal is obtained.

4. The AIS multi-level time slot synchronization method according to claim 3, characterized in that: Determine whether the received signal contains a timeslot synchronization signal based on the similarity between different time points and frequency segments, including: Determining the size of the sliding window for comparison based on the length of the standard time slot synchronization signal template as a reference sliding window; Determine the sliding step size of the reference sliding window during the comparison of received signals based on the required accuracy of real-time time slot synchronization; Comparing the sub-received signal within each reference sliding window with the standard time slot synchronization signal template to determine the signal correlation performance of each sub-received signal with the standard time slot synchronization signal template; If the signal correlation performance is greater than a preset minimum correlation performance, taking the received signal corresponding to the sub-received signal as the first received signal; If the signal correlation performance is not greater than the preset minimum correlation performance, it is determined that there is no time slot synchronization signal in the received signal corresponding to the current sub-received signal; Determine the time synchronization threshold and frequency synchronization threshold for the real-time received signal based on the characteristics of the real-time received signal and the required accuracy of the real-time time slot synchronization; If a signal peak value in the current first received signal exceeds the time synchronization threshold and the frequency synchronization threshold, the first received signal is used as the second received signal; Otherwise, it is determined that there is no time slot synchronization signal in the first received signal; Obtaining a signal peak position of the second received signal as a synchronization peak position, and obtaining delay-related parameters based on device transmission performance, thereby obtaining an initial delay range for current device transmission; Obtain the real-time bandwidth of the transmission traffic, thereby optimizing the initial delay range and obtaining the comprehensive delay range of real-time signal transmission; Determine whether the second received signal is within the comprehensive delay range by combining the signal peak position of the standard time slot synchronization signal template and the synchronization peak position of the second received signal; Obtaining an average performance similarity of the second received signal within a plurality of consecutive reference sliding windows based on the signal correlation performance; If the second received signal is within the comprehensive delay range and the average performance similarity is higher than a preset minimum similarity, determining that a time slot synchronization signal exists in the second received signal; If the second received signal is not within the comprehensive delay range, or does not have an average performance similarity higher than a preset minimum similarity, it is determined that no time slot synchronization signal exists in the received signal.

5. The AIS multi-level time slot synchronization method according to claim 1, characterized in that: Perform preliminary time slot synchronization on the extracted feature information, including: First, retrieve the characteristic information, and then perform preliminary time slot synchronization after the retrieval is completed; Time slot synchronization is as follows: confirming the absolute starting position of the time slot synchronization signal in the received signal stream based on the retrieved start timestamp; At the same time, the phase of the local clock is adjusted so that the phase of the local clock is aligned with the start time of the time slot synchronization signal; Based on the retrieved center frequency, the deviation between the local clock frequency and the timeslot synchronization signal frequency is calculated. The frequency of the local clock is adjusted using a phase-locked loop (PLL). The process is as follows: the PLL compares the local clock frequency with the timeslot synchronization signal frequency, generates an error signal after comparison, and dynamically adjusts the local clock frequency based on the error signal. During the time slot synchronization process, the time difference and frequency difference between the local clock and the time slot synchronization signal are monitored in real time; If the time difference is not within the standard monitoring range, the phase of the local clock is adjusted; If the frequency difference is not within the standard monitoring range, adjust the parameters of the phase-locked loop; Until the time difference and frequency difference meet the requirements of coarse synchronization, wherein the requirements of coarse synchronization are: time difference ≤ 50 μs, frequency difference ≤ 50 Hz; When both the time difference and the frequency difference are lower than the requirements for coarse synchronization, it is determined that coarse synchronization is completed; When the time difference and frequency difference do not meet the standards, time slot synchronization continues.

6. The AIS multi-level time slot synchronization method according to claim 5, characterized in that: Based on the initial time slot synchronization, the secondary time slot synchronization is performed, including: Acquire the data after coarse synchronization; The time difference between the local clock and the synchronization signal is measured using a time interval counter; Based on the measured time difference, the local clock is fine-tuned using a digital signal processing algorithm; Among them, the digital signal processing algorithm adjusts the timing of the local clock according to the size and direction of the time difference; Then, the frequency of the time slot synchronization signal is estimated, and the frequency of the local clock is adjusted according to the estimated frequency of the time slot synchronization signal; After adjusting the time and frequency, measure the time and frequency differences between the local clock and the timeslot synchronization signal again to determine the synchronization performance index of the secondary timeslot synchronization, thereby checking the effectiveness of the secondary timeslot synchronization. If the measurement results show that there is still an error and the error exceeds the expected high-precision synchronization standard, the time and frequency will be readjusted according to the new error data until the time difference and frequency difference meet the high-precision synchronization requirements; When the time difference and frequency difference between the local clock and the time slot synchronization signal reach the set high-precision synchronization standard, the secondary time slot synchronization is completed.

7. The AIS multi-level time slot synchronization method according to claim 1, characterized in that: After the secondary time slot synchronization, multi-level verification is performed, including: After the secondary time slot synchronization is completed, data verification is performed, which includes time verification, frequency verification and phase verification; Time verification involves using a time interval counter to measure the time difference between the local clock and the time slot synchronization signal. If the time difference is within the preset time threshold, the time verification is considered qualified. If the time difference is not within the preset time threshold, the data is marked as time synchronization abnormality. Frequency verification involves observing the time slot synchronization signal for a long time and calculating the residual frequency deviation through spectrum analysis. If the frequency deviation is within the preset time threshold, the frequency verification is qualified; if the frequency deviation is not within the preset time threshold, it is marked as frequency synchronization abnormal data. Phase verification is as follows: extract the phase change curve of the time slot synchronization signal and calculate the phase jump amplitude and phase noise power. If the phase noise power is within the preset time threshold range, the phase verification is qualified; if the phase noise power is not within the preset time threshold range, it is marked as phase synchronization abnormal data; According to the data verification results, the data with verification abnormalities are processed abnormally; Among them, the abnormal processing is to re-perform the initial time slot synchronization and the secondary time slot synchronization, and after the synchronization is completed, perform multi-level verification again until all the verifications are qualified.

8. The AIS multi-level time slot synchronization method according to claim 1, characterized in that: The time slots in the AIS base station are allocated based on the multi-level verification results, including: Monitor the time slot resources currently occupied by each AIS device in the AIS base station in real time, and record the time slot number, occupancy time, and remaining available time slots of each device. Receive the communication demand information reported by each AIS device, including data transmission volume, communication priority, and expected communication duration, and finally obtain AIS device information. The AIS equipment information uses a time division multiple access algorithm to divide time into a series of fixed-length time slots, each of which is allocated to a specific device; The allocation strategy is formulated based on the communication needs and time slot usage of the devices. The allocation strategy is as follows: for devices with high priority and large data transmission volume, continuous and long time slots are preferentially allocated; for devices with low priority and small data transmission volume, scattered or shorter time slots are allocated. Allocate each time slot to the corresponding AIS device one by one according to the allocation strategy, and generate a time slot allocation table; The generated time slot allocation table is sent to each AIS device. After receiving the allocation result, the AIS device analyzes and confirms it. Each AIS device communicates according to the allocated time slot, sending and receiving data within its own time slot.

9. The AIS multi-level time slot synchronization method according to claim 8, characterized in that: Perform synchronous execution based on the allocation results, and monitor and adjust the execution process, including: When AIS devices send and receive data in their respective time slots, the communication process of each AIS device is monitored in real time; The communication status information of the AIS device is collected, including the data transmission success rate, the integrity of the received data and the time slot occupancy; Dynamically adjust the real-time monitoring results. Dynamic adjustment means: based on the monitoring results, if there is a communication anomaly or unreasonable time slot allocation, reallocate the time slot or adjust the communication parameters of the AIS equipment; Adjusting the communication parameters of the AIS equipment includes: first analyzing and locating abnormal communication data based on monitoring results, and confirming the adjustment instructions of transmission parameters, time parameters or network parameters based on the abnormal causes of the abnormal communication data; Parameter adjustments are executed according to the adjustment instructions, and the communication status of the AIS equipment after execution is verified and optimized.

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