Serial communication method and system based on pulse width characteristics, electronic equipment and medium

Abstract

The invention provides a serial communication method and system based on pulse width characteristics, electronic equipment and a medium, and belongs to the technical field of communication. The method is applied to first electronic equipment and comprises the following steps: acquiring start mark information and pulse width mark information to generate a first digital signal; calculating according to the pulse width adjustment proportion and a reference clock pulse width of the first electronic equipment carried by the pulse width mark information to obtain a target pulse width; obtaining an ID number and target data of the first electronic equipment, and combining the target pulse width to generate a second digital signal; obtaining segmentation mark information to generate a third digital signal; performing analysis according to the target data to obtain verification information, and generating a fourth digital signal according to the verification information and the target pulse width; obtaining stop sign information to generate a fifth digital signal; and integrating the five generated digital signals to obtain a final digital signal, and sending the final digital signal to the second electronic equipment. According to the invention, high-efficiency data transmission can be realized on a physical layer.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a serial communication method and system based on pulse width characteristics, an electronic device, and a medium. Background Art

[0002] In existing serial communication technology, it is usually required that the communication baud rate between different communication devices be unified in advance, and rely on a dedicated clock line to perform clock synchronization signal control to achieve data transmission between different communication devices. However, this implementation method is not conducive to efficient data transmission. Summary of the Invention

[0003] The main purpose of this application is to propose a serial communication method and system, electronic equipment and medium based on pulse width characteristics, aiming to rely on the differentiation of pulse widths corresponding to different logical values ​​to perform data encoding so as to achieve efficient data transmission at the physical layer.

[0004] To achieve the above objectives, one aspect of the present application provides a serial communication method based on pulse width characteristics, which is applied to a first electronic device. The method includes:

[0005] Acquire start flag information and pulse width flag information and then generate a signal to obtain a first digital signal; wherein the pulse width flag information carries a first reference clock pulse width of the first electronic device;

[0006] Calculating according to a preset pulse width adjustment ratio and the first reference clock pulse width to obtain a target pulse width, wherein the target pulse width includes pulse widths corresponding to different logic values;

[0007] Obtaining the ID number of the first electronic device and the target data to be sent, and then generating a signal in combination with the target pulse width to obtain a second digital signal;

[0008] Acquire segmentation mark information and then generate a signal to obtain a third digital signal;

[0009] Analyzing the target data to obtain verification information, and then generating a signal based on the verification information and the target pulse width to obtain a fourth digital signal;

[0010] Acquire stop sign information and then generate a signal to obtain a fifth digital signal;

[0011] The first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal are integrated to obtain a final digital signal and sent to a second electronic device.

[0012] Furthermore, the analyzing the target data to obtain verification information includes:

[0013] Encoding the target data to obtain a target bit string;

[0014] Statistical analysis is performed on the target bit string to obtain the number of specific logic value bits, the number of bytes, and the cumulative sum of bytes to form the verification information.

[0015] To achieve the above objectives, one aspect of the present application provides a serial communication method based on pulse width characteristics, which is applied to a second electronic device. The method includes:

[0016] Obtaining a final digital signal sent by a first electronic device, the final digital signal comprising a first digital signal, a second digital signal, and a fourth digital signal; wherein the first digital signal carries a first reference clock pulse width of the first electronic device, the second digital signal carries target data, and the fourth digital signal carries verification information, the verification information being obtained by analyzing the target data;

[0017] Analyzing the first reference clock pulse width from the first digital signal, and then calculating based on a preset pulse width adjustment ratio range to obtain a target pulse width range, wherein the target pulse width range includes pulse width ranges corresponding to different logic values;

[0018] Identifying all pulse widths to be measured related to the target data from the second digital signal, and then parsing all the pulse widths to be measured according to the target pulse width range to obtain a target bit string;

[0019] parsing the verification information from the fourth digital signal, and then verifying the target bit string based on the verification information;

[0020] If the verification is successful, the target bit string is decoded to obtain the target data.

[0021] Furthermore, the final digital signal further includes a third digital signal, the third digital signal carries segmentation flag information, and the segmentation flag information records a specific pulse width that exceeds the target pulse width range; parsing all the pulse widths to be measured according to the target pulse width range to obtain a target bit string includes:

[0022] If all the pulse widths to be measured do not all fall within the target pulse width range, then multiple consecutive pulse widths to be measured that do not fall within the target pulse width range among all the pulse widths to be measured are accumulated to obtain updated pulse widths to be measured;

[0023] parse the specific pulse width from the third digital signal, and analyze it in combination with the target pulse width range to formulate a correction strategy, wherein the correction strategy records multiple valid pulse width ranges and all logical value combinations corresponding to each valid pulse width range;

[0024] According to the correction strategy and the target pulse width range, assignment analysis is performed on all the updated pulse widths to be measured to generate the target bit string.

[0025] Furthermore, while generating the target bit string, the method further includes:

[0026] Prompt information is generated, where the prompt information is used to indicate whether other bit strings can be generated.

[0027] Furthermore, after verifying the target bit string according to the verification information, the method further includes:

[0028] If the verification is unsuccessful and the prompt information indicates that other bit strings can be generated, the target bit string is stored in a preset history set, and then, with the constraint that the newly generated target bit string is not included in the history set, the process returns to the step of performing assignment analysis on all updated pulse widths to be measured based on the correction strategy and the target pulse width range to generate the target bit string.

[0029] Furthermore, after verifying the target bit string according to the verification information, the method further includes:

[0030] If the verification is unsuccessful and the prompt information indicates that no other bit string can be generated, the first start flag information, the second reference clock pulse width and ID number of the second electronic device, and the first stop flag information are obtained and then the signal is generated to obtain a feedback digital signal and send it to the first electronic device, so that the first electronic device resends the target data according to the second reference clock pulse width carried by the feedback digital signal.

[0031] To achieve the above object, another aspect of the present application provides a communication system based on pulse width characteristics, the system comprising a first electronic device and a second electronic device;

[0032] The first electronic device is used to: obtain start flag information and pulse width flag information and then generate a signal to obtain a first digital signal; wherein the pulse width flag information carries the first reference clock pulse width of the first electronic device; calculate according to a preset pulse width adjustment ratio and the first reference clock pulse width to obtain a target pulse width, wherein the target pulse width includes pulse widths corresponding to different logical values; obtain the ID number of the first electronic device and the target data to be sent, and then generate a signal in combination with the target pulse width to obtain a second digital signal; obtain segmentation flag information and then generate a signal to obtain a third digital signal; analyze according to the target data to obtain verification information, and then generate a signal according to the verification information and the target pulse width to obtain a fourth digital signal; obtain stop flag information and then generate a signal to obtain a fifth digital signal; integrate the first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal to obtain a final digital signal and send it to the second electronic device;

[0033] The second electronic device is used to: obtain a final digital signal sent by the first electronic device, the final digital signal including a first digital signal, a second digital signal, and a fourth digital signal; wherein the first digital signal carries a first reference clock pulse width of the first electronic device, the second digital signal carries target data, and the fourth digital signal carries verification information, the verification information being obtained by analyzing the target data; parse the first reference clock pulse width from the first digital signal, and then calculate in combination with a preset pulse width adjustment ratio range to obtain a target pulse width range, the target pulse width range including pulse width ranges corresponding to different logical values; identify all pulse widths to be measured related to the target data from the second digital signal, and then parse all pulse widths to be measured according to the target pulse width range to obtain a target bit string; parse the verification information from the fourth digital signal, and then verify the target bit string based on the verification information; if the verification is successful, decode the target bit string to obtain the target data.

[0034] To achieve the above-mentioned purpose, another aspect of the present application proposes an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the above-mentioned method applied to the first electronic device or the above-mentioned method applied to the second electronic device.

[0035] To achieve the above objectives, another aspect of the present application proposes a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above method applied to the first electronic device or the above method applied to the second electronic device.

[0036] The present application includes at least the following beneficial effects: in the data transmission stage, the pulse width corresponding to different logical values ​​is limited by introducing a first reference clock pulse width to specially encode the device ID number, target data, and the verification information obtained by analyzing the target data, thereby achieving efficient data transmission at the physical layer. In the data reception stage, the target pulse width range is first set according to the first reference clock pulse width parsed from the first digital signal, and then the second digital signal is parsed according to the target pulse width range to efficiently and reliably restore the target bit string, without relying on the clock signal and the communication baud rate to segment and restore the communication electrical signal. Subsequently, the target bit string is successfully verified according to the verification information parsed from the fourth digital signal before the target data is decoded. The implementation process has the characteristics of strong anti-interference ability and high fault tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of a communication system based on pulse width characteristics provided by an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of a final digital signal generated by a first electronic device based on specific target data provided by an embodiment of the present application;

[0039] Figure 3 1 is a flow chart of a serial communication method based on pulse width characteristics applied to a first electronic device provided in an embodiment of the present application;

[0040] Figure 4 1 is a flow chart of a serial communication method based on pulse width characteristics applied to a second electronic device provided in an embodiment of the present application;

[0041] Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0043] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0046] In existing serial communication technology, it is usually required that the communication baud rate between different communication devices be unified in advance, and rely on a dedicated clock line to perform clock synchronization signal control to achieve data transmission between different communication devices. However, this implementation method is not conducive to efficient data transmission.

[0047] In view of this, the embodiments of the present application provide a serial communication method and system based on pulse width characteristics, an electronic device, and a medium. In the data transmission phase, the scheme introduces a first reference clock pulse width to limit the pulse width corresponding to different logical values, so as to specially encode the device ID number, target data, and the verification information obtained by analyzing the target data, thereby achieving efficient data transmission at the physical layer. In addition, in the data reception phase, the scheme first sets the target pulse width range based on the first reference clock pulse width parsed from the first digital signal, and then parses the second digital signal based on the target pulse width range to efficiently and reliably restore the target bit string. There is no need to rely on the clock signal and communication baud rate to segment and restore the communication electrical signal. Subsequently, the target bit string is successfully verified based on the verification information parsed from the fourth digital signal before decoding the target data. The implementation process has the characteristics of strong anti-interference ability and high fault tolerance.

[0048] See also Figure 1 , Figure 1This is an optional composition diagram of a communication system based on pulse width characteristics provided in an embodiment of the present application. The system includes a first electronic device 101 and a second electronic device 102, and a two-way communication connection can be established between the first electronic device 101 and the second electronic device 102.

[0049] Specifically, the first electronic device 101 is mainly used to implement the following functions: obtaining start flag information and pulse width flag information and then generating a signal to obtain a first digital signal; wherein the pulse width flag information carries the first reference clock pulse width of the first electronic device 101; calculating according to a preset pulse width adjustment ratio and the first reference clock pulse width of the first electronic device 101 to obtain a target pulse width, which includes pulse widths corresponding to different logical values; obtaining the ID number of the first electronic device 101 and the target data to be sent, and then generating a signal in combination with the target pulse width to obtain a second digital signal; obtaining segmentation flag information and then generating a signal to obtain a third digital signal; analyzing according to the target data to obtain verification information, and then generating a signal according to the verification information and the target pulse width to obtain a fourth digital signal; obtaining stop flag information and then generating a signal to obtain a fifth digital signal; integrating the first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal to obtain a final digital signal and send it to the second electronic device 102.

[0050] In some embodiments of the present application, in order to enable low-passband devices to recognize the start flag so as to respond, for example, the ordinary I / O points of the logic controller PLC commonly used in industrial control can be used as communication ports to send and receive data. At the same time, considering that the communication network of the first electronic device 101 is in an idle state before sending data, that is, the communication network presents a continuous high-level state, the start flag information is set to indicate the generation of a low-level pulse with a first fixed pulse width; in addition, the pulse width flag information is set to indicate the generation of a high-level pulse of a first reference clock pulse width and a low-level pulse of a first reference clock pulse width in sequence, and the first fixed pulse width is required to be much larger than the first reference clock pulse width. It can be understood that the first fixed pulse width and the first reference clock pulse width are in an integer multiple relationship, and the corresponding multiple is preferably set to 5. For example: when the basic communication capability of the first electronic device 101 is a baud rate bandwidth of 1000, the first reference clock pulse width is 1ms, and the first fixed pulse width is set to 5ms at this time. On this basis, the first digital signal can be understood as being composed of a low-level pulse with a first fixed pulse width, a high-level pulse with a first reference clock pulse width, and a low-level pulse with a first reference clock pulse width in sequence.

[0051] In some embodiments of the present application, the target pulse width includes a pulse width corresponding to a logical value of 1 and a pulse width corresponding to a logical value of 0. The calculation process of the target pulse width may include, but is not limited to, expressing the pulse width adjustment ratio as X%, expressing the first reference clock pulse width of the first electronic device 101 as T0, and then setting the pulse width corresponding to the logical value 1 to T0*(1+X%), and setting the pulse width corresponding to the logical value 0 to T0*(1-X%).

[0052] In some embodiments of the present application, the ID (Identity Document) number of the first electronic device 101 has a value range of 0-255, and the process of determining the second digital signal may include, but is not limited to: encoding the ID number of the first electronic device 101 to obtain a first bit string, where the first bit string is a binary sequence consisting of one byte, and encoding the target data to obtain a corresponding target bit string, and then, based on the fact that the bit logic value is only related to the pulse width and is not related to the high and low level polarities, respectively generating signals for the first bit string and the target bit string according to the pulse widths corresponding to different logic values, and then merging them to obtain the second digital signal presented in alternating high and low levels, that is, the first level signal of the second digital signal is a high level, the second level signal is a low level, the third level signal is a high level, the fourth level signal is a low level, and so on, and only all the logic values ​​corresponding to all the level signals with the same pulse width are the same, so it can be seen that all the logic values ​​corresponding to all the level signals belonging to the same high level are not necessarily all 1, and all the logic values ​​corresponding to all the level signals belonging to the same low level are not necessarily all 0.

[0053] In some embodiments of the present application, the segmentation flag information is set to indicate the generation of a high-level pulse of a second fixed pulse width, and the second fixed pulse width is much larger than the first reference clock pulse width. This can be understood as an integer multiple of the second fixed pulse width and the first reference clock pulse width, with the corresponding multiple preferably set to 3. For example, when the first reference clock pulse width is 1 ms, the second fixed pulse width is set to 3 ms. On this basis, the third digital signal can be understood as a high-level pulse of the second fixed pulse width.

[0054] In some embodiments of the present application, regarding the step of analyzing the target data to obtain verification information, the corresponding implementation process may include but is not limited to: encoding the target data to obtain a corresponding target bit string, and then performing statistical analysis on the target bit string to obtain the number of specific logical value bits, the number of bytes and the cumulative sum of bytes to form the verification information; wherein, the specific logical value can be 0 or 1.

[0055] Specifically, the total number of all logical value 1s contained in the target bit string is counted and recorded as the number of bits of the specific logical value. Since a byte contains 8 bits, the total number of all bits contained in the target bit string is divided by 8 to obtain the number of bytes, and the target bit string is divided to obtain all bytes, and then the values ​​of all bytes are added together to obtain the cumulative sum of the bytes.

[0056] On this basis, the process of determining the fourth digital signal may include, but is not limited to: encoding the number of bits of the specific logic value to obtain a second bit string, the second bit string is a binary sequence consisting of two bytes, encoding the number of bytes to obtain a third bit string, the third bit string is a binary sequence consisting of one byte, and encoding the byte accumulation to obtain a fourth bit string, the fourth bit string is a binary sequence consisting of two bytes; then, based on the fact that the bit logic value is only related to the pulse width and is not related to the high and low level polarity, according to the pulse width corresponding to different logic values, the second bit string, the third bit string and the fourth bit string are respectively generated as signals and then merged to obtain the fourth digital signal presented in the form of alternating high and low levels.

[0057] In some embodiments of the present application, the stop flag information is set to indicate the sequential generation of a high-level pulse of a third fixed pulse width and a low-level pulse of a fourth fixed pulse width, and the third fixed pulse width is required to be greater than the first reference clock pulse width. This can be understood as an integer multiple of the third fixed pulse width and the first reference clock pulse width, with the corresponding multiple preferably set to 2, and the fourth fixed pulse width preferably being equal to the first reference clock pulse width. For example, when the first reference clock pulse width is 1ms, the third fixed pulse width is set to 2ms and the fourth fixed pulse width is set to 1ms. On this basis, the fifth digital signal can be understood as consisting of a high-level pulse of a third fixed pulse width and a low-level pulse of a fourth fixed pulse width, in sequence.

[0058] It should be noted that when the first electronic device 101 sends the final digital signal to the second electronic device 102, the second electronic device 102 receives the first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal in sequence, that is, the second electronic device 102 receives the start mark information, the first reference clock pulse width of the first electronic device 101, the ID number of the first electronic device 101, the target data, the segmentation mark information, the verification information and the stop mark information in sequence.

[0059] In traditional serial asynchronous communication based on level characteristics, when the data bits, check bits, stop bits and the communication network are in an idle state, they are all represented by high levels, that is, a continuous high-level signal is generated, and there is no obvious data segmentation reference point, which will make it difficult for the data receiving device to restore the data. However, in this application, the problem of difficult and inaccurate data restoration can be solved through specific segmentation mark information, check information and stop mark information, that is, high fault tolerance.

[0060] In order to more clearly explain the functions implemented by the first electronic device 101, the following description is made by taking the first electronic device 101 as an example of wanting to send specific target data "hi" to the second electronic device 102:

[0061] Determine that the ID number of the first electronic device 101 is 8, and encode the ID number of the first electronic device 101 to obtain a corresponding bit string of 00001000;

[0062] The ASCII code corresponding to the character "h" is 0x68, and the ASCII code corresponding to the character "i" is 0x69. The corresponding sub-bit string obtained by encoding the character "h" is 01101000, and the corresponding sub-bit string obtained by encoding the character "i" is 01101001. Then, these two sub-bit strings are directly merged to obtain the bit string corresponding to the specific target data: 01101000 01101001;

[0063] After statistical analysis of the specific target bit string, it is determined that the number of bits of the specific logic value is 7, the number of bytes is 2, and the cumulative sum of the bytes is 0x68+0x69=0xD1. The number of bits of the specific logic value is then encoded to obtain a corresponding sub-bit string of 00000000 00000111, the number of bytes is encoded to obtain a corresponding sub-bit string of 00000010, and the cumulative sum of bytes is encoded to obtain a corresponding sub-bit string of 00000000 11010001. Finally, these three bit strings are directly combined to obtain a bit string corresponding to the check information of 00000000 00000111 0000001000000000 11010001.

[0064] Determine that the pulse width of the first reference clock of the first electronic device 101 is 1 ms and the preset pulse width adjustment ratio is 15%. In this case, the pulse width corresponding to the logic value 1 is set to 1.15 ms and the pulse width corresponding to the logic value 0 is set to 0.85 ms.

[0065] Signals are generated respectively according to the start flag information, pulse width flag information, segmentation flag information and stop flag information. At the same time, based on the fact that the bit logic value is only related to the pulse width and has nothing to do with the high and low level polarities, signals are generated respectively for the bit string corresponding to the ID number of the first electronic device 101, the bit string corresponding to the specific target data and the bit string corresponding to the verification information according to the pulse width corresponding to different logic values. Then, the final digital signal is formed by sequentially merging the relevant signals. Figure 2 shown.

[0066] In the embodiment of the present application, by using pulse width instead of level to represent different bit logic values, communication between different devices can be achieved regardless of the baud rate, that is, devices with different baud rates can communicate with each other without the need for a clock signal line, nor the need to prioritize the unification of the baud rate, parity bit, and stop bit configuration between devices. Moreover, sending a message is a frame of data (the frame of data can contain multiple bytes), which has higher communication efficiency than the traditional serial asynchronous communication method characterized by level. In addition, by including the ID number of the first electronic device in the final digital signal, it is conducive to the realization of a distributed multi-point to multi-point communication mode in the fields of intelligent manufacturing and the Internet of Things.

[0067] Specifically, the second electronic device 102 is mainly used to implement the following functions: obtain the final digital signal sent by the first electronic device 101, which at least includes a first digital signal, a second digital signal and a fourth digital signal; wherein the first digital signal carries the first reference clock pulse width of the first electronic device 101, the second digital signal carries the target data that the first electronic device 101 actually wants to send, and the fourth digital signal carries verification information, which is obtained by analyzing the target data; parse the first reference clock pulse width of the first electronic device 101 from the first digital signal, and then calculate it in combination with a preset pulse width adjustment ratio range to obtain a target pulse width range, which includes pulse width ranges corresponding to different logical values; identify all pulse widths to be measured related to the target data from the second digital signal, and then parse all pulse widths to be measured according to the target pulse width range to obtain a target bit string; parse the verification information from the fourth digital signal, and then verify the target bit string based on the verification information; if the verification is successful, decode the target bit string to obtain the target data.

[0068] It should be noted that a bidirectional communication line is formed between the first electronic device 101 and the second electronic device 102. Before obtaining the final digital signal sent by the first electronic device 101, the second electronic device 102 will continuously monitor the level changes on the communication line, that is, determine whether a continuous high level is converted to a low level on the communication line.

[0069] In some embodiments of the present application, the target pulse width range includes a pulse width range corresponding to a logic value of 1 and a pulse width range corresponding to a logic value of 0. The calculation process of the target pulse width range may include, but is not limited to, the following steps: expressing the pulse width adjustment ratio range as [X min %,X max %], the first reference clock pulse width of the first electronic device 101 is expressed as T0, and the pulse width range corresponding to the logic value 1 is set to [T0*(1+X min %),T0*(1+X max %)], and set the pulse width range corresponding to the logic value 0 to [T0*(1-X max %)),T0*(1-X min %)].

[0070] For example, when the first reference clock pulse width of the first electronic device 101 is 1ms and the pulse width adjustment ratio range is [5%, 15%], the pulse width range corresponding to the logical value 1 is set to [1.05ms, 1.15ms], and the pulse width range corresponding to the logical value 0 is set to [0.85ms, 0.95ms].

[0071] In some embodiments of the present application, regarding the step of identifying all pulse widths to be measured related to the target data from the second digital signal, the corresponding implementation process may be but is not limited to including: since the first eight level signals contained in the second digital signal are only related to the ID number of the first electronic device 101, detection is performed one by one starting from the ninth level signal contained in the second digital signal to obtain all pulse widths to be measured corresponding to all remaining level signals.

[0072] In some embodiments of the present application, regarding the step of parsing all pulse widths to be measured according to the target pulse width range to obtain the target bit string, the corresponding implementation process may include but is not limited to the following:

[0073] The first case: if all the pulse widths to be measured fall within the target pulse width range, then the logic value corresponding to each pulse width to be measured is determined in turn according to the relationship between each pulse width to be measured and the pulse width range corresponding to different logic values, thereby forming the target bit string.

[0074] For example, if a pulse width to be measured falls within the pulse width range corresponding to the logical value 1, the logical value corresponding to the pulse width to be measured is determined to be 1; or if the pulse width to be measured falls within the pulse width range corresponding to the logical value 0, the logical value corresponding to the pulse width to be measured is determined to be 0.

[0075] The second case: if not all of the pulse widths to be measured fall within the target pulse width range, indicating that the communication signal has generated a change in the width of the electrical pulse signal due to electromagnetic interference, then first, multiple consecutive pulse widths to be measured that do not fall within the target pulse width range in all the pulse widths to be measured are accumulated to obtain all updated pulse widths to be measured; considering that the final digital signal also includes a third digital signal carrying segmentation flag information, and the segmentation flag information records a specific pulse width that exceeds the target pulse width range, secondly, the specific pulse width is parsed from the third digital signal, and then analyzed in combination with the target pulse width range to formulate a correction strategy, which records multiple valid pulse width ranges and all logical value combinations corresponding to each valid pulse width range; finally, according to the correction strategy and the target pulse width range, all updated pulse widths to be measured are assigned and analyzed to generate the target bit string. At the same time, prompt information is also generated, which is used to indicate whether other bit strings can be generated.

[0076] For example, when the specific pulse width is set to 3ms, the pulse width range corresponding to the logical value 1 is set to [1.05ms, 1.15ms], and the pulse width range corresponding to the logical value 0 is set to [0.85ms, 0.95ms], the maximum value 1.15ms contained in the pulse width range corresponding to the logical value 1 is recorded as the maximum pulse width, and the minimum value 0.85ms contained in the pulse width range corresponding to the logical value 0 is recorded as the minimum pulse width. At least one of the following conditions is used as the first constraint condition: the integer multiples of the maximum pulse width fall within the valid pulse width range, the integer multiples of the minimum pulse width fall within the valid pulse width range, and the sum of the integer multiples of the maximum pulse width and the integer multiples of the minimum pulse width fall within the valid pulse width range. The specific pulse width exceeds the valid pulse width range as the second constraint condition. At this time, according to the first constraint condition and the second constraint condition, multiple valid pulse widths can be formulated. The effective pulse width ranges are [1.7ms, 1.9ms), [1.9ms, 2.1ms), [2.1ms, 2.4ms), [2.4ms, 2.7ms), and [2.7ms, 2.9ms], and the logic value combination corresponding to the effective pulse width range [1.7ms, 1.9ms) is 00, the logic value combination corresponding to the effective pulse width range [1.7ms, 1.9ms) is 00, the logic value combination corresponding to the effective pulse width range [1.9ms, 2.1ms) is 01 or 10, the logic value combination corresponding to the effective pulse width range [2.1ms, 2.4ms) is 11, the logic value combination corresponding to the effective pulse width range [2.4ms, 2.7ms) is 000, and the logic value combination corresponding to the effective pulse width range [2.7ms, 2.9ms] is 001 or 010 or 100.

[0077] On this basis, taking the pulse widths to be measured as 0.9ms, 0.8ms, 0.2ms, 0.15ms, 1.11ms, 0.88ms, 1.18ms and 0.82ms as an example, the specific implementation process of parsing all the pulse widths to be measured to obtain the target bit string is described as follows:

[0078] Three consecutive pulse widths to be measured that do not fall within the target pulse width range (i.e., 0.8ms, 0.2ms, and 0.15ms) are accumulated to obtain an updated pulse width to be measured of 1.15ms, and two consecutive pulse widths to be measured that do not fall within the target pulse width range (i.e., 1.18ms and 0.82ms) are accumulated to obtain an updated pulse width to be measured of 2ms. Thus, all updated pulse widths to be measured include 0.9ms, 1.15ms, 1.11ms, 0.88ms, and 2ms in sequence;

[0079] Since the measured pulse width of 0.9ms falls within the pulse width range corresponding to the logical value 0, the logical value corresponding to the measured pulse width of 0.9ms is determined to be 0; since the measured pulse width of 1.15ms falls within the pulse width range corresponding to the logical value 1, the logical value corresponding to the measured pulse width of 1.15ms is determined to be 1; since the measured pulse width of 1.11ms falls within the pulse width range corresponding to the logical value 1, the logical value corresponding to the measured pulse width of 1.11ms is determined to be 1; since the measured pulse width of 0.88ms falls within the pulse width range corresponding to the logical value 0, the logical value corresponding to the measured pulse width of 0.88ms is determined to be 0; since the measured pulse width of 2ms falls within the valid pulse width range [1.9ms, 2.1ms), the logical value corresponding to the measured pulse width of 2ms is determined to be 01 or 10; in summary, the target bit string is generated as 011001, and prompt information is generated to indicate that other bit strings (i.e., 011010) can be generated.

[0080] In some embodiments of the present application, regarding the step of verifying the target bit string based on the verification information, the corresponding implementation method may include: performing statistical analysis on the target bit string to obtain the corresponding specific logic value bit number, number of bytes and cumulative byte sum; if at least one of the above three data is different from the original data recorded in the verification information, it is determined that the verification is unsuccessful, which means that the target bit string is incorrect and needs to be re-parsed; if the above three data are all the same as the original data recorded in the verification information, it is determined that the verification is successful, which means that the target bit string is accurate.

[0081] In some embodiments of the present application, after executing the step of verifying the target bit string according to the verification information, it also includes: if the verification is unsuccessful and the prompt information indicates that other bit strings can be generated, the target bit string is first stored in a preset historical set, and the historical set is used to store all historical bit strings that were unsuccessfully verified for the second digital signal; then, with the constraint that the latest generated target bit string is not included in the historical set, return to the step of performing assignment analysis on all updated pulse widths to be measured according to the correction strategy and the target pulse width range to generate the target bit string, thereby ensuring that the interfered signal is restored as much as possible without the need for the first electronic device 101 to retransmit the final digital signal.

[0082] In some embodiments of the present application, after executing the step of verifying the target bit string according to the verification information, it also includes: if the verification is unsuccessful and the prompt information indicates that other bit strings cannot be generated, indicating that the communication bandwidth of the second electronic device 102 is relatively narrow, then obtaining the first start flag information, the second reference clock pulse width and ID number of the second electronic device 102, and the first stop flag information and then generating a signal, obtaining a feedback digital signal and sending it to the first electronic device 101, so that the first electronic device 101 resends the target data according to the second reference clock pulse width carried by the feedback digital signal, thereby ensuring reliable adaptive communication between devices with different baud rates, that is, a device will send messages with different reference clock pulse widths according to different receiving objects.

[0083] It should be noted that the final digital signal sent by the first electronic device 101 also includes a fifth digital signal, which carries stop flag information, and the first digital signal also carries start flag information. The first start flag information can be independently set by the second electronic device 102, or it can be the start flag information parsed from the first digital signal. Similarly, the first stop flag information can be independently set by the second electronic device 102, or it can be the stop flag information parsed from the fifth digital signal.

[0084] In some embodiments of the present application, regarding the step of decoding the target bit string to obtain the target data, the corresponding implementation method may include: dividing the target bit string into multiple byte data, then converting each byte data into ASCII code to restore the corresponding character information, and then integrating the multiple character information corresponding to the multiple bytes to obtain the target data.

[0085] The communication system based on pulse width characteristics provided in the embodiment of the present application limits the pulse widths corresponding to different logical values ​​by introducing a first reference clock pulse width in a first electronic device, so as to specially encode the device ID number, target data, and verification information obtained by analyzing the target data, thereby realizing efficient data transmission at the physical layer; and in a second electronic device, firstly sets a target pulse width range according to the first reference clock pulse width parsed from the first digital signal, and then parses the second digital signal according to the target pulse width range to efficiently and reliably restore the target bit string, without relying on the clock signal and the communication baud rate to segment and restore the communication electrical signal, and then decodes the target data after the target bit string is successfully verified according to the verification information parsed from the fourth digital signal. The entire implementation process has the characteristics of strong anti-interference ability and high fault tolerance.

[0086] The embodiments of the present application provide a serial communication method based on pulse width characteristics, which relates to the field of communication technology and is applied to a first electronic device, which can be a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a vehicle-mounted terminal, etc., but is not limited thereto; the server can be configured as an independent physical server, or as a server cluster or distributed system consisting of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network.

[0087] See also Figure 3 , Figure 3 This is an optional flow chart of a serial communication method based on pulse width characteristics provided in an embodiment of the present application. The method is mainly applied to a first electronic device. The method may include, but is not limited to, the following steps S201 to S207:

[0088] Step S201: Acquire start flag information and pulse width flag information and then generate a signal to obtain a first digital signal; wherein the pulse width flag information carries a first reference clock pulse width of the first electronic device;

[0089] Step S202: Calculate according to a preset pulse width adjustment ratio and the first reference clock pulse width to obtain a target pulse width, where the target pulse width includes pulse widths corresponding to different logic values;

[0090] Step S203: obtaining the ID number of the first electronic device and the target data to be sent, and then generating a signal in combination with the target pulse width to obtain a second digital signal;

[0091] Step S204: Acquire segmentation mark information and then generate a signal to obtain a third digital signal;

[0092] Step S205: Analyze the target data to obtain verification information, and then generate a signal based on the verification information and the target pulse width to obtain a fourth digital signal;

[0093] Step S206: Acquire stop sign information and then generate a signal to obtain a fifth digital signal;

[0094] Step S207: Integrate the first digital signal, the second digital signal, the third digital signal, the fourth digital signal, and the fifth digital signal to obtain a final digital signal and send the final digital signal to the second electronic device.

[0095] In an embodiment of the present application, a first reference clock pulse width is introduced to limit the pulse width corresponding to different logical values, so as to specially encode the device ID number, target data, and verification information obtained by analyzing the target data, thereby achieving efficient data transmission at the physical layer.

[0096] In step S205 of some embodiments, regarding the step of analyzing the target data to obtain verification information, the corresponding implementation process may include, but is not limited to, steps S301 to S302:

[0097] Step S301: Encode the target data to obtain a target bit string;

[0098] Step S302: Statistically analyze the target bit string to obtain the number of bits of a specific logic value, the number of bytes, and the cumulative sum of bytes to form the verification information.

[0099] It should be noted that for detailed description of the specific implementation methods of the above steps, please refer directly to the detailed description of the functions implemented by the first electronic device in the above embodiment of the communication system based on pulse width characteristics. The beneficial effects achieved by the two are also the same and will not be repeated here.

[0100] The embodiment of the present application provides a serial communication method based on pulse width characteristics, which relates to the field of communication technology and is applied to a second electronic device, which can be a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a vehicle-mounted terminal, etc., but is not limited thereto; the server can be configured as an independent physical server, or as a server cluster or distributed system consisting of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network.

[0101] See also Figure 4 , Figure 4 This is an optional flow chart of a serial communication method based on pulse width characteristics provided in an embodiment of the present application. The method is mainly applied to a second electronic device. The method may include, but is not limited to, the following steps S401 to S405:

[0102] Step S401: Acquire a final digital signal sent by a first electronic device, the final digital signal comprising a first digital signal, a second digital signal, and a fourth digital signal; wherein the first digital signal carries a first reference clock pulse width of the first electronic device, the second digital signal carries target data, and the fourth digital signal carries verification information, the verification information being obtained by analyzing the target data;

[0103] Step S402: parse the first reference clock pulse width from the first digital signal, and calculate the target pulse width range based on the preset pulse width adjustment ratio range to obtain the target pulse width range, where the target pulse width range includes pulse width ranges corresponding to different logic values;

[0104] Step S403: identifying all pulse widths to be measured related to the target data from the second digital signal, and then parsing all pulse widths to be measured according to the target pulse width range to obtain a target bit string;

[0105] Step S404: parsing the verification information from the fourth digital signal, and then verifying the target bit string based on the verification information;

[0106] Step S405: If the verification is successful, the target bit string is decoded to obtain the target data.

[0107] In an embodiment of the present application, a target pulse width range is first set based on the first reference clock pulse width parsed from the first digital signal, and then the second digital signal is parsed based on the target pulse width range to efficiently and reliably restore the target bit string, without relying on the clock signal and the communication baud rate to perform segmentation and restoration of the communication electrical signal. Subsequently, the target bit string is successfully verified based on the check information parsed from the fourth digital signal before the target data is decoded. The entire implementation process has the characteristics of strong anti-interference ability and high fault tolerance.

[0108] In step S403 of some embodiments, regarding the step of parsing all pulse widths to be measured according to the target pulse width range to obtain the target bit string, the corresponding implementation process may include, but is not limited to, steps S501 to S503:

[0109] Step S501: If all the pulse widths to be measured do not fall within the target pulse width range, then multiple consecutive pulse widths to be measured that do not fall within the target pulse width range are accumulated among all the pulse widths to be measured to obtain updated pulse widths to be measured.

[0110] Step S502: The final digital signal further includes a third digital signal, the third digital signal carrying segmentation flag information, the segmentation flag information recording a specific pulse width that exceeds the target pulse width range, parsing the specific pulse width from the third digital signal, and then analyzing it in combination with the target pulse width range to formulate a correction strategy, the correction strategy recording multiple valid pulse width ranges and all logical value combinations corresponding to each valid pulse width range;

[0111] Step S503: performing value analysis on all updated pulse widths to be measured according to the correction strategy and the target pulse width range to generate the target bit string.

[0112] It should be noted that, while generating the target bit string, prompt information will be further generated. The prompt information is used to indicate whether other bit strings can be generated, providing a reference for subsequent verification work.

[0113] In some embodiments, after executing step S404, the following two situations may also be included:

[0114] In the first case, if the verification is unsuccessful and the prompt information indicates that other bit strings can be generated, the target bit string is stored in a preset history set, and the process returns to step S503 with the constraint that the newly generated target bit string is not included in the history set.

[0115] In the second case, if the verification is unsuccessful and the prompt information indicates that other bit strings cannot be generated, the first start flag information, the second reference clock pulse width and ID number of the second electronic device, and the first stop flag information are obtained and then the signal is generated to obtain a feedback digital signal and send it to the first electronic device, so that the first electronic device resends the target data according to the second reference clock pulse width carried by the feedback digital signal.

[0116] It should be noted that for detailed description of the specific implementation methods of the above steps, please refer to the detailed description of the functions implemented by the second electronic device in the above embodiment of the communication system based on pulse width characteristics. The beneficial effects achieved by both are the same and will not be repeated here.

[0117] An embodiment of the present application further provides an electronic device, comprising a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the aforementioned serial communication method based on pulse width characteristics applied to the first electronic device, or the aforementioned serial communication method based on pulse width characteristics applied to the second electronic device. The electronic device may include any intelligent terminal, such as a tablet computer or an in-vehicle computer.

[0118] It can be understood that the contents of the above method embodiments are all applicable to the embodiments of the present device, the functions specifically implemented by the embodiments of the present device are the same as the functions specifically implemented by the above method embodiments, and the beneficial effects achieved by the embodiments of the present device are also the same as the beneficial effects achieved by the above method embodiments.

[0119] See also Figure 5 , Figure 5 The hardware structure of an electronic device according to another embodiment is shown. The electronic device includes:

[0120] The processor 601 may be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0121] The memory 602 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called by the processor 601 to execute the technical solutions provided by the embodiments of the present application.

[0122] Input / output interface 603, used to implement information input and output;

[0123] Communication interface 604, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0124] Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 );

[0125] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0126] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above-mentioned serial communication method based on pulse width characteristics applied to the first electronic device, or the above-mentioned serial communication method based on pulse width characteristics applied to the second electronic device.

[0127] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiment, the functions specifically implemented by the present storage medium embodiment are the same as the functions specifically implemented by the above method embodiments, and the beneficial effects achieved by the present storage medium embodiment are also the same as the beneficial effects achieved by the above method embodiments.

[0128] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0129] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0130] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0131] The system embodiment described above is merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0132] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0133] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0134] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0135] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the above units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0136] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0138] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0139] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A serial communication method based on pulse width characteristics, characterized in that: Applied to a first electronic device, the method includes: Acquire start flag information and pulse width flag information and then generate a signal to obtain a first digital signal; wherein the pulse width flag information carries a first reference clock pulse width of the first electronic device; Calculating according to a preset pulse width adjustment ratio and the first reference clock pulse width to obtain a target pulse width, wherein the target pulse width includes pulse widths corresponding to different logic values; Obtaining the ID number of the first electronic device and the target data to be sent, and then generating a signal in combination with the target pulse width to obtain a second digital signal; Acquire segmentation mark information and then generate a signal to obtain a third digital signal; Analyzing the target data to obtain verification information, and then generating a signal based on the verification information and the target pulse width to obtain a fourth digital signal; Acquire stop sign information and then generate a signal to obtain a fifth digital signal; The first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal are integrated to obtain a final digital signal and sent to a second electronic device.

2. The serial communication method based on pulse width characteristics according to claim 1, wherein The analyzing the target data to obtain verification information includes: Encoding the target data to obtain a target bit string; Statistical analysis is performed on the target bit string to obtain the number of specific logic value bits, the number of bytes, and the cumulative sum of bytes to form the verification information.

3. A serial communication method based on pulse width characteristics, characterized in that: Applied to a second electronic device, the method includes: Obtaining a final digital signal sent by a first electronic device, the final digital signal comprising a first digital signal, a second digital signal, and a fourth digital signal; wherein the first digital signal carries a first reference clock pulse width of the first electronic device, the second digital signal carries target data, and the fourth digital signal carries verification information, the verification information being obtained by analyzing the target data; Analyzing the first reference clock pulse width from the first digital signal, and then calculating based on a preset pulse width adjustment ratio range to obtain a target pulse width range, wherein the target pulse width range includes pulse width ranges corresponding to different logic values; Identifying all pulse widths to be measured related to the target data from the second digital signal, and then parsing all the pulse widths to be measured according to the target pulse width range to obtain a target bit string; parsing the verification information from the fourth digital signal, and then verifying the target bit string based on the verification information; If the verification is successful, the target bit string is decoded to obtain the target data.

4. The serial communication method based on pulse width characteristics according to claim 3, wherein: The final digital signal further includes a third digital signal, the third digital signal carries segmentation flag information, and the segmentation flag information records a specific pulse width that exceeds the target pulse width range; The step of parsing all the pulse widths to be measured according to the target pulse width range to obtain a target bit string includes: If all the pulse widths to be measured do not all fall within the target pulse width range, then multiple consecutive pulse widths to be measured that do not fall within the target pulse width range among all the pulse widths to be measured are accumulated to obtain updated pulse widths to be measured; parse the specific pulse width from the third digital signal, and analyze it in combination with the target pulse width range to formulate a correction strategy, wherein the correction strategy records multiple valid pulse width ranges and all logical value combinations corresponding to each valid pulse width range; According to the correction strategy and the target pulse width range, assignment analysis is performed on all the updated pulse widths to be measured to generate the target bit string.

5. The serial communication method based on pulse width characteristics according to claim 4, characterized in that: While generating the target bit string, the method includes: Prompt information is generated, where the prompt information is used to indicate whether other bit strings can be generated.

6. The serial communication method based on pulse width characteristics according to claim 5, characterized in that: After verifying the target bit string according to the verification information, the method includes: If the verification is unsuccessful and the prompt information indicates that other bit strings can be generated, the target bit string is stored in a preset history set, and then, with the constraint that the newly generated target bit string is not included in the history set, the process returns to the step of performing assignment analysis on all updated pulse widths to be measured based on the correction strategy and the target pulse width range to generate the target bit string.

7. The serial communication method based on pulse width characteristics according to claim 5, characterized in that: After verifying the target bit string according to the verification information, the method includes: If the verification is unsuccessful and the prompt information indicates that no other bit string can be generated, the first start flag information, the second reference clock pulse width and ID number of the second electronic device, and the first stop flag information are obtained and then the signal is generated to obtain a feedback digital signal and send it to the first electronic device, so that the first electronic device resends the target data according to the second reference clock pulse width carried by the feedback digital signal.

8. A communication system based on pulse width characteristics, characterized in that: The system includes a first electronic device and a second electronic device; The first electronic device is used to: obtain start flag information and pulse width flag information and then generate a signal to obtain a first digital signal; wherein the pulse width flag information carries the first reference clock pulse width of the first electronic device; calculate according to a preset pulse width adjustment ratio and the first reference clock pulse width to obtain a target pulse width, wherein the target pulse width includes pulse widths corresponding to different logical values; obtain the ID number of the first electronic device and the target data to be sent, and then generate a signal in combination with the target pulse width to obtain a second digital signal; obtain segmentation flag information and then generate a signal to obtain a third digital signal; analyze according to the target data to obtain verification information, and then generate a signal according to the verification information and the target pulse width to obtain a fourth digital signal; obtain stop flag information and then generate a signal to obtain a fifth digital signal; integrate the first digital signal, the second digital signal, the third digital signal, the fourth digital signal and the fifth digital signal to obtain a final digital signal and send it to the second electronic device; The second electronic device is used to: obtain a final digital signal sent by the first electronic device, the final digital signal including a first digital signal, a second digital signal, and a fourth digital signal; wherein the first digital signal carries a first reference clock pulse width of the first electronic device, the second digital signal carries target data, and the fourth digital signal carries verification information, the verification information being obtained by analyzing the target data; parse the first reference clock pulse width from the first digital signal, and then calculate in combination with a preset pulse width adjustment ratio range to obtain a target pulse width range, the target pulse width range including pulse width ranges corresponding to different logical values; identify all pulse widths to be measured related to the target data from the second digital signal, and then parse all pulse widths to be measured according to the target pulse width range to obtain a target bit string; parse the verification information from the fourth digital signal, and then verify the target bit string based on the verification information; if the verification is successful, decode the target bit string to obtain the target data.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 2 or the method according to any one of claims 3 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 2 or the method according to any one of claims 3 to 7 is implemented.

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