FPGA-based ethercat master station topology dynamic control system

By using an FPGA chip to process the EtherCAT protocol and dynamically switch network topology in the EtherCAT master station, the real-time performance and topology adaptability issues of the EtherCAT master station system are solved, achieving efficient and reliable EtherCAT master station control.

CN120658618BActive Publication Date: 2026-06-26BEIJING LANPUFENG TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING LANPUFENG TECH CO LTD
Filing Date
2025-06-20
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

Existing EtherCAT master station systems have shortcomings in terms of real-time performance and network topology flexibility. The latency caused by software implementation and the fixed topology make it difficult to adapt to different network environments, affecting the system's deployment flexibility and reliability.

Method used

The system employs an FPGA chip to achieve high real-time processing of the EtherCAT protocol, and dynamically identifies and controls the network topology through redundant network ports, supporting switching between linear and ring modes. Combined with the parallel processing capabilities of the FPGA, it enables efficient and real-time EtherCAT protocol task processing.

Benefits of technology

It achieves high-precision synchronization and low-latency control of the EtherCAT master station system, improves the system's fault tolerance and deployment flexibility, and ensures stable operation in different network environments.

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Abstract

The application provides an FPGA-based EtherCAT master station topology dynamic control system, comprising: an EtherCAT master station integrated with an FPGA chip, the EtherCAT master station being configured with a main network port and a redundant network port; a plurality of EtherCAT slave stations connected in sequence, the main network port of the EtherCAT master station being connected to a first end slave station of the plurality of EtherCAT slave stations; the FPGA chip being used to confirm that a network topology formed by the EtherCAT master station and the EtherCAT slave stations is in a linear mode or a ring mode according to a connection state of the redundant network port; wherein in the linear mode, the redundant network port is in a disabled state, and in the ring mode, the redundant network port is connected to a last end slave station of the plurality of EtherCAT slave stations; and the FPGA chip is further used to control the connection state of the redundant network port to switch the network topology between the linear mode and the ring mode.
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