Impedance-optimized PCB structure with different medium thicknesses and line widths and impedance optimization method

Abstract

The invention relates to an impedance-optimized PCB structure with different medium thicknesses and line widths and an impedance optimization method, the impedance-optimized PCB structure comprises a surface layer substrate, a transmission line is arranged in the surface layer substrate, the transmission line comprises a narrow transmission line segment, an asymptotic line segment, a wide transmission line segment and a wider transmission line segment which are connected in sequence, and the narrow transmission line segment, the asymptotic line segment, the wide transmission line segment and the wider transmission line segment are arranged on the surface layer substrate. Along the interval direction of the narrow transmission line segment and the wide transmission line segment, the width of the asymptotic line segment is gradually increased, and the width of the wider transmission line segment is smaller than that of the wide transmission line segment. The transmission line adopts the connection of a narrow transmission line section, an asymptotic line section, a wide transmission line section and a relatively wide transmission line section, the width of the asymptotic line section is gradually increased along the transmission direction, the problem of discontinuous impedance caused by sudden change of line width in a traditional scheme is avoided, the smooth width change of the asymptotic line section enables impedance transition to be smoother, and signal reflection is reduced; the width of the wider transmission line section is slightly smaller than that of the wide transmission line section, so that the size requirement of a connector insulator is further met, and impedance matching is maintained at the same time.

Description

Technical Field

[0001] The present application relates to the field of PCB board design, and specifically to an impedance-optimized PCB structure and an impedance optimization method for different dielectric thicknesses and line widths. Background Art

[0002] With the widespread application of high-frequency packaging substrates and the increasing demand for signal bandwidth and rate in various fields, the requirements for signal transmission quality are becoming increasingly stringent. When the characteristic impedance of the input and output ports of a high-frequency circuit does not match the characteristic impedance of the signal source or load, problems such as reflection, loss, and noise can occur, resulting in degraded signal quality. Therefore, optimizing impedance matching in high-frequency circuits is crucial to improving signal transmission quality and system performance.

[0003] In related technologies, in order to cooperate with the connector insulator connection and increase the contact area between the insulator and the transmission line, it is necessary to widen the transmission line width at the connection with the insulator, resulting in a sudden change in the line width at the connection between the original transmission line and the widened transmission line, making it impossible to achieve impedance matching, thereby generating signal crosstalk and reflection, affecting the integrity of signal transmission. Summary of the Invention

[0004] The present application provides an impedance-optimized PCB structure and impedance optimization method for different dielectric thicknesses and line widths, which can solve the technical problem that, in order to match the traditional connector insulator connection, the transmission line width at the connection with the insulator is widened, resulting in a sudden change in the line width at the connection between the original transmission line and the widened transmission line, making it impossible to achieve impedance matching, thereby generating signal crosstalk and reflection, and affecting the integrity of signal transmission.

[0005] In a first aspect, embodiments of the present application provide an impedance-optimized PCB structure for different dielectric thicknesses and line widths, comprising: A surface substrate is provided with a transmission line, wherein the transmission line includes a narrow transmission line segment, an asymptotic line segment, a wide transmission line segment and a relatively wide transmission line segment connected in sequence, and along the spacing direction between the narrow transmission line segment and the wide transmission line segment, the width of the asymptotic line segment gradually widens, and the width of the relatively wide transmission line segment is smaller than the width of the wide transmission line segment.

[0006] In conjunction with the first aspect, in one embodiment, the impedance-optimized PCB structure with different dielectric thicknesses and line widths further includes: A first inner dielectric layer, an inner substrate, a second inner dielectric layer and a bottom substrate, wherein the surface substrate, the first inner dielectric layer, the inner substrate, the second inner dielectric layer and the bottom substrate are stacked from top to bottom; The narrow transmission line segment is located in an overlapping area between the surface substrate and the inner substrate, so that the narrow transmission line segment uses the inner substrate as a reference plane; the wide transmission line segment and the wider transmission line segment are located in a non-overlapping area between the surface substrate and the inner substrate, so that the wide transmission line segment and the wider transmission line segment use the bottom substrate as a reference plane.

[0007] In combination with the first aspect, in one embodiment, a notch groove is formed on the side wall of the inner substrate, and when projected in a direction perpendicular to the end surface of the surface substrate, the notch groove is located directly below the asymptote segment.

[0008] In combination with the first aspect, in one embodiment, the notched groove includes a trapezoidal groove and an arcuate groove.

[0009] In combination with the first aspect, in one embodiment, the notched groove is a trapezoidal groove, the short side length of the trapezoidal groove is 100 um, the long side length is 300 um, and the height is 220 um.

[0010] In combination with the first aspect, in one embodiment, the thickness of the surface substrate and the bottom substrate is 35 μm, the thickness of the inner substrate is 17.5 μm, and the thickness of the first inner dielectric layer and the second inner dielectric layer is 100 μm; The line width of the narrow transmission line segment is 160um or 105um.

[0011] In combination with the first aspect, in one embodiment, the narrow transmission line segment, the asymptotic line segment, the wide transmission line segment and the wider transmission line segment are integrally formed.

[0012] In a second aspect, an embodiment of the present application provides an impedance optimization method based on different dielectric thicknesses and line widths, which includes the following steps: The transmission line in the surface substrate is width-processed to obtain a narrow transmission line segment, an asymptotic line segment, a wide transmission line segment, and a relatively wide transmission line segment connected in sequence; wherein, along the spacing direction between the narrow transmission line segment and the wide transmission line segment, the width of the asymptotic line segment gradually widens, and the width of the relatively wide transmission line segment is smaller than the width of the wide transmission line segment In conjunction with the second aspect, in one embodiment, after the transmission line in the surface substrate is width-processed to obtain a narrow transmission line segment, an asymptotic segment, a wide transmission line segment, and a relatively wide transmission line segment connected in sequence, the following steps are further included: A first inner dielectric layer, an inner substrate, a second inner dielectric layer and a bottom substrate are sequentially arranged below the surface substrate; The narrow transmission line segment is arranged in an overlapping area of ​​the surface substrate and the inner substrate, so that the narrow transmission line segment is set as a reference plane with the inner substrate; The wide transmission line segment and the relatively wide transmission line segment are arranged in the non-overlapping area of ​​the surface substrate and the inner substrate, so that the wide transmission line segment and the relatively wide transmission line segment use the bottom substrate as a reference plane.

[0013] In conjunction with the second aspect, in one embodiment, after arranging the wide transmission line segment and the relatively wide transmission line segment in the non-overlapping area of ​​the surface substrate and the inner substrate so that the wide transmission line segment and the relatively wide transmission line segment use the bottom substrate as a reference plane, the following steps are further included: A notch groove is provided on the side wall of the inner substrate; wherein, when projected in a direction perpendicular to the end surface of the surface substrate, the notch groove is located directly below the asymptotic segment.

[0014] The beneficial effects of the technical solutions provided in the embodiments of the present application include: The transmission line is connected by narrow transmission line segments, asymptotic line segments, wide transmission line segments and wider transmission line segments. The width of the asymptotic line segment gradually widens along the transmission direction, avoiding the impedance discontinuity problem caused by sudden line width changes in traditional solutions. The smooth width change of the asymptotic line segment makes the impedance transition smoother and reduces signal reflection; the width of the wider transmission line segment is slightly smaller than that of the wide transmission line segment, further adapting to the size requirements of the connector insulator while maintaining impedance matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 It is a three-dimensional structural diagram of the PCB structure; Figure 2 It is a side view structural diagram of the PCB structure; Figure 3 It is a schematic diagram of a partial top view of the PCB structure.

[0017] In the figure: 1, surface substrate; 2, first inner dielectric layer; 3, inner substrate; 31, notch groove; 4, second inner dielectric layer; 5, bottom substrate; 6, transmission line; 61, narrow transmission line segment; 62, asymptotic line segment; 63, wide transmission line segment; 64, relatively wide transmission line segment. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] It's important to understand that with the widespread adoption of high-frequency packaging substrates and the increasing demand for signal bandwidth and rate across various fields, the requirements for signal transmission quality are becoming increasingly stringent. When the characteristic impedance of a high-frequency circuit's input and output ports doesn't match that of the signal source or load, problems like reflection, loss, and noise can occur, degrading signal quality. Therefore, optimizing impedance matching in high-frequency circuits is crucial for improving signal transmission quality and system performance.

[0020] Among them, in order to cooperate with the connector insulator connection and increase the contact area between the insulator and the transmission line, it is necessary to widen the transmission line width at the connection with the insulator, resulting in a sudden change in the line width at the connection between the original transmission line and the widened transmission line, making it impossible to achieve impedance matching, thereby generating signal crosstalk and reflection, affecting the integrity of signal transmission.

[0021] The embodiments of the present application provide a PCB structure and impedance optimization method for impedance optimization for different dielectric thicknesses and line widths. This can solve the technical problem that, in order to match the traditional connector insulator connection, the transmission line width at the connection with the insulator is widened, resulting in a sudden change in the line width at the connection between the original transmission line and the widened transmission line, making it impossible to achieve impedance matching, thereby generating signal crosstalk and reflection, and affecting the integrity of signal transmission.

[0022] First, as Figure 1 、 Figure 2 and Figure 3 As shown, an embodiment of the present application provides an impedance-optimized PCB structure for different dielectric thicknesses and line widths, which may include: a surface substrate 1, in which a transmission line 6 is arranged, and the transmission line 6 includes a narrow transmission line segment 61, an asymptotic line segment 62, a wide transmission line segment 63 and a wider transmission line segment 64 connected in sequence. Along the spacing direction between the narrow transmission line segment 61 and the wide transmission line segment 63, the width of the asymptotic line segment 62 gradually widens, and the width of the wider transmission line segment 64 is smaller than the width of the wide transmission line segment 63.

[0023] In this embodiment, the transmission line 6 is connected in the following manner: a narrow transmission line segment 61 → an asymptotic line segment 62 → a wide transmission line segment 63 → a wider transmission line segment 64. The width of the asymptotic line segment 62 gradually widens along the transmission direction, thereby avoiding the impedance discontinuity problem caused by a sudden change in line width in traditional solutions. The smooth width change of the asymptotic line segment 62 makes the impedance transition smoother and reduces signal reflections. The width of the wider transmission line segment 64 is slightly smaller than that of the wide transmission line segment 63, further adapting to the size requirements of the connector insulator while maintaining impedance matching.

[0024] In combination with the first aspect, in one embodiment, Figure 1 、 Figure 2 and Figure 3 As shown, the impedance-optimized PCB structure for different dielectric thicknesses and line widths further includes: a first inner dielectric layer 2, an inner substrate 3, a second inner dielectric layer 4, and a bottom substrate 5; the surface substrate 1, the first inner dielectric layer 2, the inner substrate 3, the second inner dielectric layer 4, and the bottom substrate 5 are stacked from top to bottom; a narrow transmission line segment 61 is located in the overlapping area of ​​the surface substrate 1 and the inner substrate 3, so that the narrow transmission line segment 61 uses the inner substrate 3 as a reference plane; and a wide transmission line segment 63 and a relatively wide transmission line segment 64 are located in the non-overlapping area of ​​the surface substrate 1 and the inner substrate 3, so that the wide transmission line segment 63 and the relatively wide transmission line segment 64 use the bottom substrate 5 as a reference plane.

[0025] In this embodiment, the laminated structure of the surface substrate 1, the first inner dielectric layer 2, the inner substrate 3, the second inner dielectric layer 4, and the bottom substrate 5 adjusts the impedance distribution by varying the thickness of the dielectric layers to reduce signal reflections. The narrow transmission line segment 61 uses the inner substrate 3 as a reference plane, utilizing a relatively close reference distance to reduce the risk of impedance mutations. The wide transmission line segment 63 and the relatively wide transmission line segment 64 switch to the bottom substrate 5 as a reference plane to accommodate impedance matching requirements after the line width increases. The physical isolation of the overlapping and non-overlapping areas ensures that segments of different line widths achieve optimal impedance continuity at corresponding dielectric thicknesses.

[0026] In combination with the first aspect, in one embodiment, Figure 1 and Figure 3 As shown, a notch 31 is provided on the side wall of the inner substrate 3. Projected in a direction perpendicular to the end face of the surface substrate 1, the notch 31 is located directly below the asymptote 62 to reduce the impact of impedance mutation caused by the sudden change in dielectric thickness.

[0027] In this embodiment, the notch 31 is formed on the side wall of the inner substrate 3, and its vertical projection is aligned directly below the asymptote 62. By partially removing material from the inner substrate 3, the dielectric thickness in this area is adjusted to compensate for the impedance fluctuation caused by the gradual width change of the asymptote 62. The presence of the notch 31 forms a hybrid reference plane below the asymptote 62 (partially based on the inner substrate 3 and partially based on the bottom substrate 5), thereby smoothly transitioning the impedance difference between the narrow transmission line segment 61 and the wide transmission line segment 63.

[0028] In combination with the first aspect, in one embodiment, Figure 1 and Figure 3 As shown, the notch groove 31 includes a trapezoidal groove or an arc-shaped groove.

[0029] In this embodiment, the shape of the notch 31 is not particularly limited, as long as the impedance difference between the narrow transmission line segment 61 and the wide transmission line segment 63 is ensured to be smoothly transitioned.

[0030] In combination with the first aspect, in one embodiment, the narrow transmission line segment 61 , the asymptotic line segment 62 , the wide transmission line segment 63 and the relatively wide transmission line segment 64 are integrally formed.

[0031] In this embodiment, each line segment is integrated in the surface substrate 1 , and crosstalk and reflection are suppressed through gradual adjustment of the geometric shape.

[0032] In conjunction with the first aspect, in one embodiment, the first inner dielectric layer 2 and the second inner dielectric layer 4 are made of Panasonic MEGTRON7-R5785 dielectric material. The thickness of the surface substrate 1 and the bottom substrate 5 are both 35 μm, and the thickness of the inner substrate 3 is 17.5 μm. The surface substrate 1, the inner substrate 3, and the bottom substrate 5 are all made of copper. The thickness of the first inner dielectric layer 2 is 100 μm, and the thickness of the second inner dielectric layer is 100 μm. To ensure impedance matching of the surface transmission line 6, the line width and line spacing of the surface narrow transmission line segment 61 are set to 160 μm or 105 μm according to the impedance calculation formula. The impedance calculation formula is:

[0033] Wherein, W represents the line width of the narrow transmission line segment 61, h represents the thickness of the first inner dielectric layer 2, and εr is the relative dielectric constant of the dielectric substrate.

[0034] In combination with the first aspect, in one embodiment, a trapezoidal groove is opened in the inner substrate below the asymptotic segment to reduce the impact of impedance mutation caused by the sudden change in dielectric thickness. The short side of the trapezoidal groove is 100 μm, the long side is 300 μm, and the height is 220 μm. The relationship between the groove size and impedance of the corresponding trapezoidal groove is:

[0035] Wherein, k is the ratio of the short side to the long side of the trapezoidal slot, W represents the average value of the line width of the narrow transmission line segment 61 and the line width of the wide transmission line segment 63, h represents the thickness of the first inner dielectric layer 2, and εr is the relative dielectric constant of the dielectric substrate.

[0036] In summary, the present application addresses the impedance mutation problem caused by changes in the dielectric thickness and line width of high-frequency transmission lines. An asymptote segment 62 is used to transition between the narrow transmission line segment 61 and the wide transmission line segment 63, and a groove is formed on the inner substrate 3 below the asymptote segment 62. The structure is simple, and the influence of changes in line width and dielectric thickness on impedance matching is effectively reduced, thereby achieving impedance optimization.

[0037] In a second aspect, an embodiment of the present application provides an impedance optimization method based on different dielectric thicknesses and line widths, which includes the following steps: S1: The transmission line 6 in the surface substrate 1 is subjected to width processing to obtain a narrow transmission line segment 61, an asymptotic line segment 62, a wide transmission line segment 63, and a relatively wide transmission line segment 64 connected in sequence; wherein, along the spacing direction between the narrow transmission line segment 61 and the wide transmission line segment 63, the width of the asymptotic line segment 62 gradually widens, and the width of the relatively wide transmission line segment 64 is smaller than the width of the wide transmission line segment 63.

[0038] In this embodiment, the narrow transmission line segment 61 serves as the signal input end, adopts a small line width to match the high impedance requirement and reduce initial reflection; the width of the asymptotic line segment 62 gradually changes to achieve a smooth impedance transition; the wide transmission line segment 63 reduces the impedance by increasing the line width to meet the power transmission requirement; the relatively wide transmission line segment 64 is locally narrowed to compensate for the impedance mutation at the end and suppress signal ringing.

[0039] In conjunction with the second aspect, in one embodiment, after S1, the following steps are included: S2: a first inner dielectric layer 2, an inner substrate 3, a second inner dielectric layer 4 and a bottom substrate 5 are sequentially arranged below the surface substrate 1; S3: arranging the narrow transmission line segment 61 in the overlapping area of ​​the surface substrate 1 and the inner substrate 3, so that the narrow transmission line segment 61 and the inner substrate 3 are set as a reference plane; S4: The wide transmission line segment 63 and the relatively wide transmission line segment 64 are arranged in the non-overlapping area of ​​the surface substrate 1 and the inner substrate 3 , so that the wide transmission line segment 63 and the relatively wide transmission line segment 64 are set with the bottom substrate 5 as a reference plane.

[0040] In this embodiment, the impedance distribution is adjusted by using different dielectric layer thicknesses to reduce signal reflection. The narrow transmission line segment 61 uses the inner substrate 3 as the reference plane, and utilizes a closer reference distance to reduce the risk of impedance mutation. The wide transmission line segment 63 and the wider transmission line segment 64 switch to the bottom substrate 5 as the reference plane to adapt to the impedance matching requirements after the line width is increased. By physically isolating the overlapping area and the non-overlapping area, it is ensured that different line width segments achieve optimal impedance continuity under the corresponding dielectric thickness.

[0041] In conjunction with the second aspect, in one embodiment, after S4, the following steps are included: S5: a notch 31 is opened on the side wall of the inner substrate 3 ; wherein, when projected in a direction perpendicular to the end surface of the surface substrate 1 , the notch 31 is located directly below the asymptote 62 .

[0042] In this embodiment, the notch 31 is formed on the side wall of the inner substrate 3, and its vertical projection is aligned directly below the asymptote 62. By partially removing material from the inner substrate 3, the dielectric thickness in this area is adjusted to compensate for the impedance fluctuation caused by the gradual width change of the asymptote 62. The presence of the notch 31 forms a hybrid reference plane below the asymptote 62 (partially based on the inner substrate 3 and partially based on the bottom substrate 5), thereby smoothly transitioning the impedance difference between the narrow transmission line segment 61 and the wide transmission line segment 63.

[0043] In summary, the embodiment of the present application addresses the impedance mutation problem caused by changes in the dielectric thickness and line width of high-frequency transmission lines. An asymptote segment 62 is used to transition between the narrow transmission line segment 61 and the wide transmission line segment 63, and a groove is formed on the inner substrate 3 below the asymptote segment 62. The structure is simple, and the influence of changes in line width and dielectric thickness on impedance matching is effectively reduced, thereby achieving impedance optimization.

[0044] In the description of this application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0045] It should be noted that, in this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0046] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. An impedance optimized PCB structure with different dielectric thicknesses and line widths, characterized in that: It includes: A surface substrate (1) is provided with a transmission line (6) in the surface substrate (1), wherein the transmission line (6) comprises a narrow transmission line segment (61), an asymptotic line segment (62), a wide transmission line segment (63) and a relatively wide transmission line segment (64) connected in sequence, wherein along the spacing direction between the narrow transmission line segment (61) and the wide transmission line segment (63), the width of the asymptotic line segment (62) gradually widens, and the width of the relatively wide transmission line segment (64) is smaller than the width of the wide transmission line segment (63).

2. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 1, wherein: The impedance-optimized PCB structure with different dielectric thicknesses and line widths further includes: A first inner dielectric layer (2), an inner substrate (3), a second inner dielectric layer (4) and a bottom substrate (5), wherein the surface substrate (1), the first inner dielectric layer (2), the inner substrate (3), the second inner dielectric layer (4) and the bottom substrate (5) are stacked from top to bottom; The narrow transmission line segment (61) is located in an overlapping area between the surface substrate (1) and the inner substrate (3), so that the narrow transmission line segment (61) uses the inner substrate (3) as a reference plane, and the wide transmission line segment (63) and the wider transmission line segment (64) are located in a non-overlapping area between the surface substrate (1) and the inner substrate (3), so that the wide transmission line segment (63) and the wider transmission line segment (64) use the bottom substrate (5) as a reference plane.

3. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 2, wherein: A notch groove (31) is provided on the side wall of the inner substrate (3), and when projected in a direction perpendicular to the end face of the surface substrate (1), the notch groove (31) is located directly below the asymptote segment (62).

4. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 3, wherein: The notched groove (31) includes a trapezoidal groove and an arcuate groove.

5. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 3, wherein: The notched groove (31) is a trapezoidal groove, the short side length of the trapezoidal groove is 100 μm, the long side length is 300 μm, and the height is 220 μm.

6. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 2, wherein: The thickness of the surface substrate (1) and the bottom substrate (5) is 35 μm, the thickness of the inner substrate (3) is 17.5 μm, and the thickness of the first inner dielectric layer (2) and the second inner dielectric layer (4) is 100 μm; The line width of the narrow transmission line segment (61) is 160um or 105um.

7. The impedance optimized PCB structure with different dielectric thicknesses and line widths according to claim 1, wherein: The narrow transmission line segment (61), the asymptotic line segment (62), the wide transmission line segment (63) and the relatively wide transmission line segment (64) are integrally formed.

8. An impedance optimization method based on different dielectric thicknesses and line widths, characterized in that: It includes the following steps: The transmission line (6) in the surface substrate (1) is subjected to width processing to obtain a narrow transmission line segment (61), an asymptotic line segment (62), a wide transmission line segment (63) and a wider transmission line segment (64) connected in sequence; wherein, along the spacing direction between the narrow transmission line segment (61) and the wide transmission line segment (63), the width of the asymptotic line segment (62) gradually becomes wider, and the width of the wider transmission line segment (64) is smaller than the width of the wide transmission line segment (63).

9. The impedance optimization method based on different dielectric thicknesses and line widths according to claim 8, wherein: It includes the following steps: After the transmission line (6) in the surface substrate (1) is subjected to width processing to obtain a narrow transmission line segment (61), an asymptotic line segment (62), a wide transmission line segment (63) and a relatively wide transmission line segment (64) connected in sequence, the method further includes the following steps: A first inner dielectric layer (2), an inner substrate (3), a second inner dielectric layer (4) and a bottom substrate (5) are sequentially arranged below the surface substrate (1); The narrow transmission line segment (61) is arranged in an overlapping area between the surface substrate (1) and the inner substrate (3), so that the narrow transmission line segment (61) is set with the inner substrate (3) as a reference plane; The wide transmission line segment (63) and the relatively wide transmission line segment (64) are arranged in a non-overlapping area of ​​the surface substrate (1) and the inner substrate (3), so that the wide transmission line segment (63) and the relatively wide transmission line segment (64) are set with the bottom substrate (5) as a reference plane.

10. The impedance optimization method based on different dielectric thicknesses and line widths according to claim 9, wherein: It includes the following steps: After the wide transmission line segment (63) and the relatively wide transmission line segment (64) are arranged in the non-overlapping area of ​​the surface substrate (1) and the inner substrate (3), and the wide transmission line segment (63) and the relatively wide transmission line segment (64) are set as a reference plane with the bottom substrate (5), the following steps are also included: A notch groove (31) is provided on the side wall of the inner substrate (3); wherein, when projected in a direction perpendicular to the end face of the surface substrate (1), the notch groove (31) is located directly below the asymptote segment (62).

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