Three-dimensional memory and manufacturing method thereof

Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof, and the three-dimensional memory. The three-dimensional memory comprises a substrate; the stacking structure comprises a first storage area, a step area and a second storage area; the step region comprises a sub-step region; a partition wall structure; the first top selection step structure comprises a first main step structure and a first auxiliary step structure which are distributed in the first transverse direction, and the first main step structure and the first auxiliary step structure are provided with first gate layers with the corresponding layer number and height in the longitudinal direction; and the first connecting structures are connected with the first gate layers with the corresponding layer number and height in the first main step structures and the first auxiliary step structures. The first gate layers in the first main step structure and the first auxiliary step structure are connected through the first connecting structure, the length of the connecting line of the first connecting structure can be effectively reduced, the resistance value of the connecting line is reduced, meanwhile, the subsequent process difficulty is simplified, and the reliability of the device is improved.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of November 16, 2021, application number 202111352637.3, and application name "Three-dimensional memory and its manufacturing method".

Technical field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional memory and a manufacturing method thereof. [Background Technology]

[0003] 3D NAND Flash is widely used in computers, solid-state drives, and electronic devices due to its high storage density and fast programming speed. 3D NAND Flash can achieve higher data storage density by using vertical device technology. 3D NAND Flash consists of alternating layers of data storage cells, transforming a planar structure into a three-dimensional structure to increase the storage density and integration of 3D NAND Flash. 3D NAND Flash can accommodate higher storage capacity in a smaller space, resulting in significant cost savings, reduced energy consumption, and significant performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.

[0004] As the number of stacked layers of three-dimensional memory increases, the process of forming three-dimensional memory becomes increasingly difficult, resulting in a decrease in the yield and reliability of the three-dimensional memory. Therefore, it is necessary to continuously optimize the process of forming three-dimensional memory to continuously improve the yield and reliability of the device. [Summary of the invention]

[0005] The present invention provides a three-dimensional memory and a manufacturing method thereof, so as to improve the yield and reliability of the device.

[0006] In order to solve the above problems, the present invention provides a three-dimensional memory, including: a substrate; a stacking structure, the stacking structure is located in the longitudinal direction of the substrate, the stacking structure includes a first storage area, a step area and a second storage area distributed in sequence along the first transverse direction; the step area includes: a sub-step area; a partition wall structure, the partition wall structure is close to the sub-step area and distributed along the first transverse direction, extending toward the first storage area and the second storage area; a first top selection step structure, the first top selection step structure is close to the first storage area, the first top selection step structure includes a first main step structure and a first sub-step structure distributed along the first transverse direction, the first main step structure and the first sub-step structure have first gate layers with corresponding numbers of layers and heights in the longitudinal direction; a first connection structure, the first connection structure connects the first gate layers with corresponding numbers of layers and heights in the first main step structure and the first sub-step structure.

[0007] The stepped area also includes:

[0008] a second top selection staircase structure, the second top selection staircase structure being close to the second storage area, the first top selection staircase structure comprising a second main step structure and a second sub-step structure distributed along the first transverse direction, the second main step structure and the second sub-step structure having second gate layers of corresponding number and height in the longitudinal direction;

[0009] The second connecting structure connects the second gate layers of corresponding number and height in the second main step structure and the second sub-step structure.

[0010] The number of the first connection structure and the number of the second connection structure each include at least one group.

[0011] The first gate layer and the second gate layer have corresponding numbers of layers and heights, and the first connection structure and the second connection structure are electrically connected via the first sub-step structure, the second sub-step structure and the partition wall structure.

[0012] The first connection structure and the second connection structure each include a conductive connection layer, wherein the conductive connection layer includes a plurality of conductive pillars and at least one metal line.

[0013] Wherein, the conductive connecting layer comprises:

[0014] a first metal wire, at least one first main conductive pillar and a first secondary conductive pillar, wherein the first main conductive pillar is located on the first gate layer of the first main step structure, the first secondary conductive pillar is located on the first gate layer having a corresponding number of layers and height in the first secondary step structure, and the first metal wire connects the first main conductive pillar and the first secondary conductive pillar.

[0015] Wherein, the conductive connecting layer comprises:

[0016] A second main conductive column, a second secondary conductive column and a second metal wire, the second main conductive column is located on the second gate layer of the second main step structure, the second secondary conductive column is located on the second gate layer with a corresponding number of layers and height in the second secondary step structure, and the second metal wire connects the second main conductive column and the second secondary conductive column.

[0017] In order to solve the above problems, an embodiment of the present application also provides a method for manufacturing a three-dimensional memory, including: providing a substrate; forming a stacking structure in the longitudinal direction of the substrate, the stacking structure including a first storage area, a step area and a second storage area distributed in sequence along the first horizontal direction, the step area including a sub-step area; forming a first top selection step structure in the step area, the first top selection step structure is close to the first storage area, the first top selection step structure includes a first main step structure and a first sub-step structure distributed along the first horizontal direction, the first main step structure and the first sub-step structure have a first gate layer with a corresponding number of layers and height in the longitudinal direction; forming a partition wall structure in the step area, the partition wall structure is close to the sub-step area and distributed along the first horizontal direction, extending toward the first storage area and the second storage area; forming a first connection structure above the first top selection step structure, the first connection structure connecting the first gate layers with corresponding numbers of layers and heights in the first main step structure and the first sub-step structure.

[0018] The first main step structure and the first secondary step structure are formed simultaneously.

[0019] After forming the stacked structure on the substrate, the method further includes:

[0020] A second top selection staircase structure is formed in the staircase region, the second top selection staircase structure being close to the second storage region, the second top selection staircase structure comprising a second main step structure and a second sub-step structure distributed along the first transverse direction, the second main step structure and the second sub-step structure having second gate layers of corresponding number and height in the longitudinal direction;

[0021] A second connecting structure is formed above the second top selection step structure, and the second connecting structure connects the second gate layers of corresponding number and height in the second main step structure and the second sub-step structure. The number and height of the first gate layer correspond to the second gate layer, and the first connecting structure and the second connecting structure are electrically connected through the first sub-step structure, the second sub-step structure and the partition wall structure.

[0022] The second main step structure and the second secondary step structure are formed simultaneously.

[0023] The first sub-step structure and the second sub-step structure are formed simultaneously.

[0024] The beneficial effects of the present invention are: different from the prior art, the present invention provides a three-dimensional memory and a manufacturing method thereof, the three-dimensional memory including: a substrate; a stacking structure, the stacking structure is located in the longitudinal direction of the substrate, the stacking structure includes a first storage area, a step area and a second storage area distributed in sequence along the first transverse direction; the step area includes: a sub-step area; a partition wall structure, the partition wall structure is close to the sub-step area and distributed along the first transverse direction, extending toward the first storage area and the second storage area; a first top selection step structure, the first top selection step structure is close to the first storage area, the first top selection step structure includes a first main step structure and a first sub-step structure distributed along the first transverse direction, the first main step structure and the first sub-step structure have first gate layers with corresponding numbers and heights in the longitudinal direction; a first connection structure, the first connection structure connects the first gate layers with corresponding numbers and heights in the first main step structure and the first sub-step structure. The first main step structure and the first gate layer in the first sub-step structure are connected through the first connecting structure. At the same time, a second connecting structure and a second top selection step structure are formed. The second main step structure and the second gate layer in the second sub-step structure are connected through the second connecting structure, so that the first connecting structure and the second connecting structure are electrically connected through the first sub-step structure, the second sub-step structure and the partition structure. The connection length of the first connecting structure and the second connecting structure can be reduced, thereby reducing the resistance value of the connection, improving the reliability of the device, and at the same time, simplifying the difficulty of subsequent processes.

Brief Description of the Drawings

[0025] Figure 1 A schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention;

[0026] Figure 2 for Figure 1 A schematic diagram of the top view structure of the three-dimensional memory;

[0027] Figure 3 A schematic diagram of the structure of a three-dimensional memory according to some embodiments of the present invention;

[0028] Figure 4 A schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of a stacked structure formed in one embodiment of the present invention;

[0030] Figure 6 A schematic diagram of a structure for forming a first top selection ladder structure and a second top selection ladder structure in one embodiment of the present invention;

[0031] Figure 7 Schematic diagram of a partition wall structure formed in one embodiment of the present invention. [Specific implementation method]

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It is particularly noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention and are not intended to be exhaustive. All other embodiments obtained by those of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present invention.

[0033] In addition, directional terms used herein, such as [upper], [lower], [front], [back], [left], [right], [inner], [outer], and [side], refer only to directions in the accompanying drawings. Therefore, the directional terms used are intended to illustrate and facilitate understanding of the present invention and are not intended to limit the present invention. In the various figures, similar structural elements are denoted by the same reference numerals. For clarity, parts in the figures are not drawn to scale. Furthermore, some well-known parts may not be shown in the figures.

[0034] like Figure 1 , which is a schematic structural diagram of a three-dimensional memory provided in an embodiment of the present application. Among them, the three-dimensional memory includes: a substrate (not shown in the figure); a stacking structure 110, the stacking structure 110 is located in the longitudinal direction (Z direction) of the substrate, and the stacking structure 110 includes a first storage area, a step area and a second storage area distributed in sequence along the first transverse direction (X direction); the step area includes: a sub-step area; a partition wall structure 130, the partition wall structure 130 is close to the sub-step area and distributed along the first transverse direction, extending toward the first storage area and the second storage area; a first top selection step structure 120, the first top selection step structure 120 is close to the first storage area, the first top selection step structure 120 includes a first main step structure 121 and a first sub-step structure 122 distributed along the first transverse direction, the first main step structure 121 and the first sub-step structure 122 have a first gate layer 111 with a corresponding number of layers and height in the longitudinal direction; a first connection structure 140, the first connection structure 140 connects the first gate layers 111 with corresponding numbers of layers and heights in the first main step structure 121 and the first sub-step structure 122.

[0035] It should be noted that if Figure 1 As shown, the first transverse direction refers to a direction parallel to the X direction, the longitudinal direction refers to a direction parallel to the Z direction, and the second transverse direction refers to a direction parallel to the Y direction. The following is similar to this and will not be repeated hereafter.

[0036] Specifically, the three-dimensional memory includes Figure 1The first storage area (A1 region), the stepped area (A3 region), and the second storage area (A2 region) are shown as being sequentially distributed along the first lateral direction (X direction). The first storage area and the second storage area can be used to form a storage structure to store charge or data, while the stepped area can be used to form a control structure. For example, the stepped area is formed with a first top selection stepped structure 120. The first top selection stepped structure 120 includes a first main stepped structure 121 and a first sub-stepped structure 122 distributed along the first lateral direction (X direction). Both the first main stepped structure 121 and the first sub-stepped structure 122 include a first gate layer 111 and an insulating layer (not shown) alternately stacked in the form of steps in the longitudinal direction (Z direction). The first main stepped structure 121 can be one or more layers of an upper select gate (TSG, also known as an upper select transistor or upper select gate). The first main stepped structure 121 is used to control the storage structure by applying a voltage to the gate.

[0037] The embodiment of the present application introduces a first sub-step structure 122, and the first main step structure 121 and the first sub-step structure 122 have corresponding numbers of layers and heights in the longitudinal direction (Z direction), so that the first main step structure 121 and the first sub-step structure 122 can be electrically connected through the first connecting structure 140 on the first gate layer 111 having corresponding numbers of layers and heights. Since the numbers of layers and heights of the first gate layers 111 of the first main step structure 121 and the first sub-step structure 122 correspond to each other, the connection length of the first connecting structure 140 can be reduced, and correspondingly, the resistance value of the connection is reduced, thereby improving the reliability of the device.

[0038] Furthermore, since the number of layers and height of the first gate layer 111 of the first main step structure 121 and the first sub-step structure 122 correspond to each other, at this time, the structure of the mask forming the first main step structure 121 can be improved so that the pattern of the mask can correspond to the patterns of the first main step structure 121 and the first sub-step structure 122, that is, appropriate modifications can be made to the original mask, and then the first sub-step structure 122 can be formed at the same time as the first main step structure 121 through photolithography, trimming and etching processes, etc., without adding a new mask. The structure of the embodiment of the present application can be formed without increasing additional production costs.

[0039] In addition, it should be noted that the correspondence between the number of layers and the height means that, for example, when the first main step structure 121 corresponds to the first storage area in terms of the number of layers and the height, assuming that the first main step structure 121 includes three layers of first gate layers 111 with a control function (for the sake of convenience, the three layers of the first gate layers 111 of the first main step structure 121 are respectively named as the first main gate layer, the second main gate layer and the third main gate layer), correspondingly, the first sub-step structure 122 also has three layers of first gate layers 111 that can be controlled by the first main step structure 121 (for the sake of convenience, the first sub-step structure 122 is respectively named as the first main gate layer 111 and the third main gate layer). The three-layer first gate layer 111 is named as the first auxiliary gate layer, the second auxiliary gate layer and the third auxiliary gate layer respectively. The number of layers of the first main gate layer, the second main gate layer and the third main gate layer is the same as or proportional to the number of layers of the first auxiliary gate layer, the second auxiliary gate layer and the third auxiliary gate layer respectively, and corresponds to each other in height. For example, the heights of the first auxiliary gate layer, the second auxiliary gate layer and the third auxiliary gate layer are successively increased. Correspondingly, the heights of the first auxiliary gate layer, the second auxiliary gate layer and the third auxiliary gate layer are also successively increased or decreased. The correspondence between the number of layers and the height below is similar to this principle and will not be repeated hereafter. In addition, it should be noted that the correspondence between the number of layers and the height only limits the existence of the first gate layer 111 with the corresponding number of layers and height in the first main step structure 121 and the first auxiliary step structure 122, and does not impose any special restrictions on whether there are other gate layers or other film layers.

[0040] In addition, it should be noted that Figure 1 and Figure 2 Only structures related to the present invention are shown. The three-dimensional memory of the present invention may further include other components and / or structures for realizing the complete functions of the device.

[0041] The first connection structure 140 includes a conductive connection layer, and the conductive connection layer includes a plurality of conductive pillars and at least one metal line.

[0042] Specifically, the first connection structure 140 can be a conductive connection layer, also known as a metal interconnect layer (BEOL, backend ofline). The conductive connection layer can include multiple conductive pillars and at least one metal line. The first gate layer 111 on the first main step structure 121 and the first sub-step structure 122 is led out through the multiple conductive pillars, and the multiple conductive pillars are then connected through the metal line. It is understood that the resistance of the conductive connection layer is the sum of the resistance of the conductive pillars and the metal line. When multiple conductive pillars and multiple metal lines are used, the resistance of the conductive connection layer is relatively large, that is, the resistance of the first connection structure 140 is relatively large, which may affect the read and write speed of the device.

[0043] The first connection structure 140 includes:

[0044] The first main conductive pillar 141, the first secondary conductive pillar 142 and the first metal wire 143 are respectively located on the first gate layer 111 of the first main step structure 121 and the first secondary step structure 122. The first metal wire 143 connects the first main conductive pillar 141 and the first secondary conductive pillar 142 that is close to the first main conductive pillar 141 and corresponds to the number of layers and height of the first main conductive pillar 141 in the longitudinal direction (Z direction), so that the first main step structure 121 and the first secondary step structure 122 are electrically connected to the first gate layer 111 that corresponds to the number of layers and height of the first secondary step structure 122 in the longitudinal direction (Z direction).

[0045] Specifically, in order to electrically connect the first main step structure 121 and the first sub-step structure 122 on the first gate layer 111 having corresponding layers and heights through the first connection structure 140 and reduce the resistance of the first connection structure 140, a first connection structure 140 including a first main conductive pillar 141, a first sub-conductive pillar 142, and a first metal wire 143 can be used. First, the first main conductive pillar 141 and the first sub-conductive pillar 142 are located on the first gate layer 111 of the first main step structure 121 and the first sub-step structure 122, respectively. The first gate layers 111 of the first main step structure 121 and the first sub-step structure 122 can be first led out through the conductive pillars. Then, the first main conductive pillar 141 is electrically connected to the first sub-conductive pillar 142, which is adjacent to the first main conductive pillar 141 and has corresponding layers and heights in the Z direction, through the first metal wire 143. Among them, the first main conductive column 141 and the first secondary conductive column 142 are a kind of connecting wire with conductive function. A contact hole (CT) can be formed by an etching process, and then a conductive material such as tungsten, copper or aluminum is filled in the contact hole to form the first main conductive column 141 and the first secondary conductive column 142.

[0046] Among them, the stepped area (A3 area) also includes:

[0047] a second top selection stepped structure 150, which is located in the stepped region and close to the second storage region. The second top selection stepped structure 150 includes a second main stepped structure 151 and a second sub-stepped structure 152 distributed along a first transverse direction (X direction). The second main stepped structure 151 and the second sub-stepped structure 152 have second gate layers 112 with corresponding numbers and heights in the longitudinal direction (Z direction);

[0048] The second connection structure 160 connects the second gate layers 112 of the second main step structure 151 and the second sub-step structure 152 with corresponding number of layers and heights.

[0049] Specifically, in some embodiments, for example, Figure 3In the GBCSS (GB center stairstructure, i.e. the structure where the stair area is located in the middle of the storage area) design shown in FIG, the stair area (i.e. Figure 3 The A3 region shown in FIG. 1 , wherein the A3 region further includes a sub-step region A31 and a partition wall region A32 for forming a partition wall structure 130) is located in the first storage region (ie, Figure 3 A1 area shown) and a second storage area (ie, Figure 3 In the design of the GBCSS, an upper select gate 210 and an upper select gate 220 (TSG, also known as an upper select transistor) are formed in the stepped area near the first storage area and the second storage area, respectively, and the upper select gate 210 and the upper select gate 220 are electrically connected by a first conductive pillar 231 located on the upper select gate 210, a first conductive pillar 232 located on the upper select gate 220, and a metal line 233. However, Figure 3 The metal line 233 shown needs to span the entire step region, which can cause certain difficulties in the process and the subsequent routing of other connecting lines. At the same time, since the metal line 233 needs to span the entire step region, the metal line 233 is very long, and accordingly, the resistance of the connecting line is very large, which affects the reliability of the device.

[0050] Based on this, the embodiment of the present application introduces a first sub-step structure 122 and a second sub-step structure 152. First, the first main step structure 121 and the first sub-step structure 122 have a first gate layer 111 with a corresponding number of layers and height in the longitudinal direction (Z direction), which can realize the electrical connection of the first main step structure 121 and the first sub-step structure 122 on the first gate layer 111 with a corresponding number of layers and height through the first connecting structure 140. Secondly, the second main step structure 151 and the second sub-step structure 152 have a second gate layer 112 with a corresponding number of layers and height in the longitudinal direction (Z direction), which can realize the electrical connection of the second main step structure 151 and the second sub-step structure 152 on the second gate layer 112 with a corresponding number of layers and height through the second connecting structure 160. Thirdly, through the partition wall structure 130, also known as the Great Wall (Great Wall), the first gate layer 111 with a corresponding number of layers and height can be electrically connected to the first main step structure 151 and the second sub-step structure 152. The partition wall structure 130 is composed of alternately stacked interlayer gate layers and interlayer insulating layers. The partition wall structure 130 is conductive with the first gate layer 111 in the adjacent first sub-step structure 122 and the second gate layer 112 in the second sub-step structure 152, which has the same number of layers and height. Therefore, a loop is formed by the electrical connection between the first main step structure 121 and the first sub-step structure 122, the electrical connection between the first sub-step structure 122 and the second sub-step structure 152 through the partition wall structure 130, and the electrical connection between the second main step structure 151 and the second sub-step structure 152. By electrically connecting the first gate layer 111 in the first main step structure 121 to the second gate layer 112 in the second main step structure 151 of corresponding layer number and height, when a voltage is applied to the first gate layer 111 in the first main step structure 121 or the second gate layer 112 in the second main step structure 151, the second main step structure 151 corresponding to the second gate layer 112 or the first main step structure 121 corresponding to the first gate layer 111 is turned on through the partition wall structure 130 and the same voltage is applied. In addition to achieving simultaneous control of the first and second storage areas, the length of the connection between the first and second main step structures 121, 151 and the external circuit can be effectively reduced, and the resistance of the connection can be correspondingly reduced, thereby improving the reliability of the device. At the same time, it can also effectively improve the problem of subsequent connection wire winding.

[0051] The second connection structure 160 includes a conductive connection layer (not shown in the figure), and the conductive connection layer includes a plurality of conductive pillars and at least one metal line.

[0052] Specifically, the second connection structure 160 can be a conductive connection layer, also known as a metal interconnect layer (BEOL, backend ofline). The conductive connection layer can include multiple conductive pillars and at least one metal line. The second gate layer 112 on the second main step structure 151 and the second sub-step structure 152 is led out through the multiple conductive pillars, and the multiple conductive pillars are then connected through the metal line. It is understood that the resistance of the conductive connection layer is the sum of the resistance of the conductive pillars and the metal line. When multiple conductive pillars and multiple metal lines are used, the resistance of the conductive connection layer is relatively large, that is, the resistance of the second connection structure 160 is relatively large, which may affect the read and write speed of the device.

[0053] Wherein, the conductive connecting layer comprises:

[0054] A second main conductive column 161, a second secondary conductive column 162 and a second metal wire 163, the second main conductive column 161 is located on the second gate layer 112 of the second main step structure 151, the second secondary conductive column 162 is located on the second gate layer 112 with a corresponding number of layers and height in the second secondary step structure 152, and the second metal wire 163 connects the second main conductive column 161 and the second secondary conductive column 162.

[0055] Specifically, in order to electrically connect the second main step structure 151 and the second sub-step structure 152 on the second gate layer 112 with corresponding number of layers and height through the second connection structure 160, and reduce the resistance value of the second connection structure 160, a second connection structure 160 including a second main conductive column 161, a second sub-conductive column 162 and a second metal wire 163 can be used. Since the second connection structure 160 is basically the same as the first connection structure 140, and the first connection structure 140 has been described in detail above, it will not be repeated here.

[0056] The first sub-step structure 122 and the second sub-step structure 152 have corresponding layers and heights in the longitudinal direction, and the first connection structure 140 and the second connection structure 160 are electrically connected through the first sub-step structure 122 , the second sub-step structure 152 and the partition wall structure 130 .

[0057] Furthermore, since the first sub-step structure 122 and the second sub-step structure 152 have corresponding numbers of layers and heights in the longitudinal direction, at this time, the mask plate for forming the first main step structure 121 and the second main step structure 151 can be improved so that the pattern of the mask plate corresponds to the patterns of the first main step structure 121, the first sub-step structure 122, the second main step structure 151 and the second sub-step structure 152, that is, appropriate modifications can be made to the original mask plate, and then the first sub-step structure 122 and the second sub-step structure 152 are formed at the same time as the first main step structure 121 and the second main step structure 151 through photolithography, shearing and etching processes, etc., without adding a new mask plate, and the structure of the embodiment of the present application is formed without increasing additional production costs.

[0058] The number of the first connection structure 140 and the number of the second connection structure 160 each include at least one group.

[0059] Specifically, since the first main step structure 121 and the second main step structure 151 can form one or more layers of the first gate layer 111, correspondingly, the number of each first connecting structure 140 and the second connecting structure 160 can be one or more groups. The first main step structure 121 and the corresponding first gate layer 111 of the first sub-step structure 122 are electrically connected through the first connecting structure 140, and the second main step structure 151 and the corresponding first gate layer 111 of the second sub-step structure 152 are electrically connected through the second connecting structure 160, which can effectively reduce the connection length between the first main step structure 121 and the second main step structure 151 and the external circuit. Correspondingly, the resistance value of the connection is reduced, thereby improving the reliability of the device.

[0060] In which, channel structures are formed in the first storage area and the second storage area respectively, penetrating the stack structure 110 and located on the substrate. The channel structure may include a blocking layer, a charge trapping layer, a tunneling layer and a poly channel layer distributed in sequence from the outside to the inside in the radial direction of the channel structure.

[0061] Specifically, the channel structure is a key structure in three-dimensional memory devices. The channel structure typically has a multilayer structure, including a channel layer, a tunneling layer, a charge-trapping layer, and a barrier layer. The film layers of the channel structure are sequentially arranged on the sidewall surfaces of the channel. The charge-trapping layer contains a large number of traps. After electrons or holes tunnel through the tunneling layer into the charge-trapping layer, they are captured by the traps in the charge-trapping layer, thus achieving storage.

[0062] Based on the three-dimensional memory described in the above embodiment, the embodiment of the present application also provides a method for manufacturing a three-dimensional memory, such as Figure 4 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. Figures 5 to 7 as well as Figure 1 The structure diagram may include the following:

[0063] Step S101: providing a substrate.

[0064] Specifically, a substrate (not shown in the figure) serves as the basis for forming a semiconductor device. The substrate is a semiconductor material, which can be silicon (Si), germanium (Ge) or silicon germanium (GeSi), silicon carbide (SiC), etc., or other materials without special restrictions.

[0065] Step S102: forming a stacking structure 110 in the longitudinal direction of the substrate, the stacking structure 110 including a first storage area, a stepped area, and a second storage area sequentially distributed along a first transverse direction, the stepped area including a sub-stepped area.

[0066] Figure 5 The structure formed in step S102 is shown, including: forming a stacked structure 110 on a substrate. Generally, the stacked structure 110 includes alternately stacked interlayer gate layers and insulating layers (not shown in the figure), and the stacked structure 110 is sequentially formed with a first storage area, a stepped area, and a second storage area (respectively) along the X direction. Figure 5 A1 area, A2 area and A3 area shown).

[0067] Specifically, first, a stacking structure 110 including a plurality of sacrificial layers and a plurality of insulating layers stacked alternately can be formed on a substrate through a deposition process, wherein the insulating layer is used to separate the plurality of sacrificial layers, and the material of the insulating layer can be composed of an oxide, such as silicon oxide (SiO2), and the material of the sacrificial layer can be composed of a nitride, such as silicon nitride (SiN). However, since the material of the sacrificial layer is mostly nitride, it is conducive to the simultaneous formation of a stacking structure 110 of a plurality of sacrificial layers and a plurality of insulating layers stacked alternately, but it is impossible to achieve control of the three-dimensional memory. In this case, the sacrificial layer needs to be removed, and then an interlayer gate layer is formed in the position of the original sacrificial layer. For example, the sacrificial layer can be removed by acid, and then a metal material, such as tungsten, is filled in the position of the original sacrificial layer to form a gate layer. Figure 5 The structure of the three-dimensional memory is shown.

[0068] In addition, it should be noted that Figure 5-7 and Figure 1 Only structures related to the present invention are shown. The three-dimensional memory of the present invention may further include other components and / or structures for realizing the complete functions of the device.

[0069] Step S103: A first top selection step structure 120 is formed in the step area. The first top selection step structure 120 is close to the first storage area. The first top selection step structure 120 includes a first main step structure 121 and a first sub-step structure 122 distributed along the first horizontal direction (X direction). The first main step structure 121 and the first sub-step structure 122 have a first gate layer 111 with a corresponding number of layers and height in the vertical direction (Z direction).

[0070] Figure 6 The structure formed in step S103 is shown, including: forming a stacking structure 110 on the substrate; simultaneously forming a first top selection step structure 120 near the first storage area in the step area, including a first main step structure 121 and a first sub-step structure 122 distributed along the first horizontal direction, the first main step structure 121 and the first sub-step structure 122 having corresponding numbers of layers and heights in the Z direction.

[0071] The first main step structure 121 and the first secondary step structure 122 are formed simultaneously.

[0072] Specifically, based on the structure formed in step S102, step S103 is continued to be performed, and the first sub-step structure 122 can be formed simultaneously with the formation of the first main step structure 121 through photolithography, shearing, and etching processes. For example, since the number of layers and heights of the first gate layer 111 of the first main step structure 121 and the first sub-step structure 122 correspond to each other, a photoresist can be coated on the structure formed in step S102 through photolithography. After exposure, development, drying, and other process steps, a patterned photoresist layer corresponding to the first main step structure 121 and the first sub-step structure 122 can be formed simultaneously in the stepped area near the first storage area. Subsequently, the first sub-step structure 122 can be formed simultaneously with the formation of the first main step structure 121 through photolithography, shearing, and etching processes. Since the number of layers and the height of the first gate layer 111 in the first main step structure 121 and the first sub-step structure 122 correspond to each other, at this time, the mask for forming the first main step structure 121 can be structurally improved so that the pattern of the mask corresponds to the patterns of the first main step structure 121 and the first sub-step structure 122. That is, a pattern corresponding to the pattern of the first sub-step structure 122 is added to the original mask corresponding to the pattern of the first main step structure 121. Then, through photolithography, shearing and etching processes, the first sub-step structure 122 is formed at the same time as the first main step structure 121, without adding a new mask, and without increasing additional production costs, the following is formed. Figure 6 The structure shown.

[0073] Step S104: forming a partition wall structure 130 in the stepped region. The partition wall structure 130 is close to the sub-stepped region and distributed along the first transverse direction (X direction), extending toward the first storage region and the second storage region.

[0074] Figure 7 The structure formed in step S104 is shown, including: a stacked structure 110 formed on the substrate; a first main step structure 121 and a first sub-step structure 122 formed simultaneously in the step area near the first storage area, wherein the first top selection step structure 120 includes the first main step structure 121 and the first sub-step structure 122 distributed along the first horizontal direction (X direction); and a partition wall structure 130 close to the sub-step area (A31 area) and distributed along the first horizontal direction (X direction).

[0075] Specifically, if Figure 7 As shown, one or more step structures can be formed in the step region through photolithography, shearing, and etching processes. The number and height of the step structures correspond to the number and height of the memory cells formed in the first and second memory regions. While the step structures are being formed, the remaining portion of the stacked structure 110 in the step region (i.e., the partition wall region A32) forms a partition wall structure 130. The partition wall structure 130 includes alternating interlayer gate layers and insulating layers. Furthermore, the partition wall structure 130 can be formed by other methods, as long as a partition wall structure 130 comprising alternating interlayer gate layers and insulating layers can be formed. There is no particular limitation on the method for forming the partition wall structure 130.

[0076] Step S105 : forming a first connection structure 140 above the first top selection stepped structure 120 , wherein the first connection structure 140 connects the first gate layers 111 of the first main stepped structure 121 and the first sub-stepped structure 122 with corresponding layers and heights.

[0077] The first connection structure 140 includes a conductive connection layer (not shown in the figure), and the conductive connection layer includes a plurality of conductive pillars and at least one metal line.

[0078] Specifically, the first connection structure 140 can be a conductive connection layer, also known as a metal interconnection layer (BEOL, backend ofline). The conductive connection layer can include multiple conductive pillars and at least one metal line. The first gate layer 111 on the first main step structure 121 and the first sub-step structure 122 is led out through multiple conductive pillars, and then the multiple conductive pillars are connected through metal lines.

[0079] It is understandable that the resistance of the conductive connection layer is the sum of the resistances of the conductive pillars and the metal lines. When multiple conductive pillars and multiple metal lines are used, the resistance of the conductive connection layer is relatively large, which may affect the read and write speed of the device.

[0080] The first connection structure 140 includes a first main conductive column 141 , a first secondary conductive column 142 , and a metal wire. Step S105 specifically includes:

[0081] Forming a first main conductive pillar 141 and a first sub-conductive pillar 142 on the first gate layer 111 of the first main stepped structure 121 and the first sub-stepped structure 122 respectively;

[0082] Metal wires are formed on the first main conductive pillar 141 and the first secondary conductive pillar 142 that is close to the first main conductive pillar 141 and corresponds to the number of layers and height of the first main conductive pillar 141 in the longitudinal direction (Z direction). The metal wires connect the first main step structure 121 and the first secondary step structure 122 in the longitudinal direction (Z direction) and the first gate layer 111 that corresponds to the number of layers and height.

[0083] Figure 1 The structure formed in step S105 is shown, including: a stacked structure 110 formed on a substrate; a first main step structure 121 and a first sub-step structure 122 formed simultaneously in the step area near the first storage area, wherein the first top selection step structure 120 includes the first main step structure 121 and the first sub-step structure 122 distributed along the first horizontal direction (X direction); a partition wall structure 130 distributed near the sub-step area (A31 area) and along the first horizontal direction (X direction); a first connection structure 140 formed above the first top selection step structure 120, the first connection structure 140 connecting the first main step structure 121 and the first sub-step structure 122. The first gate layer 111.

[0084] Specifically, based on the structure formed in step S104, step S105 is performed. For example, a first dielectric layer, which may be made of an oxide, may be formed on the structure formed in step S104. Subsequently, a plurality of first and second contact holes are formed in the first dielectric layer through an etching process. The first and second contact holes extend through the first dielectric layer to the top of the first main step structure 121 and the first gate layer 111 of the first sub-step structure, respectively. The first and second contact holes are then filled with a conductive material, such as tungsten, copper, or aluminum, respectively, to form a first main conductive pillar 141 and a first sub-conductive pillar 142. A second dielectric layer, which may be made of an oxide, is then formed above the first main conductive pillar 141 and the first sub-conductive pillar 142. Subsequently, a plurality of grooves are formed in the second dielectric layer, which extend through the second dielectric layer and extend to the top of the first main conductive pillar 141 and the first sub-conductive pillar 142, respectively. The grooves are then filled with a conductive material to form a first metal wire 143, thereby forming the first connection structure 140.

[0085] After step S102, the method further includes:

[0086] Step S106: A second top selection step structure 150 is formed in the step area. The second top selection step structure 150 is close to the second storage area. The second top selection step structure 150 includes a second main step structure 151 and a second sub-step structure 152 distributed along the first horizontal direction (X direction). The second main step structure 151 and the second sub-step structure 152 have a second gate layer 112 with a corresponding number of layers and height in the vertical direction.

[0087] Step S107: A second connecting structure 160 is formed above the second top selection step structure 150. The second connecting structure 160 connects the second gate layer 112 of corresponding layers and heights in the second main step structure 151 and the second sub-step structure 152. The number of layers and heights of the first gate layer 111 and the second gate layer 112 correspond to each other. The first connecting structure 140 and the second connecting structure 160 are electrically connected through the first sub-step structure 122, the second sub-step structure 152 and the partition wall structure 130.

[0088] Figure 6 The structure formed in step S106 is shown, including: a stacked structure 110 formed on the substrate; a second main step structure 151 and a second sub-step structure 152 formed simultaneously in the step area near the second storage area, wherein the second top selection step structure 150 includes the second main step structure 151 and the second sub-step structure 152 distributed along the first horizontal direction (X direction); a partition wall structure 130 distributed near the sub-step area (A31 area) and along the first horizontal direction (X direction); a second connection structure 160 formed above the second top selection step structure 150, the second main step structure 151 and the second sub-step structure 152 having a second gate layer 112 with a corresponding number of layers and height in the vertical direction.

[0089] Figure 1 The structure formed in step S107 is shown, including: a substrate; a stacked structure 110 located on the substrate; a first top selection stepped structure 120, the first top selection stepped structure 120 including a first main step structure 121 and a first sub-step structure 122; a partition wall structure 130; a first connection structure 140, the first connection structure 140 including a first main conductive column 141, a first sub-conductive column 142 and a first metal wire 143; a second top selection stepped structure 150, the second top selection stepped structure 150 including a second main step structure 151 and a second sub-step structure 152; a second connection structure 160, the second connection structure 160 including a second main conductive column 161, a second sub-conductive column 162 and a second metal wire 163.

[0090] Specifically, based on the structure formed in step S102, steps S106 and S107 are continued. Since the second top selective stepped structure 150 is substantially identical to the first top selective stepped structure 120, the second top selective stepped structure 150 can be formed using process steps similar to those performed in step S103. Specifically, some adjustments may need to be made based on the location of the second top selective stepped structure 150 and the number and height of the second top selective stepped structure 150. Since the process steps for forming the first top selective stepped structure 120 have been described in detail above, and the principles for forming the second top selective stepped structure 150 are substantially identical to those for forming the first top selective stepped structure 120, they will not be further described here. Furthermore, since the second connecting structure 160 is substantially identical to the first connecting structure 140, the second connecting structure 160 can be formed using process steps similar to those performed in step S105, which will not be further described here.

[0091] Specifically, as can be seen from the above, by electrically connecting the first gate layer 111 in the first main step structure 121 with the second gate layer 112 in the second main step structure 151 with the corresponding number of layers and height, it is achieved that when a voltage is applied to the first gate layer 111 in the first main step structure 121 or the second gate layer 112 in the second main step structure 151, the second main step structure 151 corresponding to the second gate layer 112 or the first main step structure 121 corresponding to the first gate layer 111 is turned on through the partition structure 130 and the same voltage is applied. In addition to achieving simultaneous control of the first storage area and the second storage area, the length of the connection between the first main step structure 121 and the second main step structure 151 and the external circuit can be effectively reduced. Correspondingly, the resistance value of the connection is reduced, thereby improving the reliability of the device. At the same time, it can also effectively improve the problem of subsequent connecting wire winding.

[0092] The second main step structure 151 and the second secondary step structure 152 are formed simultaneously.

[0093] Specifically, as can be seen from the above, since the number of layers and height of the second gate layer 112 of the second main step structure 151 and the second sub-step structure 152 correspond to each other, the mask for forming the second main step structure 151 can be structurally improved so that the pattern of the mask corresponds to the pattern of the second main step structure 151 and the second sub-step structure 152. The second sub-step structure 152 is formed at the same time as the second main step structure 151, and there is no need to add a new mask. Without increasing additional production costs, the second main step structure 151 can be formed. Figure 1 The structure shown.

[0094] The first secondary step structure 122 and the second secondary step structure 152 are formed simultaneously.

[0095] Furthermore, since the first sub-step structure 122 and the second sub-step structure 152 have corresponding numbers of layers and heights in the longitudinal direction, at this time, the mask plate for forming the first main step structure 121 and the second main step structure 151 can be improved so that the pattern of the mask plate corresponds to the patterns of the first main step structure 121, the first sub-step structure 122, the second main step structure 151 and the second sub-step structure 152, that is, a pattern corresponding to the pattern of the first sub-step structure 122 and the second sub-step structure 152 is added to the original mask plate corresponding to the pattern of the first main step structure 121 and the second main step structure 151, and then the first sub-step structure 122 and the second sub-step structure 152 are formed at the same time as the first main step structure 121 and the second main step structure 151 are formed through photolithography, shearing and etching processes, without adding a new mask plate, and the first top selection step structure 120 and the second top selection step structure 150 are formed at the same time without increasing additional production costs. At the same time, the first main step structure 121 and the second main step structure 151 of the same gate layer are electrically connected through the first connecting structure 140 and the second connecting structure 160, which can improve the winding problem of subsequent processes and effectively simplify the difficulty of subsequent processes.

[0096] After step S102, the method further includes:

[0097] Channel structures penetrating the stacked structure 110 and extending into the substrate are formed in the first storage area and the second storage area respectively. The channel structures include a blocking layer, a charge trapping layer, a tunneling layer and a channel layer sequentially distributed from outside to inside in the radial direction of the channel structure.

[0098] Specifically, based on the structure formed in step S102, a channel trench can be formed in the first storage area and the second storage area respectively through an etching process, penetrating the stacked structure 110 and extending into the substrate. Subsequently, a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer can be formed on the inner wall of the channel trench from the outside to the inside through chemical vapor deposition, atomic layer deposition, or any other appropriate deposition process, thereby forming a channel structure. As can be seen from the above, there are a large number of traps in the charge trapping layer of the channel structure. After electrons or holes tunnel into the charge trapping layer through the tunneling layer, they will be captured by the traps in the charge trapping layer, thereby achieving storage.

[0099] The number of the first connection structure 140 and the number of the second connection structure 160 each include at least one group.

[0100] Specifically, since the first main step structure 121 and the second main step structure 151 can be formed with one or more layers of the first gate layer 111 or the second gate layer 112, the number of the first connecting structures 140 and the second connecting structures 160 can be one or more groups. The first connecting structure 140 electrically connects the first gate layer 111 corresponding to the first main step structure 121 and the first sub-step structure 122, and the second connecting structure 160 electrically connects the second gate layer 112 corresponding to the second main step structure 151 and the second sub-step structure 152. This can effectively reduce the length of the connection between the first main step structure 121 and the second main step structure 151 and the external circuit, and correspondingly, reduce the resistance of the connection, thereby improving the reliability of the device. At the same time, it can improve the winding problem of subsequent processes, effectively simplifying the difficulty of subsequent processes.

[0101] Different from the prior art, the three-dimensional memory and the manufacturing method thereof in this embodiment, the three-dimensional memory includes: a substrate; a stacking structure, the stacking structure is located in the longitudinal direction of the substrate, the stacking structure includes a first storage area, a step area and a second storage area distributed in sequence along the first transverse direction; the step area includes: a sub-step area; a partition wall structure, the partition wall structure is close to the sub-step area and distributed along the first transverse direction, extending toward the first storage area and the second storage area; a first top selection step structure, the first top selection step structure is close to the first storage area, the first top selection step structure includes a first main step structure and a first sub-step structure distributed along the first transverse direction, the first main step structure and the first sub-step structure have first gate layers with corresponding numbers and heights in the longitudinal direction; a first connection structure, the first connection structure connects the first gate layers with corresponding numbers and heights in the first main step structure and the first sub-step structure. The first main step structure and the first gate layer in the first sub-step structure are connected through the first connecting structure. At the same time, a second connecting structure and a second top selection step structure are formed. The second main step structure and the second gate layer in the second sub-step structure are connected through the second connecting structure, so that the first connecting structure and the second connecting structure are electrically connected through the first sub-step structure, the second sub-step structure and the partition structure. The connection length of the first connecting structure and the second connecting structure can be reduced, thereby reducing the resistance value of the connection, improving the reliability of the device, and at the same time, simplifying the difficulty of subsequent processes.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A three-dimensional memory, comprising: A stacking structure, comprising a first storage area, a stepped area, and a second storage area sequentially distributed along a first transverse direction; wherein, The stepped area includes a stepped structure and a partition wall structure distributed along a second transverse direction, wherein the second transverse direction is perpendicular to the first transverse direction; The partition wall structure extends along the first transverse direction toward the first storage area and the second storage area; The stepped structure includes a first top selected stepped structure and an intermediate stepped structure distributed along the first transverse direction; The first top selection stepped structure is closer to the first storage area than the intermediate stepped structure, and includes a first main stepped structure and a first sub-stepped structure distributed along the first transverse direction, wherein the first main stepped structure and the first sub-stepped structure have first gate layers of corresponding number and height in a longitudinal direction, and the longitudinal direction is perpendicular to the first and second transverse directions; The intermediate step structure includes a first step pair, the first step pair including a first sub-step and a second sub-step distributed along the first transverse direction; and The first sub-staircase includes a plurality of first steps distributed along the first transverse direction and decreasing along the longitudinal direction, and the second sub-staircase includes a plurality of second steps distributed along the first transverse direction and increasing along the longitudinal direction, and the first steps and the second steps are located at different heights in the longitudinal direction.

2. The memory according to claim 1, further comprising: a first main conductive column, the first main conductive column extending along the longitudinal direction and connected to the first gate layer of the first main step structure; as well as A first secondary conductive pillar extends along the longitudinal direction and is connected to the first gate layer of the first secondary stepped structure.

3. The memory according to claim 2, further comprising: The first connection structure includes the first main conductive pillar and the first sub-conductive pillar, and connects the first gate layers of corresponding number and height in the first main step structure and the first sub-step structure.

4. The memory according to claim 1, wherein The stepped structure also includes a second top selection stepped structure, which is located on a side of the intermediate stepped structure close to the second storage area and includes a second main step structure and a second sub-step structure distributed along the first transverse direction. The second main step structure and the second sub-step structure have second gate layers with corresponding numbers and heights in the longitudinal direction.

5. The memory according to claim 4, further comprising: a second main conductive column, the second main conductive column extending along the longitudinal direction and connected to the second gate layer of the second main step structure; as well as A second secondary conductive pillar extends along the longitudinal direction and is connected to the second gate layer of the second secondary stepped structure. The memory according to claim 4 , wherein: The first gate layer of the first sub-step structure and the second gate layer of the second sub-step structure are electrically connected through the partition wall structure.

7. The memory according to claim 1, wherein The intermediate step structure includes a second step pair, the second step pair and the first step pair are distributed along the first transverse direction, and the second step pair includes a third sub-step and a fourth sub-step distributed along the first transverse direction; and The third sub-staircase includes a plurality of third steps distributed along the first transverse direction and decreasing along the longitudinal direction, and the fourth sub-staircase includes a plurality of fourth steps distributed along the first transverse direction and increasing along the longitudinal direction. The third steps and the fourth steps are located at different heights in the longitudinal direction.

8. The memory according to claim 7, wherein The intermediate step structure includes a third step pair, the third step pair, the first step pair, and the second step pair are distributed along the first transverse direction, and the third step pair includes a fifth sub-step and a sixth sub-step distributed along the first transverse direction; and The fifth sub-staircase includes a plurality of fifth steps distributed along the first transverse direction and decreasing along the longitudinal direction. The sixth sub-staircase includes a plurality of sixth steps distributed along the first transverse direction and increasing along the longitudinal direction. The fifth step and the sixth step are located at different heights in the longitudinal direction.

9. A three-dimensional memory, comprising: substrate; A stacking structure, the stacking structure is located in the longitudinal direction of the substrate, and the stacking structure includes a first storage area, a stepped area, and a second storage area sequentially distributed along a first transverse direction; wherein, The stepped area includes a stepped structure and a partition wall structure distributed along a second transverse direction, wherein the second transverse direction is perpendicular to the first transverse direction; The partition wall structure extends along the first transverse direction toward the first storage area and the second storage area; The stepped structure includes a first top selected stepped structure and a second top selected stepped structure distributed along the first transverse direction; The first top selection step structure is closer to the first storage area than the second top selection step structure, and includes a first main step structure and a first sub-step structure distributed along the first transverse direction, the first main step structure and the first sub-step structure having first gate layers with corresponding numbers and heights in the longitudinal direction, and the longitudinal direction is perpendicular to the first and second transverse directions; The second top selection step structure is closer to the second storage area relative to the first top selection step structure, and includes a second main step structure and a second sub-step structure distributed along the first horizontal direction. The second main step structure and the second sub-step structure have second gate layers with corresponding numbers and heights in the vertical direction.

10. The memory according to claim 9, further comprising: a first main conductive column, the first main conductive column extending along the longitudinal direction and connected to the first gate layer of the first main step structure; as well as A first secondary conductive pillar extends along the longitudinal direction and is connected to the first gate layer of the first secondary stepped structure.

11. The memory according to claim 10, further comprising: The first connection structure includes the first main conductive pillar and the first sub-conductive pillar, and connects the first gate layers of corresponding number and height in the first main step structure and the first sub-step structure.

12. The memory according to claim 9, further comprising: a second main conductive column, the second main conductive column extending along the longitudinal direction and connected to the second gate layer of the second main step structure; as well as A second secondary conductive pillar extends along the longitudinal direction and is connected to the second gate layer of the second secondary stepped structure.

13. The memory according to claim 9, wherein The first gate layer of the first sub-step structure and the second gate layer of the second sub-step structure are electrically connected through the partition wall structure.

14. The memory according to claim 9, wherein The stepped structure further includes an intermediate stepped structure, wherein the intermediate stepped structure is located between the first top selected stepped structure and the second top selected stepped structure in the first lateral direction; The intermediate step structure includes a first step pair, the first step pair including a first sub-step and a second sub-step distributed along the first transverse direction; and The first sub-staircase includes a plurality of first steps distributed along the first transverse direction and decreasing along the longitudinal direction, and the second sub-staircase includes a plurality of second steps distributed along the first transverse direction and increasing along the longitudinal direction, and the first steps and the second steps are located at different heights in the longitudinal direction.

15. The device according to claim 14, wherein The intermediate step structure includes a second step pair, the second step pair and the first step pair are distributed along the first transverse direction, and the second step pair includes a third sub-step and a fourth sub-step distributed along the first transverse direction; and The third sub-staircase includes a plurality of third steps distributed along the first transverse direction and decreasing along the longitudinal direction, and the fourth sub-staircase includes a plurality of fourth steps distributed along the first transverse direction and increasing along the longitudinal direction. The third steps and the fourth steps are located at different heights in the longitudinal direction.

16. The memory according to claim 15, wherein The intermediate step structure includes a third step pair, the third step pair, the first step pair, and the second step pair are distributed along the first transverse direction, and the third step pair includes a fifth sub-step and a sixth sub-step distributed along the first transverse direction; and The fifth sub-staircase includes a plurality of fifth steps distributed along the first transverse direction and decreasing along the longitudinal direction. The sixth sub-staircase includes a plurality of sixth steps distributed along the first transverse direction and increasing along the longitudinal direction. The fifth step and the sixth step are located at different heights in the longitudinal direction.

17. A method for manufacturing a three-dimensional memory, comprising: providing a substrate; forming a stacking structure in the longitudinal direction of the substrate, the stacking structure comprising a first storage area, a stepped area, and a second storage area sequentially distributed along a first transverse direction; forming a first top selection stepped structure in the stepped region; and A partition wall structure and an intermediate step structure are formed in the step area; wherein, The stepped area includes a stepped structure and the partition wall structure distributed along a second transverse direction, the second transverse direction is perpendicular to the first transverse direction, and the stepped structure includes the first top selected stepped structure and the middle stepped structure distributed along the first transverse direction; The first top selection step structure is closer to the first storage area than the intermediate step structure, and includes a first main step structure and a first sub-step structure distributed along the first transverse direction. The first main step structure and the first sub-step structure have first gate layers with corresponding numbers and heights in the longitudinal direction, and the longitudinal direction is perpendicular to the first and second transverse directions. The partition wall structure extends along the first transverse direction toward the first storage area and the second storage area; The intermediate step structure includes a first step pair, the first step pair including a first sub-step and a second sub-step distributed along the first transverse direction; and The first sub-staircase includes a plurality of first steps distributed along the first transverse direction and decreasing along the longitudinal direction, and the second sub-staircase includes a plurality of second steps distributed along the first transverse direction and increasing along the longitudinal direction, and the first steps and the second steps are located at different heights in the longitudinal direction.

18. The memory manufacturing method according to claim 17, further comprising: A second top selection step structure is formed in the step area. The second top selection step structure is closer to the second storage area than the first top selection step structure. The second top selection step structure includes a second main step structure and a second sub-step structure distributed along the first transverse direction. The second main step structure and the second sub-step structure have second gate layers with corresponding numbers and heights in the longitudinal direction.

19. The memory manufacturing method according to claim 18, wherein: The second main step structure and the second secondary step structure are formed simultaneously.

20. The memory manufacturing method according to claim 17, wherein: The first main step structure and the first secondary step structure are formed simultaneously.

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