Memory device and method of manufacturing memory device

Abstract

Memory devices and methods of manufacturing memory devices are provided herein. The method of manufacturing the memory device includes forming a stack including a first material layer and a second material layer on a lower structure; forming a first opening through the laminate; filling the first openings with preliminary contact plugs, respectively; forming a step structure on the laminated body, wherein the step structure comprises steps corresponding to the preliminary contact plugs respectively; forming a second opening that passes through each step of the stepped structure and opens at least a portion of the first opening at different depths, respectively; exposing a side surface of the second material layer by removing a respective portion of the preliminary contact plug adjacent to a respective first side of the first opening through the second opening; and forming a laminate having a reverse step structure by removing the exposed portion of the second material layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a memory block having a three-dimensional (3D) structure and a method of manufacturing the memory device. Background Art

[0002] The memory device may include a nonvolatile memory device in which stored data is retained even when power is interrupted. The nonvolatile memory device may be divided into a two-dimensional (2D) structure and a three-dimensional (3D) structure according to the arrangement structure of the memory cells. The memory cells of the nonvolatile memory device having a 2D structure may be arranged in a single layer on a substrate, while the memory cells of the nonvolatile memory device having a 3D structure may be vertically stacked on the substrate. Because the integration of the nonvolatile memory device having a 3D structure is higher than that of the nonvolatile memory device having a 2D structure, the number of electronic devices using the nonvolatile memory device having a 3D structure has recently increased. Summary of the Invention

[0003] Embodiments of the present disclosure may provide a method for manufacturing a memory device. The method may include: forming a stack including a first material layer and a second material layer on a lower structure; forming first openings through the stack; filling the first openings with preliminary contact plugs; forming a stepped structure on the stack, the stepped structure including steps corresponding to the preliminary contact plugs; forming second openings that pass through each step of the stepped structure and open at least a portion of the first opening at different depths; exposing side surfaces of the second material layer by removing corresponding portions of the preliminary contact plugs adjacent to corresponding first sides of the first openings through the second openings; and forming a stack having an inverted stepped structure by removing the exposed portions of the second material layer.

[0004] One embodiment of the present disclosure may provide a memory device. The memory device may include: a lower structure including a pass transistor; a plurality of contact plugs, each connected to the pass transistor and configured to extend in a first direction, the plurality of contact plugs having different lengths; and a plurality of conductive layers, each contacting the plurality of contact plugs and stacked in a manner spaced apart from each other in the first direction, the plurality of conductive layers having an inverted step structure, wherein a first conductive layer among the plurality of conductive layers contacts a first contact plug among the plurality of contact plugs, and the first conductive layer is penetrated by a gap-filling insulating layer provided in the first direction, the gap-filling insulating layer extending from a second contact plug among the plurality of contact plugs in the first direction, and the second contact plug is shorter than the first contact plug in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0006] Figure 2 is a diagram illustrating in detail global lines and local lines according to an embodiment of the present disclosure.

[0007] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D is a diagram illustrating a cell region and a contact region in a memory device according to an embodiment of the present disclosure.

[0008] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4H 、 Figure 4I 、 Figure 4J 、 Figure 4K 、 Figure 4L 、 Figure 4M and Figure 4N is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0009] Figure 5A and Figure 5B is a diagram illustrating a conductive layer of a memory device according to an embodiment of the present disclosure.

[0010] Figure 6 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0011] Figure 7 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0012] The specific structural or functional descriptions in the embodiments of the present disclosure concept introduced in this specification or application are only used to describe the embodiments according to the present disclosure concept. The embodiments according to the present disclosure concept can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings showing embodiments of the present disclosure, so that those skilled in the art to which the present disclosure belongs can practice the technical spirit of the present disclosure. In the description of the present disclosure, the terms "first" and "second" can be used to describe various components, but the components are not limited by the terms. These terms can be used to distinguish one component from another. For example, without departing from the scope of the present disclosure, the first component can be referred to as the second component, and the second component can be referred to as the first component. It should be understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, directly connected to or directly coupled to another element or layer; or there can be an intervening element or layer. On the contrary, when an element or layer is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. Similar reference numerals refer to similar elements. For ease of description, spatially relative terms such as "under," "below," "down," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the drawings, the elements described as being "under" or "below" other elements or features will be oriented as being "above" the other elements or features. Thus, the example of the term "under" can cover both upper and lower orientations. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] Various embodiments of the present disclosure relate to a memory device capable of improving electrical efficiency in a contact region of the memory device and a method of manufacturing the memory device.

[0015] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0016] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0017] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a plurality of memory cells capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly coupled to the first to i-th memory blocks BLK1 to BLKi.

[0018] Each of the first to i-th memory blocks BLK1 to BLKi may be formed to have a three-dimensional (3D) structure. Each memory block having the 3D structure may include memory cells stacked in a vertical direction on a substrate.

[0019] Depending on the programming scheme, each memory cell can store 1 bit of data or 2 or more bits of data. For example, a scheme for storing 1 bit of data in a memory cell is called a single-level cell (SLC) scheme, while a scheme for storing 2 bits of data in a memory cell is called a multi-level cell (MLC) scheme. A scheme for storing 3 bits of data in a memory cell is called a triple-level cell (TLC) scheme, while a scheme for storing 4 bits of data in a memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data can be stored in a memory cell.

[0020] The peripheral circuit 170 may perform a program operation for storing data in the memory cell array 110, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0021] The voltage generator 120 can generate various operating voltages Vop for a program operation, a read operation, or an erase operation in response to the operation code OPCD. For example, the voltage generator 120 can generate a program voltage, an on voltage, an off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operating voltage Vop generated by the voltage generator 120 can be applied to the drain select line DSL, the word line WL, and the source select line SSL of the memory block selected by the row decoder 130.

[0022] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. The precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used for a verification operation to determine whether the threshold voltage of a selected memory cell has increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0023] A read voltage may be applied to a selected word line during a read operation performed on a selected memory cell. For example, the read voltage may be set to various levels depending on the programming scheme for the selected memory cell. A pass voltage may be a voltage applied to an unselected word line among word lines WL during a programming operation or a read operation, and may be used to turn on memory cells connected to the unselected word lines. An erase voltage may be used during an erase operation to erase memory cells included in a selected memory block.

[0024] The row decoder 130 may transmit the operating voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL connected to the memory block selected according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through a global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through a local line (e.g., the drain select line DSL, the word line WL, and the source select line SSL). This will be referred to later. Figure 2 Describe global and local lines in detail.

[0025] The voltage generator 120 may include a source driver. The source driver may generate a source line voltage applied to the source line SL. The source line voltage may include a ground voltage or a positive voltage applied to the source line SL.

[0026] The page buffer group 140 may include page buffers (not shown) connected to the first to i-th memory blocks BLK1 to BLKi, respectively. The page buffers (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi through bit lines BL. During a read operation, the page buffers (not shown) may sense a current or voltage of a bit line that varies with a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG and may store the sensed data.

[0027] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 via a column line CL and may transmit an enable signal via the column line CL. The page buffers (not shown) included in the page buffer group 140 may receive or output data via the data lines DL in response to the enable signal.

[0028] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data via an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller via the input / output line I / O to the control circuit 180, and may transmit data received from the external controller via the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller via the input / output line I / O.

[0029] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 so that a program operation is performed on the memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 so that a read operation is performed on the memory block selected by the address and the read data is output. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 so that an erase operation is performed on the selected memory block.

[0030] Figure 2 is a diagram illustrating in detail global lines and local lines according to an embodiment of the present disclosure.

[0031] Reference Figure 2 , the row decoder 130 may include first to i-th pass switching groups PSG1 to PSGi corresponding to the first to i-th memory blocks BLK1 to BLKi, respectively. Figure 2 The configuration of the i-th transmission switch group PSGi is described below, but the description of the i-th transmission switch group PSGi can also be applied to the remaining transmission switch groups.

[0032] The i-th pass switch group PSGi may include a decoder DEC, a block word line BWL, and a pass transistor group PTRG. The pass transistor group PTRG may include a plurality of pass transistors PTR.

[0033] The plurality of pass transistors PTR included in the pass transistor group PTRG may be coupled to the voltage generator 120 via a global line GL and may be connected to the i-th memory block BLKi via a local line LL. The local line LL may include a drain select line DSL, a word line WL, and a source select line SSL. The global line GL may include a global drain select line G_DSL, a global word line G_WL, and a global source select line G_SSL.

[0034] The row decoder 130 may connect the global line GL to the local line LL connected to the memory block selected according to the row address RADD among the first to i-th memory blocks BLK1 to BLKi. In addition, the row decoder 130 may not connect the global line GL to the local line LL connected to the memory block not selected according to the row address RADD among the first to i-th memory blocks BLK1 to BLKi.

[0035] The decoder DEC can turn on or off the pass transistor PTR by applying a block control signal to the block word line BWL according to the received row address RADD. In an example, when the decoder DEC receives the row address RADD for activating the i-th transfer switch group PSGi, the decoder DEC can turn on the pass transistor PTR included in the i-th transfer switch group PSGi by applying a block control signal having a high voltage to the block word line BWL. In an example, when the decoder DEC receives the row address RADD for deactivating the i-th transfer switch group PSGi, the decoder DEC can turn off the pass transistor PTR included in the i-th transfer switch group PSGi by deactivating the block control signal. For example, the deactivated block control signal can have a cut-off voltage.

[0036] When the pass transistor PTR of the i-th pass switch group PSGi is turned on, the global drain select line G_DSL and the drain select line DSL, the global word line G_WL and the word line WL, and the global source select line G_SSL and the source select line SSL can be electrically connected to each other through the corresponding pass transistor PTR. When the pass transistor PTR is turned on, the operating voltage (e.g., Figure 1 Vop) can be transmitted to the i-th memory block BLKi through the global line GL, the transfer transistor PTR and the local line LL.

[0037] When the pass transistor PTR of the i-th pass switch group PSGi is turned off, the global drain select line G_DSL and the drain select line DSL, the global word line G_WL and the word line WL, and the global source select line G_SSL and the source select line SSL may be electrically disconnected from each other through the corresponding pass transistor PTR. When the pass transistor PTR is turned off, the operating voltage Vop generated by the voltage generator 120 and applied to the global line GL may not be transmitted to the i-th memory block BLKi.

[0038] The source line SL may not be coupled to the pass transistor PTR of the pass transistor group PTRG. For example, the source line SL may be directly connected to the source driver in the voltage generator 120. Therefore, regardless of whether the pass transistor PTR of the i-th pass switch group PSGi is turned on or off, the source line SL may be electrically connected to the source driver.

[0039] Figures 3A to 3D is a diagram illustrating a cell region and a contact region of a memory device according to an embodiment of the present disclosure. Figure 3A is a cross-sectional view of a cell region and a contact region of a memory device. Figure 3B FIG. 1 is a diagram illustrating the structure of a conductive layer and a contact plug of a memory device. Figure 3C It is along Figure 3A A cross-sectional view taken along line AA′. Figure 3D It is along Figure 3A A cross-sectional view taken along line BB′.

[0040] Reference Figure 3A , the memory device 100 may include a lower structure SUB. The lower structure SUB may include a substrate. The lower structure SUB may include Figure 1 For example, Figure 2 The pass transistors PTR and the first pass lines 1PL respectively connected to the pass transistors PTR may be provided in the lower structure SUB. The first pass line 1PL may be understood as Figure 2 For example, the first transmission line 1PL can be understood as being included in the drain or source of each transmission transistor PTR. Figure 2 In the local line LL. Figure 3A and Figure 3B , the transmission transistor PTR, the first transmission line 1PL and the second transmission line 2PL can be arranged in the lower structure SUB. The second transmission line 2PL can be understood as the source or drain of each transmission transistor PTR. For example, the first transmission line 1PL can be included in the local line LL (in Figure 3B 1PL), and the second transmission line 2PL may be included in the global line GL (in Figure 3B It is represented as (GL)2PL).

[0041] Reference Figure 3A , the memory device 100 may include a stacked body STK above the lower structure SUB. The stacked body STK may include conductive layers CD and interlayer insulating layers IIL alternately stacked along the Z direction (i.e., for some embodiments, this may be the first direction). The conductive layers CD may be stacked spaced apart from each other in the Z direction. The conductive layers CD and the interlayer insulating layers IIL may extend separately along the X direction. The stacked body STK may correspond to Figure 1 and Figure 2 Any one of the memory blocks BLK1 to BLKi.

[0042] Each conductive layer CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (Poly-Si). The conductive layer CD may be used as a gate line, for example, a drain select line DSL (in Figure 3A Indicated as CD(DSL)), word line WL (in Figure 3A Indicated as CD(WL)) or source select line SSL (in Figure 3A Each interlayer insulating layer IIL may be formed of an oxide layer (eg, a silicon oxide layer).

[0043] The stacked body STK may include a cell region CR and a contact region CTR. The contact region CTR may extend from the cell region CR in the X direction. One or more cell plugs CPL may be formed in the cell region CR. One or more contact plugs CT may be formed in the contact region CTR. Figure 3A The positions, numbers, and arrangements of the cell plugs CPL and contact plugs CT shown are examples and are not intended to limit the scope of this disclosure. In this example, the number of contact plugs CT may vary depending on the number of conductive layers CD. In this example, the contact plugs CT may not be arranged in a straight line along the X-direction but may be arranged misaligned. Furthermore, the cell plugs CPL and contact plugs CT may have various positions, numbers, and arrangements.

[0044] The cell plug CPL may extend in the Z direction within the cell region CR of the stack body STK. The cell plug CPL may penetrate the cell region CR of the stack body STK in the Z direction. Each cell plug CPL may include a cylindrical memory layer ML. The memory layer ML may include a barrier layer, a charge trapping layer formed along the inner wall of the barrier layer, or a tunnel isolation layer formed along the inner wall of the charge trapping layer, or a combination of at least two thereof. Each cell plug CPL may include a channel layer CH formed along the inner wall of the memory layer ML and a core column CO formed in the channel layer CH.

[0045] Each of the blocking layer and the tunnel isolation layer included in the memory layer ML may be formed of an oxide layer (e.g., a silicon oxide layer), an oxynitride layer (e.g., a silicon oxynitride layer), or a combination thereof. The charge trapping layer included in the memory layer ML may be a charge storage layer and may include a nitride layer or a variable resistance material. The channel layer CH may be formed of a conductive layer (e.g., a doped silicon layer). The channel layer CH may be replaced by an electrode structure. The core column CO may be formed of an insulating layer or a conductive layer. In an embodiment, a capping layer for improving the electrical characteristics of the selection transistor may be further formed on the core column CO.

[0046] The cell plugs CPL may be coupled to source lines SL. The source lines SL may be disposed between the cell region CR of the stacked body STK and the lower structure SUB. The source lines SL may overlap the cell region CR. The source lines SL may contact the channel layer CH included in each cell plug CPL. Although not shown in the drawings, the source lines SL may be electrically connected to the peripheral circuit 170 of the lower structure SUB.

[0047] Reference Figure 3A and Figure 3B , the contact region CTR may have a stepped structure including a plurality of steps. Each of the plurality of steps may include a conductive layer CD and an interlayer insulating layer IIL. The contact region CTR may include a reverse step structure. The conductive layer CD may have a reverse step structure. In the present disclosure, the reverse step structure may refer to a stepped structure whose horizontal length decreases from the top (e.g., the Z direction) to the bottom (e.g., the direction opposite to the Z direction). In addition, in the present disclosure, the forward step structure may refer to a stepped structure whose horizontal length increases from the top to the bottom. Figure 3A and Figure 3B In the embodiment, the length of the conductive layer CD in the X direction may increase along the Z direction. For example, the length of the drain select line DSL in the X direction may be greater than the length of the word line WL in the X direction, and the length of the word line WL in the X direction may be greater than the length of the source select line SSL in the X direction. In some embodiments, the X direction may be referred to as a second direction.

[0048] Reference Figure 3A and Figure 3B , the contact plugs CT may correspond to the respective steps included in the stepped structure of the contact region CTR. Each contact plug CT may be connected to the conductive layer CD included in any one of the plurality of steps. The contact plugs CT may respectively contact the side surfaces of the conductive layer CD. For example, the first contact plug CT1 (in Figure 3B CT (CT1) in FIG. 1 ) can contact the drain select line DSL (in FIG. Figure 3B In addition, the second contact plug CT2 (indicated as CD (DSL)) corresponds to the conductive layer CD. Figure 3B Indicated as CT(CT2)), the third contact plug CT3 (in Figure 3B Indicated as CT (CT3)) and the fourth contact plug CT4 (in Figure 3B CT (CT4)) can contact the word line WL (in Figure 3B In addition, the fifth contact plug CT5 (indicated as CD (WL)) corresponds to the conductive layer CD. Figure 3B Indicated as CT (CT5) in FIG. 1 ) can contact the source selection line SSL (in Figure 3B The conductive layer CD corresponding to the SSL is represented as CD(SSL)).

[0049] Reference Figure 3A and Figure 3B The contact plugs CT can connect the conductive layer CD to the transfer transistors PTR, respectively. The contact plugs CT can electrically connect the conductive layer CD to the transfer transistors PTR, respectively, by connecting the conductive layer CD to the first transfer lines 1PL. For example, the first contact plug CT1 can connect the drain select line DSL to any of the first transfer lines 1PL. The second contact plug CT2 can connect the corresponding word line WL to any of the first transfer lines 1PL. The fifth contact plug CT5 can connect the source select line SSL to any of the first transfer lines 1PL. Each contact plug CT can include a conductive material (e.g., silicon). The contact plug CT can penetrate the lower insulating layer UIL between the stack body STK and the lower structure SUB.

[0050] The contact plugs CT may have different lengths in the Z direction. The heights of the contact plugs CT may be formed to be different from each other. For example, in the Z direction, the first contact plug CT1 may be longer than the second contact plug CT2. Furthermore, in the Z direction, the second contact plug CT2 may be longer than the third contact plug CT3. Furthermore, in the Z direction, the third contact plug CT3 may be longer than the fourth contact plug CT4. Furthermore, in the Z direction, the fourth contact plug CT4 may be longer than the fifth contact plug CT5.

[0051] The bottom surfaces of the contact plugs CT may have the same height as each other. The bottom surfaces of the contact plugs CT may be located at the same height to contact the first transmission lines 1PL. For example, the bottom surfaces of the contact plugs CT may have the same height as the top surfaces of the first transmission lines 1PL.

[0052] The top surfaces of the contact plugs CT may each have a height corresponding to the top surface height of the conductive layer CD. The top surfaces of the contact plugs CT may have different heights. For example, the top surface of the first contact plug CT1 may be located at the same height as the top surface of the conductive layer CD corresponding to the drain select line DSL. Furthermore, the top surfaces of the second, third, and fourth contact plugs CT2, CT3, and CT4 may be located at the same height as the top surfaces of the conductive layer CD corresponding to the word lines WL. Furthermore, the top surface of the fifth contact plug CT5 may be located at the same height as the top surface of the conductive layer CD corresponding to the source select line SSL.

[0053] Reference Figure 3B In an embodiment, the contact plugs CT may each have a semi-cylindrical or semi-elliptical shape. In an embodiment, the planes of the contact plugs CT may each have a semi-circular or semi-elliptical shape. In an embodiment, the cross-section of each contact plug CT observed in the Z direction may have a semi-circular or semi-elliptical shape. For example, the left surface of the contact plug CT may be a curved surface, and the right surface thereof may be a flat surface. A local upper portion of the left surface of each contact plug CT may contact the corresponding conductive layer CD. The right surface of each contact plug CT and the right surface of the corresponding conductive layer CD may be located on the same plane. Figure 3B In FIG. 1 , the right direction may indicate the X direction, and the left direction may indicate the direction opposite to the X direction.

[0054] Reference Figure 3A , gap-filling insulating layers GIL1 and GIL2 may be disposed on the contact plug CT. The first gap-filling insulating layer GIL1 may extend from the contact plug CT in the Z direction. In an embodiment, each first gap-filling insulating layer GIL1 may have a cylindrical shape. The first gap-filling insulating layer GIL1 may contact the conductive layer CD and the interlayer insulating layer IIL. The second gap-filling insulating layer GIL2 may fill the first gap-filling insulating layer GIL1. The second gap-filling insulating layer GIL2 may contact the inner surface of the first gap-filling insulating layer GIL1. The first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may be formed of the same or similar material. For example, each of the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may include an oxide layer. Therefore, the interface between the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may not be observed.

[0055] The second gap-filling insulating layer GIL2 may extend to the side surface of the contact plug CT. Each second gap-filling insulating layer GIL2 may protrude toward a height lower than the bottom surface of the corresponding first gap-filling insulating layer GIL1. The second gap-filling insulating layer GIL2 may contact the side surface of the contact plug CT. In an embodiment, the plane of the contact plug CT and the second gap-filling insulating layer GIL2 observed in the Z direction may have a circular or elliptical shape. In addition, the second gap-filling insulating layer GIL2 may contact the lower insulating layer UIL. The second gap-filling insulating layer GIL2 and the lower insulating layer UIL may be formed of the same or similar material, so that the interface therebetween may not be observed.

[0056] The second gap-filling insulating layer GIL2 may extend into the space between the interlayer insulating layers IIL. The second gap-filling insulating layer GIL2 may be located at the same height as the conductive layer CD. The second gap-filling insulating layer GIL2 may fill the space between the interlayer insulating layers IIL of the stack STK. The second gap-filling insulating layer GIL2 may contact the top and bottom surfaces of the interlayer insulating layer IIL. The second gap-filling insulating layer GIL2 and the interlayer insulating layer IIL may be formed of the same or similar material, so that an interface therebetween may not be observed.

[0057] Reference Figure 3A and Figure 3B , the gap-filling insulating layers GIL1 and GIL2 provided on the contact plugs CT may penetrate the conductive layer CD. For example, the conductive layer CD corresponding to the drain select line DSL may be penetrated by the gap-filling insulating layers GIL1 and GIL2 provided on the second contact plug CT2, the third contact plug CT3, the fourth contact plug CT4, and the fifth contact plug CT5. In addition, among the conductive layers CD corresponding to the word lines WL, the uppermost conductive layer CD may be penetrated by the gap-filling insulating layers GIL1 and GIL2 provided on the third contact plug CT3, the fourth contact plug CT4, and the fifth contact plug CT5. Because Figure 3B Illustration of the interlayer insulating layer IIL, the gap-filling insulating layers GIL1 and GIL2, and the lower insulating layer UIL is omitted, so regions corresponding to the gap-filling insulating layers GIL1 and GIL2 penetrating the conductive layer CD may be shown as empty spaces.

[0058] In addition, refer to Figure 3A and Figure 3B, portions of the gap-filling insulating layers GIL1 and GIL2 disposed on the contact plug CT may overlap with the contact plug CT. For example, the area occupied by the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 at a first height (e.g., a height corresponding to the interlayer insulating layer IIL between the DSL and the WL) may be the same as the area occupied by the second contact plug CT2 and the second gap-filling insulating layer GIL2 at a second height (e.g., a height corresponding to the interlayer insulating layer IIL between the WL and the WL). Furthermore, the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 at the first height may overlap with the second contact plug CT2 and the second gap-filling insulating layer GIL2 at the second height.

[0059] about Figure 3C and Figure 3D , can be omitted or briefly described with reference to Figure 3A and Figure 3B The construction described. Figure 3C Illustrated along Figure 3A The cross section is taken along line AA′, and Figure 3D Illustrated along Figure 3A The cross section is taken along line BB′.

[0060] Reference Figure 3C , and the conductive layer CD corresponding to the drain selection line DSL (in Figure 3C The conductive layer CD (denoted as CD(DSL)) may contact the first contact plug CT1. The side surface of the conductive layer CD in the X direction may include a recessed portion. The first contact plug CT1 may fill the recessed portion of the conductive layer CD. The side surface of the conductive layer CD in the X direction may include a concave surface. The first contact plug CT1 may contact the concave surface of the conductive layer CD.

[0061] The side surface of the conductive layer CD in the X direction may contact the second gap-filling insulating layer GIL2. Since the second gap-filling insulating layer GIL2 fills the space between the interlayer insulating layers IIL at the same height as the conductive layer CD, the second gap-filling insulating layer GIL2 may be disposed in the X direction of the conductive layer CD. Figure 3C , the second gap-filling insulating layer GIL2 is illustrated as being divided into two regions, but this illustration is provided for ease of description, and the regions of the second gap-filling insulating layer GIL2 may be connected without an interface. That is, in the second gap-filling insulating layer GIL2, the region adjacent to the first contact plug CT1 and the remaining region may extend to each other without an interface.

[0062] The conductive layer CD may be penetrated by the gap-filling insulating layers GIL1 and GIL2 disposed on the second to fifth contact plugs CT2 to CT5. The first gap-filling insulating layer GIL1 may be disposed between the second gap-filling insulating layer GIL2 and the conductive layer CD. An interface between the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may not be observed.

[0063] Reference Figure 3D , and the conductive layer CD corresponding to the word line WL (in Figure 3D The conductive layer CD (indicated by CD(WL) in the figure) may contact the second contact plug CT2. The side surface of the conductive layer CD in the X direction may include a recessed portion. The second contact plug CT2 may fill the recessed portion of the conductive layer CD. The side surface of the conductive layer CD in the X direction may include a concave surface. The second contact plug CT2 may contact the concave surface of the conductive layer CD.

[0064] The side surface of the conductive layer CD in the X direction may contact the second gap-filling insulating layer GIL2. Since the second gap-filling insulating layer GIL2 fills the space between the interlayer insulating layers IIL at the same height as the conductive layer CD, the second gap-filling insulating layer GIL2 may be disposed in the X direction of the conductive layer CD.

[0065] The first contact plug CT1 may be disposed in the X direction of the second contact plug CT2. The first contact plug CT1 may not contact the conductive layer CD corresponding to the word line WL. In the cross section of BB', the first contact plug CT1 may be surrounded by the second gap-filling insulating layer GIL2.

[0066] Despite Figure 3D , the second gap-filling insulating layer GIL2 is illustrated as being divided into three regions, but this illustration is provided for ease of description, and the regions of the second gap-filling insulating layer GIL2 may be connected without an interface. That is, in the second gap-filling insulating layer GIL2, the region adjacent to the first contact plug CT1, the region adjacent to the second contact plug CT2, and the remaining region may extend to each other without an interface.

[0067] The conductive layer CD may be penetrated by the gap-filling insulating layers GIL1 and GIL2 disposed on the third to fifth contact plugs CT3 to CT5. The first gap-filling insulating layer GIL1 may be disposed between the second gap-filling insulating layer GIL2 and the conductive layer CD. An interface between the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may not be observed.

[0068] According to various embodiments of the present disclosure, the stack body STK has an inverted step structure, thereby simplifying the electrical path connecting the conductive layer CD to the transfer transistor PTR. For example, because the conductive layer CD has an inverted step structure, each conductive layer CD can be connected to the first transfer line 1PL via a single contact plug CT. Therefore, in embodiments, the length of the electrical path connecting the peripheral circuit 170 to the conductive layer CD can be shortened compared to conventional structures. In other words, various embodiments of the present disclosure can improve the electrical efficiency used to control the memory device 100 by reducing the length of the wires included in the contact region CTR.

[0069] Figures 4A to 4N is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure. Figures 4A to 4N , for convenience of description, the contact region CTR is mainly illustrated, and components included in the cell region CR may be omitted.

[0070] Reference Figure 4A , a lower structure SUB may be formed. The lower structure SUB may include a first transmission line 1PL. The lower structure SUB may include Figure 3B The first transmission line 1PL and the second transmission line 2PL may be coupled to corresponding transmission transistors PTR.

[0071] Subsequently, a lower insulating layer UIL may be formed on the lower structure SUB. The lower insulating layer UIL may include an oxide layer. Although not shown in the drawings, a lower insulating layer UIL may also be formed. Figure 3A The source line SL.

[0072] Subsequently, a preliminary stack pSTK may be formed on the lower insulating layer UIL. The preliminary stack pSTK may include a first material layer 1M and a second material layer 2M. The first material layer 1M and the second material layer 2M may be alternately stacked along the Z direction. The first material layer 1M may correspond to Figure 3A Each first material layer 1M may be formed of an insulating material. For example, each first material layer 1M may be formed of an oxide layer (for example, a silicon oxide layer). Each second material layer 2M may be formed of a material that can be selectively removed in a subsequent process. The second material layer 2M may be formed of a material having an etching selectivity different from that of the first material layer 1M. For example, each second material layer 2M may be formed of a nitride layer.

[0073] Reference Figure 4B , a first opening OP1 may be formed through the preliminary stack pSTK. The first opening OP1 may pass through the lower insulating layer UIL. The first opening OP1 may be formed in a contact region (eg, Figure 3A The first openings OP1 may expose the first transmission lines 1PL, respectively.

[0074] The plane of each first opening OP1 may have a circular or elliptical shape. Alternatively, the first opening OP1 may be formed to have various planar shapes other than the circular or elliptical shape.

[0075] Reference Figure 4C , the first openings OP1 may be filled with preliminary contact plugs pCT. The preliminary contact plugs pCT may fill the first openings OP1. The preliminary contact plugs pCT may respectively contact the first transmission lines 1PL. The height of the top surface of the preliminary contact plugs pCT may be the same as the height of the top surface of the preliminary stack body pSTK. The preliminary contact plugs pCT may include a conductive material (e.g., polysilicon).

[0076] Subsequently, a sacrificial stack sSTK may be formed on the preliminary stack pSTK. The sacrificial stack sSTK may include a third material layer 3M and a fourth material layer 4M. The third material layer 3M and the fourth material layer 4M may be alternately stacked along the Z direction. Each third material layer 3M may be formed of an insulating material. For example, each third material layer 3M may be formed of an oxide layer (e.g., a silicon oxide layer). The fourth material layer 4M may include polycrystalline silicon. In an embodiment, the length of the third material layer 3M and the fourth material layer 4M in the Z direction may correspond to the length of the first material layer 1M and the second material layer 2M in the Z direction.

[0077] Reference Figure 4D , a portion of the sacrificial stack sSTK may be removed, and then a stepped structure STS may be formed. The sacrificial stack sSTK may include a stepped structure STS. The stepped structure STS may include a plurality of steps. The steps of the stepped structure STS may respectively correspond to the preliminary contact plugs pCT. Each step of the stepped structure STS may overlap with any one of the preliminary contact plugs pCT. Each preliminary contact plug pCT may overlap with any one of the steps.

[0078] The stepped structure STS may have a positive step structure. Therefore, the length of the stepped structure STS in the X direction may increase from the top (e.g., the Z direction) to the bottom (e.g., the direction opposite to the Z direction). For example, the number of the third material layer 3M and the fourth material layer 4M stacked on the rightmost preliminary contact plug pCT among the preliminary contact plugs pCT may be greater than the number of the third material layer 3M and the fourth material layer 4M stacked on the remaining preliminary contact plugs pCT.

[0079] Reference Figure 4EA cover layer CV may be formed on the sacrificial stack sSTK. The cover layer CV may cover the step structure STS. The cover layer CV may cover the steps included in the step structure STS. The steps of the step structure STS may be covered by the cover layer CV.

[0080] Then, a preliminary second opening pOP2 may be formed through the cover layer CV. The preliminary second opening pOP2 may penetrate the cover layer CV to expose portions of the stepped structure STS. The preliminary second openings pOP2 may correspond to steps of the stepped structure STS, respectively. The preliminary second openings pOP2 may overlap with the first opening OP1. The preliminary second openings pOP2 may expose the top surfaces of the respective steps included in the stepped structure STS. Some of the preliminary second openings pOP2 may expose the top surfaces of corresponding preliminary contact plugs pCT.

[0081] Because the heights (eg, lengths in the Z direction) of the steps included in the stepped structure STS are different from each other, the respective depths of the preliminary second openings pOP2 may be different from each other. For example, the depth of the preliminary second openings pOP2 may decrease in the X direction.

[0082] Reference Figure 4F , as the corresponding depth of the preliminary second opening pOP2 increases, the second opening OP2 can be formed. Each bottom surface of the preliminary second opening pOP2 can be additionally etched, and then the second opening OP2 can be formed. For example, corresponding portions of the third material layer 3M and the fourth material layer 4M of the stepped structure STS can be etched through the preliminary second opening pOP2. In addition, corresponding portions of the preliminary contact plug pCT can be etched through the preliminary second opening pOP2.

[0083] The second openings OP2 may pass through each step of the stepped structure STS. At least some of the second openings OP2 may extend into the preliminary stack pSTK. The second openings OP2 may expose the side surfaces of the stepped structure STS and the side surfaces of the preliminary stack pSTK. The second openings OP2 may open at least a portion of the first openings OP1 at different depths. For example, at least one second opening OP2 may open a portion of a corresponding first opening OP1. That is, at least one first opening OP1 may include an area opened by the corresponding second opening OP2.

[0084] The second opening OP2 may have different depths. The bottom surface of the second opening OP2 may be located at different heights. For example, the depth of the second opening OP2 may decrease in the X direction.

[0085] A preliminary contact plug pCT′ may be provided below the second opening OP2. The lengths of the preliminary contact plugs pCT′ in the Z direction may be different from each other. The preliminary contact plugs pCT′ may have different heights. The top surfaces of the preliminary contact plugs pCT′ may correspond to the top surfaces of the second material layers 2M, respectively. The top surfaces of the preliminary contact plugs pCT′ may be located at the same height as the top surfaces of the second material layers 2M, respectively.

[0086] Reference Figure 4G , sacrificial pillars SP may be formed in the second openings OP2 , respectively. The sacrificial pillars SP may fill the second openings OP2 . The sacrificial pillars SP may include a material having an etching selectivity with respect to the first to fourth material layers 1M to 4M and the preliminary contact plugs pCT′.

[0087] Reference Figure 4H , third openings OP3 may be formed, each third opening OP3 exposing a portion of a corresponding first opening OP1 and a portion of a corresponding second opening OP2. The third opening OP3 may expose a first side of the corresponding first opening OP1 and a first side of the corresponding second opening OP2. Each third opening OP3 may have a semicircular or semi-elliptical plane. The third opening OP3 may expose a side surface of the corresponding first opening OP1 in the X direction and a side surface of the corresponding second opening OP2 in the X direction.

[0088] The third opening OP3 can be formed by removing corresponding portions of the sacrificial pillar SP and corresponding portions of the preliminary contact plug pCT′. A corresponding portion of the sacrificial pillar SP′ adjacent to the corresponding first side of the second opening OP2 (e.g., a semicircle or a semi-ellipse in the X direction) can be removed. Furthermore, a corresponding portion of the preliminary contact plug pCT′ adjacent to the corresponding first side of the first opening OP1 (e.g., a semicircle or a semi-ellipse in the X direction) can be removed. A corresponding portion of the preliminary contact plug pCT′ can be removed, thereby retaining the contact plug CT. That is, the portion remaining after etching the preliminary contact plug pCT′ while forming the third opening OP3 can be retained as the contact plug CT.

[0089] The side surface of the sacrificial pillar SP can be exposed through the corresponding left surface of the third opening OP3. In addition, the side surface of the contact plug CT can be exposed through the corresponding left surface of the third opening OP3. In addition, the side surfaces of the third material layer 3M and the fourth material layer 4M of the stepped structure STS can be exposed through the corresponding right surface of the third opening OP3. In addition, the side surfaces of the first material layer 1M and the second material layer 2M of the preliminary stacked body pSTK can be exposed through the corresponding right surface of the third opening OP3.

[0090] Reference Figure 4I, the sacrificial pillars SP′ may be removed. In order to selectively etch the sacrificial pillars SP′, an isotropic wet etching process may be performed.

[0091] Then, a preliminary gap-filling insulating layer pGIL may be formed on the contact plug CT. The preliminary gap-filling insulating layer pGIL may fill the space from which the sacrificial pillar SP' is removed. For example, the preliminary gap-filling insulating layer pGIL may fill Figure 4F Therefore, the depths of the preliminary gap-filling insulating layers pGIL may be different from each other. For example, the length of the preliminary gap-filling insulating layer pGIL in the Z direction may decrease in the X direction.

[0092] The preliminary gap-fill insulating layer pGIL may not protrude toward the side of the contact plug CT. Therefore, an air gap AG may be formed in the X direction of the contact plug CT. The air gap AG may contact the side surface of the contact plug CT in the X direction. The air gap AG may be surrounded by the contact plug CT, the preliminary gap-fill insulating layer pGIL, the first transmission line 1PL, and the preliminary stacked body pSTK.

[0093] The preliminary gap-fill insulating layer pGIL may include a material having poor step coverage. Therefore, the preliminary gap-fill insulating layer gGIL may not be formed in the air gap AG having a relatively small width.

[0094] Reference Figure 4J , a portion of the preliminary gap-filling insulating layer pGIL may be removed, thereby forming the fourth opening OP4. For example, a corresponding central portion of the preliminary gap-filling insulating layer pGIL may be removed. The partially removed preliminary gap-filling insulating layer pGIL may remain as the first gap-filling insulating layer GIL1. The first gap-filling insulating layer GIL1 may be disposed between the fourth opening OP4 and the sacrificial stack sSTK.

[0095] The fourth opening OP4 may have different depths. The depth of the fourth opening OP4 may correspond to the depth of the fourth opening OP4 as described above. Figure 4F That is, the fourth opening OP4 can be respectively Figure 4F The second opening OP2 has the same depth as the fourth opening OP4. The bottom surface of the fourth opening OP4 may correspond to the top surface of the contact plug CT. The bottom surface of the fourth opening OP4 may expose a corresponding portion of the top surface of the contact plug CT.

[0096] The air gap AG may be exposed through the fourth opening OP4. For example, Figure 4H The plane of the third opening OP3 shown Figure 4JThe planes of the fourth openings OP4 may partially overlap with each other. Therefore, the fourth openings OP4 may be respectively connected to the air gaps AG. In an embodiment, the fourth openings OP4 may be respectively connected to the air gaps AG to form corresponding continuous openings between the single air gaps and the single fourth openings that overlap with each other, as shown in FIG. Figure 4J shown.

[0097] The second material layer 2M of the preliminary stack pSTK may be exposed through the fourth opening OP4 , and portions of the second material layer 2M that are not covered by the first gap-filling insulating layer GIL1 or the contact plug CT may be exposed to the outside.

[0098] Reference Figure 4K , the portion of the second material layer 2M exposed by the fourth opening OP4 and the air gap AG can be removed. The exposed portion of the second material layer 2M can be removed, and then the recessed portion RC can be formed. As the corresponding portion of the second material layer 2M is removed, the remaining portion of the second material layer 2M can have an inverted step structure. For example, when the second material layer 2M is located in the lower portion, a larger area can be exposed to the outside through the fourth opening OP4 or the air gap AG. Therefore, the lower the second material layer 2M is positioned, the more of the second material layer 2M can be removed.

[0099] Reference Figure 4L , a second gap-filling insulating layer GIL2 may be formed in the fourth opening OP4, the air gap AG, and the recessed portion RC. The second gap-filling insulating layer GIL2 may fill the fourth opening OP4, the air gap AG, and the recessed portion RC. The second gap-filling insulating layer GIL2 may fill the air gap AG and the recessed portion RC through the fourth opening OP4. The second gap-filling insulating layer GIL2 may include a material having good step coverage. Therefore, the second gap-filling insulating layer GIL2 may be filled. Figure 4I The area (eg, the air gap AG) not filled by the preliminary gap-filling insulating layer pGIL is defined.

[0100] Reference Figure 4M The sacrificial laminate sSTK on the preliminary laminate pSTK may be removed. The third material layer 3M and the fourth material layer 4M stacked on the preliminary laminate pSTK may be removed. Furthermore, the stepped structure STS and the capping layer CV may be removed. Furthermore, portions of the first gap-filling insulating layer GIL1 and the second gap-filling insulating layer GIL2 may be removed.

[0101] Reference Figure 4N , the second material layer 2M can be replaced by the fifth material layer 5M. Figure 4K The fifth material layer 5M may correspond to Figures 3A to 3DThe first material layers 1M and the fifth material layers 5M alternately stacked may form a stacked body STK. The stacked body STK may include a fifth material layer 5M having an inverted step structure.

[0102] Figure 5A and Figure 5B is a diagram illustrating a conductive layer of a memory device according to an embodiment of the present disclosure. Figure 5A It is along Figure 3A A cross-sectional view taken along line AA′. Figure 5B It is along Figure 3A A cross-sectional view taken along line BB′. Figure 5A and Figure 5B , can briefly describe the above reference Figures 3A to 3D and Figures 4A to 4N The configuration has been described, or its description may be omitted.

[0103] As mentioned above Figure 4K Described, Figure 3C and Figure 3D The cross section of the second material layer 2M may be changed to: Figure 5A and Figure 5B cross section.

[0104] Reference Figure 5A , the side surface of the first contact plug CT1 in the X direction may protrude in the X direction beyond the side surface of the conductive layer CD corresponding to the drain select line DSL in the X direction. In addition, a dummy layer DML may be provided in the X direction of the conductive layer CD. The dummy layer DML may be located at the same height as the conductive layer CD. The dummy layer DML may include the same material as the conductive layer CD. The dummy layer DML may contact the second gap-filling insulating layer GIL2. The interface between the second gap-filling insulating layer GIL2 and the dummy layer DML may form a curved surface. For example, when Figure 4K The area where the second material layer 2M is removed is Figure 3C When tilted to the left (eg, in the direction opposite to the X direction), each having a shape such as Figure 5A The plane shown is a planar conductive layer CD and a dummy layer DML.

[0105] Reference Figure 5BThe side surface of the second contact plug CT2 in the X direction may protrude in the X direction beyond the side surface of the conductive layer CD corresponding to the word line WL in the X direction. Furthermore, a dummy layer DML may be provided in the X direction on the conductive layer CD. The first contact plug CT1 may contact any of the dummy layers DML. However, in embodiments, since the dummy layer DML is floating, even if the dummy layer DML contacts the first contact plug CT1, the dummy layer DML is unlikely to affect the operation of the memory device 100.

[0106] Figure 5A and Figure 5B The illustrated cross section may correspond to one example, and the conductive layer CD, the dummy layer DML, and the second gap-filling insulating layer GIL2 may have various planar shapes other than this example.

[0107] Figure 6 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0108] Reference Figure 6 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0109] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200, or may control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In an example, the controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0110] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. For example, the controller 3100 can communicate with an external device through at least one of the following various communication standards: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA) Protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe). For example, the connector 3300 can be defined according to at least one of the various communication standards mentioned above.

[0111] The memory device 3200 may include a plurality of memory cells and may be connected to Figure 1 The memory device 100 shown is constructed in the same manner.

[0112] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device, and then a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MicroMMC, or eMMC), an SD card (SD, MiniSD, MicroSD, or SDHC), or a Universal Flash Storage (UFS) may be formed.

[0113] Figure 7 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0114] Reference Figure 7 , an SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001 and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0115] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the received signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be defined according to at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), WiFi, Bluetooth, and non-volatile memory express (NVMe).

[0116] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Figure 1 The memory device 100 shown in FIG is constructed in the same manner. A plurality of memory devices 4221 to 422n can communicate with the controller 4210 through channels CH1 to CHn.

[0117] The auxiliary power supply 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply 4230 can be supplied with the power voltage from the host 4100 and can be charged. When the power supply from the host 4100 cannot be performed smoothly, the auxiliary power supply 4230 can provide the power voltage of the SSD 4200. For example, the auxiliary power supply 4230 can be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 can be located in the motherboard and can provide auxiliary power to the SSD 4200.

[0118] The buffer memory 4240 can be used as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n for a limited duration, or can store metadata (e.g., a mapping table) of the memory devices 4221 to 422n for a limited duration. The buffer memory 4240 can include volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, and low power DDR (LPDDR) SDRAM, or non-volatile memory such as ferroelectric RAM (FRAM), resistive RAM (ReRAM), spin transfer torque magnetic RAM (STT-MRAM), and phase change RAM (PRAM).

[0119] Various embodiments of the present disclosure may improve electrical efficiency for controlling a memory device by reducing line length in a contact region.

[0120] CROSS-REFERENCE TO RELATED APPLICATIONS

[0121] This application claims priority from Korean Patent Application No. 10-2024-0035747 filed on March 14, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a memory device, the method comprising the following steps: forming a stack including a first material layer and a second material layer on the lower structure; forming a first opening through the stack; filling the first openings respectively with preliminary contact plugs; forming a stepped structure on the stacked body, the stepped structure including steps corresponding to the preliminary contact plugs respectively; forming a second opening, the second opening passing through each step of the stepped structure and opening at least a portion of the first opening at different depths; exposing side surfaces of the second material layer by removing corresponding portions of the preliminary contact plugs adjacent to corresponding first sides of the first openings through the second openings; as well as A stacked body having an inverted step structure is formed by removing the exposed portion of the second material layer.

2. The method according to claim 1, further comprising the steps of: Before forming the laminate, The lower structure including transfer transistors and transfer lines respectively connected to the transfer transistors is formed.

3. The method according to claim 2, wherein: The step of forming the first opening comprises the following steps: The first openings are respectively formed to expose the transmission lines.

4. The method according to claim 1, wherein The step of forming the stepped structure comprises the following steps: forming a sacrificial laminate including a third material layer and a fourth material layer on the laminate; and The stepped structure having a positive step structure is formed by removing a portion of the sacrificial laminate.

5. The method according to claim 1, wherein The step of forming the second opening comprises the following steps: forming a covering layer covering the stepped structure; forming a preliminary second opening through the cover layer to expose a top surface of each step; and The stepped structure and the preliminary contact plug are etched through the preliminary second opening.

6. The method according to claim 1, wherein After forming the second opening, the preliminary contact plugs have different heights.

7. The method according to claim 1, wherein After forming the second opening, the respective top surfaces of the preliminary contact plugs are located at a height substantially flush with the respective top surfaces of the second material layer.

8. The method according to claim 1, wherein The step of exposing the side surface of the second material layer by removing the corresponding portion of the preliminary contact plug adjacent to the corresponding first side of the first opening through the second opening includes the following steps: filling the second opening with a corresponding sacrificial post; forming a third opening that opens a corresponding first side of the first opening and a corresponding first side of the second opening; and The side surface of the second material layer is exposed through the third opening.

9. The method according to claim 8, wherein The step of forming the third opening comprises the following steps: removing respective portions of the sacrificial posts adjacent to respective first sides of the second openings; and Respective portions of the preliminary contact plugs adjacent to respective first sides of the first openings are removed.

10. The method according to claim 8, wherein The step of forming the third opening comprises the following steps: Contact plugs are formed by removing corresponding portions of the preliminary contact plugs.

11. The method according to claim 10, further comprising the steps of: After exposing the side surface of the second material layer through the third opening, removing the sacrificial post; forming a preliminary gap-filling insulating layer on the contact plug to fill the second opening; as well as A fourth opening is formed by removing corresponding portions of the preliminary gap-filling insulating layer.

12. The method according to claim 11, wherein The step of forming the preliminary gap-filling insulating layer comprises the following steps: An air gap is formed in contact with a side surface of the contact plug.

13. The method according to claim 12, wherein: The step of forming the fourth opening comprises the following steps: The air gap is exposed through the fourth opening.

14. The method according to claim 11, wherein The step of forming the stacked body having the reverse step structure by removing the exposed portion of the second material layer comprises the following steps: The second material layer is removed through the fourth opening.

15. The method according to claim 1, further comprising the steps of: After forming a stacked body having the reverse step structure by removing the exposed portion of the second material layer, filling the region from which the exposed portion of the second material layer is removed with a gap-fill insulating layer; as well as The remaining portion of the second material layer is replaced with a fifth material layer.

16. A memory device, the memory device comprising: a lower structure comprising a pass transistor; a plurality of contact plugs, the plurality of contact plugs being respectively connected to the transfer transistors and extending in a first direction, the plurality of contact plugs having different lengths from one another; as well as a plurality of conductive layers, the plurality of conductive layers respectively contacting the plurality of contact plugs and being stacked in a manner spaced apart from each other in the first direction, the plurality of conductive layers having an inverted step structure, In which, a first conductive layer among the multiple conductive layers contacts a first contact plug among the multiple contact plugs, and the first conductive layer is penetrated by a gap-filling insulating layer arranged in the first direction, the gap-filling insulating layer extends from a second contact plug among the multiple contact plugs in the first direction, and the second contact plug is shorter than the first contact plug in the first direction.

17. The memory device according to claim 16, wherein: A top surface of the first contact plug is located at substantially the same height as a top surface of the first conductive layer.

18. The memory device according to claim 16, wherein: A side surface of the first contact plug contacts a side surface of the first conductive layer.

19. The memory device of claim 16, wherein: A second conductive layer among the plurality of conductive layers contacts the second contact plug and is located in a direction opposite to the first direction with respect to the first conductive layer.

20. The memory device of claim 19, wherein: The length of the second conductive layer in the second direction is smaller than the length of the first conductive layer in the second direction, and The second direction intersects the first direction.

21. The memory device of claim 16, wherein: A portion of the gap-fill insulation layer overlaps the second contact plug.

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