Multilayer spiral inductor structure and fabrication method based on RDL technology

Abstract

This invention relates to the fields of radio frequency integrated circuits and advanced semiconductor packaging technology, and particularly to a multilayer spiral inductor structure and its fabrication method based on RDL technology. The fabrication method includes seed layer deposition, photolithography and electroplating to form gradient linewidth coils, alternating dielectric layer deposition, via etching to form vertical interconnect copper pillars, photoresist sacrificial layer process to form air bridges, and silicon nitride passivation packaging. This invention effectively improves the self-resonant frequency bandwidth and reduces conductor and dielectric losses through a fan-shaped topology layout, synergistic optimization of dielectric materials, and three-dimensional interconnect structure design, achieving miniaturized integration and high reliability of high-frequency inductor components.

Description

Technical Field

[0001] This invention relates to the fields of radio frequency integrated circuits and advanced semiconductor packaging technology, and in particular to a multilayer spiral inductor structure based on RDL process and its fabrication method. Background Technology

[0002] Redistribution Layer (RDL) technology is a key technology for achieving high-density interconnects in semiconductor packaging. It involves forming a metal wiring layer on the chip surface through photolithography, electroplating, and etching, redistributing the original pad locations to a more suitable layout for package connections, thereby increasing package density and optimizing signal integrity. This process often uses copper as the conductive material, combined with a polymer dielectric layer to achieve multi-layer stacking. Multilayer spiral inductors are three-dimensional integrated passive components based on RDL technology, consisting of multiple concentric metal coils stacked vertically. They utilize magnetic flux coupling between adjacent layers to enhance the equivalent inductance. The inductance value is determined by the number of coil turns, linewidth, interlayer spacing, and dielectric constant. In high-frequency circuits, it can effectively reduce parasitic capacitance and improve the quality factor, making it suitable for scenarios with stringent miniaturization and high-frequency performance requirements, such as RF front-end modules. Together, these technologies achieve high-performance electromagnetic integration within a limited package space, driving the evolution of advanced packaging towards system-level functional integration.

[0003] Existing planar spiral inductors, when stacked in multiple layers, generate significant parasitic capacitance due to excessive interlayer overlap, reducing the applicable bandwidth of the self-resonant frequency. Conductor losses caused by the skin effect and proximity effect are particularly pronounced in the submillimeter-wave frequency band, while the dielectric loss of conventional dielectric materials further exacerbates energy dissipation. For example, in high-frequency operation, multilayer inductors fabricated using existing processes suffer from interlayer capacitive coupling leading to a shift in effective inductance, uneven current distribution causing a sharp increase in conductor impedance, and significant reduction in energy transfer efficiency due to polarization relaxation losses in the dielectric layers. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a multilayer spiral inductor structure and its fabrication method based on RDL technology. This solves the problems in high-frequency multilayer spiral inductor structures caused by excessive interlayer overlap area leading to parasitic capacitance coupling, skin effect and proximity effect resulting in conductor loss accumulation, and dielectric loss superposition caused by polarization relaxation of conventional dielectric materials. These problems result in limited bandwidth of the self-resonant frequency, a sharp increase in nonlinear conductor impedance, and deterioration of energy transfer efficiency.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] In a first aspect, the multilayer spiral inductor structure based on RDL technology provided by the present invention includes:

[0007] Vertically stacked copper coil layers, each layer adopts a fan-shaped topology layout, the radial overlap area between adjacent layers of copper coils is less than a preset threshold of the area of ​​a single layer of copper coils, and the arc length and spacing angle of the fan shape are optimized by an electromagnetic field simulation model to optimize the magnetic field distribution of the copper coil layers, so that the magnetic flux is concentrated in the central region of the coil.

[0008] Alternating deposition of low-loss dielectric layers, including a low-dielectric-constant polymer material layer filling the gaps between copper coils, and a low-loss inorganic dielectric layer covering the surface of the copper coils and serving as a mechanical support layer.

[0009] An air bridge interconnection structure is located at the connection node between the top layer copper coil and the lower layer copper coil. It is a suspended electroplated copper bridge that spans the adjacent layers of copper coil. The pier part of the air bridge is supported by electroplated copper pillars, and the bridge body is suspended and formed by photoresist sacrificial layer process.

[0010] The copper coil layer has a submicron linewidth, with the linewidth decreasing radially. This gradient decrease is achieved through a critical size compensation algorithm in the photolithography process, and the copper coil edges are chamfered to suppress the high-frequency current edge-gathering effect.

[0011] A passivation encapsulation layer, covering the surface of the multilayer spiral inductor structure, is made of silicon nitride.

[0012] Secondly, the method for fabricating a multilayer spiral inductor structure based on RDL technology provided by the present invention, applied to the multilayer spiral inductor structure based on RDL technology, includes the following steps:

[0013] A titanium or copper composite seed layer is formed on a silicon substrate or an organic packaging substrate by physical vapor deposition.

[0014] The first fan-shaped copper coil pattern is defined on the seed layer by photolithography, and the opening area of ​​the photoresist is filled by electroplated copper to form a copper coil layer with controllable thickness, and the line width accuracy is controlled within ±0.1μm.

[0015] A low dielectric constant polymer dielectric is spin-coated onto the surface of the copper coil layer and cured, followed by the growth of a low-loss inorganic dielectric layer by plasma-enhanced chemical vapor deposition.

[0016] A through-hole is formed in the low-loss inorganic dielectric layer using a dry etching process to expose the connection end of the underlying copper coil.

[0017] A vertical interconnect channel is formed by electroplating copper pillars at the through-hole location. The photolithography process is repeated to define the pattern, electroplating copper filler, and dielectric layer deposition steps. Fan-shaped copper coil layers are stacked layer by layer, wherein the fan-shaped angle and radius of each copper coil layer are increased according to the preset gradient optimized by the electromagnetic field simulation model.

[0018] Photoresist is spin-coated at the top copper coil connection node as a sacrificial layer. After photolithography defines the air bridge body pattern, copper is electroplated to form the bridge body. The sacrificial layer is removed by wet etching to form the suspended air bridge structure.

[0019] Copper is electroplated at the end of the top copper coil to form an external connection electrode. The surface is planarized by chemical mechanical polishing, and a silicon nitride passivation layer is deposited to cover the entire structure.

[0020] Furthermore, in the method for fabricating a multilayer spiral inductor structure based on RDL process described in this invention, the low dielectric constant polymer material layer is a polyimide layer, and the low loss inorganic dielectric layer is a silicon dioxide layer. In the alternating deposition step, the thickness of the polymer dielectric layer is 1-5 μm, and the thickness of the inorganic dielectric layer is 0.5-2 μm.

[0021] Furthermore, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the radial overlap area of ​​the fan-shaped copper coil layer is formed by adjusting the decreasing ratio of the arc length of the adjacent fan-shaped layers, and the decreasing ratio of the arc length of each layer is adjusted by a preset gradient.

[0022] Furthermore, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the submicron-level linewidth copper coil layer achieves a radial gradient decrease in linewidth through a critical size compensation algorithm in photolithography, with a gradient decrease rate of 0.05-0.1 μm reduction in linewidth per turn.

[0023] Furthermore, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the pier portion of the air bridge structure is supported by electroplated copper pillars, the height of which is 5-10 μm and the diameter of which is 3-5 μm.

[0024] Furthermore, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the copper pillars of the vertical interconnect channel and the connection ends of the adjacent copper coils are formed into an integral structure through a copper electroplating process. The diameter of the copper pillars is 2-4 μm and the height is 3-6 μm.

[0025] Beneficial effects of this invention;

[0026] This invention utilizes a vertically stacked fan-shaped topology of copper coil layers and a radially gradient decreasing linewidth design. Combined with an electromagnetic field simulation model, it optimizes the overlap area and magnetic field distribution of adjacent layers, significantly reducing interlayer parasitic capacitance coupling and broadening the applicable bandwidth of the self-resonant frequency. Alternating deposition of low-dielectric-constant polymer dielectric layers and low-loss inorganic dielectric layers synergistically suppresses polarization relaxation loss, reducing energy transfer efficiency degradation. The submicron-level linewidth chamfered edge structure disperses the high-frequency current density distribution, suppressing conductor loss accumulation caused by skin and proximity effects. The air-bridge interconnect structure, through a suspended bridge body and integrated electroplated copper pillar design, reduces parasitic capacitance and improves conductivity stability. Combined with the encapsulation protection of a silicon nitride passivation layer, it ultimately achieves miniaturized integration, low-loss transmission, and high reliability of high-frequency inductor components, meeting the performance requirements of RF integrated circuits for high-frequency passive components. Attached Figure Description

[0027] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0028] Figure 1 A flowchart illustrating the fabrication method of a multilayer spiral inductor structure based on RDL technology provided in this embodiment of the invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions provided by various embodiments of this invention will be described in detail below with reference to the accompanying drawings. To better understand the objectives of this invention, it will be described in further detail below.

[0030] In a first aspect, the multilayer spiral inductor structure based on RDL technology provided by the present invention includes:

[0031] Vertically stacked copper coil layers, each layer adopts a fan-shaped topology layout, the radial overlap area between adjacent layers of copper coils is less than a preset threshold of the area of ​​a single layer of copper coils, and the arc length and spacing angle of the fan shape are optimized by an electromagnetic field simulation model to optimize the magnetic field distribution of the copper coil layers, so that the magnetic flux is concentrated in the central region of the coil.

[0032] Alternating deposition of low-loss dielectric layers, including a low-dielectric-constant polymer material layer filling the gaps between copper coils, and a low-loss inorganic dielectric layer covering the surface of the copper coils and serving as a mechanical support layer.

[0033] An air bridge interconnection structure is located at the connection node between the top layer copper coil and the lower layer copper coil. It is a suspended electroplated copper bridge that spans the adjacent layers of copper coil. The pier part of the air bridge is supported by electroplated copper pillars, and the bridge body is suspended and formed by photoresist sacrificial layer process.

[0034] The copper coil layer has a submicron linewidth, with the linewidth decreasing radially. This gradient decrease is achieved through a critical size compensation algorithm in the photolithography process, and the copper coil edges are chamfered to suppress the high-frequency current edge-gathering effect.

[0035] A passivation encapsulation layer, covering the surface of the multilayer spiral inductor structure, is made of silicon nitride.

[0036] In the multilayer spiral inductor structure based on RDL technology, the vertically stacked copper coil layers adopt a fan-shaped topology. The radial overlap area between adjacent copper coil layers is optimized by adjusting the geometric parameters of the fan-shaped arc length and spacing angle to achieve interlayer magnetic flux coupling. An electromagnetic field simulation model analyzes the magnetic field distribution characteristics by setting different combinations of fan-shaped arc lengths and spacing angles, and selects a configuration scheme where the magnetic flux is concentrated in the central region of the coil. This scheme can reduce parasitic capacitive coupling between adjacent coil layers and reduce energy loss during high-frequency signal transmission.

[0037] Alternating layers of low-dielectric-constant polymer material and low-loss inorganic dielectric material are deposited between copper coil layers. The polymer material layer fills the gaps between the copper coils using a spin-coating process, and after curing, forms a uniform insulating layer, reducing dielectric loss. The inorganic dielectric layer covers the surface of the copper coils using plasma-enhanced chemical vapor deposition, enhancing the mechanical stability of the structure while avoiding the risk of delamination due to differences in thermal expansion coefficients. The alternating stacking of these two types of dielectric layers balances dielectric performance and mechanical support requirements.

[0038] The air-bridge interconnect structure is located at the connection node between the top and bottom copper coils, and the suspended electroplated copper bridge is formed using a photoresist sacrificial layer process. The electroplated copper pillars serve as the bridge pier support structure, and their location and number are designed based on the distribution density of the bridging nodes. After electroplating, the photoresist sacrificial layer is selectively removed by wet etching to form the suspended bridge body, reducing parasitic capacitance between the bridge body and the dielectric layer, and improving high-frequency signal transmission efficiency.

[0039] The copper coil layer employs a submicron-level linewidth design, with the linewidth decreasing radially. A critical size compensation algorithm is introduced into the photolithography process to compensate for linewidth deviations during photoresist exposure and development by adjusting the mask pattern size, achieving precise control of the gradient linewidth. The edges of the copper coil are chamfered using dry etching to smooth the conductor surface morphology, suppress the accumulation effect of high-frequency current at the conductor edges, and reduce additional losses caused by the skin effect.

[0040] The passivation encapsulation layer is formed on the surface of the multilayer spiral inductor structure using a chemical vapor deposition process, creating a silicon nitride protective layer. This silicon nitride layer covers the copper coil and dielectric layer surfaces, preventing the intrusion of environmental moisture and contaminants while providing mechanical protection. The encapsulation layer thickness must meet insulation withstand voltage requirements, and the surface must be planarized after a chemical mechanical polishing process to facilitate interconnection and integration with other components in subsequent encapsulation steps.

[0041] The above steps, through the collaborative design of dielectric layer deposition, patterning processes, and interconnect structures, achieve the three-dimensional integration of multilayer spiral inductors. The combination of fan-shaped topology and gradient linewidth optimizes the magnetic field distribution and current path, while the low-loss dielectric layer and air-bridge interconnects reduce parasitic effects, ultimately improving the high-frequency performance and reliability of the inductor within a limited package space.

[0042] Secondly, please refer to Figure 1 The method for fabricating a multilayer spiral inductor structure based on RDL technology provided by this invention, applied to the multilayer spiral inductor structure based on RDL technology, includes the following steps:

[0043] Step 1: Form a titanium or copper composite seed layer on a silicon substrate or organic packaging substrate by physical vapor deposition.

[0044] Step 2: Define the first fan-shaped copper coil pattern on the seed layer using photolithography, and fill the photoresist opening area with electroplated copper to form a copper coil layer with controllable thickness, with linewidth accuracy controlled within ±0.1μm;

[0045] Step 3: Spin-coat a low dielectric constant polymer dielectric onto the surface of the copper coil layer and cure it, then grow a low-loss inorganic dielectric layer by plasma-enhanced chemical vapor deposition;

[0046] Step 4: A through-hole is formed in the low-loss inorganic dielectric layer using a dry etching process to expose the connection end of the lower copper coil.

[0047] Step 5: Electroplat copper pillars are formed at the via locations to create vertical interconnect channels. The photolithography process is repeated to define the pattern, electroplat copper filling, and dielectric layer deposition steps. Fan-shaped copper coil layers are stacked layer by layer, wherein the fan-shaped angle and radius of each copper coil layer are increased according to the preset gradient optimized by the electromagnetic field simulation model.

[0048] Step 6: Spin-coat photoresist as a sacrificial layer at the top copper coil connection node, photolithographically define the air bridge body pattern, electroplat copper to form the bridge body, remove the sacrificial layer by wet etching, and form the suspended air bridge structure.

[0049] Step 7: Electroplat copper at the end of the top copper coil to form an external connection electrode, planarize the surface by chemical mechanical polishing, and deposit a silicon nitride passivation layer to cover the entire structure.

[0050] In the fabrication method of multilayer spiral inductor structures based on RDL technology, a titanium or copper composite seed layer is first formed on a silicon substrate or organic packaging substrate using physical vapor deposition (PVD). The seed layer serves as the conductive substrate for copper electroplating, and its material selection must consider both adhesion to the substrate and compatibility with the electroplating process. PVD forms a uniform thin film through sputtering or evaporation, providing the initial interface for the subsequent patterned copper coil layer electrochemical reaction.

[0051] The photolithography process defines the first fan-shaped copper coil pattern on the seed layer surface. An opening region is formed through spin-coating photoresist, mask alignment, exposure, and development. Copper is then electroplated to fill the opening region. During electroplating, the copper layer thickness is controlled by adjusting the current density and time, ensuring a linewidth accuracy within ±0.1 μm. This step achieves precise patterning of the copper coil, laying the foundation for multilayer stacking.

[0052] A low-dielectric-constant polymer dielectric is spin-coated onto the surface of the copper coil layer and then cured. The polymer material fills the gaps between the copper coils using a spin-coating process, forming a continuous insulating layer after curing, reducing capacitive coupling between the coils. Subsequently, a low-loss inorganic dielectric layer is grown on the surface of the polymer layer using plasma-enhanced chemical vapor deposition. The inorganic dielectric layer covers the surface of the copper coil, providing mechanical support and reducing interlayer deformation caused by thermal stress, while maintaining low dielectric loss characteristics.

[0053] Dry etching creates vias in an inorganic dielectric layer, exposing the connection terminals of the underlying copper coils. Dry etching utilizes reactive ion etching (RIE) technology to achieve high aspect ratio via structures, precisely controlling the etching endpoint to avoid damage to the underlying copper coils. The location and size of the vias must match the interconnect nodes optimized by the electromagnetic field simulation model to ensure the conductive continuity of the vertical interconnect channels.

[0054] Electroplated copper pillars within the through-holes form vertical interconnect channels, and the copper pillars and the underlying copper coils are integrated into a single structure through electroplating. Photolithography, electroplating, and dielectric deposition steps are repeated layer by layer to stack fan-shaped copper coil layers. The fan-shaped angle and radius of each copper coil layer increase according to a preset gradient, which is optimized based on an electromagnetic field simulation model to concentrate magnetic flux distribution and reduce eddy current losses between adjacent layers.

[0055] Photoresist is spin-coated at the connection nodes of the top copper coil as a sacrificial layer. After photolithography defines the air bridge pattern, copper is electroplated to form the bridge body. After wet etching removes the sacrificial layer, the suspended electroplated copper bridge bridges connect adjacent copper coil layers, with the bridge piers supported by electroplated copper pillars. The air bridge structure reduces the contact area between the bridge body and the dielectric layer, thereby reducing the impact of parasitic capacitance on high-frequency signal transmission.

[0056] The top-layer copper coil ends are electroplated with copper to form external connection electrodes. The surface is planarized using a chemical mechanical polishing process to eliminate interlayer height differences. A silicon nitride passivation layer covers the entire structure via chemical vapor deposition, providing moisture and mechanical protection while maintaining surface insulation properties. The passivation layer thickness must meet packaging process requirements to avoid introducing short-circuit risks in subsequent interconnection processes.

[0057] The above steps, including seed layer preparation, patterned electroplating, alternating dielectric layer deposition, and interconnect structure optimization, achieve three-dimensional integration of multilayer spiral inductors. The gradient layout of the fan-shaped copper coils and the low-loss dielectric layer synergistically reduce parasitic effects, while the air-bridge interconnect structure improves high-frequency performance, ultimately meeting the requirements of RF integrated circuits for miniaturization and high-frequency response characteristics.

[0058] Specifically, in the method for fabricating a multilayer spiral inductor structure based on RDL process described in this invention, the low dielectric constant polymer material layer is a polyimide layer, and the low loss inorganic dielectric layer is a silicon dioxide layer. In the alternating deposition step, the thickness of the polymer dielectric layer is 1-5 μm, and the thickness of the inorganic dielectric layer is 0.5-2 μm.

[0059] The low dielectric constant polymer material layer is a polyimide layer, which is used to cover the surface of the copper coil and fill the coil gaps via spin coating. After spin coating with a spin coater, the polyimide precursor solution is cured using a stepped temperature increase to form a dense insulating layer. The curing temperature and time are set according to the thermal decomposition characteristics of polyimide to avoid carbonization caused by high temperatures. The thickness of this layer is controlled within the range of 1-5 μm; too thin a layer may lead to insulation breakdown, while too thick a layer increases dielectric loss and affects the accuracy of subsequent patterning.

[0060] The low-loss inorganic dielectric layer is a silicon dioxide layer, grown on the surface of the polyimide layer using plasma-enhanced chemical vapor deposition (PECVD). During silicon dioxide deposition, the reactive gas is ionized under a radio frequency electric field to form plasma, which promotes a chemical reaction between the silicon and oxygen sources on the substrate surface to form a film. The deposition rate and reactive gas pressure are synergistically regulated to keep the silicon dioxide layer thickness stable between 0.5-2 μm. If it is too thin, the mechanical support is insufficient; if it is too thick, additional stress is introduced, leading to interlayer cracking.

[0061] When polyimide and silica layers are deposited alternately, the polymer dielectric preferentially fills the sidewall gaps of the copper coil, reducing capacitive coupling between coils. The silica layer then covers the polyimide surface, using its high Young's modulus to suppress thermal expansion deformation of the copper coil and reduce the risk of interlayer misalignment. The thickness ratio of the two dielectric layers is adjusted based on the parasitic capacitance optimization results from the electromagnetic field simulation model to achieve a balance between the overall dielectric constant and mechanical strength.

[0062] In the alternating deposition process, the spin-coating step of the polyimide layer must be performed in a clean environment to avoid particulate contamination leading to defects in the dielectric layer. After deposition, the silica layer requires annealing to eliminate dangling bond defects introduced by the plasma process and improve the insulation reliability of the dielectric layer. The annealing temperature is lower than the glass transition temperature of the polyimide to prevent thermal degradation of the polymer layer.

[0063] The above steps achieve a synergistic effect of low dielectric constant and low loss dielectric by matching material properties and process parameters. The polyimide layer reduces parasitic capacitance between coils, while the silicon dioxide layer enhances structural rigidity. The alternating stacking of these two layers provides support for the high-frequency performance and long-term reliability of the multilayer spiral inductor, meeting the technical requirements of RF integrated circuit packaging for three-dimensional integrated passive components.

[0064] Specifically, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the radial overlap area of ​​the fan-shaped copper coil layer is formed by adjusting the decreasing ratio of the arc length of the adjacent fan-shaped layers, and the decreasing ratio of the arc length of each layer is adjusted by a preset gradient.

[0065] The radial overlap area of ​​the sector-shaped copper coil layers is achieved by adjusting the decreasing ratio of the sector arc length of adjacent layers. The sector arc length of adjacent copper coil layers decreases layer by layer according to the preset gradient parameters output by the electromagnetic field simulation model, and the decreasing ratio is related to the number of coil layers and the target inductance. The specific value of the arc length decreasing ratio is determined by the balance between the magnetic field distribution characteristics and the parasitic capacitance coupling strength in the electromagnetic field simulation model, in order to optimize the concentration of magnetic flux in the central region of the coil and suppress interlayer electric field coupling.

[0066] In photolithography, the geometric parameters of the arc length of each fan-shaped section of the mask pattern are adjusted according to a preset gradient. By modifying the central angle and radius parameters of the fan-shaped openings in the mask, the decreasing ratio of the arc length of the electroplated copper coils is controlled. The central angle of the fan-shaped openings of adjacent copper coil layers gradually decreases, while the radius increases according to the gradient, forming a spirally expanding coil layout. This layout reduces the area of ​​the radial overlap region between adjacent coil layers, thereby reducing the interference of interlayer capacitance on high-frequency signal transmission.

[0067] The electromagnetic field simulation model uses preset gradient parameters as input variables to analyze the axial distribution of the magnetic field and eddy current loss characteristics under different arc length reduction ratios. Simulation results select the arc length reduction scheme that maximizes the magnetic flux density in the central region, while constraining the overlapping area to be lower than a preset threshold of the area of ​​a single-layer copper coil. This threshold is dynamically adjusted based on the resistivity of the coil material and the operating frequency range to avoid additional losses caused by the high-frequency skin effect.

[0068] During the layer-by-layer stacking process, the fan-shaped arc length reduction ratio of each copper coil layer is designed in conjunction with the dielectric layer thickness. The thickness of the low-dielectric-constant polymer dielectric layer varies with the arc length reduction ratio to compensate for the electric field distribution distortion caused by the reduction in overlap area. The inorganic dielectric layer, acting as a mechanical support layer, has a thickness that matches the linewidth gradient reduction rate of the copper coils, maintaining the uniformity of interlayer stress distribution.

[0069] The above steps, through photolithography mask design, electromagnetic field simulation optimization, and coordinated adjustment of dielectric layer parameters, achieve gradient stacking of fan-shaped copper coil layers. Precise control of the arc length reduction ratio and overlap area reduces parasitic capacitance and eddy current losses while maintaining inductance stability, meeting the integration requirements of RF integrated circuits for high-frequency passive components.

[0070] Specifically, in the multilayer spiral inductor structure fabrication method based on RDL process described in this invention, the submicron-level linewidth copper coil layer achieves radial gradient reduction of linewidth through a critical size compensation algorithm of photolithography process, with a gradient reduction rate of 0.05-0.1 μm reduction in linewidth per turn.

[0071] The submicron-level linewidth copper coil layer achieves radial gradient reduction of linewidth through a critical size compensation algorithm in the photolithography process. This algorithm, based on the optical proximity effect correction requirements during photoresist exposure, performs reverse pre-compensation design on the mask pattern dimensions. The linewidth geometry parameters of the fan-shaped copper coils on the mask are preset to decrease according to their radial position; each coil's linewidth is reduced in a gradient of 0.05-0.1 μm during the mask design stage to compensate for the actual shrinkage deviation of the linewidth after development.

[0072] In photolithography, the mask pattern is converted into a photoresist exposure pattern by setting linewidth compensation values ​​for different regions. The exposure equipment dynamically adjusts the exposure dose or focus depth according to the radial position, so that the opening width of the developed photoresist precisely matches the preset gradient. The trapezoidal sidewalls formed after photoresist development are transferred to the lower seed layer through a dry etching process, forming a copper coil electroplating substrate with gradient linewidth characteristics.

[0073] During the copper plating process, the plating solution deposits a copper layer on the seed layer surface through the photoresist opening area. The gradient linewidth structure leads to differences in current density distribution at different radial locations. By adjusting the plating time and current parameters, the uniformity of the copper layer thickness is controlled within the process window. The chamfering design of the copper coil edge is achieved through a dry etching process. The etching gas performs anisotropic etching on the copper surface, forming a smooth transition conductor edge profile and reducing the accumulation of high-frequency current at the conductor edge.

[0074] The gradient reduction rate is set based on the optimization results of the skin depth and current density distribution from the electromagnetic field simulation model. A gradient range of 0.05-0.1 μm reduction in linewidth per turn balances the relationship between conductor cross-sectional area and high-frequency loss. The linewidth reduction rate and the fan-shaped arc length reduction ratio are adjusted in tandem, resulting in a spiral distribution of sparse outer layers and dense inner layers in the copper coil, optimizing magnetic field coupling efficiency while reducing eddy current interference between adjacent layers.

[0075] The above steps, through mask compensation design, dynamic adjustment of photolithography process parameters, and coordinated control of electroplating and etching, achieve precise forming of submicron-level gradient linewidth copper coils. The combination of decreasing linewidth gradient and chamfered structure effectively suppresses the high-frequency current convergence effect, improves the inductance quality factor, and meets the technical requirements of RF integrated circuits for miniaturization and high-performance integration of high-frequency passive components.

[0076] Specifically, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the pier portion of the air bridge structure is supported by electroplated copper pillars, with the height of the electroplated copper pillars being 5-10 μm and the diameter being 3-5 μm.

[0077] The piers of the air bridge structure are supported by electroplated copper pillars. The height of these pillars is designed to be 5-10 μm, and the diameter is controlled within the range of 3-5 μm. The electroplated copper pillars are formed through a through-hole photolithography and electroplating process. The location of the through-holes is determined based on the optimized connection node distribution according to an electromagnetic field simulation model. After the through-hole pattern is defined by a photoresist mask, the electroplated copper grows vertically within the through-holes. Its height is precisely controlled by coordinating the electroplating time and current density, while the diameter is limited by the through-hole opening size. This size range balances the requirements of mechanical support strength and minimizing parasitic capacitance; excessively tall copper pillars can easily introduce stress concentration, while excessively small diameters may reduce conductivity stability.

[0078] A photoresist sacrificial layer process is used to create the suspended structure of the air bridge. Photoresist is spin-coated as a sacrificial layer at the connection nodes of the top-layer copper coils, and the patterned areas of the bridge body are defined by exposure using a mask. Electroplated copper is deposited on the surface of the sacrificial layer to form the bridge structure. The electroplating parameters must match the process conditions of the copper columns of the piers to avoid gaps or cracks at the interface between the bridge body and the piers. After the photoresist sacrificial layer is selectively removed by a wet etching process, the bridge body is connected to the lower-layer copper coils only through the copper columns of the piers, forming a suspended interconnect structure. The composition and time of the etching solution must be precisely controlled to prevent over-etching and damage to the copper bridge or dielectric layer.

[0079] The connection between the electroplated copper pillar and the adjacent copper coil layer is formed through an integrated electroplating process. During the through-hole electroplating stage, the bottom of the copper pillar is in direct contact with the surface of the lower copper coil. Copper ions are uniformly deposited on the seed layer surface during electroplating, forming a metallurgical bond without interface defects. The top of the copper pillar and the bridge body are continuously deposited through the same electroplating step, reducing contact resistance and improving interconnect reliability. The ratio of the copper pillar's diameter to its height must be coordinated with the linewidth gradient decrease rate of the fan-shaped copper coil to avoid uneven interlayer stress distribution due to dimensional mismatch.

[0080] The above steps, through the synergistic process of through-hole photolithography, electroplating parameter optimization, and sacrificial layer etching, achieve reliable molding of the air bridge structure. The size design of the pier copper columns and the integrated electroplating process ensure the stability of mechanical support and electrical connection. The suspended bridge structure improves high-frequency signal transmission efficiency by reducing parasitic capacitance, meeting the low-loss and high-integration requirements of RF integrated circuit packaging for three-dimensional interconnect structures.

[0081] Specifically, in the method for fabricating a multilayer spiral inductor structure based on RDL technology described in this invention, the copper pillars of the vertical interconnect channel and the connection ends of the copper coils of the adjacent layers are formed into an integral structure through a copper electroplating process. The diameter of the copper pillars is 2-4 μm and the height is 3-6 μm.

[0082] The copper pillars of the vertical interconnect channel are integrated with the connection points of the adjacent copper coil layers through copper electroplating. The diameter of the copper pillars is designed to be 2-4 μm, and the height is controlled within the range of 3-6 μm. The via etching process forms vertical channels in a low-loss inorganic dielectric layer. The etching endpoint is precisely determined using optical endpoint detection technology to avoid damaging the surface of the underlying copper coil. The sidewall morphology of the vias must maintain perpendicularity to accommodate subsequent electroplating processes. The gas ratio and RF power parameters for reactive ion etching are optimized based on the characteristics of the dielectric layer material.

[0083] In the copper electroplating process, a seed layer on the inner wall of the through-hole is covered by physical vapor deposition, serving as a conductive substrate for copper ion deposition. The electroplating solution fills the through-hole through diffusion and electric field drive, with current density and electroplating time being synergistically adjusted to ensure the height and diameter of the copper pillar reach a preset range. At low current densities, the copper deposition rate slows down, which is beneficial for filling high aspect ratio through-holes and reducing void defects. The connection point between the top of the copper pillar and the adjacent copper coil layer forms a continuous metallurgical interface, eliminating abrupt changes in contact resistance.

[0084] The ratio of the copper pillar's diameter to its height must match the linewidth gradient descent rate of the sector-shaped copper coil. An excessively small diameter may lead to concentrated current density and electromigration risks, while an excessively large diameter increases interlayer capacitive coupling. The ratio of the copper pillar's height to the dielectric layer thickness is optimized using an electromagnetic field simulation model to balance the conductivity of the vertical interconnect with the interlayer insulation requirements. The top surface of the copper pillar is planarized using a chemical mechanical polishing process to eliminate microscopic protrusions on the electroplated surface, providing a flat substrate for the patterning of the upper copper coil.

[0085] An integrated electroplating process enables seamless connection between the copper pillars and adjacent copper coil layers. During electroplating, copper ions are uniformly nucleated on the surface of the seed layer, grow vertically along the sidewalls of the vias, and ultimately form a conformal coverage with the seed layer of the upper copper coil. The interface between the copper pillars and the connection ends eliminates grain boundary defects through the natural extensibility of the electroplating process, improving the mechanical strength of the interconnect structure and the stability of high-frequency signal transmission.

[0086] The above steps, through through-hole etching precision control, electroplating parameter optimization, and integrated interface design, achieve low resistance and high reliability of the vertical interconnect channel. The coordinated matching of copper pillar dimensions and process parameters reduces the risks of parasitic capacitance and electromigration, providing structural support for the high-frequency performance and three-dimensional integration of the multilayer spiral inductor, and meeting the technical requirements of semiconductor packaging processes for miniaturized interconnect components.

[0087] This invention utilizes a vertically stacked, fan-shaped topology design for copper coil layers to control the radial overlap area of ​​adjacent layers to below a preset threshold for single-layer area. The fan-shaped arc length and spacing angle are optimized based on an electromagnetic field simulation model, concentrating the magnetic field distribution in the central region of the coils and reducing interlayer electric field coupling paths. The fan-shaped arc length of adjacent layers decreases according to a preset gradient, combined with a spiral expansion layout with increasing radius, effectively reducing the edge field strength in the interlayer overlap region and suppressing the limitation of self-resonant frequency bandwidth by parasitic capacitance.

[0088] Alternating deposition of low-dielectric-constant polymer dielectric layers and low-loss inorganic dielectric layers synergistically optimizes dielectric properties. A polyimide layer fills the gaps between copper coils, reducing inter-coil capacitive coupling through its low dielectric constant; a silicon dioxide layer covers the surface of the copper coils, providing mechanical support and reducing polarization relaxation losses. The dielectric layer thickness ratio is dynamically adjusted based on parasitic capacitance optimization results from an electromagnetic field simulation model, balancing dielectric constant and thermal stress distribution to suppress degradation of energy transfer efficiency.

[0089] The submicron-level linewidth copper coil layer employs a radial gradient decreasing design, achieving precise linewidth control through a critical size compensation algorithm in photolithography. The chamfered edges of the copper coils smooth the conductor surface morphology, dispersing high-frequency current density distribution and reducing conductor loss accumulation caused by skin and proximity effects. The air-bridge interconnect structure bridges adjacent copper coil layers with suspended electroplated copper bridges. The integrated electroplating process of the bridge piers and vertical interconnect channels reduces contact resistance, and the suspended bridge design reduces parasitic capacitance, ultimately improving high-frequency signal transmission efficiency and inductance quality factor.

Claims

1. A multilayer spiral inductor structure based on RDL process, characterized in that, The application relates to a vertical stacked copper coil layer, each copper coil layer adopts a fan-shaped topology layout, the radial overlapping area of copper coils between adjacent layers is less than a preset threshold of the area of a single-layer copper coil, and the fan-shaped arc length and interval angle optimize the magnetic field distribution of the copper coil layer through an electromagnetic field simulation model, so that the magnetic flux is concentrated in the central area of the coil. The application relates to an air bridge interconnection structure, which is located at the connecting node of the top copper coil and the lower copper coil, is bridged by a suspended electroplated copper bridge between adjacent copper coils, the pier part of the air bridge is supported by an electroplated copper column, and the bridge body is suspended and formed through a photoresist sacrificial layer process. The application relates to a submicron-level copper coil layer, the line width of which is radially gradiently decreased, the gradiently decreasing is realized through a critical dimension compensation algorithm of a photoetching process, and the edge of the copper coil adopts a chamfer design to inhibit the edge effect of high-frequency current. The application relates to a passivation packaging layer which covers the surface of the multilayer spiral inductor structure and is composed of silicon nitride material. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure.

2. The method for preparing a multilayer spiral inductor structure based on RDL process, applied to the multilayer spiral inductor structure based on RDL process as claimed in claim 1, characterized in that, The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure.

3. The method for fabricating a multilayer spiral inductor structure based on RDL technology according to claim 2, characterized in that: The application relates to a method for manufacturing a multilayer spiral inductor structure.

4. The method for fabricating a multilayer spiral inductor structure based on RDL technology according to claim 2, characterized in that: The application relates to a method for manufacturing a multilayer spiral inductor structure.

5. The method of claim 2, wherein the RDL process based multilayer spiral inductor structure fabrication method is characterized by: The application relates to a method for manufacturing a multilayer spiral inductor structure.

6. The method of claim 2, wherein the RDL process based multilayer spiral inductor structure fabrication method is characterized by: The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. The application relates to a method for manufacturing a multilayer spiral inductor structure. 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