Preparation method of SiC bipolar junction transistor

Abstract

The invention discloses a preparation method of a SiC bipolar junction transistor. The preparation method comprises the following steps: 1) using a pre-grown epitaxial layer as a base contact layer of the transistor; aligning the emitter region with the base contact layer using an emitter ohmic metal as a self-alignment mask, where the emitter ohmic metal is a plurality of metals, including a single metal composition selected from titanium, nickel, aluminum, gold or platinum, or a multi-metal stack, the single metal composition being directly deposited on the semiconductor surface; the multi-metal stack consists of at least two metals selected from titanium, nickel, aluminum, gold or platinum, tungsten and alloys thereof; 2) aligning the edge of the base metal layer with the etching process of the collector region by using the base metal layer as a self-alignment guide; an active region of the device is aligned with a collector metal edge through a self-alignment method, so that accurate space definition of a functional region is ensured; wherein the substrate is a semi-insulating 4H silicon carbide substrate, the high resistivity of the substrate is greater than 1e6 ohm * cm, the substrate is suitable for radio frequency application, and the substrate is subjected to homoepitaxial growth on the substrate at an axial deviation angle of 4 degrees.

Description

Technical Field

[0001] The present invention relates to a bipolar junction transistor (BJT) and a method for manufacturing the same, in particular to self-alignment of emitter and base contacts, especially a bipolar junction transistor (BJT) made of silicon carbide (SiC) material. Background Art

[0002] A bipolar transistor is a current-amplifying transistor consisting of two back-to-back PN junctions. Originating from the point-contact transistor invented in 1948, it evolved into the junction transistor, now known as the bipolar transistor, in the early 1950s. Bipolar transistors have two basic structures: PNP and NPN. The center semiconductor layer is called the base, while the outer two layers are called the emitter and collector regions, respectively. When a small amount of current is injected into the base region, a larger current flows between the emitter and collector regions, representing the transistor's amplification effect. This amplification effect can be utilized in conjunction with components such as resistors and capacitors to form an amplifier circuit, amplifying electrical signals. Bipolar transistors are current-controlled devices, in which both electrons and holes conduct electricity simultaneously. Compared to field-effect transistors, bipolar transistors have slower switching speeds, lower input impedance, and higher power consumption. Bipolar transistors are small in size, light in weight, consume little power, have a long lifespan, and are highly reliable. They have been widely used in broadcasting, television, communications, radar, computers, automatic control devices, electronic instruments, household appliances, and other fields, playing the roles of amplification, oscillation, and switching.

[0003] The prior art, such as CN201910850313.9, discloses a bipolar junction transistor, in which two heterojunction surfaces are formed by bonding silicon carbide and silicon, and a P-type base region and an N+ emitter region are formed into a heterojunction by using bonding technology. A bipolar junction transistor comprises a collector (8), a first N+ substrate (7), an N-collector region (6), a P-type base region (9), an N+ emitter region (3), a second N+ substrate (2), an emitter (1), a first base (4) and a second base (5); the collector (8), the first N+ substrate (7), the N-collector region (6) and the P-type base region (9) are stacked in sequence from bottom to top, and the N+ emitter region (3) is located on the P-type substrate. On the base region (9), the second N+ substrate (2) and the emitter (1) are sequentially located on the N+ emitter region (3), the first base (4) and the second base (5) are respectively located on both sides of the N+ emitter region (3), and are located on the P-type base region (9); the first N+ substrate (7) and the N-collector region (6) are made of silicon carbide material, the P-type base region (9) is made of silicon material, the N+ emitter region (3) and the second N+ substrate (2) are made of silicon carbide material, the N-collector region (6) and the P-type base region (9) form a heterojunction by bonding technology, and the P-type base region (9) and the N+ emitter region (3) form a heterojunction by bonding technology. The P-type base region and the N-collector region are bonded to form a heterojunction. The efficiency of electron injection in the heterojunction is very high. This is because the reverse injection of holes is almost completely blocked by an additional hole barrier. The hole diffusion current injected from the base region into the emitter region is extremely small. Therefore, the injection efficiency of the emitter junction is extremely high, which greatly improves the current gain of the device. Figure 1 . Summary of the Invention

[0004] The present invention aims to describe a silicon carbide bipolar transistor and its fabrication for higher frequency, high voltage, and high temperature applications. The present invention allows for the design of higher frequency bipolar transistors that take into account the minimization of transistor parasitics while also improving the high voltage performance of the transistor through design.

[0005] The technical solution of the present invention is a method for preparing a SiC bipolar junction transistor (BJT), that is, a method for manufacturing a self-aligned silicon carbide bipolar junction transistor.

[0006] 1) Using a pre-grown epitaxial layer as the base contact layer of the transistor; using an emitter ohmic metal as a self-aligned mask to align the emitter region with the base contact layer, wherein the emitter ohmic metal is a plurality of metals, including a single metal composition or a multi-metal stack, the single metal composition is selected from titanium (Ti), nickel (Ni), aluminum (Al), gold (Au) or platinum (Pt), and is directly deposited on the semiconductor surface; the multi-metal stack is composed of at least two metals selected from titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), tungsten (W) and alloys thereof;

[0007] 2) Using the base metal layer as a self-alignment guide, the base metal layer edge is aligned with the collector area etching process; the active area of ​​the device is aligned with the collector metal edge through the self-alignment method, ensuring the precise spatial definition of the functional area;

[0008] The substrate is a semi-insulating 4H silicon carbide substrate with a high resistivity greater than 1e6 ohm*cm, suitable for RF applications. The substrate is angled 4 degrees off-axis (a small off-angle (4° toward the <11-20> direction) to enhance epitaxial layer growth. Homoepitaxial growth on a substrate with this low off-angle can significantly reduce defect density and improve epitaxial layer crystalline quality by optimizing temperature and growth rate parameters.

[0009] 1) The step of using a pre-grown epitaxial layer as the base contact layer of the transistor, which is a basic structure for subsequent processing; see Figure 3

[0010] The 4H silicon carbide substrate comprises, from bottom to top, 1-1) a buffer layer: providing a semi-insulating substrate; depositing a highly doped n-type (or first conductivity type) semiconductor buffer layer on the semi-insulating substrate to form an n+ buffer layer, which ensures crystal matching with the upper epitaxial layer and helps suppress or eliminate defects in the subsequent epitaxial growth process;

[0011] 1-2) growing a heavily doped n-type semiconductor layer on the buffer layer to form an n+ collector layer, with doping optimized to reduce resistance and ensure the required electrical performance and low contact resistance;

[0012] 1-3) depositing a heavily doped p-type semiconductor layer on the n+ collector layer to form a p+ base layer, with a thickness appropriate to ensure accurate electrical contact and minimize surface resistance;

[0013] 1-4) forming an n emitter layer on the p+ base layer, followed by forming a heavily doped n+ emitter cap layer with a thickness configured to ensure sufficient gain and good electrical performance;

[0014] 2) using emitter metal to automatically align the emitter to the base layer; wherein the emitter region is aligned with the base contact layer by using the emitter ohmic metal as a self-aligned mask to define and align the emitter contact with subsequent layers:

[0015] depositing a layer of photoresist on the base contact layer;

[0016] forming a pattern of a photoresist layer;

[0017] depositing a layer of metal on the patterned photoresist layer by evaporation;

[0018] removing the photoresist layer by a lift-off or etching step, including immersion removal of the photoresist layer while precisely preserving the emitter metal layer;

[0019] An etch mask is applied that is aligned with the photoresist layer; the exposed portion of the metal layer is etched using either a wet chemical etch or a plasma etch process; the photoresist layer is removed to define the emitter metal layer; the mask is removed and the excess metal is etched away, leaving the desired ohmic contact.

[0020] By using a manufacturing process that automatically and precisely aligns certain layers or features, transistor parasitics are minimized and high-frequency performance metrics, including transition frequency (Ft) and maximum oscillation frequency (Fmax) are achieved:

[0021] A step of using a pre-grown epitaxial layer as a base contact layer for a transistor, which is a foundation structure for subsequent processing;

[0022] wherein the emitter region is aligned with the base contact layer by using the emitter ohmic metal as a self-aligned mask, Figure 5 Steps: The base layer is exposed for further processing and aligned with the emitter metal layer;

[0023] Using the emitter ohmic metal layer as a self-aligned mask for the etching process and selectively removing the first two epitaxial layers to the p+ substrate layer, including: etching each layer using a chemical solution; or removing the first two epitaxial layers using dry plasma etching;

[0024] The etching process provides self-alignment to the p+ substrate layer and minimizes undercutting of the substrate layer to maintain accuracy;

[0025] The etching process is controlled to ensure that the underlying layers are not damaged, by timing the etching process including stopping the etching process at a predetermined etching time or by an etching endpoint detection process to monitor the endpoint of the etching process.

[0026] The step of self-aligning the base metal edge to the collector etching comprises: Figure 6, the base contact is precisely aligned and functions properly; the surface is cleaned before metal deposition to ensure ohmic contact and reduce contamination; the base metal layer is aligned relative to the emitter to ensure that there is a gap between the base edge and the emitter edge, including depositing and patterning a layer of resist material on the p+ base metal layer and around the emitter, and the gap between the base edge and the emitter edge is defined by the resist material and the resolution of the imaging used to pattern the resist layer; evaporating the base metal layer onto the patterned resist layer; removing the resist layer by immersion, leaving the base metal layer; annealing the formed base metal layer at a temperature lower than the emitter annealing temperature to avoid damaging the previously deposited emitter contact; and testing the formed base-emitter contact to evaluate the base-emitter diode characteristics.

[0027] The step of etching from the edge of the base metal to the collector region comprises: Figure 7 As shown, a base metal layer is used as a self-aligned mask for etching the collector region; a non-critical alignment resist mask is applied to protect the emitter metal and the base-emitter region, wherein the non-critical alignment resist mask covers a major portion of the emitter metal and the base-emitter region while leaving a portion of the emitter metal exposed; the SiC material is removed using wet or dry etching to expose the n+ collector layer; the wet or dry etching process is monitored to ensure precise removal of material to the n+ collector layer; and the n+ collector layer is etched to prepare the surface for subsequent ohmic contact formation.

[0028] Further, the steps of depositing the collector metal and removing the resist layer include: Figure 8 , clean the collector area using standard cleaning or etch cleaning to prepare for the deposition of a resist layer on the n+ collector layer; deposit the collector metal using evaporation technology to facilitate the subsequent removal of the resist layer step; apply lift-off or etching technology to pattern the collector metal layer and remove excess material; skip the implantation step if the collector layer is highly doped and no further modification is required; alloy the collector metal to optimize contact performance; and test the functionality of the transistor to verify the collector contact and overall device performance.

[0029] Further, the method includes dry etching SiC to the SI substrate, including: Figure 9 , determine the area to be etched, including the collector and buffer layer, down to the SI substrate; use the collector metal edge as a self-aligned mask for precise etching; apply a resist layer with a wide position tolerance to assist in masking the etched area; perform etching to remove the collector and buffer layer, exposing the SI substrate; monitor the etching process to ensure it penetrates deep into the SI substrate to ensure complete isolation between transistors; verify isolation by inspecting the etched area to confirm electrical separation.

[0030] Further, it includes selecting silicon dioxide (SiO2) or silicon nitride (Si3N4) as the passivation material; depositing the passivation layer using plasma deposition techniques to achieve uniform coverage; ensuring that the passivation fills the gaps between contacts without voids; determining the passivation thickness based on the gap size and metal layer thickness; electrically isolating the contacts by minimizing surface leakage current through the passivation layer; and verifying that the passivation conforms to the surface and provides effective isolation.

[0031] Further, the passivation and etching steps include: applying a photolithographic mask to define contact hole locations;

[0032] patterning a photolithographic mask to achieve precise alignment on the ohmic metal layer;

[0033] etching the first passivation layer to expose the ohmic metal using wet etching, dry etching, or a combination of both;

[0034] Removing the photolithographic mask to clearly reveal the vias;

[0035] Inspect etched holes to confirm proper alignment and exposure of underlying metal;

[0036] Prepare the device for further processing, ensuring that the exposed ohmic metal is clean and intact.

[0037] Further, including power metal deposition:

[0038] Depositing a power metal layer across the wafer using sputtering;

[0039] Make metal contact with the ohmic layer through the through hole to ensure electrical connection;

[0040] applying a photolithographic mask to define metal retention and removal areas;

[0041] Etch the power metal using sputtering and / or wet etching techniques to isolate the contacts;

[0042] Stop etching at the first passivation layer to maintain proper insulation;

[0043] Forming surface pads in low-impedance areas for wire bonding and testing purposes;

[0044] 10(16) The method of claim 9, further comprising a second deposition comprising:

[0045] Spin-coat polyimide or other equivalent passivation material to cover the entire wafer;

[0046] masking the second passivation layer to define etched or developed areas;

[0047] Etching or developing the passivation layer to open the area above the power metal pad;

[0048] Curing the polyimide layer to form a durable, thick barrier;

[0049] Thinning the wafer to the required thickness for package installation and functional optimization;

[0050] Depositing an ohmic metal layer on the back side of the wafer;

[0051] Creates a ground plane layer to support package mounting and improve frequency response.

[0052] Beneficial effects: Self-aligned process technology can be used to reduce emitter and base capacitance, resistance, and inductance characteristics to improve frequency response (Ft and Fmax). Using silicon carbide as a material will provide the high voltage and high temperature environment required for these applications. Self-alignment means that the material or structure in a step will automatically align with the corresponding structure in other steps without the need for additional lithography or alignment steps. This technology can reduce parasitic capacitance in transistors, thereby increasing operating frequency and speed; Figure 1 and Figure 2 The following figure shows the outline of the advantageous process flow required to produce self-aligned emitter and collector BJTs. The process flow uses standard cleanroom processes and procedures at all stages. Figure 1 and Figure 2 The top to bottom run is shown. Generally, all alignments between layers are standard and can be aligned between the first layer or from layer to layer. The surface characteristics of the ohmic contact can be adjusted by many different surface treatments, including implants, cleaning, or different ohmic metallizations. For the present invention, it is assumed that a good ohmic contact is formed between any metal and the SiC semiconductor surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 Schematic diagram of the structure of SiC bipolar junction transistor;

[0054] Figure 2 This is a typical process flow chart of the present invention;

[0055] Figure 3 is a growth structure diagram of the starting material of the present invention;

[0056] Figure 4 This is a structural diagram of emitter ohmic metal deposition of the present invention;

[0057] Figure 5 The emitter layer of SiC is etched in the present invention - the etching and emitter metal self-aligned structure;

[0058] Figure 6 The structure of the base metal deposition and stripping of the present invention

[0059] Figure 7 The present invention is a SiC dry etching base layer - a structure in which the etching and the base layer are self-aligned;

[0060] Figure 8 A schematic diagram showing the collector metal deposition stage for the present invention is shown.

[0061] Figure 9 A schematic diagram showing the etching process from the current collecting layer to the semi-insulating substrate according to the present invention.

[0062] Figure 10 A cross section of the completed device is shown for the present invention before the metallization and passivation stages.

[0063] Figure 11 Showing the first passivation deposition.

[0064] Figure 12 A photoresist mask is shown, opening contact holes to expose the underlying ohmic metal.

[0065] Figure 13 Top metallization process diagram.

[0066] Figure 14 A second passivation deposition is shown.

[0067] Figure 15 Schematic diagram of the completed device viewed from above. DETAILED DESCRIPTION

[0068] like Figure 1 As shown, the SiC bipolar junction transistor (BJT), the P-type base region and the N+ emitter region are formed into a heterojunction using bonding technology, including a collector, a first N+ substrate 7, and the lower part of the substrate can be further provided with an N-collector region, a P-type base region 9, an N+ emitter region 3, a second N+ substrate 2, an emitter 1, a first base 4 and a second base 5; the collector 8 and the first N+ substrate 7 are provided with collectors, especially collectors on both sides, located on the upper surface of the lower N+ substrate, the N-collector region and the P-type base region 9 are stacked in sequence from bottom to top, and the N+ emitter region 3 is located On the P-type base region 9, the upper substrate of the second N+ substrate 2 and the emitter (1emitter) are successively located on the N+ emitter region 3, the first base 4 and the second base 5 are respectively located on both sides of the N+ emitter region 3, and are located on the P-type base region 9; the first N+ substrate 7 and the N-collector region are made of silicon carbide material, the P-type base region 9 is made of silicon material, the N+ emitter region 3 and the second N+ substrate 2 are made of silicon carbide material, the N-collector region and the P-type base region 9 form a heterojunction through bonding technology, and the P-type base region 9 and the N+ emitter region 3 form a heterojunction through bonding technology.

[0069] The bipolar junction transistor layers, including the emitter, base, and collector, are all present in the epitaxial layer of the grown starting material. The growth of the epitaxial layer is manufactured on a semi-insulating 4H silicon carbide substrate; the 4H silicon carbide substrate is composed of a buffer layer, n+, p+, n-, and n+ layers from bottom to top; again, in order to form a good ohmic contact, metal annealing can be performed. Three independent low-ohmic metals can be used, so the annealing can be completed separately or as a single annealing at the end of the third metal deposition (collector). The present invention has pointed out the annealing stage for each metal. The temperature of these anneals will be from high to low so as not to affect the previous metallization.

[0070] Metallization, which is often performed in a standard cleanroom configuration, is used to carry current and reduce overall resistance. Materials such as silicon nitride or silicon dioxide are used to isolate the contacts from each other to reduce field breakdown between the base emitter and collector layers. The process flow does not show any limitations.

[0071] Self-aligned processes are used in the manufacture of bipolar transistors and their integrated circuits. A polysilicon emitter with a micron-level linewidth is used as a mask, and then a concentrated base region is formed by diffusion of impurities, achieving self-alignment between the emitter and base regions. Self-aligned double patterning (SADP) is a more advanced self-aligned technology that uses non-photolithographic process steps (such as thin film deposition and etching) to spatially multiply the photolithographic pattern. Finally, another photolithography and etching step removes the excess pattern, achieving higher pattern density and performance.

[0072] This self-aligned transistor structure has not been used before on a silicon carbide substrate. The silicon carbide bipolar junction transistor (BJT) is a wide-bandgap, high-performance power device with low on-resistance and low switching losses. They are also very capable of operating at high temperatures with high breakdown electric fields, high thermal conductivity and high electron drift velocity.

[0073] Because SiC has a 10-fold greater breakdown field, SiC devices can operate at 10 times the voltage for a given drift region thickness. The achievable power density is also higher due to SiC's excellent thermal conductivity and wide energy bandgap. As high-power BJTs become an increasingly mature technology, standard RF design techniques can be applied. All transistor designs are a trade-off between active area for power considerations and don't care area, which does not contribute to the higher frequency performance of the device. The process flow included in this invention describes a design and process that will maintain a high active area while reducing the inactive parasitic area, enhancing the high-frequency aspects of the transistor. Self-alignment provides parasitic reduction to increase transistor frequencies Ft and Fmax.

[0074] The present invention is equally applicable to heterojunction bipolar transistors and standard bipolar junction transistors. For simplicity, a standard bipolar junction transistor is shown. Figure 1 .

[0075] Figure 2 In, 1) emitter ohmic metal deposition;

[0076] 2) Dry etching of the emitter layer – Etching is self-aligned with the emitter metal: etching away the silicon carbide material to expose the base layer

[0077] Emitter ohmic metal such as Figure 5 As shown in Figure 1. A mask is provided for etching the upper two epitaxial layers down to the p+ base layer. This etch can be done with wet chemical or dry plasma and provides self-alignment with the base layer with minimal cut-through. The etch must be controlled to ensure that the underlying layers are not damaged and must be precise enough to ensure that the etch stops within the p+ layer.

[0078] 3) Deposition of the base metal layer. This layer is aligned with the lower part of the emitter region, and there is a gap between the base and the emitter edge. After this stage, the base emitter contact can be tested and the base emitter diode can be verified.

[0079] 4) Dry etching of the base layer – the etch is self-aligned with the base layer; the base metal etch is self-aligned to the collector region. A non-critically aligned photoresist mask is required to protect the emitter metal and base emitter region from the next level.

[0080] 5) Collector metal deposition stage. Etching from the collector layer to the semi-insulating substrate. The areas to be etched are the collector layer and epitaxial buffer layer, as shown in the figure.

[0081] 6) First passivation deposition. This is typically a silicon dioxide or silicon nitride plasma deposition to fill the gaps between the contacts (the metal electrode layers). A photoresist mask is applied to open the contact holes to expose the ohmic metal underneath. The first passivation layer is then etched onto the metal using wet or dry etching, or a combination of both, depending on the design rules. The photoresist can then be removed, leaving the vias for further processing.

[0082] 7) Second passivation;

[0083] 8) Metallization process.

[0084] Specific steps: 101 start;

[0085] 102 using a mask layer to complete the metal deposition of the emitter of the emitter region - masking and etching or stripping; metal alloying as needed; the metal layer can be deposited by sputtering deposition, anti-etching mask and metal etching;

[0086] 103 Dry etching is used to prepare the emitter layer. The silicon carbide material is etched away to expose the base layer. The emitter metal is used as a mask at this stage. The emitter metal is etched in a self-aligned manner.

[0087] 104 masks and etches away the SiC material to expose the collector layer; the metal edge of the base region is used for self-aligning the collector region;

[0088] 105 Deposition of a base metal layer (aligned with the lower portion of the emitter region), dry etching of the base layer: masking a layer to complete base metal deposition - masking and stripping. Metal alloying as needed;

[0089] 106 mask layer is used to etch away the SiC material to expose the semi-insulating substrate; etching is performed until the Si substrate is self-aligned with the edge of the collector;

[0090] 107 First passivation deposition – can be silicon dioxide or silicon nitride, or a mixture of both, to provide isolation between contacts;

[0091] 108 Contact etching – etching the passivation layer to the ohmic metal layer;

[0092] 109 sputter depositing a power metal overlying the resulting structure, masking and sputter / wet etching down to the first passivation layer;

[0093] 110-0 Second passivation deposition – can be polyimide or more;

[0094] 110-1 Silicon Dioxide / Silicon Nitride. This provides scratch protection and further isolation.

[0095] 111 Second passivation deposition – can be polyimide or more silicon dioxide / silicon nitride. This provides scratch protection and further isolation.

[0096] 112 thinning to reduce SI layer;

[0097] 113 Return to the metallization of the base plane field layer; 114 Completed.

[0098] Starting materials such as Figure 3 As shown, all bipolar layers, emitter base, and collector electrodes are present in the grown starting material. The epitaxial layers are grown on a semi-insulating 4H silicon carbide substrate. Semi-insulating substrates are now available with >1e6 ohms, specifically for RF applications. The substrate is shown off-axis (nominal 4 degrees).

[0099] The doping of each layer is determined by reducing the resistance of each layer to provide the gain required for the application and reducing the contact resistance required to form a good ohmic contact. The thickness of each layer is determined by ensuring sufficient depth to make precise contact with the layer and reducing the layer resistance so that the completed device has good electrical performance. The collector layer is built on the substrate and can include a buffer layer to ensure crystallinity with the upper epitaxial layer and for defect suppression / elimination.

[0100] Emitter ohmic metal deposition such as Figure 4 The metal deposition layer can be deposited by sputtering deposition, anti-etching mask and metal etching, or by stripping, as shown. Figure 4 As shown in Figure 2. Either solution results in the emitter being deposited in the center of the bipolar transistor. To lift off the metal, after developing the photoresist, the metal is typically deposited by evaporation. The photoresist is then removed by soaking, leaving the emitter metal.

[0101] depositing a layer of photoresist on the base contact layer; forming a pattern of the photoresist layer;

[0102] depositing a layer of metal on the patterned photoresist layer by evaporation;

[0103] The photoresist layer is removed by an etching step, including immersion removal, while accurately preserving the emitter metal layer.

[0104] Applying an etch mask aligned with the photoresist layer; etching the exposed portion of the metal layer using either a wet chemical etch or a plasma etch process; removing the photoresist layer to define an emitter metal layer; wherein the emitter region is aligned with the base contact layer by utilizing the emitter ohmic metal as a self-aligned mask, and the surface is cleaned to remove contaminants before the metal deposition step; after the metal deposition or after removing the photoresist layer, an annealing step can be performed to ensure that the contact resistance is reduced by improving the metal semiconductor interface; testing the emitter contact to ensure that the achieved ohmic contact has a low resistance suitable for device operation.

[0105] Figure 5 SiC dry etching emitter layer – etching and emitter metal self-alignment: the emitter region is aligned with the base contact layer by using the emitter ohmic metal as a self-aligned mask, including Figure 5 Steps shown: The base layer is exposed for further processing and aligned with the emitter metal layer;

[0106] Using the emitter ohmic metal layer as a self-aligned mask for the etching process and selectively removing the first two epitaxial layers to the p+ substrate layer, including: etching each layer using a chemical solution; or removing the first two epitaxial layers using dry plasma etching;

[0107] The etching process provides self-alignment to the p+ substrate layer and minimizes undercutting of the substrate layer to maintain accuracy;

[0108] The etching process is controlled to ensure that the underlying layers are not damaged, by timing the etching process including stopping the etching process at a predetermined etching time or by an etching endpoint detection process to monitor the endpoint of the etching process.

[0109] Figure 6 Base metal deposition and stripping: The self-aligned base metal edge to collector etch steps include: Figure 6 Deposition of the base metal layer is shown. The base contact is precisely aligned and functional. The surface is cleaned prior to metal deposition to ensure ohmic contact and reduce contamination. The base metal layer is aligned relative to the emitter to ensure a gap between the base edge and the emitter edge, including depositing and patterning a layer of resist material over the p+ base metal layer and around the emitter. The gap between the base edge and the emitter edge is defined by the resist material and the resolution of the imaging used to pattern the resist layer. The base metal layer is evaporated onto the patterned photoresist. The gap between the emitter and base metal is determined by the photoresist material and the resolution of the imaging. The base metal layer is then removed from beneath the resist layer (photoresist) by immersion. The formed base metal layer is annealed at a temperature lower than the emitter annealing temperature to avoid damaging the previously deposited emitter contact. The formed base-emitter contact is then tested to evaluate base-emitter diode characteristics.

[0110] Figure 7 SiC dry etching base layer – etching is self-aligned with the base layer; wherein the steps of self-aligning the etching from the edge of the base metal to the collector area include: Figure 7 Showing the base metal layer as a self-aligned mask for etching the collector region; applying a non-critically aligned resist mask (with a certain tolerance, meaning the dimensions can be achieved on many different alignment machine types) to the emitter region, where the non-critically aligned resist mask covers the emitter metal and a major portion of the base-emitter region, while leaving a portion of the emitter metal exposed; removing the SiC material using a wet or dry etch to expose the n+ collector layer; monitoring the wet or dry etch process to ensure precise removal of material to the n+ collector layer; etching into the n+ collector layer to prepare for subsequent ohmic contact formation.

[0111] Figure 8 The collector metal deposition phase is shown. The steps involved in depositing the collector metal and removing the resist layer include: Figure 8 Clean the collector area using standard or etch clean to prepare for deposition of a resist layer on the n+ collector layer; deposit the collector metal using evaporation techniques to facilitate the subsequent resist removal step; apply lift-off or etching techniques to pattern the collector metal layer and remove excess material; skip the implant step if the collector layer is highly doped and does not require further modification; alloy the collector metal to optimize contact performance; and test the transistor functionality to verify the collector contact and overall device performance.

[0112] Figure 9Shows etching from the collector layer to the semi-insulating substrate. Identify the area to etch, including the collector and buffer layers, down to the SI substrate. Use the collector metal edge as a self-aligned mask for precise etching. Apply a resist layer with wide positional tolerance to help mask the etched area. Perform the etch to remove the collector and buffer layers, exposing the SI substrate. Monitor the etch to ensure it penetrates deep into the SI substrate, ensuring complete isolation between transistors. Verify isolation by inspecting the etched area to confirm electrical separation.

[0113] Figure 10 A cross section of a completed device is shown before the metallization and passivation stages. At this stage, each section of the BJT can be tested to ensure that it is handled correctly at low voltages and that the device is electrically within specifications. Without passivation, care must be taken at this stage to avoid excessive leakage current.

[0114] Figure 11 The first passivation deposition is shown. This is typically a plasma deposition of silicon dioxide or silicon nitride to fill the gaps between the contacts. The passivation thickness is determined by the gap size and the metal thickness to ensure isolation between the conformal coating and the contacts. Passivation minimizes surface leakage between the contacts, ensuring a fully functional transistor. This is standard for nearly all BJT designs.

[0115] Figure 12 1st Passivation Mask and Etch 1st Passivation Mask and Etch

[0116] Figure 12 A photoresist mask is shown, opening the contact holes to expose the ohmic metal underneath. The first passivation layer is then etched down to the metal using either wet or dry etching, or a combination of both, depending on the design rules. The photoresist can then be removed, leaving the vias for further processing.

[0117] Figure 13 Top metallization process, Figure 13 The following stages of metal sputter deposition and etching are shown. The first stage involves metal deposition via sputtering across the entire wafer, with ohmic metal contacts made through vias. The metal is then masked and sputter-etched or wet-etched down to the first passivation layer to isolate the contacts and provide surface pads for wire bonding and probe testing away from the active areas. The power metal pads are located in areas free of epitaxial growth, minimizing impedance impact and generally reducing the capacitance of the pad layout.

[0118] Figure 14A second passivation deposition is shown. This material is typically a polyimide or similar passivation layer that is spin deposited, masked, etched / developed, and then cured to provide a thick isolation layer. The second passivation will be open only above the power metal pads to allow probe access or wire bond / clip access for testing and packaging. The wafer can then be thinned to the appropriate thickness and an ohmic metal deposited on the back side, both for package mounting purposes and to create a ground plane to help improve the overall frequency response of the transistor. Cross-section letters A and A' indicate that the cross-section view is relative to Figure 15 The top-down layout is shown where the device will be drawn. This will include the device's pad openings (not shown in the cross-sectional view). Top-down view of the completed device – single emitter finger and multiple emitter finger designs

[0119] Figure 15 Completed devices—single-emitter and multi-emitter finger designs. For typical single-emitter and multi-emitter finger layouts, contact resistance can be further reduced by increasing the via size in the finger region. Finger width is limited by the minimum via size in the process and the design rule spacing between the via and the active finger edge. For example, if the via opening is 2 microns and the distance between the via and the finger edge is limited to 0.5 microns, the active finger width is 3 microns.

[0120] The emitter region is aligned with the base contact layer by using the emitter ohmic metal as a self-aligned mask, using a method including Figure 5 Steps shown: The base layer is exposed for further processing and aligned with the emitter metal layer;

[0121] Using the emitter ohmic metal layer as a self-aligned mask for the etching process and selectively removing the first two epitaxial layers to the p+ substrate layer, including: etching each layer using a chemical solution; or removing the first two epitaxial layers using dry plasma etching;

[0122] The etching process provides self-alignment to the p+ substrate layer and minimizes undercutting of the substrate layer to maintain accuracy;

[0123] The etching process is controlled to ensure that the underlying layers are not damaged, by timing the etching process including stopping the etching process at a predetermined etching time or by an etching endpoint detection process to monitor the endpoint of the etching process.

[0124] Further steps include obtaining the SiC bipolar junction transistor (BJT) structure at an intermediate stage in the process before applying power metal and passivation layers; testing each section of the BJT at low voltage to verify functionality and ensure machining accuracy; inspecting the device for any defects or signs of misalignment in the emitter, base, and collector regions; handling the device carefully to prevent additional leakage current or contamination; verifying that electrical specifications meet design requirements before proceeding to the final stages; and preparing for the power metal deposition and passivation processes.

[0125] It further includes selecting silicon dioxide (SiO2) or silicon nitride (Si3N4) as the passivation material; depositing the passivation layer using plasma deposition techniques to achieve uniform coverage; ensuring that the passivation fills the gaps between contacts without voids; determining the passivation thickness based on the gap size and metal layer thickness; electrically isolating the contacts by minimizing surface leakage current through the passivation layer; and verifying that the passivation conforms to the surface and provides effective isolation.

[0126] Further comprising passivation and etching steps, including:

[0127] applying a photolithographic mask to define contact hole locations;

[0128] patterning a photolithographic mask to achieve precise alignment on the ohmic metal layer;

[0129] etching the first passivation layer to expose the ohmic metal using wet etching, dry etching, or a combination of both;

[0130] Removing the photolithographic mask to clearly reveal the vias;

[0131] Inspect etched holes to confirm proper alignment and exposure of underlying metal;

[0132] Prepare the device for further processing, ensuring that the exposed ohmic metal is clean and intact.

[0133] This further includes a power metal deposition phase, including:

[0134] Depositing a power metal layer across the wafer using sputtering;

[0135] Make metal contact with the ohmic layer through the through hole to ensure electrical connection;

[0136] applying a photolithographic mask to define metal retention and removal areas;

[0137] Etch the power metal using sputtering and / or wet etching techniques to isolate the contacts;

[0138] Stop etching at the first passivation layer to maintain proper insulation;

[0139] Create surface pads in low-impedance areas for wire bonding and testing purposes.

[0140] The above method, including the second deposition, comprises:

[0141] Spin-coat polyimide or other equivalent passivation material to cover the entire wafer;

[0142] masking the second passivation layer to define etched or developed areas;

[0143] Etching or developing the passivation layer to open the area above the power metal pad;

[0144] Curing the polyimide layer to form a durable, thick barrier;

[0145] Thinning the wafer to the required thickness for package installation and functional optimization;

[0146] Depositing an ohmic metal layer on the back side of the wafer;

[0147] Creates a ground plane layer to support package mounting and improve frequency response.

[0148] The above method determines the minimum through-hole size based on design rules and process specifications;

[0149] Define the design rule clearance between the edge of the through hole and the edge of the active finger;

[0150] Calculate the active finger width by adding the via size to twice the design rule clearance;

[0151] Design the emitter layout to maximize the contact area while adhering to manufacturing constraints;

[0152] Use multi-emitter configurations when needed to optimize current flow and performance;

[0153] Align the vias onto the emitter fingers to ensure proper electrical contact and minimize resistance.

[0154] Before depositing a photolithography mask covering the base contact layer, the method further includes: implanting dopants, including nitrogen for n-type SiC and aluminum for p-type, into the base contact layer to form a highly doped contact layer to form a low resistance.

[0155] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a SiC bipolar junction transistor, characterized in that: 1) Using a pre-grown epitaxial layer as the base contact layer of the transistor; using an emitter ohmic metal as a self-aligned mask to align the emitter region with the base contact layer, wherein the emitter ohmic metal is a plurality of metals, including a single metal composition or a multi-metal stack, the single metal composition is selected from titanium (Ti), nickel (Ni), aluminum (Al), gold (Au) or platinum (Pt), and is directly deposited on the semiconductor surface; the multi-metal stack is composed of at least two metals selected from titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), tungsten (W) and alloys thereof; 2) Using the base metal layer as a self-alignment guide, the base metal layer edge is aligned with the collector area etching process; the active area of ​​the device is aligned with the collector metal edge through the self-alignment method, ensuring the precise spatial definition of the functional area; The substrate is a semi-insulating 4H silicon carbide substrate with a high resistivity greater than 1e6 ohm*cm, suitable for radio frequency applications, and the substrate is homoepitaxially grown at an off-axis angle of 4 degrees. 1) A step in which a pre-grown epitaxial layer is used as a base contact layer for a transistor, which is a base structure for subsequent processing; The 4H silicon carbide substrate is formed from bottom to top as follows: 1-1) Buffer layer: providing a semi-insulating substrate; depositing a highly doped n-type semiconductor buffer layer on the semi-insulating substrate to form an n+ buffer layer, which ensures crystal matching with the upper epitaxial layer and helps to suppress or eliminate defects in the subsequent epitaxial growth process; 1-2) growing a heavily doped n-type semiconductor layer on the buffer layer to form an n+ collector layer, with doping optimized to reduce resistance and ensure the required electrical performance and low contact resistance; 1-3) depositing a heavily doped p-type semiconductor layer on the n+ collector layer to form a p+ base layer, with a thickness appropriate to ensure accurate electrical contact and minimize surface resistance; 1-4) forming an n emitter layer on the p+ base layer, followed by forming a heavily doped n+ emitter cap layer with a thickness configured to ensure sufficient gain and good electrical performance; 2) using emitter metal to automatically align the emitter to the base layer; wherein the emitter region is aligned with the base contact layer by using the emitter ohmic metal as a self-aligned mask to define and align the emitter contact with subsequent layers: depositing a layer of photoresist on the base contact layer; forming a pattern of a photoresist layer; depositing a layer of metal on the patterned photoresist layer by evaporation; removing the photoresist layer by a lift-off or etching step, including immersion removal of the photoresist layer while precisely preserving the emitter metal layer; applying an etch mask aligned with the photoresist layer; etching exposed portions of the metal layer using either a wet chemical etch or a plasma etch process; The photoresist layer is removed to define the emitter metal layer; that is, the mask is removed and the excess metal is etched away, leaving the required ohmic contact.

2. The method for preparing a SiC bipolar junction transistor according to claim 1, wherein: wherein the emitter region is aligned with the base contact layer by utilizing the emitter ohmic metal as a self-aligned mask, with the bottom layer exposed for further processing and aligned with the emitter metal layer; The emitter ohmic metal layer is used as a self-aligned mask for the etching process, and the first two epitaxial layers are selectively removed to the p+ base layer, including: etching each layer using a chemical solution; or removing the first two epitaxial layers using dry plasma etching; wherein the etching process provides self-alignment to the p+ base layer and minimizes the undercutting of the base layer to maintain accuracy; the etching process is controlled to ensure that the underlying layer is not damaged, and the endpoint of the etching process is monitored by a timing etching process including a predetermined etching time to stop the etching process or an etching endpoint detection process.

3. The method for preparing a SiC bipolar junction transistor according to claim 1, wherein: The self-alignment The steps of etching the base metal edge to the collector include: the base contact is precisely aligned and functioning properly; cleaning the surface before metal deposition to ensure ohmic contact and reduce contamination; aligning the base metal layer relative to the emitter to ensure that there is a gap between the base edge and the emitter edge, including depositing and patterning a layer of resist material on the p+ base metal layer and around the emitter, and defining the gap between the base edge and the emitter edge by the resolution of the resist material and the imaging used to pattern the resist layer; evaporating the base metal layer onto the patterned resist layer; removing the resist layer by immersion, leaving the base metal layer; annealing the formed base metal layer at a temperature lower than the emitter annealing temperature to avoid damaging the previously deposited emitter contact; and testing the formed base-emitter contact to evaluate the base-emitter diode characteristics.

4. The method according to claim 1, wherein: The self-alignment The steps of etching from the edge of the base metal to the collector region include: using the base metal layer as a self-aligned mask for etching the collector region; applying a non-critical alignment resist mask to protect the emitter metal and the base-emitter region, wherein the non-critical alignment resist mask covers a major portion of the emitter metal and the base-emitter region while leaving a portion of the emitter metal exposed; using wet or dry etching to remove the SiC material to expose the n+ collector layer; monitoring the wet or dry etching process to ensure precise removal of material to the n+ collector layer; etching into the n+ collector layer to prepare the surface for subsequent ohmic contact formation.

5. The method according to claim 1, wherein: including the steps of depositing collector metal and removing the resist layer, cleaning the collector area using standard cleaning or etch cleaning in preparation for depositing a resist layer on the n+ collector layer; Depositing the collector metal using evaporation techniques to facilitate subsequent removal of the resist layer; applying lift-off or etching techniques to pattern the collector metal layer and remove excess material; If the collector layer is highly doped and requires no further processing, the implantation step is skipped; Alloy the collector metal to optimize contact performance; and test the functionality of the transistor.

6. The method according to claim 1, wherein: The process involves dry etching SiC down to the SI substrate, determining the area to be etched, including the collector and buffer layer, down to the SI substrate; utilizing the collector metal edge as a self-aligned mask for precise etching; applying a resist layer with a wide positional tolerance to assist in masking the etched area; and performing etching to remove the collector and buffer layer, exposing the SI substrate. Monitor the etching process to ensure it penetrates deep into the SI substrate, guaranteeing complete isolation between transistors; verify isolation by inspecting the etched area to confirm electrical separation.

7. The method according to claim 6, characterized in that Choose silicon dioxide or silicon nitride as the passivation material; use plasma deposition techniques to deposit the passivation layer to achieve uniform coverage; ensure that the passivation fills the gaps between contacts without voids; Determine passivation thickness based on gap size and metal layer thickness; electrically isolate contacts by minimizing surface leakage current through the passivation layer; and verify that the passivation conforms to the surface and provides effective isolation.

8. The method according to claim 7, wherein: The method includes passivation and etching steps, applying a photolithography mask to define the contact hole location; patterning the photolithography mask to achieve precise alignment on the ohmic metal layer; etching the first passivation layer using wet etching, dry etching, or a combination of the two to expose the ohmic metal; Removing the photolithographic mask to clearly reveal the vias; Inspect the etched holes to confirm proper alignment and exposure of the underlying metal.

9. The method according to claim 8, wherein: This includes the power metal deposition phase, which uses sputtering to deposit a power metal layer across the entire wafer; making contact between the metal and the ohmic layer through vias to ensure electrical connection; Apply photolithographic masks to define metal retention and removal areas; etch the power metal using sputtering and / or wet etching techniques to isolate the contacts; Etching stops at the first passivation layer, maintaining proper insulation; creating surface pads in low-resistance areas for wire bonding and testing.

10. The method according to claim 9, wherein: Includes a second deposition, spin-coating polyimide or other equivalent passivation material to cover the entire wafer; masking the second passivation layer to define etched or developed areas; Etching or developing the passivation layer to open the area above the power metal pad; Curing the polyimide layer to form a durable, thick barrier; Thin the wafer to the required thickness to facilitate package installation and functional optimization; deposit an ohmic metal layer on the back side of the wafer.

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