Electronic device and manufacturing method thereof

Abstract

The invention relates to an electronic device and a manufacturing method thereof. An example method includes arranging an N-type semiconductor body having a lattice structure with spatial symmetry; forming a damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry in the semiconductor body; a P-type edge termination region is formed in the semiconductor body, including performing a channelized implantation of a P-type dopant at the damaged region and a portion of the semiconductor body adjacent an opposite side of the damaged region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian patent application serial number 102024000005770, filed on March 14, 2024, entitled “MOSFET DIPOTENZA PROVVISTO DI ANELLO DI BORDO A TRASPARENZA VARIABILEFORMATO MEDIANTE UN IMPIANTO AUTOALLINEATO AD ELEVATA PROMONDITA”, which is hereby incorporated by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates to an electronic device and a method for manufacturing the same, and more particularly to a method for forming an edge ring at least partially surrounding an active area of ​​the electronic device by utilizing an intentionally damaged area to achieve implantation of the edge ring in a self-aligned manner. Background Art

[0004] Ion implantation is a well-established technique for introducing dopants into silicon carbide (SiC). However, dopant diffusion is not an applicable technique due to the low diffusion rate of SiC compared to other semiconductor materials (e.g., silicon), and epitaxial growth may not be a useful alternative, especially for locally confined volumes.

[0005] As is known, the crystal structure of SiC influences the depth profile achieved during implantation. In fact, the so-called channeling effect can significantly increase the penetration depth of ions into crystalline materials compared to amorphous targets. This phenomenon can occur if the direction of the impinging ion beam is close to parallel to the main crystal axes or crystal planes. In these directions, the reduction in energy loss per ion path length is smaller, so the ions migrate deeper into the target.

[0006] To theoretically describe the probability of channeling, the concept of the "critical angle for channeling" has been introduced. In this context, the critical angle is considered to be the maximum angle between the axial atomic row and the incident beam at which ions will still be guided along that axis. To study and predict channeling phenomena during ion implantation, various Monte Carlo simulation software for crystal targets exists, such as the binary collision approximation (MC-BCA).

[0007] Channeling is generally an undesirable effect, and SiC wafers are typically tilted in random, non-channeling directions to minimize channeling during implantation. Consequently, a more or less Gaussian doping profile is obtained with respect to depth, where the depth is determined by the energy, the ions used, and the target atomic structure. On the other hand, if the implantation is performed along the crystal axis, a completely different profile is obtained, where the ions penetrate deep into the target along the crystal's axis. In SiC, it has been demonstrated that the deepest channeling ions can penetrate many times deeper than the intended range for a corresponding random implantation.

[0008] In order to form locally confined implantation areas, it is known to use an implantation hard mask, such as a silicon oxide (SiO2) hard mask, which is configured to locally shield the SiC wafer during the implantation step. However, the Applicant has demonstrated that the use of a hard mask of this type can lead to planarity problems of the layer to which it is applied, due to the effects of lattice stresses generated on the SiC substrate by the presence of the hard mask after removal of the same mask.

[0009] Furthermore, the use of such a hard mask limits the mutual spatial distance between adjacent implants, for example in the case of variable transparency edge termination rings. Figure 1 An electronic device equipped with this type of edge termination ring is shown according to an example (which is not necessarily prior art).

[0010] Reference Figure 1 , shows a portion of a chip housing an electronic device 1 , such as a power MOSFET, limited to its edge region surrounding the active area. Figure 1 The chip portion is shown in a three-axis Cartesian reference system with the X, Y, and Z axes being orthogonal to each other. The electronic device 1 comprises: a SiC semiconductor body 10 having a first conductivity (N-type), defined by a front side 10a and a back side 10b opposite to each other along an axis Z; and having a side surface 10c connecting the front side 10a to the back side 10b along the axis Z; a body region 14 having a second conductivity (P-type) opposite to the first conductivity (N-type), extending into the semiconductor body 10; a source region 17 in the body region 14; a first edge termination region 16 having the second conductivity, a doping value higher than the doping value of the body region 14, which is in electrical contact with the body region 14 and faces the front side 10b. a extending from a; a second edge termination region 18 (which is the above-mentioned variable transparent ring) having a second conductivity and a doping value lower than the doping value of the first edge termination region 16; a dielectric layer 20 on the front side 10a; a conductive layer 22 on the dielectric layer 20, forming an edge field plate of the electronic device 10; a first metallization 24a in electrical contact with the conductive layer 22 and a second metallization 24b in electrical contact with the first edge termination region 16 and the source 17, so as to apply a predetermined bias voltage (typically in the voltage range of 10-20V) between the first and second metallizations 24a, 24b. Figure 1 Further shown is a channel stop zone 19 which extends laterally to the second edge termination zone 18, in particular between the second edge termination zone 18 and the side surface 10c. The channel stop zone 19 has the function of forming an equipotential ring.

[0011] The second edge termination region 18 is formed by implanting a dopant having the second conductivity and extends into the semiconductor body 10 to a depth of several micrometers, for example, up to 5 μm along the Z-axis. The second edge termination region 18 comprises a plurality of implanted sub-regions 18 ′, which extend sequentially along the X-axis and are separated from one another by corresponding portions of the semiconductor body 10. Each implanted sub-region 18 ′ may have an extension along the X-axis that differs from the extensions of the other implanted sub-regions 18 ′, in particular an extension that gradually decreases from the first edge termination region 16 towards the channel stop region 19.

[0012] The first and second edge termination regions 16, 18 have the function of preventing or suppressing the generation of electric fields that damage the electronic device 1. In particular, the applicant has verified that Figure 1 Edge termination regions of the type shown serve to improve the electric field distribution in components with voltage levels up to 3300 V by distributing the field lines in the edge region below the critical breakdown value of the semiconductor material used.

[0013] The formation of the second edge termination region 18 envisages in particular the use of high-energy and highly doped deep-channel ion implantations, in order to reach the desired depth while locally reversing the conductivity of the semiconductor body 10 (from N-type to P-type), until the desired doping value of the implanted sub-region 18' is obtained. The formation of the second edge termination region 18 envisages the use of a hard mask for the deep implantation of dopants of the second conductivity (P), as previously mentioned, up to a depth of 5 μm along the Z axis; however, as previously mentioned, this type of hard mask limits the minimum separation dimension between the implanted sub-regions 18' along the X axis, in particular it limits the mutual distance between the sub-regions 18' to values ​​greater than 1 μm.

[0014] Therefore, there is a need to overcome the above-mentioned shortcomings, particularly with respect to the formation of the second edge termination region 18 . Summary of the Invention

[0015] This object is achieved by an electronic device and a method for manufacturing the same as defined in the appended claims.

[0016] One embodiment provides an electronic device. The electronic device includes: a semiconductor body having a first conductivity and a first doping value and provided with a front side, wherein the semiconductor body is made of a material having a lattice structure with spatial symmetry; an active region configured to accommodate a conductive channel of the electronic device in use; an edge region surrounding the active region and structurally continuous with the active region and at least partially accommodating: a first edge termination region having a second conductivity opposite to the first conductivity and extending from the front side into the semiconductor body, the first edge termination region including at least a first sub-region and a second sub-region, the first and second sub-regions having the second conductivity and separated from each other by a portion of the semiconductor body having the first conductivity; and a damage region extending between the first and second sub-regions at the portion of the semiconductor body, facing the front side, the damage region having an amorphous lattice structure or a lattice structure without spatial symmetry.

[0017] An embodiment of the present disclosure provides a method. The method includes: arranging a semiconductor body having a first conductivity and a first doping value, and providing a front side, wherein the semiconductor body is made of a material having a lattice structure with spatial symmetry, the semiconductor body having an active region and an edge region, the active region being configured to accommodate a conductive channel of an electronic device in use, the edge region surrounding the active region and being structurally continuous with the active region, forming a damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry at a portion of the front side; forming a first edge termination region having a second conductivity opposite to the first conductivity in the semiconductor body starting from the front side, including: performing a channeling implantation of a dopant substance having the second conductivity at the damaged region and at a portion of the semiconductor body adjacent to an opposite side of the damaged region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better understanding of the present disclosure, please refer to the accompanying drawings, in which:

[0019] Figure 1 An electronic device according to an example is shown in a cross-sectional view, limited to an edge region of the electronic device, which example is not the purpose of the present disclosure;

[0020] Figure 2 A die including an active region and an edge region of an electronic device according to one aspect of the present disclosure is shown in top view;

[0021] Figure 3 Along Figure 2 The cross-sectional view along line III-III shows the Figure 2 The electronic devices housed in the die are confined to the edge area;

[0022] Figure 4 The flow chart shows Figure 3 The steps of the method for manufacturing an electronic device;

[0023] Figure 5 The cross-sectional view shows the Figure 3 Another embodiment of the electronic device of the embodiment is limited to the edge area. DETAILED DESCRIPTION

[0024] Preferred embodiments of the present disclosure are described below by way of non-limiting examples.

[0025] refer to Figure 2 , a die or chip 30 or a portion thereof is shown in a Cartesian three-axis reference system of orthogonal axes X, Y, Z. The die 30 is obtained after a step of dicing a semiconductor wafer (not shown). The die 30 is shown in a top view on a plane XY.

[0026] The die 30 includes an outer edge 32 that physically defines the die 30. The die 30 houses at least one electronic device 40 (e.g., Figure 3 In the following description, the terms "electronic device" and "MOSFET" are used interchangeably without loss of generality.

[0027] The die 30 includes at least two functional regions: an active region 34, which generally extends to a central portion of the die 30, and an edge or peripheral region 36 that completely surrounds the active region 34. The edge region actually extends between the active region 34 and the outer edge 32 and is externally bounded by the outer edge 32. The active region 34 includes the conductive channel region when the MOSFET 40 is in use. In contrast, the edge region 36 is the region that does not have a conductive channel when in use. The edge region 36 includes functional elements for reducing or preventing crowding of electric field lines outside the active region, such as, for example, one or more edge termination regions, also called guard rings, as described in reference Figure 3 Better described and illustrated as is.

[0028] Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of a portion of die 30 on plane XZ along scribe line III-III. Figure 3 The dashed line that separates the active region 34 from the edge region 36 is to be understood as qualitative.

[0029] Figure 2 Only displayed Figure 3 Some elements of Figure 3 Compare Figure 2 More details.

[0030] MOSFET 40 includes a semiconductor body 50, in particular of silicon carbide (SiC), more in particular of 4H-SiC polytype. Alternatively, semiconductor body 50 may be of 3C-SiC or 6H-SiC or other SiC polytypes.

[0031] Typically, the semiconductor body 50 is made of a material having a crystal structure or lattice configured to allow ion implantation by utilizing a channeling implantation method (called channeling). Such a lattice can be described by a periodic distribution of atomic (or ionic / molecular) groups. Ideally, considering a crystal that extends infinitely in a spatial coordinate system, the periodicity leads to translational invariance (or translational symmetry). Therefore, the entire crystal is generated by the periodic repetition of a basic unit called a unit cell, which can contain atomic and / or ionic and / or molecular groups. Translational symmetry means that the general points belonging to the basic unit correspond one to one with the points of the basic unit obtained by appropriate translation from the first basic unit.

[0032] The semiconductor body 50 has a first conductivity (eg, N-type) and a 15 -1.10 20 atoms / cm 3 In one embodiment, the semiconductor body 50 includes a substrate on which a drift layer (not shown in detail) is formed (e.g., epitaxially grown). In this case, the doping of the substrate is, for example, approximately 1.10 18 -1.10 20 atoms / cm 3 , the drift layer doping is about 1·10 15 -1.10 17 atoms / cm 3 For example, the thickness of the drift layer is comprised between 3 and 100 μm (inclusive).

[0033] Semiconductor body 50 is delimited upwardly by a front side 50a and downwardly by a back side 50b, which are opposite each other along axis Z. Side surfaces 50c laterally delimit die 30; side surfaces 50c extend along axis Z between front side 50a and back side 50b to connect front side 50a and back side 50b to each other.

[0034] At the front side 50a, there is a body region 51 having a second conductivity (P type) opposite to the first conductivity. A source region 52 extends into the body region 51 at the front side 50a. A drain region 54 extends at the back side 50b. A gate region 56 extends on the front side 50a in a manner known per se and includes a gate dielectric 56a and a gate conductive region 56b on the gate dielectric 56a.

[0035] To simplify the representation, Figure 3A single body region 51, a single source region 52, and a single gate region 56 are shown. However, it will be apparent that MOSFET 40 may include any number of bodies 51, sources 52, and gate regions 56. In particular, body 51, source region 52, and gate region 56 are shown extending near the ends of active region 34.

[0036] The MOSFET 40 further comprises a first edge termination region 58 within the semiconductor body 50, which is implanted at and faces the front side 50a. The first edge termination region 58 has a second conductivity and a higher doping (P+) than the body region 51. The first edge termination region 58 comprises an end portion (or end region) 58' extending within the edge region 36 (and optionally also partially extending into the region of the active region 34); thus, the first edge termination region 58 is in direct electrical contact with the body region 51. The first edge termination region 58, when biased to the body and source voltages, has the function of shielding the structures of the device extending above the edge termination region 58 (in particular, the portion 62a of the conductive layer 62 described below) from the effects of high electric fields. The source region 52 may be omitted within the body region 51, such that the body region 51 is not exposed to the influence of the high electric field. Figure 3 Direct electrical contact is shown to the first edge termination region 58 .

[0037] A field dielectric layer ("field oxide") 60 extends over the first edge termination region 58 (on the front side 50a), and a conductive layer 62 (e.g., metal or N-type doped polysilicon) extends over the dielectric layer 60. The layer 62 is configured to distribute the gate bias to the device (the gate conductive region 56b is electrically connected to the layer 62).

[0038] Conductive layer 62 includes a first portion 62a extending over first edge termination region 58 and electrically insulated therefrom by a dielectric or oxide (e.g., SiO2) layer; and a second portion 62b extending over dielectric layer 60. First portion 62a and second portion 62b are structurally and electrically continuous with each other. Second portion 62b forms the edge field plate of MOSFET 40 because it carries the gate potential to edge termination region 36.

[0039] Conductive layer 62 is electrically connected to gate conductive region 56 b (in a manner not shown in the figure). In particular, conductive layer 62 is formed in the same step as gate conductive region 56 b. Passivation layer 64 extends over conductive layer 62 to protect and insulate conductive layer 62. Passivation layer 64 is interrupted where metallization layer 63 makes electrical contact with conductive layer 62.

[0040] Joint Reference Figure 2 and Figure 3MOSFET 40 includes a second edge termination region 68 (or second edge ring 68) having a second conductivity (P-type) and a lower doping value than the first edge termination region 58 (or first edge ring 58). The second edge termination region 68 extends at an end portion (or "end region") 58 of the first edge termination region 58 (which is opposite to the end 58' extending within the body region 51). Therefore, the second edge termination region 68 extends as an extension of the first edge termination region 58 and is in direct electrical contact with the first edge termination region 58. The second edge termination region 68 has the function of distributing or thinning the field lines of the electric potential in a manner that avoids thickening of the field lines over the radius of curvature of the first edge termination region 58, thereby maximizing the value of the edge breakdown voltage, similar to the reference Figure 1 The situation described.

[0041] Figure 3 An optional channel stop region 90 is further shown, which extends laterally toward the second edge termination region 68 at and facing the front side 50a. In particular, the channel stop region 90 extends between the second edge termination region 68 and the side surface 50c of the die 30. The channel stop region 90 is formed by implanting a dopant substance having a first conductivity (N-type, for example, obtained by doping with phosphorus) at a dose of 1.10 19 Until May 10 20 atoms / cm 3 The channel stop region 90 has the function of forming an equipotential ring with the drain electrode on the edge of the die.

[0042] The doping concentration of the first edge termination region 58 is about 1.10 18 -1.10 20 atoms / cm 3 The doping concentration of the second edge termination region 68 is approximately 1.10 16 -1.10 18 atoms / cm 3 .

[0043] The thickness of the first edge termination region 58 (starting from the front side 50a in the direction Z) is, for example, between 0.3 and 1 μm (inclusive). The thickness of the second edge termination region 68 (starting from the front side 50a in the direction Z) is, for example, between 0.5 μm and 5 μm (inclusive), in particular between 1 and 5 μm (inclusive).

[0044] According to one aspect of the present disclosure, Figure 2 and Figure 3 As shown, the second edge termination region 68 includes a plurality of sub-regions 68a-68d (individually designated by reference numeral 68) extending along the X-axis (in the Figure 3), are separated from one another by respective portions 69 a - 69 c (of a first conductivity, here N-type) of the semiconductor body 50. In a non-limiting manner according to the present disclosure, each sub-region 68 a - 68 d has an extension along the X-axis that differs from the extension of the other sub-regions 68 a - 68 d, in particular a decreasing extension from the first edge termination region 58 towards the channel stop zone 90.

[0045] from Figure 2 It can be clearly seen from the plan view that the sub-regions 68a-68d surround the active region, especially completely surround the active region, so Figure 3 What is shown in FIG. 5 (limited to the shape and extension of sub-regions 68a - 68d along the X-axis) applies analogously to a cross section taken along the Y-axis.

[0046] Figure 3 Four sub-regions 68a-68d are shown, but this representation should not be considered as limiting the present disclosure, as the number of sub-regions 68a-69d can be selected as needed during the design step, such as equal to two or greater than two (e.g., between two and six).

[0047] Subregion 68a is directly electrically connected to first edge termination region 58, i.e., end 58″ of first edge termination region 58 extends within subregion 68a. Subregion 68b extends laterally toward subregion 68a and is separated from the latter by portion 69a of semiconductor body 50. The distance between subregion 68a and subregion 68b along the X-axis is equal to 1 μm or less than 1 μm, for example, between 0.25 and 1 μm. Similarly, subregion 68c extends laterally toward subregion 68b and is separated from the latter by portion 69b of semiconductor body 50. The distance between subregion 68b and subregion 68c along the X-axis is equal to 1 μm or less than 1 μm, for example, between 0.25 and 1 μm. Similarly, subregion 68d extends laterally toward subregion 68c and is separated from the latter by portion 69c of semiconductor body 50. The distance between subregion 68c and subregion 68d along the X-axis is equal to 1 μm or less than 1 μm, for example, between 0.25 and 1 μm.

[0048] The distances between the sub-regions 68a-68d along the X-axis can be equal or different. Design requirements determined by the net epitaxial concentration may envisage distances between the sub-regions 68a-68d along the X-axis greater than 1 μm, for example up to 3 μm.

[0049] The sub-regions 68 a - 68 d all face the front side 50 a and terminate within the semiconductor body 50 without reaching the back side 50 b .

[0050] According to one aspect of the present disclosure, individual damaged regions 80 a - 80 c extend between sub-regions 68 a - 68 d , respectively; the damaged regions 80 a - 80 c face the front side 50 a and terminate within the semiconductor body 50 in respective portions 69 a - 69 c .

[0051] It should be noted that reference Figure 2 The damaged regions 80 a - 80 c also extend to completely or partially surround the active region 34 . Figure 3 The representation of the damaged area 80a-80c is similar to Figure 2 The cross section along the X axis is relevant, but the same applies to Figure 2 The cross section along the Y axis.

[0052] In particular, the damaged area 80a extends into the portion 69a between the sub-area 68a and the sub-area 68b and is adjacent to the sub-area 68a and the sub-area 68b; the damaged area 80b extends into the portion 69b between the sub-area 68b and the sub-area 68c and is adjacent to the sub-area 68b and the sub-area 68c; and the damaged area 80c extends into the portion 69c between the sub-area 68c and the sub-area 68d and is adjacent to the sub-area 68c and the sub-area 68d.

[0053] The applicant has demonstrated that the channeling effect can be modified by intentionally damaging a region of the surface of the semiconductor body 50 at the front side 50a, i.e., the region where the channeling implantation for forming the sub-regions 68a-68b occurs. Thus, the damaged regions 80a-80c are obtained by intentional damage, for example, by implanting ions of a non-reactive or non-doping substance into the semiconductor body 50, only in the portion thereof where the damaged regions 80a-80c are desired to form, or in the portions 69a-69c. This ion implantation, for example, causes damage to the crystal lattice of the semiconductor body 50 without locally altering its conductive properties. Suitable chemical species for this purpose include, for example, ions of Si, Ar, Ge, and He.

[0054] When present, the damaged regions 80a-80c modify or suppress the channeling effect during the formation of the second edge termination region 68, resulting in a Figure 3 The shapes shown and described above (ie, forming a sequence of sub-regions 68a-68d that are physically separated from each other).

[0055] The damaged regions 80a-80c extend from the front side 50a to a maximum depth, for example, between 0.1 and 0.6 μm (including the boundaries), in the semiconductor body 50. In one embodiment, the thickness of the damaged regions 80a-80c is uniform; in another embodiment, the thickness of the damaged regions 80a-80c is non-uniform, but varies between a maximum of 0.6 μm and a minimum of 0.1 μm.

[0056] Figure 4 The steps of the manufacturing process of MOSFET 40 are shown by a flow chart, limited to the elements useful for understanding the present disclosure.

[0057] Therefore, refer to Figure 4 In step S1, semiconductor body 50 is arranged or formed, and an implantation mask, such as an implantation mask of a photoresist or dielectric material, is formed on front side 50a (step S2) before forming previously described layers 60 and 62. This implantation mask is patterned to cover front side 50a except for regions 69a-69c where it is desired to form damaged regions 80a-80c, which therefore remain unmasked.

[0058] Then, in step S3, the damaged regions 80a-80c are formed using an implantation mask as described above. It is noteworthy that the formation of such an implantation mask does not excessively restrict the minimum size of the damaged regions 80a-80c along the X-axis, because the depth of these regions (less than one micron) does not require high implantation energy, and thus a mask material that can achieve good definition (unlike the mask material of the reference) can be used. Figure 1 The hard mask described for deep implantation (several microns) is different).

[0059] To complete the process of forming damaged regions 80a-80c, forming damaged regions 80a-80c includes using more than 10 13 atoms / cm 2 The implantation is performed with an implantation dose and energy sufficient to displace atoms from the crystal structure throughout the necessary depth (e.g., energy in the range of 30-300 keV (including the boundaries)). The damage-inducing implantation is not performed under channeling conditions, and annealing of the wafer during the process to remove the damage is avoided. According to another embodiment, the damaged regions 80a-80c are formed by one or more steps of etching the front side 50a of the semiconductor body 50, such as a RIE (reactive ion etching) process with physical etching characteristics (ion bombardment), while masking areas of the semiconductor body 50 that are not subjected to the intentional damage process.

[0060] Then, in step S4, a second edge termination region 68 is formed. This step involves forming a hard mask (e.g., one or more native oxide layers or one or more intentionally added oxide layers) on surface 50a laterally to (i.e., surrounding) the series of damaged regions 80a-80c. The hard mask of step S4 covers surface 50a except for portions thereof corresponding to damaged regions 80a-80c (e.g., portions 69a-69c) and portions of surface 50a where sub-regions 68a-68d are desired to be formed. In other words, the mask formation of step S4 contemplates forming the mask at a distance from damaged regions 80a and 80c (which are the outermost damaged regions in the series of damaged regions 80a-80c), with all other damaged regions (here, 80b) being included between these outer damaged regions 80a, 80c. In the design step, the distance between the mask and the outer damage area 80a, 80c is selected based on the required extension along X of the corresponding sub-areas 68a and 68d, which are also the outermost sub-areas in the series of sub-areas 68a-68d (the other sub-areas 68b, 68c are included between these outer sub-areas 68a and 68d).

[0061] Then, in step S5 , the method continues with a channeling implantation of a dopant species having the second conductivity at the front side 50 a to form a second edge termination region 68 .

[0062] After the above steps S1 - S5 , the structure of MOSFET 40 with respect to edge region 36 is completed, with field dielectric layer (“field oxide”) 60 , conductive layer 62 , metallization layer 63 and passivation layer 64 formed.

[0063] Referring to step S5, channeling implantation occurs when the ion beam during implantation is aligned with the channeling direction. For example, in SiC, this is the 000-1 or 11-23 direction. Typically, for a substrate with a diameter of 150 mm or 200 mm, the substrate is cut from an ingot with the growth surface tilted 4° along the 000-1 direction (for wafer cutting). This means that in order to utilize the channeling effect implantation on a 000-1 wafer, the ion beam needs to be tilted at a tilt of 4° during the implantation process, and for an 11-23 wafer, it needs to be tilted at a tilt of 13° or 21°.

[0064] As a result of the two possible damage steps described above, the semiconductor body 50 at the damaged regions 80 a-80 c does not have the same lattice structure as the semiconductor body 50 extending laterally relative to the damaged regions 80 a-80 c. In particular, the intentionally damaged semiconductor body 50 has an amorphous structure or a disordered crystal structure or a lattice structure that does not have spatial symmetry with the non-intentionally damaged portion of the semiconductor body 50. The channeling effect is altered by the presence of the damaged regions 80 a-80 c and the presence of the mask surface layer disposed on the front side 50 a of the semiconductor body 50.

[0065] The advantages of the present disclosure are apparent from the foregoing description. In particular, according to the present disclosure, Figure 4 The use of a hard mask in step S3 is unnecessary. In addition, the formation of the edge termination regions 58, 68 does not require the use of high energy and high dose ion implantation to achieve the desired depth and conductivity.

[0066] Finally, it is evident that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.

[0067] For example, the present disclosure is also applicable to electronic devices other than vertical channel MOSFETs, such as horizontal channel MOSFETs, trench FETs, diodes, triristors, MESFETs, MISFETs, and IGBTs.

[0068] Furthermore, the semiconductor body 50 may be made of a material other than SiC, such as GaN.

[0069] Furthermore, the semiconductor body 50 may include a substrate of semiconductor material (SiC, GaN, etc.) and optionally one or more epitaxial surface layers grown on the substrate.

[0070] Furthermore, in one embodiment, Figure 3 and Figure 5 The illustrated body region 51 (i.e., the body region that is directly electrically connected to the first edge termination region 58) does not accommodate the source region 52. In fact, in this embodiment, the illustrated body region 51 extends to the boundary with the edge region 36, i.e., near the region of the device 40 that is designed not to participate in electrical conduction; the absence of the source region prevents charge carriers (conduction current) from flowing to the edge region 36.

[0071] Furthermore, as previously described, the second edge termination region 68 may include only two sub-regions, such as only sub-regions 68a and 68b. In this case, there is only one damaged region (damaged region 80a) extending between sub-regions 68a and 68b.

[0072] Optionally, the MOSFET 40 (or other device manufactured according to the present disclosure) may further include a current spreading layer (CSL) 70 extending into the semiconductor body 50 facing the front side 50a. Figure 5 , which is Figure 3 Corresponding elements are identified with the same reference numerals and are not described further. The CSL 70 has a maximum thickness T along the Z axis comprised between 0.3 and 2 μm (inclusive). CSL_MAX (Starting from front side 50a). Generally, the depth of CSL 70 is equal to the depth of body 51 or extends below body 51 up to a value of 1 μm. In one embodiment, the maximum depth reached by CSL 70 is greater than the maximum depth reached by body region 51. Therefore, in this case, body region 51 is completely contained within CSL 70. CSL 70 forms a conductive layer having an improved on-resistance (referred to as R on ) value. The doping of CSL 70 is greater than that of semiconductor body 50. CSL 70 has a doping value of, for example, about 10 17 atoms / cm 3 The CSL 70 may have a doping level of the order of magnitude, or include a doping between 2 and 20 times the doping of the portion of the semiconductor body 50 housing it. The CSL 70 may have a thickness along the Z axis starting from the front side 50a that is uniform or non-uniform. In particular, the CSL 70 may be formed in the active region 34 (where it performs its R reduction function). on The CSL 70 has a maximum thickness in the portion of the second edge termination region 68 and a lower thickness in the portion of the second edge termination region 68. The CSL 70 may be formed by using channeling ion implantation.

Claims

1. An electronic device comprising: a semiconductor body having a first conductivity and a first doping value and provided with a front side, wherein the semiconductor body is made of a material having a lattice structure with spatial symmetry; an active region configured to accommodate, in use, a conductive channel of the electronic device; an edge region surrounding the active region and being structurally continuous with the active region and at least partially accommodating: a first edge termination region having a second conductivity opposite to the first conductivity and extending from the front side into the semiconductor body, the first edge termination region comprising at least a first sub-region and a second sub-region having the second conductivity and separated from each other by a portion of the semiconductor body having the first conductivity; as well as A damaged region extends between the first sub-region and the second sub-region at the portion of the semiconductor body facing the front side, the damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry.

2. The electronic device according to claim 1 , wherein the first sub-region and the second sub-region of the first edge termination region start from the front side and extend along a first direction orthogonal to the front side to respective maximum depths, the maximum depths being comprised between 1 and 5 μm, and the maximum depths of the first sub-region and the second sub-region are equal to each other. 3 . The electronic device according to claim 2 , wherein the first sub-region and the second sub-region of the first edge termination region have respective extensions different from each other along a second direction orthogonal to the first direction. 4 . The electronic device according to claim 1 , wherein the first sub-region and the second sub-region of the first edge termination region have doping values ​​that are uniform to each other.

5. The electronic device of claim 1 , wherein the active region comprises a body region having the second conductivity, wherein The first sub-region of the first edge termination region is electrically connected to the body region and has a doping that is higher than a corresponding doping of the body region.

6. The electronic device of claim 5 , further comprising a second edge termination region having the second conductivity and extending between the first sub-region and the body region of the first edge termination region, wherein the first sub-region in the edge termination region is electrically continuous with the second edge termination region.

7. The electronic device according to claim 5, wherein the second sub-region extends to a distance from the body region along the second direction, the distance being greater than a corresponding distance between the first sub-region and the body region, and The second sub-region has an extension along the second direction which is smaller than the corresponding extension of the first sub-region.

8. The electronic device of claim 6, wherein the second edge termination region has a higher doping than the first edge termination region and is in direct electrical contact with the body region, and The first sub-region of the first edge termination region is in direct electrical contact with the second edge termination region.

9. The electronic device of claim 1, wherein the damaged region contains non-reactive or non-doping ionic species, such as Si, Ar, Ge, He. 10 . The electronic device of claim 1 , wherein the damaged region extends from the front side into the semiconductor body along a first direction to a maximum depth that is lower than a maximum depth of the first edge termination region. The electronic device according to claim 10 , wherein the depth of the damaged region is between 0.1 and 0.6 μm. 12 . The electronic device according to claim 1 , wherein the semiconductor body is made of silicon carbide of 3C-SiC, 4H-SiC, or 6H-SiC.

13. A method for manufacturing an electronic device, comprising: Arranging a semiconductor body having a first conductivity and a first doping value and provided with a front side, wherein the semiconductor body is made of a material having a lattice structure with spatial symmetry, the semiconductor body having an active region and an edge region, the active region being configured to accommodate a conductive channel of an electronic device in use, the edge region surrounding the active region and being structurally continuous with the active region, forming a damaged region having an amorphous lattice structure or a lattice structure without spatial symmetry at a portion of the front side; forming a first edge termination region having a second conductivity opposite to the first conductivity in the semiconductor body starting from the front side, comprising: A channeling implantation of a dopant species having a second conductivity is performed at the damaged region and at portions of the semiconductor body adjacent to opposite sides of the damaged region. 14 . The method of claim 13 , wherein the channeling implantation results in the formation of at least a first sub-region and a second sub-region, the first sub-region and the second sub-region having the second conductivity, separated from each other by the portion of the semiconductor body. 15 . The method according to claim 14 , wherein the first and second sub-regions start from the front side and extend along a first direction orthogonal to the front side to respective maximum depths comprised between 1 and 5 μm, and the maximum depths of the first and second sub-regions are equal to each other.

16. The method of claim 13, wherein forming the damaged region comprises performing an implantation of a non-reactive or non-doping ion species of Si, Ar, Ge, or He, The injection energy is between 30keV and 300keV, and The injection dose is about 10 13 atoms / cm 2 . The method of claim 13 , wherein forming the damaged region comprises performing etching. 18 . The method according to claim 13 , wherein forming the damaged region comprises forming the damaged region having a maximum depth value comprised between 0.1 and 0.6 μm.

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