Super junction structure and preparation method thereof

Abstract

The invention provides a super junction structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, forming an N-type epitaxial layer on the substrate, forming a groove in one surface, far away from the substrate, of the N-type epitaxial layer, and forming a P-type conductive column, the P-type conductive column comprises a main body part filled in the groove, a first protruding part extending from the bottom surface of the groove to the N-type epitaxial layer, and a second protruding part extending from the preset position of the side wall of the groove to the N-type epitaxial layer. The first protruding part and the second protruding part are arranged at an interval. According to the preparation method of the super junction structure, monocrystalline silicon with specified impurity concentration is backfilled through multiple times of P-type ion implantation at different angles and a one-time silicon epitaxial filling process, and the protruding parts are formed at the bottom and the side wall of the P-type conductive column, so that the adverse effect of the abrupt change boundary of the P-type conductive column can be reduced, depletion can be assisted, and the breakdown voltage of a device can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing and relates to a super junction structure and a preparation method thereof. Background Art

[0002] The development of semiconductor power devices has long been constrained by the "silicon limit." By introducing a superjunction structure with alternating P- and N-type pillars, semiconductor power devices can achieve a high breakdown voltage while maintaining low on-resistance, thus breaking through the "silicon limit" of traditional silicon-based devices. However, in existing superjunction structures, a sharp doping change occurs at the interface where the P-type and N-type semiconductor pillars alternate, forming an abrupt boundary. This abrupt boundary affects the electric field distribution, potentially leading to electric field concentration and, in turn, reducing the device's breakdown voltage.

[0003] Therefore, how to provide a super junction structure and its preparation method to reduce the adverse effects of the abrupt boundary, assist depletion, and effectively improve the breakdown voltage of the device has become an important problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a super junction structure and a preparation method thereof, which is used to solve the problem in the prior art that there is a sudden boundary at the interface where P-type and N-type semiconductor columns are alternately arranged, resulting in a decrease in the breakdown voltage of the device.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a superjunction structure, comprising:

[0007] Providing a substrate, and forming an N-type epitaxial layer on the substrate;

[0008] forming a groove on a side of the N-type epitaxial layer away from the substrate;

[0009] A P-type conductive column is formed, wherein the P-type conductive column includes a main body filled in the groove, a first protrusion extending from the bottom surface of the groove into the N-type epitaxial layer, and a second protrusion extending from a preset position on the side wall of the groove into the N-type epitaxial layer, wherein the first protrusion and the second protrusion are spaced apart.

[0010] Optionally, forming the P-type conductive pillar includes the following steps:

[0011] Performing a first P-type ion implantation to form the first protrusion at the bottom of the groove;

[0012] Performing a second P-type ion implantation to form the second protrusion on the sidewall of the groove;

[0013] Silicon epitaxy is performed to form a P-type silicon epitaxial layer filling the groove. The P-type silicon epitaxial layer, the first protrusion, and the second protrusion together constitute the P-type conductive column.

[0014] Optionally, an angle θ is formed between the ion implantation direction of the second P-type ion implantation and the sidewall of the groove, and the angle θ is in the range of 0°<θ<90°.

[0015] Optionally, the second P-type ion implantation is performed multiple times, and the angles θ used in the multiple second P-type ion implantations are different to obtain multiple second protrusions, and the multiple second protrusions are located at different heights of the groove side wall and are spaced apart.

[0016] Optionally, the silicon epitaxy adopts an in-situ doping epitaxy process, and the epitaxy temperature adopted by the in-situ doping epitaxy process is greater than 950°C.

[0017] Optionally, the material of the P-type conductive column includes diborane.

[0018] Optionally, the boron ion doping concentration of the P-type conductive pillar is less than 1×10 18 cm -3 .

[0019] Optionally, there are multiple P-type conductive pillars, and the multiple P-type conductive pillars are arranged at equal intervals in the N-type epitaxial layer, and all the P-type conductive pillars have the same width.

[0020] The present invention also provides a super junction structure, comprising:

[0021] An N-type epitaxial layer having a first surface and a second surface opposite to each other;

[0022] A plurality of P-type conductive pillars are located in the N-type epitaxial layer and are spaced apart. Each of the P-type conductive pillars has a main body, a first protrusion, and a second protrusion. The main body starts from the first surface of the N-type epitaxial layer and extends toward the second surface of the N-type epitaxial layer. The first protrusion is located at the bottom of the main body, and the second protrusion is located on the side wall of the main body and is spaced apart from the first protrusion.

[0023] Optionally, each of the P-type conductive pillars has a plurality of second protrusions located at different heights, and the plurality of second protrusions are distributed at intervals.

[0024] As described above, the method for fabricating a superjunction structure of the present invention includes providing a substrate, forming an N-type epitaxial layer on the substrate, forming a groove on a surface of the N-type epitaxial layer away from the substrate, and forming a P-type conductive pillar. The P-type conductive pillar includes a main portion filled in the groove, a first protrusion extending from the bottom surface of the groove into the N-type epitaxial layer, and a second protrusion extending from a predetermined position on the sidewall of the groove into the N-type epitaxial layer, with the first protrusion and the second protrusion being spaced apart. The method for fabricating a superjunction structure of the present invention uses multiple P-type ion implantations at different angles and a single silicon epitaxial filling process to backfill single crystal silicon with a specified impurity concentration, forming protrusions at the bottom and sidewalls of the P-type conductive pillar. This can reduce the adverse effects of the abrupt boundary of the P-type conductive pillar, assist depletion, and effectively improve the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a process flow chart of the method for preparing a super junction structure of the present invention.

[0026] Figure 2 It is a schematic diagram showing the structure obtained after providing a substrate and forming an epitaxial layer in the method for preparing a super junction structure of the present invention.

[0027] Figure 3 It is a schematic diagram showing the structure obtained after forming grooves in the method for preparing a super junction structure of the present invention.

[0028] Figure 4 It is a schematic diagram showing the structure obtained after forming a P-type conductive column in the method for preparing a super junction structure of the present invention.

[0029] Figure 5 It is a schematic diagram showing the structure obtained after forming the first protrusion in the method for preparing a super junction structure of the present invention.

[0030] Figure 6 FIG. 1 is a schematic diagram showing a structure obtained after forming a second protrusion in the method for preparing a super junction structure of the present invention.

[0031] Figure 7 Another schematic diagram of the structure obtained after forming the second protrusion in the method for preparing the super junction structure of the present invention is shown.

[0032] Figure 8 A schematic diagram showing simulation results of the steps of the method for preparing a super junction structure of the present invention is shown.

[0033] Description of Reference Numerals

[0034] 1 substrate

[0035] 2 Epitaxial layer

[0036] 3 grooves

[0037] 4 P-type conductive pillars

[0038] 401 Main body

[0039] 402 First protrusion

[0040] 403 Second protrusion

[0041] Steps S1 to S3 DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0044] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0045] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0046] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0047] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] See also Figure 1 , which is a process flow chart of a method for preparing a super junction structure of the present invention, comprising the following steps:

[0050] S1: providing a substrate, and forming an N-type epitaxial layer on the substrate;

[0051] S2: forming a groove on a side of the N-type epitaxial layer away from the substrate;

[0052] S3: Form a P-type conductive column, wherein the P-type conductive column includes a main body filled in the groove, a first protrusion extending from the bottom surface of the groove into the N-type epitaxial layer, and a second protrusion extending from a preset position of the side wall of the groove into the N-type epitaxial layer, wherein the first protrusion and the second protrusion are spaced apart.

[0053] The following will be combined Figures 2 to 7 , detailing each step of the method for preparing the super junction structure of the present invention.

[0054] First see Figure 2 , performing step S1: providing a substrate 1 and forming an N-type epitaxial layer 2 on the substrate 1 .

[0055] As an example, the substrate 1 can be a silicon substrate 1, a strained silicon substrate 1, a germanium substrate 1, a germanium silicon substrate 1, a silicon carbide substrate 1, a III-V compound substrate 1, etc., and is not limited to the examples listed above. The thickness of the substrate 1 ranges from 50μm to 800μm. For example, the thickness of the substrate 1 can be 80μm, 120μm, 300μm, 600μm or 750μm.

[0056] As an example, the material of the epitaxial layer 2 includes silicon material, that is, the epitaxial growth of the substrate 1 is performed using silicon material epitaxy.

[0057] See also Figure 3 , executing step S2: forming a groove 3 on a side of the N-type epitaxial layer 2 away from the substrate 1 .

[0058] As an example, there are multiple grooves 3 , and the multiple grooves 3 are arranged at equal intervals in the N-type epitaxial layer 2 .

[0059] As an example, the bottom surface of the groove 3 may be in an arc shape, such as a hemispherical shape.

[0060] As an example, the etching aspect ratio of the groove 3 can be determined according to specific circumstances, and no further restrictions are imposed here.

[0061] See also Figure 4 , perform step S3: form a P-type conductive column 4, the P-type conductive column 4 includes a main body 401 filled in the groove, a first protrusion 402 extending from the bottom surface of the groove 3 into the N-type epitaxial layer 2, and a second protrusion 403 extending from a preset position on the sidewall of the groove 3 into the N-type epitaxial layer 2, the first protrusion 402 and the second protrusion 403 are arranged at intervals.

[0062] Specifically, the presence of the first protrusion 402 and the second protrusion 403 can destroy the abrupt boundary structure between the P-type conductive pillar 4 and the N-type epitaxial layer 2, thereby reducing the impact of the abrupt boundary structure on the superjunction structure device, assisting depletion, and thus effectively improving the breakdown voltage of the superjunction structure device, enabling the superjunction structure device to achieve better electrical performance. Specifically, the first protrusion 402 and the second protrusion 403 can assist in depleting the N-type epitaxial layer 2 around the P-type conductive pillar 4, allowing the superjunction device to have a higher breakdown voltage while maintaining low on-resistance.

[0063] As an example, forming the P-type conductive pillar 4 that completely fills the groove 3 includes the following steps:

[0064] (1) Please refer to Figure 5 , performing a first P-type ion implantation to form the first protrusion 402 at the bottom of the groove 3;

[0065] (2) Please refer to Figure 6 , performing a second P-type ion implantation to form the second protrusion 403 on the sidewall of the groove 3;

[0066] (3) Please refer to Figure 4 , silicon epitaxy is performed to form a P-type silicon epitaxial layer filling the groove 3. The P-type silicon epitaxial layer, the first protrusion 402 and the second protrusion 403 together constitute the P-type conductive column 4. It should be pointed out that the P-type silicon epitaxial layer fills the groove 3 to form the main body 401 of the P-type conductive column 4.

[0067] Specifically, the shapes of the first protrusion 402 and the second protrusion 403 can be arc-shaped, such as spherical, teardrop-shaped or ellipsoidal. In this embodiment, the shapes of the first protrusion 402 and the second protrusion 403 are preferably teardrop-shaped.

[0068] As an example, the ion implantation direction of the second P-type ion implantation forms an angle θ with the side wall of the groove 4 , and the angle θ ranges from 0°<θ<90°, for example, the angle θ is 15°, 45°, 60° or 75°.

[0069] As an example, the second P-type ion injection is performed multiple times, and the angles θ used in the multiple second P-type ion injections are different to obtain multiple second protrusions 403, and the multiple second protrusions 403 are located at different heights of the side wall of the groove 4 and are arranged at intervals.

[0070] Specifically, the spacing between each second protrusion 403 and the adjacent second protrusion 403 can be the same or different, depending on the specific situation, and is not limited here. Figure 7 The second P-type ion implantation is performed twice, and the angles θ of the two second P-type ion implantations are different. The angles θ are 15° and 45° respectively, forming two second protrusions 403 distributed at intervals.

[0071] As an example, the silicon epitaxy adopts an in-situ doping epitaxy process, and the epitaxy temperature adopted by the in-situ doping epitaxy process is greater than 950°C.

[0072] As an example, annealing is required before and after forming the P-type epitaxial layer. Specifically, the structure is annealed after the first and second P-type ion implantations, and again after forming the P-type epitaxial layer.

[0073] As an example, the material of the P-type conductive pillar 4 includes diborane.

[0074] As an example, the boron ion doping concentration of the P-type conductive pillar 4 is less than 1×10 18 cm -3 .

[0075] As an example, there are multiple P-type conductive pillars 4 , and the multiple P-type conductive pillars 4 are arranged at equal intervals in the N-type epitaxial layer 2 , and all the P-type conductive pillars 4 have the same width.

[0076] At this point, a super junction structure is prepared, which includes an N-type epitaxial layer 2 and multiple P-type conductive pillars 4, wherein the N-type epitaxial layer 2 has a first surface and a second surface relative to each other, and the multiple P-type conductive pillars 4 are located in the N-type epitaxial layer 2 and are spaced apart. Each of the P-type conductive pillars 4 has a main body 401, a first protrusion 402 and a second protrusion 403, and the main body 401 starts from the first surface of the N-type epitaxial layer 2 and extends toward the second surface of the N-type epitaxial layer 2. The first protrusion 402 is located at the bottom of the main body 401, and the second protrusion 403 is located on the side wall of the main body 401 and is spaced apart from the first protrusion 402.

[0077] Specifically, each of the P-type conductive pillars 4 has a plurality of second protrusions 403 at different heights, and the plurality of second protrusions 403 are distributed at intervals.

[0078] It should be noted that the type of the super junction structure application device can be a semiconductor power device or other types of devices, and no excessive restrictions are imposed here.

[0079] See also Figure 8 , which is a schematic diagram showing the simulation results of the steps of the method for preparing the super junction structure of the present invention, wherein, Figure 8 (a) corresponds to the above step S2, Figure 8 (b) Figure 8 (c) Figure 8 (d) The specific steps corresponding to completing the above step S3, Figure 8 (e) After completing the above step S3, an annealing step is performed. Specifically, Figure 8 (a) refers to forming the groove 3, Figure 8 (b) refers to performing the first P-type ion implantation on the bottom surface of the groove 3, Figure 8 (c) refers to performing the second P-type ion implantation on the sidewall of the groove 3, Figure 8 (d) refers to completely filling the groove 3 with silicon epitaxy, Figure 8 (e) refers to annealing the structure obtained in the above steps.

[0080] In summary, the preparation method of the present invention includes providing a substrate, forming an N-type epitaxial layer on the substrate, forming a groove on the side of the N-type epitaxial layer away from the substrate, and forming a P-type conductive column, wherein the P-type conductive column includes a main body filled in the groove, a first protrusion extending from the bottom surface of the groove into the N-type epitaxial layer, and a second protrusion extending from a preset position on the sidewall of the groove into the N-type epitaxial layer, wherein the first protrusion and the second protrusion are spaced apart. The preparation method of the superjunction structure of the present invention forms protrusions on the bottom and sidewalls of the P-type conductive column by backfilling single crystal silicon with a specified impurity concentration through multiple P-type ion implantations at different angles and a silicon epitaxial filling process. This can reduce the adverse effects of the abrupt boundary of the P-type conductive column, assist depletion, and effectively improve the breakdown voltage of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a super junction structure, characterized in that: include: Providing a substrate, and forming an N-type epitaxial layer on the substrate; forming a groove on a side of the N-type epitaxial layer away from the substrate; A P-type conductive column is formed, wherein the P-type conductive column includes a main body filled in the groove, a first protrusion extending from the bottom surface of the groove into the N-type epitaxial layer, and a second protrusion extending from a preset position on the side wall of the groove into the N-type epitaxial layer, wherein the first protrusion and the second protrusion are spaced apart.

2. The method for preparing a super junction structure according to claim 1, wherein: Forming the P-type conductive pillar includes the following steps: Performing a first P-type ion implantation to form the first protrusion at the bottom of the groove; Performing a second P-type ion implantation to form the second protrusion on the sidewall of the groove; Silicon epitaxy is performed to form a P-type silicon epitaxial layer filling the groove. The P-type silicon epitaxial layer, the first protrusion, and the second protrusion together constitute the P-type conductive column.

3. The method for preparing a super junction structure according to claim 2, wherein: An included angle θ is formed between the ion implantation direction of the second P-type ion implantation and the sidewall of the groove, and the angle θ is in the range of 0°<θ<90°.

4. The method for preparing a super junction structure according to claim 2, wherein: The second P-type ion implantation is performed multiple times, and the angles θ used in the multiple second P-type ion implantations are different to obtain multiple second protrusions. The multiple second protrusions are located at different heights of the groove sidewall and are spaced apart.

5. The method for preparing a super junction structure according to claim 2, wherein: The silicon epitaxy adopts an in-situ doping epitaxy process, and the epitaxy temperature adopted by the in-situ doping epitaxy process is greater than 950°C.

6. The method for preparing a super junction structure according to claim 1, wherein: The material of the P-type conductive pillar includes diborane.

7. The method for preparing a super junction structure according to claim 1, wherein: The boron ion doping concentration of the P-type conductive column is less than 1×10 18 cm -3 .

8. The method for preparing a super junction structure according to claim 1, wherein: There are multiple P-type conductive pillars, and the multiple P-type conductive pillars are arranged at equal intervals in the N-type epitaxial layer, and all the P-type conductive pillars have the same width.

9. A super junction structure, characterized in that: include: An N-type epitaxial layer having a first surface and a second surface opposite to each other; A plurality of P-type conductive pillars are located in the N-type epitaxial layer and are spaced apart. Each of the P-type conductive pillars has a main body, a first protrusion, and a second protrusion. The main body starts from the first surface of the N-type epitaxial layer and extends toward the second surface of the N-type epitaxial layer. The first protrusion is located at the bottom of the main body, and the second protrusion is located on the side wall of the main body and is spaced apart from the first protrusion.

10. The super junction structure according to claim 9, wherein: Each of the P-type conductive pillars has a plurality of second protrusions located at different heights, and the plurality of second protrusions are distributed at intervals.

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