SiC MOSFET gate oxide preparation method based on transfer

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) gate oxide preparation method based on transfer, and relates to the technical field of semiconductors. By transferring the high-quality gate dielectric layer to the target substrate, the problems of overhigh interface state density and the like caused by SiC / SiO2 interface carbon residue formed by thermal oxidation of silicon carbide can be effectively avoided, so that a high-quality and high-reliability SiC MOSFET device is obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing SiC MOSFET gate oxide based on transfer. Background Art

[0002] In recent years, wide bandgap semiconductor devices represented by silicon carbide have received widespread attention. SiC materials have a large bandgap (3.26 eV), high thermal conductivity (3.3-4.9 W cm -1 K -1 ), the breakdown field is strong (3MV / cm), the saturation drift rate is high (2×10 7 cm / s), making it an ideal material for high-temperature, high-frequency, high-power, and radiation-resistant devices. SiC MOSFET, a unipolar device with an insulated gate structure, offers numerous advantages, including low switching losses, high frequency, and fast speed. It is now widely used in key fields such as new energy vehicles, rail transportation, power systems, photovoltaic power generation, and aerospace.

[0003] Currently, SiC MOSFETs have found initial application in new energy vehicles, photovoltaics, and wind power. However, significant obstacles remain in their mass production. Numerous studies have shown that the high interface state density of the SiO2 / SiC structure leads to low inversion layer mobility and specific on-resistance in SiC MOSFETs, and gate-oxide-related reliability issues under harsh operating conditions. This severely limits device performance improvements and cost reductions, and has become one of the biggest bottlenecks hindering SiC MOSFET technology upgrades and large-scale industrial applications.

[0004] In recent years, academia and industry have conducted systematic research on the above-mentioned gate oxide problem. By continuously improving the thermal oxidation process and post-treatment process, the current conduction band edge SiC / SiO2 interface state trap density has generally dropped to 10 12 eV -1 cm -2 There is still a big gap from silicon-based devices. Studies have shown that carbon clusters are inevitably generated during the thermal oxidation of SiC. This is probably the fundamental reason why the interface optimization based on the thermal oxidation SiC process has never significantly reduced the interface state density of the SiC MOS structure. Some means are expected to avoid the thermal oxidation of SiC during the gate oxide preparation process, thereby inhibiting the generation of carbon clusters. Its feasibility in preparing high-quality SiCMOS structures has been preliminarily verified experimentally. For example, in 2020, the research group of T. Kimoto at Kyoto University in Japan prepared SiO2 by depositing Si and then oxidizing Si at 750°C. Combined with high-temperature N2 annealing at 1600°C, the interface state density was achieved as low as 1.8×10 10 eV -1 cm -2The interface state density of the SiO2 / SiC interface is higher than that of the MOS structure prepared by thermal oxidation of SiC at 1300℃ in the same work (2×10 12 eV -1 cm -2 At Ec -0.3 eV, it's two orders of magnitude lower. However, high-quality single-crystalline Si is difficult to obtain using deposition methods. Furthermore, the low-temperature oxidation process at 750°C significantly sacrifices oxidation speed, making it difficult to ensure complete oxidation of the Si while completely preserving the SiC. This makes future industrial applications highly unlikely. Furthermore, its gate oxide reliability and applicability in practical devices require further study. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the present invention provides the following technical solutions: In a first aspect, the present invention provides a method for preparing SiC MOSFET gate oxide based on transfer, comprising the following steps: S1, forming a SiO2 gate oxide film on the Si surface; S2, transferring the SiO2 gate oxide layer film to the surface of the SiC epitaxial wafer to obtain a SiC wafer with a gate oxide layer; S3. Bonding and annealing the SiC wafer with the gate oxide layer to obtain the SiC MOSFET gate oxide.

[0006] In one embodiment, step S1 includes: (a) Perform standard RCA cleaning on the Si wafer surface; (b) Place the cleaned Si wafer in step (a) into a high-temperature oxidation furnace, introduce oxygen and water vapor, and control the oxidation temperature between 750°C and 1000°C for 15 to 45 minutes. (c) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (d) Place the Si wafer in a high-temperature oxidation furnace and introduce oxygen to form a thin film oxide layer on the surface of the Si wafer.

[0007] In one embodiment, the purity of the oxygen is not less than 99.99999%.

[0008] In one embodiment, step (d) includes placing the Si wafer in a high-temperature oxidation furnace, introducing oxygen, and growing a thin film oxide layer on the surface of the Si wafer at a temperature of T1 for a growth time of t1; wherein T1 is in the range of 800°C ≤ T1 ≤ 1200°C, and the growth time t1 is 20 minutes ≤ t1 ≤ 60 minutes. Optionally, but not limiting of this, T1 is 1100°C, and the growth time t1 is 30 minutes.

[0009] By adjusting T1 and t1, those skilled in the art can adjust the thickness of the SiO2 oxide layer.

[0010] In one embodiment, step S2 includes: (e) planarizing the surface of the SiC epitaxial wafer; (f) The gate oxide film is transferred from the Si wafer to the surface of the SiC epitaxial wafer through smart peeling, support layer assisted transfer, surface activation and wafer bonding processes to obtain a SiC wafer with a gate oxide layer.

[0011] In one embodiment, the bonding annealing in step S3 is performed in a nitrogen atmosphere at a temperature of T2 and a treatment time of t2; the range of T2 is: 850°C ≤ T2 ≤ 1200°C, and the treatment time t2 is: 30 min ≤ t2 ≤ 60 min. Optionally, but not limiting, T2 is 1000°C and the treatment time t2 is 45 min.

[0012] In one embodiment, the SiC epitaxial wafer has a planar or trench structure.

[0013] In one embodiment, the SiC epitaxial wafer has a groove structure, and the steps between step S2 and step S3 further include: treating the SiC epitaxial wafer with a hydrophobic agent, casting a soft photoresist material onto a Si mold, baking, and peeling the soft photoresist material from the Si mold to produce a T-shaped mold having the same structure as the SiC wafer.

[0014] In one embodiment, the hydrophobic agent includes hexamethyldisilazane (HDMS) or octadecyltrichlorosilane (OTS).

[0015] In one embodiment, the soft lithography material includes polydimethylsiloxane (PDMS), RTV silicone, polyurethane elastomer, or hexamethyldisilazane (HDMS).

[0016] In one embodiment, the planarization process includes, but is not limited to, chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, or plasma activation.

[0017] In one embodiment, the step S2 comprises the following steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) placing the Si wafer treated in step (a) in a high-temperature oxidation furnace at an annealing temperature of 350-450°C for 30-60 min, and then cooling to room temperature; (c) Spin coating the support layer material on the Si wafer surface; (d) The wafer is flipped over and then heated to 50-100°C, applying an outward pull to the surface of the Si wafer to peel off the excess silicon wafer along the hydrogen ion layer; (e) Placing the Si wafer in a TMAH solution and removing the remaining silicon wafer by wet etching, leaving only the oxide layer and the support layer, to obtain a complete SiO2 composite gate dielectric; (f) Aligning the SiO2 composite gate dielectric and the SiC wafer and tightly fitting them together at room temperature to complete pre-bonding; (g) Remove the support layer material and retain the SiO2 gate oxide layer.

[0018] In one embodiment, the step S2 comprises the following steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen impurities into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The two wafers are placed in a wafer bonder for bonding and heated to 400-600°C. The hydrogen ion layer generates bubbles that separate the wafers along the hydrogen ion layer. (c) The wafer is placed in a TMAH solution and the remaining silicon wafer is removed by wet etching, leaving only the oxide layer and the support layer, obtaining a SiC wafer with an oxide layer on the surface.

[0019] In one embodiment, the position of the hydrogen ion implantation layer can be achieved by regulating the hydrogen ion concentration and the implantation depth.

[0020] In one embodiment, the support layer material comprises a material that exhibits good support properties after curing and can be cleaned with organic solvents or decomposed at high temperatures. Optional, but not limiting, materials include polymethyl methacrylate (PMMA), polydimethylsiloxane (PDMS), polyvinyl alcohol (PVA), poly-L-lactic acid (PLLA), or ethylene-vinyl acetate copolymer (EVA). PMMA is further optional.

[0021] In one embodiment, the concentration of the TMAH solution in step S40 is 20% to 30%, the etching temperature is 60 to 80° C., and the etching time is controlled within the range of 2 hours. The specific time is adjusted according to the thickness of the Si substrate, and the back is further thinned until the sacrificial substrate is completely removed.

[0022] In a second aspect, the present invention further provides a SiC MOSFET gate oxide prepared by the method described in the first aspect.

[0023] In a third aspect, the present invention further provides application of the method described in the first aspect in the field of semiconductor preparation.

[0024] In one embodiment, the application includes application of the method in preparation of SiC MOSFET gate oxide.

[0025] It should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features described in detail below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be listed here one by one.

[0026] Compared with the prior art, the present invention has the following beneficial effects: This invention effectively suppresses the formation of interface traps and oxide traps during the thermal oxidation process by transferring a high-quality SiO2 gate dielectric generated by thermal oxidation of single-crystal silicon. Compared to traditional silicon carbide thermal oxidation insulating layers, the SiC / SiO2 formed by gate dielectric transfer also improves the gate control capability of SiC MOSFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic structural diagram of the SiC insulating gate dielectric prepared by the method described in Example 1 and the elements involved in the steps.

[0028] Figure 2 This is a schematic structural diagram of the SiC insulating gate dielectric prepared by the method described in Example 2 and the elements involved in the steps.

[0029] Figure 3 This is a schematic structural diagram of the SiC insulating gate dielectric prepared by the method described in Example 3 and the elements involved in the steps.

[0030] Explanation of the accompanying figures: 1: silicon wafer; 2: sacrificial oxide layer; 3: silicon dioxide oxide layer; 4: hydrogen ion layer; 5: support layer; 6: SiC substrate; 7: SiC epitaxy; 8: mold. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with specific embodiments. The examples provided are only for illustrating the present invention and are not intended to limit the scope of the present invention. The examples provided below can serve as a guide for further improvements by those of ordinary skill in the art and are not intended to limit the present invention in any way.

[0032] In the present invention, the term "about" or "approximately" should be understood to include all numerical values ​​within the allowed measurement error range.

[0033] Unless otherwise specified, the experimental methods in the following examples are conventional methods and were performed according to the techniques or conditions described in the literature in the field or according to the product instructions. The materials and reagents used in the following examples, unless otherwise specified, were all commercially available. Example: Example 1

[0034] A method for preparing SiC MOSFET gate oxide based on transfer, comprising: S10: Perform standard RCA cleaning on the Si wafer surface; S20: Perform sacrificial oxidation, etching, and high-temperature oxidation on the cleaned Si wafer to form a gate oxide film, which specifically includes the following sub-steps: (a) Place the cleaned Si wafer in a high-temperature oxidation furnace, introduce oxygen and water vapor, control the oxidation temperature at 750-1000°C, and the oxidation time at 15-45 minutes; (b) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (c) The Si wafer is placed in a high-temperature oxidation furnace and ultra-high purity oxygen (99.99999%) is introduced. A thin film oxide layer is formed on the surface of the Si wafer at a temperature of T1 for a growth time of t1. S30: performing chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, and plasma activation on the surface of the SiC epitaxial wafer in sequence; S40: Transferring the gate oxide film from the Si wafer to the SiC epitaxial wafer surface through intelligent peeling technology, support layer assisted transfer, surface activation, and wafer bonding processes. This specifically includes the following sub-steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The Si wafer is then placed in a high-temperature oxidation furnace at an annealing temperature of 350-450°C for 30-60 minutes, followed by cooling to room temperature. (c) Spin-coating a support layer material, such as PMMA, PDMS, PVA, PLLA, EVA, or a polymer material similar to HRG, on the surface of the Si wafer. The support layer material is required to have good support after curing and be easily removed by washing with organic solvents or decomposition at high temperatures. In this example, PMMA is selected as the support layer material. (d) The Si wafer is flipped over and then heated to 50-100°C. An outward tensile force is applied to the surface of the Si wafer, thereby peeling off the excess silicon wafer along the hydrogen ion layer. (e) Placing the Si wafer in a TMAH solution and removing the remaining silicon wafer by wet etching, leaving only the oxide layer and the support layer. The TMAH solution has a concentration of 20% to 30%, the etching temperature is 60°C to 80°C, and the etching time is controlled within the range of 2 hours. The specific time is adjusted according to the thickness of the Si substrate. The back side is further thinned until the sacrificial substrate is completely removed to obtain a complete SiO2 composite gate dielectric. (f) Aligning the SiO2 composite gate dielectric and the S30-treated SiC epitaxial wafer at room temperature and then tightly fitting them together to complete pre-bonding; (g) PMMA is removed using acetone, leaving the SiO2 gate oxide layer intact; S50: performing post-bonding annealing on the SiC wafer with the gate oxide layer at a temperature T2 for a processing time of t2.

[0035] Based on the above embodiment, the T1 is 1100° C., the t1 is 30 min; the T2 is 1000° C., and the t2 is 45 min.

[0036] Figure 1 Schematic diagram of the structure of the planar SiC insulating gate dielectric realized based on this method. Example 2

[0037] A method for preparing SiC MOSFET gate oxide based on transfer, comprising: S10: Perform standard RCA cleaning on the Si wafer surface; S20: Perform sacrificial oxidation, etching, and high-temperature oxidation on the cleaned Si wafer to form a gate oxide film, which specifically includes the following sub-steps: (a) Place the cleaned Si wafer in a high-temperature oxidation furnace, introduce oxygen and water vapor, control the oxidation temperature at 750-1000°C, and the oxidation time at 15-45 minutes; (b) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (c) The Si wafer is placed in a high-temperature oxidation furnace and ultra-high purity oxygen (99.99999%) is introduced. A thin film oxide layer is formed on the surface of the Si wafer at a temperature of T1 for a growth time of t1. S30: First, the SiC trench was treated with hexamethyldisilazane (HMDS). Next, PDMS elastomer was cast onto the Si mold to a thickness of 2 mm, baked at 65 °C for 12 h, and peeled from the mold to produce a T-shaped PDMS mold with the same structure as the SiC wafer. S40: performing chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, and plasma activation on the surface of the SiC epitaxial wafer in sequence; S50: Transferring the gate oxide film from the Si wafer to the SiC epitaxial wafer surface through intelligent peeling technology, support layer assisted transfer, surface activation, and wafer bonding process. Specifically, it includes the following sub-steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The Si wafer is then placed in a high-temperature oxidation furnace at an annealing temperature of 350-450°C for 30-60 minutes, followed by cooling to room temperature. (c) Spin-coating a support layer material, such as PMMA, PDMS, PVA, PLLA, EVA, HRG, or similar polymer materials, on the surface of the Si wafer. The support layer material is required to have good support after curing and be easily removed by organic solvent cleaning or high-temperature decomposition. In this example, PMMA is selected as the support layer material. (d) The Si wafer is flipped over and then heated to 50-100°C. An outward tensile force is applied to the surface of the Si wafer, thereby peeling off the excess silicon wafer along the hydrogen ion layer. (e) Placing the Si wafer in a TMAH solution and removing the remaining silicon wafer by wet etching, leaving only the oxide layer and the support layer. The TMAH solution has a concentration of 20% to 30%, the etching temperature is 60°C to 80°C, and the etching time is controlled within the range of 2 hours. The specific time is adjusted according to the thickness of the Si substrate. The back side is further thinned until the sacrificial substrate is completely removed to obtain a complete SiO2 composite gate dielectric. (f) The SiO2 gate dielectric is transferred and released on top of the S30-treated SiC epitaxial wafer at room temperature, and the PDMS stamp is pushed into and completely embedded in the trench, thereby achieving close contact between the SiO2 gate dielectric and the vertical trench, completing pre-bonding; (g) PMMA is removed using acetone, leaving the SiO2 gate oxide layer intact; S60: performing post-bonding annealing on the SiC wafer with the gate oxide layer at a temperature T2 for a processing time of t2.

[0038] Based on the above embodiment, the T1 is 1100° C., the t1 is 30 min; the T2 is 1000° C., and the t2 is 45 min.

[0039] Figure 2 Schematic diagram of the structure of the trench SiC insulating gate dielectric realized based on this method. Example 3

[0040] A method for preparing SiC MOSFET gate oxide based on transfer, comprising: S10: Perform standard RCA cleaning on the Si wafer surface; S20: Perform sacrificial oxidation, etching, and high-temperature oxidation on the cleaned Si wafer to form a gate oxide film, which specifically includes the following sub-steps: (a) Place the cleaned Si wafer in a high-temperature oxidation furnace, introduce oxygen and water vapor, control the oxidation temperature at 750-1000°C, and the oxidation time at 15-45 minutes; (b) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (c) The Si wafer is placed in a high-temperature oxidation furnace and ultra-high purity oxygen (99.99999%) is introduced. A thin film oxide layer is formed on the surface of the Si wafer at a temperature of T1 for a growth time of t1. S30: performing chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, and plasma activation on the surface of the SiC epitaxial wafer in sequence; S40: Transferring the gate oxide film from the Si wafer to the SiC epitaxial wafer surface through intelligent peeling technology, support layer assisted transfer, surface activation, and wafer bonding processes. This specifically includes the following sub-steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The Si wafer and the SiC epitaxial wafer are placed in a wafer bonder for bonding. The wafers are heated to 400-600°C, and bubbles are generated in the hydrogen ion layer until sufficient stress is generated to separate the bonded SiC wafers along the hydrogen ion layer. (c) placing the SiC wafer in a TMAH solution and removing the remaining SiC wafer by wet etching, leaving only the oxide layer and the support layer; the concentration of the TMAH solution is 20% to 30%, the etching temperature is 60 to 80°C, and the etching time is controlled within the range of 2 hours, the specific time being adjusted according to the thickness of the Si substrate, and further thinning the back side until the sacrificial substrate is completely removed, thereby obtaining a SiC wafer with a SiO2 oxide layer on the surface; S50: performing post-bonding annealing on the SiC wafer with the gate oxide layer at a temperature T2 for a processing time of t2.

[0041] Based on the above embodiment, the T1 is 1100° C., the t1 is 30 min; the T2 is 1000° C., and the t2 is 45 min.

[0042] Figure 3 Schematic diagram of the structure of the planar SiC insulating gate dielectric realized based on this method. Comparative Example 1

[0043] S10: Perform standard RCA cleaning on the Si wafer surface; S20: Perform sacrificial oxidation, etching, and high-temperature oxidation on the cleaned Si wafer to form a gate oxide film, which specifically includes the following sub-steps: (a) Place the cleaned Si wafer in a high-temperature oxidation furnace, introduce oxygen and water vapor, control the oxidation temperature at 750-1000°C, and the oxidation time at 15-45 minutes; (b) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (c) The Si wafer is placed in a high-temperature oxidation furnace and ultra-high purity oxygen (99.99999%) is introduced. A thin film oxide layer is formed on the surface of the Si wafer at a temperature of T1 for a growth time of t1. S30: performing chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, and plasma activation on the surface of the SiC epitaxial wafer in sequence; S40: Transferring the gate oxide film from the Si wafer to the SiC epitaxial wafer surface through intelligent peeling technology, support layer assisted transfer, surface activation, and wafer bonding processes. This specifically includes the following sub-steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 4×10 16 cm -2 , the injection energy is 100~200keV; (b) The Si wafer is then placed in a high-temperature oxidation furnace at an annealing temperature of 350-450°C for 30-60 minutes, followed by cooling to room temperature. (c) Spin-coating a support layer material, such as PMMA, PDMS, PVA, PLLA, EVA, or a polymer material similar to HRG, on the surface of the Si wafer. The support layer material is required to have good support after curing and be easily removed by washing with organic solvents or decomposition at high temperatures. In this example, PMMA is selected as the support layer material. (d) The Si wafer is flipped over and then heated to 50-100°C. An outward tensile force is applied to the surface of the Si wafer. The Si wafer does not break along the hydrogen ion layer but rather cracks amorphously along the wafer tangentially. Based on the above embodiment, the T1 is 1100° C. and the t1 is 30 min. Comparative Example 2

[0044] A method for preparing SiC MOSFET gate oxide based on transfer, comprising: S10: Perform standard RCA cleaning on the Si wafer surface; S20: Perform sacrificial oxidation, etching, and high-temperature oxidation on the cleaned Si wafer to form a gate oxide film, which specifically includes the following sub-steps: (a) Place the cleaned Si wafer in a high-temperature oxidation furnace, introduce oxygen and water vapor, control the oxidation temperature at 750-1000°C, and the oxidation time at 15-45 minutes; (b) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (c) The Si wafer is placed in a high-temperature oxidation furnace and ultra-high purity oxygen (99.99999%) is introduced. A thin film oxide layer is formed on the surface of the Si wafer at a temperature of T1 for a growth time of t1. S30: performing chemical mechanical polishing, ultrasonic cleaning, standard RCA cleaning, and plasma activation on the surface of the SiC epitaxial wafer in sequence; S40: Transferring the gate oxide film from the Si wafer to the SiC epitaxial wafer surface through intelligent peeling technology, support layer assisted transfer, surface activation, and wafer bonding processes. This specifically includes the following sub-steps: (a) Place the Si wafer into the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the wafer with an implantation concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The Si wafer is then placed in a high-temperature oxidation furnace at an annealing temperature of 250-300°C for 40-60 minutes, followed by cooling to room temperature. (c) Spin-coating a support layer material, such as PMMA, PDMS, PVA, PLLA, EVA, or a polymer material similar to HRG, on the surface of the Si wafer. The support layer material is required to have good support after curing and be easily removed by washing with organic solvents or decomposition at high temperatures. In this example, PMMA is selected as the support layer material. (d) The Si wafer is flipped over and then heated to 50-100°C. An outward tensile force is applied to the surface of the Si wafer. The silicon wafer does not break along the hydrogen ion layer but rather cracks amorphously along the wafer tangentially. Based on the above embodiment, the T1 is 1100° C. and the t1 is 30 min.

[0045] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the definition of the claims.

Claims

1. A method for preparing SiC MOSFET gate oxide based on transfer, characterized in that: include: S1, forming a SiO2 gate oxide film on the Si surface; S2, transferring the SiO2 gate oxide layer film to the surface of the SiC epitaxial wafer to obtain a SiC wafer with a gate oxide layer; S3. Bonding and annealing the SiC wafer with the gate oxide layer to obtain the SiC MOSFET gate oxide.

2. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 1, characterized in that: The step S1 comprises: (a) Perform standard RCA cleaning on the Si wafer surface; (b) Place the cleaned Si wafer in step (a) into a high-temperature oxidation furnace, introduce oxygen and water vapor, and control the oxidation temperature between 750°C and 1000°C for 15 to 45 minutes. (c) After the Si wafer cools to room temperature, it is taken out and the sacrificial oxide layer is removed by wet etching; (d) Place the Si wafer in a high-temperature oxidation furnace and introduce oxygen to form a thin film oxide layer 0 on the surface of the Si wafer.

3. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 2, characterized in that: The step (d) includes placing the Si wafer in a high-temperature oxidation furnace, introducing oxygen, and forming a thin film oxide layer on the surface of the Si wafer at a temperature T1 for a growth time t1; the range of T1 is: 800°C ≤ T1 ≤ 1200°C, and the growth time t1 is 20min ≤ t1 ≤ 60min.

4. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 1, characterized in that: The step S2 comprises: (e) planarizing the surface of the SiC epitaxial wafer; (f) The gate oxide film is transferred from the Si wafer to the surface of the SiC epitaxial wafer through smart peeling, support layer assisted transfer, surface activation and wafer bonding processes to obtain a SiC wafer with a gate oxide layer.

5. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 1, characterized in that: The SiC epitaxial wafer is a planar or trench structure.

6. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 5, characterized in that: The SiC epitaxial wafer has a groove structure, and the steps between step S2 and step S3 further include: treating the SiC epitaxial wafer with a hydrophobic agent, casting a soft photoresist elastomer onto a Si mold, baking, and peeling the soft photoresist elastomer from the Si mold to produce a T-shaped mold having the same structure as the SiC wafer.

7. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 1, characterized in that: The S2 comprises the following steps: (a) Place the Si wafer in the ion implantation equipment and implant hydrogen ions into the wafer from the first surface of the Si wafer at a concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) placing the Si wafer treated in step (a) in a high-temperature oxidation furnace at an annealing temperature of 350-450°C for 30-60 minutes, and then cooling to room temperature; (c) Spin coating the support layer material on the Si wafer surface; (d) The wafer is flipped over and then heated to 50-100°C, applying an outward pull to the surface of the Si wafer to peel off the excess silicon wafer along the hydrogen ion layer; (e) Placing the Si wafer in a TMAH solution and removing the remaining silicon wafer by wet etching, leaving only the oxide layer and the support layer, to obtain a complete SiO2 composite gate dielectric; (f) Aligning the SiO2 composite gate dielectric and the SiC epitaxial wafer and then closely fitting them together at room temperature to complete pre-bonding; (g) Remove the support layer material and retain the SiO2 gate oxide layer.

8. The method for preparing SiC MOSFET gate oxide based on transfer according to claim 1, characterized in that: The S2 comprises the following steps: (a) Place the Si wafer in the ion implantation equipment and implant hydrogen impurities into the wafer from the first surface of the Si wafer at a concentration of 5×10 16 ~1×10 17 cm -2 , the injection energy is 100~200keV; (b) The Si wafer and the SiC epitaxial wafer are placed in a wafer bonder for bonding and heated to 400-600°C. The hydrogen ion layer generates bubbles that separate the SiC wafer along the hydrogen ion layer. (c) The SiC wafer is placed in a TMAH solution and the remaining silicon wafer is removed by wet etching, leaving only the oxide layer and the support layer, thereby obtaining a SiC wafer with an oxide layer on the surface.

9. SiC MOSFET gate oxide prepared by the method according to any one of claims 1 to 8.

10. Application of the method according to any one of claims 1 to 8 in the field of semiconductor preparation.

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