Field effect transistor and manufacturing method thereof
By adopting heterojunction structure and cascade design in silicon carbide power devices, combining SiC JFET and Si MOSFET, the problems of gate oxide reliability and high channel resistance of SiC MOSFET are solved, low on-resistance and high gate dielectric layer reliability are achieved, making it suitable for high-power, high-voltage and high-temperature applications.
Patent Information
- Application Number
- CN202510784065.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2025-09-16
AI Technical Summary
Existing SiC MOSFETs of silicon carbide power devices have problems such as poor gate oxide reliability, high channel resistance, and high driving voltage, making it difficult to fully utilize the high voltage resistance and low on-resistance advantages of silicon carbide materials.
A heterojunction structure consisting of first and second semiconductor materials with different bandgap widths is adopted, combined with a cascade design of a first JFET and a second MOSFET. The first JFET uses SiC material and the second MOSFET uses Si material. The on-off control is achieved through heterojunction connection, reducing the channel resistance and improving the reliability of the gate dielectric layer.
It achieves low on-resistance and high gate dielectric layer reliability, adapts to the driving circuit of Si MOSFET, reduces chip area, overcomes the defects of wide bandgap semiconductor materials, and is suitable for high-power, high-voltage and high-temperature applications.
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Figure CN120659378A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a field effect transistor; the present invention also relates to a method for manufacturing the field effect transistor. Background Art
[0002] As global demand for new energy sources continues to grow, power devices are increasingly being challenged for higher-temperature, higher-voltage, and higher-current applications. As third-generation semiconductors, silicon carbide power devices are poised for widespread market adoption, driven by the material's inherent wide bandgap, high thermal conductivity, and high saturation electron velocity.
[0003] Currently, research on silicon carbide power devices focuses on silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs). However, due to the excessive defects introduced by SiC gate oxide growth, the problem of poor gate oxide reliability has always been difficult to solve. This also leads to a large proportion of channel resistance in planar gate SiC MOSFETs, which cannot fully utilize the advantages of high voltage resistance and low on-resistance of silicon carbide materials. In addition, the current driving voltage of SiC MOSFETs is relatively high and cannot fully adapt to the driving circuit of Si MOSFETs, which increases the time cost of silicon carbide devices replacing silicon devices. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a field-effect transistor that combines the advantages of wide-bandgap semiconductor devices while overcoming the problems of high channel resistance, high drive voltage, and poor gate dielectric layer reliability typically associated with wide-bandgap semiconductor devices. To this end, the present invention also provides a method for manufacturing the field-effect transistor.
[0005] To solve the above technical problems, the field effect transistor provided by the present invention includes: a first epitaxial layer doped with a first conductive type composed of a first semiconductor material and a second epitaxial layer doped with a first conductive type composed of a second semiconductor material, the band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material, the second epitaxial layer is formed on the top surface of the first epitaxial layer and the contact surface between the first epitaxial layer and the second epitaxial layer is a heterojunction.
[0006] A first JFET is formed in the first epitaxial layer, and a second MOSFET is formed in the second epitaxial layer.
[0007] The first JFET includes a first drain region heavily doped with a first conductivity type, a first gate region, and a first source region heavily doped with a first conductivity type.
[0008] The first drain region is formed on the back side of the first epitaxial layer.
[0009] The first source region is formed on the front surface of the first epitaxial layer.
[0010] The first gate region is composed of a second conductive type doped region formed in the first epitaxial layer. The first epitaxial layer surrounded by the first gate region constitutes a first channel region. The first channel region is located between the first source region and the first drain region.
[0011] The second MOSFET includes: a second source region heavily doped with the first conductivity type, a second channel region doped with the second conductivity type, a second gate structure, and a second drain region heavily doped with the first conductivity type.
[0012] The second channel region is formed in the top area of the second epitaxial layer, and the second drain region is composed of the second epitaxial layer located at the bottom of the second channel region.
[0013] The second gate structure is a trench gate, and the trench gate passes through the second channel region.
[0014] The second source region is formed in a surface region of the second channel region.
[0015] A first buried metal layer is formed on the surface of the first source region, the side surface of the first buried metal layer contacts the second drain region and realizes the electrical connection between the first source region and the second drain region, and the top surface of the first buried metal layer is located below the bottom surface of the second channel region and is electrically isolated from both the second channel region and the second source region.
[0016] A second contact structure passing through the heterojunction is formed at the top of the lead-out region of the first gate region, and the second contact structure is connected to the source electrode composed of the front metal layer through a contact hole at the top; the second contact structure and the second source region, the second channel region and the second drain region are electrically isolated.
[0017] The second source region is connected to the source electrode; and the back surface of the first drain region is connected to the drain electrode formed by a back surface metal layer.
[0018] A further improvement is that the first semiconductor material includes SiC.
[0019] A further improvement is that the second semiconductor material includes Si.
[0020] A further improvement is that the first gate region comprises two first buried layers and one second buried layer.
[0021] The second buried layer is formed in a top surface region of the first epitaxial layer.
[0022] A top surface of each of the first buried layers is located below a bottom surface of the second buried layers.
[0023] A first lateral spacing region is provided between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region.
[0024] The second buried layer and the first buried layer at the bottom have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region.
[0025] The second contact structure is formed on top of the second buried layer.
[0026] A further improvement is that the trench gate includes a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.
[0027] A further improvement is that a first dielectric layer is formed on the top surface of the first buried metal layer, and the top surface of the first dielectric layer is flush with the top surface of the second epitaxial layer.
[0028] A further improvement is that the second source region, the second channel region and the second drain region are all located at the second side of the gate trench, the second contact structure is located at the first side of the gate trench, and the second contact structure is electrically isolated from the second source region, the second channel region and the second drain region through the trench gate.
[0029] A further improvement is that the second contact structure is composed of a heavily doped region of the second conductivity type formed in the second epitaxial layer at the first side of the gate structure.
[0030] A further improvement is that the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0031] To solve the above technical problems, the present invention provides a method for manufacturing a field effect transistor, comprising the following steps:
[0032] A first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material is formed on a first semiconductor material substrate. The first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region of a first JFET.
[0033] forming a first gate region of a first JFET composed of a second conductivity type doped region in the first epitaxial layer;
[0034] A first source region of the first JFET that is heavily doped with a first conductivity type is formed in the front surface area of the first epitaxial layer; the first epitaxial layer surrounded by the first gate region constitutes a first channel region of the first JFET, and the first channel region is located between the first source region and the first drain region.
[0035] A second epitaxial layer doped with a first conductive type and composed of a second semiconductor material is formed on the top surface of the first epitaxial layer. The band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material. The contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction.
[0036] A first trench is formed through the second epitaxial layer over a surface of the first source region.
[0037] A metal layer is filled in the first trench and metal etching is performed to form a first buried metal layer located at the bottom of the first trench.
[0038] A first dielectric layer is filled in the first trench on top of the first buried metal layer.
[0039] A second channel region doped with a second conductive type of the second MOSFET is formed in the second epitaxial layer using a well region formation process. The bottom surface of the second channel region is located above the top surface of the first buried metal layer. The second epitaxial layer at the bottom of the second channel region constitutes a second drain region of the second MOSFET.
[0040] A second gate structure of the second MOSFET is formed, where the second gate structure is a trench gate, and the trench gate passes through the second channel region.
[0041] A second source region of the second MOSFET heavily doped with the first conductivity type is formed in a surface area of the second channel region.
[0042] A second contact structure passing through the heterojunction is formed on a top portion of an extraction region of the first gate region. The second contact structure is electrically isolated from the second source region, the second channel region, and the second drain region.
[0043] An interlayer film is formed, and a contact hole passes through the interlayer film; corresponding contact holes are formed on the top of the second source region and the top of the second contact structure.
[0044] A front metal layer is formed and patterned to form a source electrode, and the second contact structure and the source region are both connected to the source electrode through the corresponding contact hole on the top.
[0045] A drain electrode composed of a back metal layer is formed on the back side of the first drain region.
[0046] A further improvement is that the first semiconductor material includes SiC.
[0047] A further improvement is that the second semiconductor material includes Si.
[0048] A further improvement is that the steps of forming the first gate region include:
[0049] Two first buried layers are formed at a selected depth of the first epitaxial layer, with a first lateral spacing region between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region.
[0050] A second buried layer is formed in the top surface area of the first epitaxial layer; the top surface of each first buried layer is located at the bottom of the bottom surface of the second buried layer; the second buried layer and the first buried layer at the bottom have a first intersection area and the first intersection area serves as a lateral extension area of the first channel region; the second contact structure is formed on the top of the second buried layer.
[0051] A further improvement is that the steps of forming the trench gate include:
[0052] A gate trench is formed.
[0053] A gate dielectric layer is formed on the inner surface of the gate trench.
[0054] A gate conductive material layer is filled in the gate trench.
[0055] A further improvement is that the second source region, the second channel region and the second drain region are all located at the second side of the gate trench, the second contact structure is located at the first side of the gate trench, and the second contact structure is electrically isolated from the second source region, the second channel region and the second drain region through the trench gate.
[0056] A further improvement is that the second contact structure is formed by implanting heavily doped ions of the second conductivity type into the second epitaxial layer at the first side of the gate structure.
[0057] A further improvement is that the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0058] The field effect transistor of the present invention is formed by connecting a first JFET formed in a first epitaxial layer and a second MOSFET formed in a second epitaxial layer. The first epitaxial layer is composed of a first semiconductor material with a wide bandgap width, such as SiC, so that the first JFET has the advantages of a wide bandgap semiconductor material device, such as the ability to achieve high power, high voltage, high temperature and radiation resistance.
[0059] The second epitaxial layer is composed of a second semiconductor material with a lower bandgap width, such as silicon, and a second MOSFET is used to control the channel conduction current of the entire field effect transistor, thereby avoiding the high interface state density problem of the channel of wide bandgap semiconductor material devices, improving the channel mobility of the device, and reducing the channel resistance.
[0060] Furthermore, in the present invention, the use of a second MOSFET to control the conduction of the field-effect transistor minimizes on-resistance and makes the device fully compatible with the drive scheme of a low-bandgap semiconductor device, i.e., the second MOSFET. Simultaneously, the use of the second MOSFET to control the field-effect transistor's turn-off allows the portion directly driving the voltage to be the low-bandgap semiconductor device corresponding to the second MOSFET, thus avoiding the problem of low reliability of gate dielectric layers, such as gate oxide layers, in wide-bandgap semiconductor devices.
[0061] In addition, in the present invention, the first source region of the first JFET and the second drain region of the second MOSFET are connected through a first buried metal layer. Since the first buried metal layer passes through the heterojunction formed by the first epitaxial layer and the second epitaxial layer, the forward conduction current does not cross the potential barrier of the heterojunction, thereby avoiding the adverse effects of the heterojunction on the conduction characteristics of the device.
[0062] At the same time, the second contact structure at the top of the first gate region also passes through the heterojunction. When the device is reversely cut off, the first JFET bears the high voltage, and the reverse leakage current will pass through the first gate region and the second contact structure and the source at the top of the second contact structure. Therefore, the reverse leakage current will not pass through the heterojunction, thereby avoiding the problem of increased leakage caused by heterogeneous crystal lattice mismatch.
[0063] In addition, the cascaded integration of the first JFET and the second MOSFET in the present invention into one device will reduce the chip area of the cascade package of the two.
[0064] Therefore, the present invention can have the advantages of wide bandgap semiconductor material devices while overcoming the problems of low channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of wide bandgap semiconductor material devices; it can also avoid the adverse effects of the heterojunction barrier on forward conduction current and reverse current, and can also reduce the chip area. BRIEF DESCRIPTION OF THE DRAWINGS
[0065] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0066] Figure 1 1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;
[0067] Figure 2 Schematic diagram of the flow direction of source-drain current of the field effect transistor when it is forward-conducting according to an embodiment of the present invention;
[0068] Figure 3 Schematic diagram of the distribution of the depletion region of the first JFET of the field effect transistor when the source-drain current is turned off according to an embodiment of the present invention;
[0069] Figure 4 1 is a schematic diagram of an equivalent circuit of a field effect transistor according to an embodiment of the present invention;
[0070] Figure 5-Figure 18 It is a schematic diagram of the device structure in each step of the method for manufacturing a field effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION
[0071] like Figure 1 As shown in FIG, it is a schematic diagram of the structure of the field effect transistor according to an embodiment of the present invention; Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a field effect transistor according to an embodiment of the present invention; Figure 1 The corresponding cross-sectional position in the figure is the XY plane. The field effect transistor in the embodiment of the present invention includes: a first epitaxial layer 2 doped with a first conductive type composed of a first semiconductor material and a second epitaxial layer 5 doped with a first conductive type composed of a second semiconductor material. The band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material. The second epitaxial layer 5 is formed on the top surface of the first epitaxial layer 2 and the contact surface between the first epitaxial layer 2 and the second epitaxial layer 5 is a heterojunction.
[0072] The first JFET 201 is formed in the first epitaxial layer 2 , and the second MOSFET 202 is formed in the second epitaxial layer 5 .
[0073] The first JFET 201 includes a first drain region 1 heavily doped with a first conductivity type, a first gate region, and a first source region 4 heavily doped with a first conductivity type.
[0074] The first drain region 1 is formed on the back side of the first epitaxial layer 2 .
[0075] The first source region 4 is formed on the front surface of the first epitaxial layer 2 .
[0076] The first gate region is composed of a second conductivity type doped region formed in the first epitaxial layer 2 . The first epitaxial layer 2 surrounded by the first gate region constitutes a first channel region, which is located between the first source region 4 and the first drain region 1 .
[0077] The second MOSFET 202 includes a second source region 7 heavily doped with the first conductivity type, a second channel region 6 doped with the second conductivity type, a second gate structure, and a second drain region heavily doped with the first conductivity type.
[0078] The second channel region 6 is formed in the top region of the second epitaxial layer 5 , and the second drain region is formed by the second epitaxial layer 5 located at the bottom of the second channel region 6 .
[0079] The second gate structure is a trench gate, and the trench gate passes through the second channel region 6 .
[0080] The second source region 7 is formed in a surface region of the second channel region 6 .
[0081] A first buried metal layer 10 is formed on the surface of the first source region 4. The side surface of the first buried metal layer 10 contacts the second drain region and realizes the electrical connection between the first source region 4 and the second drain region. The top surface of the first buried metal layer 10 is located below the bottom surface of the second channel region 6 and is electrically isolated from the second channel region 6 and the second source region 7.
[0082] A second contact structure 12 passing through the heterojunction is formed at the top of the lead-out area of the first gate region. The second contact structure 12 is connected to the source electrode composed of the front metal layer 15 through a contact hole 14 at the top; the second contact structure 12 and the second source region 7, the second channel region 6 and the second drain region are all electrically isolated.
[0083] The second source region 7 is connected to the source electrode; the back surface of the first drain region 1 is connected to the drain electrode formed by the back metal layer 16 .
[0084] In the embodiment of the present invention, the first semiconductor material includes SiC. The second semiconductor material includes Si. Therefore, Figure 4 In the figure, the second MOSFET 202 is also represented by Si MOSFET. Compared with the existing SiC MOSFET, Si MOSFET can overcome various defects of SiCMOSFET, such as: low channel interface density, so the channel mobility is high; only the driving scheme of Si MOSFET, such as driving voltage, is required for driving, and the driving voltage of more than 18V required by SiC MOSFET is not required; the tunneling current between Si and SiO2 is smaller than the tunneling current between SiC and SiO2, so the reliability of the gate dielectric layer 8, such as the gate oxide layer, is improved. Figure 4 In the example, the first JFET 201 is also represented by SiC JFET. Figure 1 As shown, the first JFET 201 is at the drain end, so the characteristics of the SiC material can be used to improve the performance of the device, making it suitable for high power, high voltage, high temperature and radiation resistance conditions.
[0085] In other embodiments, specific materials of the first semiconductor material and the second semiconductor material can also be selected as needed.
[0086] In the embodiment of the present invention, components of the first gate region include two first buried layers 3 a and one second buried layer 3 b .
[0087] The second buried layer 3 b is formed in the top surface region of the first epitaxial layer 2 .
[0088] The top surface of each first buried layer 3a is located below the bottom surface of the second buried layer 3b.
[0089] A first lateral spacing region is provided between the two first buried layers 3 a , and the first lateral spacing region serves as a longitudinal extension region of the first channel region.
[0090] The second buried layer 3 b and the bottom first buried layer 3 a have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region.
[0091] The second contact structure 12 is formed on the top of the second buried layer 3b.
[0092] In other embodiments, the first gate region 3 can also be adjusted as needed, as long as it is ensured that the first channel region can be controlled.
[0093] In the embodiment of the present invention, the trench gate includes a gate trench 202, a gate dielectric layer 8 formed on the inner surface of the gate trench 202, and a gate conductive material layer 9 filled in the gate trench 202. Figure 13 In some embodiments, the gate dielectric layer 8 includes a gate oxide layer, and the gate conductive material layer 9 includes a polysilicon gate.
[0094] In the embodiment of the present invention, a first dielectric layer 11 is formed on the top surface of the first buried metal layer 10. The top surface of the first dielectric layer 11 is flush with the top surface of the second epitaxial layer 5. In some embodiments, the first dielectric layer 11 is an oxide layer.
[0095] An ohmic contact alloy is formed at the contact position between the first buried metal layer 10 and the first source region 4 at the bottom. The material of the ohmic contact alloy includes nickel (Ni) alloy.
[0096] In an embodiment of the present invention, the second source region 7, the second channel region 6, and the second drain region are all located at the second side of the gate trench 202, and the second contact structure 12 is located at the first side of the gate trench 202. The second contact structure 12 is electrically isolated from the second source region 7, the second channel region 6, and the second drain region through the trench gate. Figure 1 Two adjacent trench gates are shown in FIG. 1 , wherein first side surfaces of the two trench gates are adjacent to each other, and the second contact structure 12 is located right between the two adjacent trench gates.
[0097] The second contact structure 12 is composed of a heavily doped region of the second conductivity type formed in the second epitaxial layer 5 at the first side of the gate structure. In other embodiments, the second contact structure 12 can also adopt other structures, such as a deep contact hole structure or a deep contact hole combined with a doped region structure.
[0098] In the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0099] like Figure 2 , which is a schematic diagram of the flow direction of the source-drain current of the field effect transistor when it is forward-conducting according to an embodiment of the present invention; Figure 2 In the figure, each gate conductive material layer 9 is connected to the gate composed of the front metal layer 15 (the specific structure is not shown). When the gate conductive material layer 9 increases the positive voltage greater than the threshold voltage, the second MOSFET 202 is turned on, the source-drain current is turned on, and the current flows in the direction as shown by the arrow line 101, that is, starting from the drain corresponding to the back metal layer 16, passing through the first channel region corresponding to the first epitaxial layer 2 to reach the first source region 4, passing through the first metal buried layer 10 to reach the second drain region formed by the second epitaxial layer 5, passing through the second channel region 6 to reach the second source region 7 and finally passing through the through hole 14 to reach the source composed of the front metal layer 15.
[0100] like Figure 3 , which is a schematic diagram of the depletion region distribution of the first JFET 201 when the field effect transistor is turned off according to an embodiment of the present invention; when a zero potential or a negative voltage less than the threshold voltage is applied to the gate conductive material layer 9, Figure 3 The "-" in the figure indicates a negative potential. The second MOSFET 202 is turned off, and the entire field effect transistor is turned off and is in a reverse cutoff state. For the first JFET 201, the second buried layer 3b is connected to the source potential through the second contact structure, and the drain potential is a high potential. Therefore, the first buried layer 3a and the second buried layer 3b will deplete the first epitaxial layer 2 and form a depletion region. Figure 3 The middle dotted line 102 represents the boundary of the corresponding depletion region. It can be seen that the depletion region between the two first buried layers 3a is connected together, and the depletion region between the second buried layer 3b and the bottom first buried layer 3a is also connected together. Therefore, the longitudinal extension area and the lateral extension area of the first channel region are both turned off, which can reduce the reverse leakage of the device; at the same time, the depletion region is mainly located in the first epitaxial layer 2, and the depletion region in the first epitaxial layer 2 will be subjected to high voltage; the reverse leakage enters the first epitaxial layer 2 through the drain, and finally is connected to the source through the second contact structure on the top of the second buried layer 3b, and will not pass through the heterojunction, which can avoid the risk of increased leakage caused by the lattice mismatch of the heterojunction.
[0101] The field effect transistor in the embodiment of the present invention is formed by connecting a first JFET 201 formed in the first epitaxial layer 2 and a second MOSFET 202 formed in the second epitaxial layer 5. The first epitaxial layer 2 is composed of a first semiconductor material with a wide bandgap width, such as SiC, so that the first JFET 201 has the advantages of a wide bandgap semiconductor material device, such as the ability to achieve high power, high voltage, high temperature and radiation resistance.
[0102] In an embodiment of the present invention, the second epitaxial layer 5 is composed of a second semiconductor material with a lower bandgap width, such as silicon, and a second MOSFET202 is used to control the channel conduction current of the entire field effect transistor, thereby avoiding the problem of high interface state density in the channel of wide bandgap semiconductor material devices, improving the channel mobility of the device, and reducing the channel resistance.
[0103] In addition, in the embodiment of the present invention, the use of the second MOSFET 202 to control the conduction of the field-effect transistor can minimize the on-resistance and make the device fully compatible with the driving scheme of the low-bandgap semiconductor material device, namely the second MOSFET 202. At the same time, the use of the second MOSFET 202 to control the turn-off of the field-effect transistor allows the portion directly driving the voltage to be the low-bandgap semiconductor material device corresponding to the second MOSFET 202, thereby avoiding the problem of low reliability of the gate dielectric layer 8, such as the gate oxide layer, of the wide-bandgap semiconductor material device.
[0104] In addition, in the embodiment of the present invention, the first source region 4 of the first JFET 201 and the second drain region of the second MOSFET 202 are connected via the first buried metal layer 10. Since the first buried metal layer 10 passes through the heterojunction formed by the first epitaxial layer 2 and the second epitaxial layer 5, the forward conduction current does not cross the potential barrier of the heterojunction, thereby avoiding the adverse effects of the heterojunction on the conduction characteristics of the device.
[0105] At the same time, the second contact structure 12 at the top of the first gate region also passes through the heterojunction. When the device is reversely cut off, the first JFET201 bears the high voltage, and the reverse leakage current will pass through the first gate region and the second contact structure 12 and the source at the top of the second contact structure 12. Therefore, the reverse leakage current will not pass through the heterojunction, thereby avoiding the problem of increased leakage caused by heterogeneous crystal lattice mismatch.
[0106] In addition, in the embodiment of the present invention, the first JFET 201 and the second MOSFET 202 are cascaded and integrated into one device, which reduces the chip area of the cascade package.
[0107] Therefore, the embodiment of the present invention can have the advantages of wide bandgap semiconductor material devices while overcoming the problems of low channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer 8 of wide bandgap semiconductor material devices; it can also avoid the adverse effects of the heterojunction barrier on forward conduction current and reverse current, and can also reduce the chip area.
[0108] like Figures 5 to 18 , which is a schematic diagram of the device structure in each step of the method for manufacturing a field effect transistor according to an embodiment of the present invention; the method for manufacturing a field effect transistor according to an embodiment of the present invention includes the following steps:
[0109] Step 1: Figure 5 As shown, a first epitaxial layer 2 doped with a first conductivity type and composed of a first semiconductor material is formed on a first semiconductor material substrate. The first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region 1 of the first JFET 201 .
[0110] In the embodiment of the present invention, the first semiconductor material includes SiC. In other embodiments, the first semiconductor material can be selected as needed to ensure that the band gap of the first semiconductor material is larger than the band gap of the subsequent second semiconductor material.
[0111] Step 2: forming a first gate region of the first JFET 201 composed of a second conductivity type doped region in the first epitaxial layer 2 .
[0112] The steps of forming the first gate region 3 include:
[0113] Step 21: Figure 5 As shown, two first buried layers 3 a are formed at a selected depth of the first epitaxial layer 2 , with a first lateral spacing region between the two first buried layers 3 a , and the first lateral spacing region serves as a longitudinal extension region of the first channel region of the first JFET 201 .
[0114] The formation area of the first buried layer 3a is defined by photolithography. Before the photolithography process is performed, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In this case, the first buried layer 3a is a P-type buried layer, and the impurities implanted in the first buried layer 3a include P-type impurities such as Al or B. The implantation temperature condition is 300K to 1000K. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. In this case, the first buried layer 3a is an N-type buried layer.
[0115] Step 22: Figure 6 As shown, a second buried layer 3b is formed in the top surface area of the first epitaxial layer 2; the top surface of each first buried layer 3a is located at the bottom of the bottom surface of the second buried layer 3b; the second buried layer 3b and the bottom first buried layer 3a have a first intersection area and the first intersection area serves as a lateral extension area of the first channel region.
[0116] In the method of this embodiment of the present invention, the region for forming the second buried layer 3b is defined by photolithography. Prior to the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer is patterned before ion implantation. The ion implantation mask layer is then removed and the surface cleaned. The implanted impurities in the second buried layer 3b include P-type impurities such as Al or B. The implantation temperature is between 300K and 1000K.
[0117] Step 3: Figure 7 As shown, a first source region 4 of the first conductivity type heavily doped with the first JFET 201 is formed in the front surface area of the first epitaxial layer 2; the first epitaxial layer 2 surrounded by the first gate region constitutes a first channel region of the first JFET 201, and the first channel region is located between the first source region 4 and the first drain region 1.
[0118] In the method of the embodiment of the present invention, the formation area of the first source region 4 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. The impurities implanted into the first source region 4 include N-type impurities such as phosphorus (P) or nitrogen (N), and the implantation temperature is 500K to 1000K.
[0119] Step 4: Figure 8 As shown, a second epitaxial layer 5 doped with a first conductive type and composed of a second semiconductor material is formed on the top surface of the first epitaxial layer 2. The band gap width of the first semiconductor material is greater than the band gap width of the second semiconductor material. The contact surface between the first epitaxial layer 2 and the second epitaxial layer 5 is a heterojunction.
[0120] In the embodiment of the present invention, the second semiconductor material includes Si and is formed by chemical vapor deposition. In other embodiments, the second semiconductor material can also be other suitable materials, but the band gap of the first semiconductor material must be greater than the band gap of the second semiconductor material.
[0121] In some exemplary embodiments, the thickness of the second epitaxial layer 5 is 2 micrometers to 10 micrometers.
[0122] Step 5: Figure 9 As shown, a first trench 201 is formed on the surface of the first source region 4 and passes through the second epitaxial layer 5 .
[0123] In some embodiment methods, a hard mask layer needs to be formed before etching the first groove 201. Then, a photolithography process is used to define the formation area of the first groove 201. Then, the hard mask layer and the second epitaxial layer 5 are etched in sequence to form the first groove 201.
[0124] Step 6: Figure 10 As shown, the metal layer of the first buried metal layer 10 is filled in the first trench 201 .
[0125] like Figure 11 As shown, metal etching is performed to lower the top surface of the metal layer and thereby form a first buried metal layer 10 at the bottom of the first trench 201. The top surface of the first buried metal layer 10 needs to be lower than the bottom surface of the second channel region 6 to be formed subsequently.
[0126] Step 7: Figure 11 As shown, the first dielectric layer 11 is filled in the first trench 201 on the top of the first buried metal layer 10 .
[0127] In the method of the embodiment of the present invention, the first dielectric layer 11 is an oxide layer, which is formed by a deposition process. After deposition, CMP is required to be performed for planarization.
[0128] Step 8: Figure 12 As shown, a second channel region 6 doped with a second conductive type of the second MOSFET 202 is formed in the second epitaxial layer 5 by a well region formation process. The bottom surface of the second channel region 6 is located above the top surface of the first buried metal layer 10. The second drain region of the second MOSFET 202 is composed of the second epitaxial layer 5 at the bottom of the second channel region 6.
[0129] In the embodiment of the present invention, the second channel region is formed by a P-type doped well region 6. The well region 6 is formed in the surface region of the second epitaxial layer 5 by P-type impurity ion implantation, such as boron ion implantation, and high-temperature push-in.
[0130] Step 9: Figure 13 As shown, a second gate structure of the second MOSFET 202 is formed. The second gate structure is a trench gate, and the trench gate passes through the second channel region 6 .
[0131] In the method of the embodiment of the present invention, the steps of forming the trench gate include:
[0132] like Figure 13 As shown, a gate trench 202 is formed.
[0133] In some embodiment methods, a hard mask layer needs to be formed before etching the gate trench 202. Then, a photolithography process is used to define the formation area of the gate trench 202. Then, the hard mask layer and the second epitaxial layer 5 are etched in sequence to form the gate trench 202. Figure 13 In the embodiment, the gate trench 13 passes through the entire second epitaxial layer 5, that is, the second epitaxial layer 5 as the second drain region at the bottom of the second channel region 6 is also passed through by the gate trench 13, so that it is convenient to use the trench gate to realize the electrical isolation between the subsequently formed second contact structure 12 and the second source region 7, the second channel region 6 and the second drain region.
[0134] like Figure 14 As shown, a gate dielectric layer 8 is formed on the inner surface of the gate trench 202 .
[0135] In the method of the embodiment of the present invention, the gate dielectric layer 8 includes a gate oxide layer, which is formed by a thermal oxidation process.
[0136] like Figure 14 As shown, the gate trench 202 is filled with a gate conductive material layer 9 .
[0137] The gate conductive material layer 9 includes a polysilicon gate and is formed by polysilicon deposition and etching.
[0138] Figure 14 , two second gate structures are shown, each second gate structure corresponding to a second MOSFET 202 .
[0139] Step 10: Figure 15 As shown, a second source region 7 of the second MOSFET 202 heavily doped with the first conductivity type is formed in the surface region of the second channel region 6 .
[0140] In the method of the embodiment of the present invention, the second source region 7 is an N+ implantation region, and the implanted impurities include phosphorus or arsenic. After the ion implantation is completed, high-temperature push-in junction needs to be performed.
[0141] Step 11: Figure 16 As shown, a second contact structure 12 passing through the heterojunction is formed on the top of the lead-out region of the first gate region. The second contact structure 12 is electrically isolated from the second source region 7, the second channel region 6, and the second drain region.
[0142] In the embodiment method of the present invention, the second source region 7, the second channel region 6, and the second drain region are all located at the second side of the gate trench 202, and the second contact structure 12 is located at the first side of the gate trench 202. The second contact structure 12 is electrically isolated from the second source region 7, the second channel region 6, and the second drain region through the trench gate.
[0143] The second contact structure 12 is formed by heavily doping the second conductivity type ion implantation in the second epitaxial layer 5 at the first side of the gate structure. In some embodiments, the impurities implanted into the second contact structure 12 include boron. After the ion implantation, a high temperature push-up is performed. The ion implantation dose includes: 1E14 cm -3 ~1E16cm -3 .
[0144] Step 12: Figure 17 As shown, an interlayer film 13 is formed.
[0145] Step 13: Figure 18 As shown, a contact hole 14 passes through the interlayer film 13 ; corresponding contact holes 14 are formed on the top of the second source region 7 and the top of the second contact structure 12 .
[0146] The steps of forming the contact hole 14 include:
[0147] Photolithography definition and etching are performed to form the opening 203 of the contact hole 14. Figure 18 The corresponding cross section shows three openings 203, which are respectively located in the second source region 7 and the second contact structure 12. At other cross-sectional positions, corresponding openings 203 are also formed on the top of the gate conductive material layer 9.
[0148] An ohmic contact alloy is formed.
[0149] Back to Figure 1 As shown, a front metal layer 15 is formed and patterned to form a source electrode. The second contact structure 12 and the source region are connected to the source electrode through the corresponding contact hole 14 on the top. After the front metal layer 15 is patterned, a gate electrode is also formed. The gate electrode is not located at Figure 1 The cross section shown is not shown.
[0150] In some embodiments, the material of the front metal layer 15 includes Al.
[0151] Step 14: Figure 18 As shown, a drain electrode composed of a back metal layer 16 is formed on the back side of the first drain region 1 .
[0152] In some embodiments, before forming the back metal layer 16 , an ohmic contact alloy is further formed.
[0153] In the embodiment of the present invention, the field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the field effect transistor may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0154] The field effect transistor of the embodiment of the present invention can realize a silicon carbide heterojunction field effect transistor, and the corresponding equivalent circuit is as follows: Figure 4 As shown. Figure 2 As shown in the figure, when the device works in the first quadrant, when a positive voltage is applied to the gate, the SiMOSFET channel above the SiC JFET is inverted and the forward current is conducted. Figure 3 As shown in the figure, when a negative voltage is applied to the gate, the Si MOSFET channel above the SiC JFET is closed, the SiC JFET source is at a negative potential, the SiC JFET depletion region is pinched off, and the high withstand voltage is mainly borne by the SiC JFET.
[0155] The silicon carbide heterojunction field-effect transistor implemented in the embodiments of the present invention has the following main advantages over the existing traditional SiC MOSFET:
[0156] 1. SiC JFET gate-oxide-free process solves the gate-oxide reliability issue of SiC MOSFET.
[0157] 2. The Si MOSFET and SiC JFET are cascaded and integrated into one device, reducing the chip area of the SiC JFET and Si MOSFET cascade package.
[0158] 3. The SiC JFET current enters the Si MOFET through the metal and does not pass through the SiC / Si heterojunction, thus avoiding the influence of the heterojunction barrier on the device conduction characteristics.
[0159] 4. The integrated Si MOSFET only plays the role of controlling the channel switch. Its on-resistance can be extremely small and is compatible with all current Si MOFET drive circuits.
[0160] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.
Claims
1. A field effect transistor, characterized in that: include: a first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material, and a second epitaxial layer doped with the first conductivity type and composed of a second semiconductor material, wherein the band gap of the first semiconductor material is greater than the band gap of the second semiconductor material, the second epitaxial layer is formed on a top surface of the first epitaxial layer, and a contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction; A first JFET is formed in the first epitaxial layer, and a second MOSFET is formed in the second epitaxial layer; The first JFET comprises: a first drain region heavily doped with a first conductivity type, a first gate region, and a first source region heavily doped with a first conductivity type; The first drain region is formed on the back side of the first epitaxial layer; The first source region is formed on the front surface of the first epitaxial layer; The first gate region is composed of a second conductivity type doped region formed in the first epitaxial layer, the first epitaxial layer surrounded by the first gate region constitutes a first channel region, and the first channel region is located between the first source region and the first drain region; The second MOSFET comprises: a second source region heavily doped with the first conductivity type, a second channel region doped with the second conductivity type, a second gate structure, and a second drain region heavily doped with the first conductivity type; The second channel region is formed in the top area of the second epitaxial layer, and the second drain region is composed of the second epitaxial layer located at the bottom of the second channel region; The second gate structure is a trench gate, and the trench gate passes through the second channel region; The second source region is formed in a surface region of the second channel region; A first buried metal layer is formed on a surface of the first source region, a side surface of the first buried metal layer contacts the second drain region and realizes electrical connection between the first source region and the second drain region, and a top surface of the first buried metal layer is located below a bottom surface of the second channel region and is electrically isolated from both the second channel region and the second source region; A second contact structure is formed on the top of the lead-out region of the first gate region, passing through the heterojunction. The second contact structure is connected to the source electrode composed of the front metal layer through a contact hole on the top. The second contact structure is electrically isolated from the second source region, the second channel region, and the second drain region. The second source region is connected to the source electrode; and the back surface of the first drain region is connected to the drain electrode formed by a back surface metal layer.
2. The field effect transistor according to claim 1, wherein: The first semiconductor material includes SiC.
3. The field effect transistor according to claim 2, wherein: The second semiconductor material includes Si.
4. The field effect transistor according to claim 1, wherein: The first gate region comprises two first buried layers and a second buried layer; the second buried layer being formed in a top surface region of the first epitaxial layer; The top surface of each of the first buried layers is located below the bottom surface of the second buried layer; A first lateral spacing region is provided between the two first buried layers, and the first lateral spacing region serves as a longitudinal extension region of the first channel region; The second buried layer and the first buried layer at the bottom have a first intersection region, and the first intersection region serves as a lateral extension region of the first channel region; The second contact structure is formed on top of the second buried layer.
5. The field effect transistor according to claim 1, wherein: The trench gate includes a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.
6. The field effect transistor according to claim 1, wherein: A first dielectric layer is formed on the top surface of the first buried metal layer, and the top surface of the first dielectric layer is flush with the top surface of the second epitaxial layer.
7. The field effect transistor according to claim 1, wherein: The second source region, the second channel region and the second drain region are all located at the second side of the gate trench, the second contact structure is located at the first side of the gate trench, and the second contact structure is electrically isolated from the second source region, the second channel region and the second drain region through the trench gate.
8. The field effect transistor according to claim 7, wherein: The second contact structure is composed of a heavily doped region of the second conductivity type formed in the second epitaxial layer at a first side of the gate structure.
9. The field effect transistor according to any one of claims 1 to 8, characterized in that: The field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
10. A method for manufacturing a field effect transistor, characterized in that: The steps include: forming a first epitaxial layer doped with a first conductivity type and composed of a first semiconductor material on a first semiconductor material substrate, wherein the first semiconductor substrate has a heavily doped region of the first conductivity type and serves as a first drain region of a first JFET; forming a first gate region of a first JFET composed of a second conductivity type doped region in the first epitaxial layer; A first source region of the first JFET that is heavily doped with a first conductivity type is formed in the front surface area of the first epitaxial layer; the first epitaxial layer surrounded by the first gate region constitutes a first channel region of the first JFET, and the first channel region is located between the first source region and the first drain region; forming a second epitaxial layer doped with a first conductivity type and composed of a second semiconductor material on a top surface of the first epitaxial layer, wherein the band gap of the first semiconductor material is greater than the band gap of the second semiconductor material, and a contact surface between the first epitaxial layer and the second epitaxial layer forms a heterojunction; forming a first trench through the second epitaxial layer on a surface of the first source region; Filling the first trench with a metal layer and performing metal etching to form a first buried metal layer located at the bottom of the first trench; Filling the first trench on top of the first buried metal layer with a first dielectric layer; forming a second channel region of the second MOSFET doped with a second conductivity type in the second epitaxial layer using a well region formation process, wherein a bottom surface of the second channel region is located above a top surface of the first buried metal layer, and the second epitaxial layer at the bottom of the second channel region constitutes a second drain region of the second MOSFET; forming a second gate structure of the second MOSFET, wherein the second gate structure is a trench gate, and the trench gate passes through the second channel region; forming a second source region of the second MOSFET heavily doped with the first conductivity type in a surface region of the second channel region; forming a second contact structure passing through the heterojunction on a top portion of an extraction region of the first gate region, wherein the second contact structure is electrically isolated from the second source region, the second channel region, and the second drain region; forming an interlayer film and a contact hole passing through the interlayer film; forming corresponding contact holes on the top of the second source region and the top of the second contact structure; forming a front metal layer and patterning it to form a source electrode, wherein the second contact structure and the source region are both connected to the source electrode through the corresponding contact holes at the top; A drain electrode composed of a back metal layer is formed on the back side of the first drain region.
11. The method for manufacturing a field effect transistor according to claim 10, wherein: The first semiconductor material includes SiC.
12. The method for manufacturing a field effect transistor according to claim 11, wherein: The second semiconductor material includes Si.
13. The method for manufacturing a field effect transistor according to claim 10, wherein: The steps of forming the first gate region include: forming two first buried layers at a selected depth of the first epitaxial layer, with a first lateral spacing region between the two first buried layers, and the first lateral spacing region serving as a longitudinal extension region of the first channel region; A second buried layer is formed in the top surface area of the first epitaxial layer; the top surface of each first buried layer is located at the bottom of the bottom surface of the second buried layer; the second buried layer and the first buried layer at the bottom have a first intersection area and the first intersection area serves as a lateral extension area of the first channel region; the second contact structure is formed on the top of the second buried layer.
14. The method for manufacturing a field effect transistor according to claim 10, wherein: The steps of forming the trench gate include: forming a gate trench; forming a gate dielectric layer on the inner surface of the gate trench; A gate conductive material layer is filled in the gate trench.
15. The method for manufacturing a field effect transistor according to claim 14, wherein: The second source region, the second channel region and the second drain region are all located at the second side of the gate trench, the second contact structure is located at the first side of the gate trench, and the second contact structure is electrically isolated from the second source region, the second channel region and the second drain region through the trench gate.
16. The method for manufacturing a field effect transistor according to claim 15, wherein: The second contact structure is formed by implanting heavily doped ions of the second conductivity type into the second epitaxial layer at the first side of the gate structure.
17. The method for manufacturing a field effect transistor according to any one of claims 10 to 16, wherein: The field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the field effect transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.