Circuit for detecting current in microarray synthesis chip, resulting chip and system, and method of use thereof
By introducing a current comparator circuit into the microarray chip to evaluate and select units with uniform current for synthesis, the problem of inconsistent quality of synthetic products caused by current non-uniformity in the electrode array is solved, and efficient quality control and uniform synthesis are achieved.
Patent Information
- Application Number
- CN202380088121.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-12-21
- Filing Date
- 2023-12-14
- Publication Date
- 2025-09-16
AI Technical Summary
In microarray chips, the current non-uniformity of the electrode array leads to inconsistent quality of the synthesized products, and existing technologies are difficult to effectively solve this problem.
By introducing multiple current comparator circuits into the microarray chip, current is converted into voltage using current mirrors and capacitors, and a digital signal is generated through the voltage comparator to evaluate the current capability of each unit, so that units that meet the specifications are selected for synthesis.
The method realizes efficient measurement and quality control of unit current in microarray chips, ensures the uniformity and consistency of synthesis products, and improves synthesis efficiency and product quality.
Smart Images
Figure CN120659876A_ABST
Abstract
Claims
1. A microarray chip comprising: an electrode array comprising a plurality of cells, each of the plurality of cells comprising an anode and a cathode, each of the anode and the cathode comprising a conductive material; as well as a plurality of current comparator circuits, each of the plurality of current comparator circuits comprising: a first current mirror connected to a reference current source; a first capacitor connected to the first current mirror; a second current mirror configured to be connected to one of the plurality of cells; a second capacitor and a third capacitor, the second capacitor and the third capacitor being connected to the second current mirror, the second capacitor and the third capacitor being connected in parallel; a first voltage comparator connected to the first capacitor and the second capacitor and configured to compare a first voltage from the first capacitor with a second voltage from the second capacitor and provide a first digital signal selected from 0 and 1; and A second voltage comparator is connected to the first capacitor and the third capacitor and is configured to compare the first voltage from the first capacitor with a third voltage from the third capacitor and provide a second digital signal selected from 0 and 1.
2. microarray chip as claimed in claim 1, wherein said microarray chip is configured to be used for the parallel synthesis of the oligomer selected from the group of being composed of DNA, RNA and peptide on the unit of selection.
3. microarray chip as claimed in claim 1, wherein said anode is a central electrode, and said negative electrode is an annular electrode or the grid around said anode.
4. microarray chip as claimed in claim 1, further comprises current supply circuit, switching circuit and the readback control circuit that are connected with each unit in described multiple units, wherein said readback control circuit is configured to control described switching circuit to open the unit of selection and will supply the electric current from described current supply circuit to the unit of described selection.
5. microarray chip as claimed in claim 1, each in wherein said multiple current comparator circuit is configured to be connected with two or more units in described multiple units, and measures the electric current from the described two or more units in described multiple units.
6. microarray chip as claimed in claim 1, wherein said first voltage comparator is configured to: when said first voltage was lower than or equal to said second voltage, provide 0 as said first digital signal; when said first voltage was higher than said second voltage, provide 1 as said first digital signal.
7. microarray chip as claimed in claim 6, wherein said second voltage comparator is configured to: when said first voltage was higher than or equal to said 3rd voltage, provide 0 as said second digital signal; when said first voltage was lower than said 3rd voltage, provide 1 as said second digital signal.
8. microarray chip as claimed in claim 7, wherein said first voltage comparator and said second voltage comparator are configured to the signal combination of the current capability of the format output indication corresponding unit with (described first digital signal, described second digital signal), and described signal combination is selected from the group of being formed by (0,0), (0,1) and (1,0).
9. microarray chip as claimed in claim 8, wherein only when the described signal combination of corresponding unit is (0,0), described corresponding unit just meets specification and is configured to be used for synthesis.
10. microarray chip as claimed in claim 1, each in wherein said first capacitor, said second capacitor and said third capacitor comprises one or more capacitors that are configured to open or close, so that adjustable capacitor is provided.
11. microarray chip as claimed in claim 10, each in wherein said first capacitor, said second capacitor and said third capacitor comprises four capacitors that are configured to open or close.
12. microarray chip as claimed in claim 1, wherein said multiple units comprise the units in quantity in the scope of 10,000 to 2,000,000.
13. microarray chip as claimed in claim 1, wherein said multiple units comprise 1,000,000 to 2,000,000 units.
14. microarray chip as claimed in claim 1, the quantity of wherein said multiple current comparator circuits is less than the quantity of said multiple units.
15. microarray chip as claimed in claim 1, wherein said multiple units are arranged at the central area of said microarray chip, and said multiple current comparator circuits are arranged at the edge of said microarray chip.
16. A system comprising the microarray chip according to claim 1.
17. system as claimed in claim 16, further comprise controller and the display that is connected with described controller, described controller is configured to couple with described microarray chip, wherein said controller is configured to control the test current of each unit in described multiple units, and described display is configured to show the result that comprises described the first digital signal and described the second digital signal.
18. The system of claim 16, wherein the first voltage comparator and the second voltage comparator are configured to output a signal combination indicating the current capability of the corresponding unit in the format of (the first digital signal, the second digital signal), the signal combination being selected from the group consisting of (0,0), (0,1) and (1,0).
19. A method for testing or using a microarray chip as claimed in claim 1, comprising: supplying a current to a cell selected from the plurality of cells for a test current; activating a corresponding current comparator circuit among the plurality of current comparator circuits corresponding to the cell selected from the plurality of cells; supplying a reference current to a reference current source in the corresponding current comparator circuit; as well as The first digital signal from the first voltage comparator and the second digital signal from the second voltage comparator are output.
20. The method of claim 19, wherein when the first voltage is lower than or equal to the second voltage, the first voltage comparator provides 0 as the first digital signal; when the first voltage is higher than the second voltage, the first voltage comparator provides 1 as the first digital signal.
21. The method of claim 20, wherein when the first voltage is higher than or equal to the third voltage, the second voltage comparator provides 0 as the second digital signal; when the first voltage is lower than the third voltage, the second voltage comparator provides 1 as the second digital signal.
22. The method of claim 19, wherein the first voltage comparator and the second voltage comparator output a signal combination indicating the current capability of the corresponding unit in the format of (the first digital signal, the second digital signal), the signal combination being selected from the group consisting of (0, 0), (0, 1), and (1, 0).
23. The method of claim 19, wherein the plurality of current comparator circuits are activated simultaneously for parallel testing of a corresponding number of cells selected from the plurality of cells.
24. The method of claim 19, further comprising selecting the corresponding unit for synthesis only when the signal combination of the corresponding unit is (0, 0).
Citation Information
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